author | lucy |
Mon, 18 Nov 2019 17:11:06 +0100 | |
changeset 59122 | 5d73255c2d52 |
parent 54983 | 81becad91321 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include "precompiled.hpp" |
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#include "jvm.h" |
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#include "asm/macroAssembler.inline.hpp" |
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#include "logging/log.hpp" |
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#include "logging/logStream.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "oops/compressedOops.hpp" |
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#include "runtime/java.hpp" |
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#include "runtime/os.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
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#include "runtime/vm_version.hpp" |
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#include <sys/mman.h> |
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uint VM_Version::_L2_data_cache_line_size = 0; |
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void VM_Version::initialize() { |
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assert(_features != 0, "System pre-initialization is not complete."); |
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guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
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|
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PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
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PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
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PrefetchFieldsAhead = prefetch_fields_ahead(); |
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// Allocation prefetch settings |
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AllocatePrefetchDistance = allocate_prefetch_distance(); |
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AllocatePrefetchStyle = allocate_prefetch_style(); |
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intx cache_line_size = prefetch_data_size(); |
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if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) { |
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AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size); |
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} |
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if (AllocatePrefetchInstr == 1) { |
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if (!has_blk_init()) { |
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warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable"); |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
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} |
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if (cache_line_size <= 0) { |
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warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work"); |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
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} |
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} |
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UseSSE = false; // Only used on x86 and x64. |
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_supports_cx8 = true; // All SPARC V9 implementations. |
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_supports_atomic_getset4 = true; // Using the 'swap' instruction. |
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if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) { |
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// Indirect and direct branches are cost equivalent. |
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FLAG_SET_DEFAULT(UseInlineCaches, false); |
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} |
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// Align loops on the proper instruction boundary to fill the instruction |
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// fetch buffer. |
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if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
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FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment); |
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} |
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// 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit |
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// VM has the same registers and smaller objects. |
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CompressedOops::set_shift(LogMinObjAlignmentInBytes); |
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CompressedKlassPointers::set_shift(LogKlassAlignmentInBytes); |
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#ifdef COMPILER2 |
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if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) { |
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// Indirect and direct branches are cost equivalent. |
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FLAG_SET_DEFAULT(UseJumpTables, true); |
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} |
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// Entry and loop tops are aligned to fill the instruction fetch buffer. |
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if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
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FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment); |
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} |
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if (UseTLAB && cache_line_size > 0 && |
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FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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if (has_fast_bis()) { |
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// Use BIS instruction for TLAB allocation prefetch. |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1); |
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} |
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else if (has_sparc5()) { |
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// Use prefetch instruction to avoid partial RAW issue on Core C4 processors, |
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// also use prefetch style 3. |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
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if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
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} |
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} |
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} |
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if (AllocatePrefetchInstr == 1) { |
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// Use allocation prefetch style 3 because BIS instructions require |
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// aligned memory addresses. |
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
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} |
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if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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if (AllocatePrefetchInstr == 0) { |
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// Use different prefetch distance without BIS |
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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} else { |
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// Use smaller prefetch distance with BIS |
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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} |
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} |
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// We increase the number of prefetched cache lines, to use just a bit more |
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// aggressive approach, when the L2-cache line size is small (32 bytes), or |
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// when running on newer processor implementations, such as the Core C4. |
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bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5()); |
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|
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if (inc_prefetch) { |
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// We use a factor two for small cache line sizes (as before) but a slightly |
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// more conservative increase when running on more recent hardware that will |
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// benefit from just a bit more aggressive prefetching. |
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if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { |
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const int ap_lns = AllocatePrefetchLines; |
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const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2; |
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FLAG_SET_ERGO(AllocatePrefetchLines, ap_lns + ap_inc); |
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} |
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if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { |
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const int ip_lns = AllocateInstancePrefetchLines; |
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const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2; |
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FLAG_SET_ERGO(AllocateInstancePrefetchLines, ip_lns + ip_inc); |
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} |
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} |
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#endif /* COMPILER2 */ |
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151 |
|
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// Use hardware population count instruction if available. |
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if (has_popc()) { |
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154 |
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
2342 | 155 |
FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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156 |
} |
10252 | 157 |
} else if (UsePopCountInstruction) { |
158 |
warning("POPC instruction is not available on this CPU"); |
|
159 |
FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
|
160 |
} |
|
161 |
||
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// Use compare and branch instructions if available. |
10252 | 163 |
if (has_cbcond()) { |
164 |
if (FLAG_IS_DEFAULT(UseCBCond)) { |
|
165 |
FLAG_SET_DEFAULT(UseCBCond, true); |
|
166 |
} |
|
167 |
} else if (UseCBCond) { |
|
168 |
warning("CBCOND instruction is not available on this CPU"); |
|
169 |
FLAG_SET_DEFAULT(UseCBCond, false); |
|
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} |
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171 |
|
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// Use 'mpmul' instruction if available. |
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if (has_mpmul()) { |
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if (FLAG_IS_DEFAULT(UseMPMUL)) { |
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FLAG_SET_DEFAULT(UseMPMUL, true); |
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} |
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} else if (UseMPMUL) { |
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warning("MPMUL instruction is not available on this CPU"); |
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FLAG_SET_DEFAULT(UseMPMUL, false); |
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} |
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181 |
|
10501 | 182 |
assert(BlockZeroingLowLimit > 0, "invalid value"); |
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183 |
|
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184 |
if (has_blk_zeroing() && cache_line_size > 0) { |
10501 | 185 |
if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
186 |
FLAG_SET_DEFAULT(UseBlockZeroing, true); |
|
187 |
} |
|
188 |
} else if (UseBlockZeroing) { |
|
189 |
warning("BIS zeroing instructions are not available on this CPU"); |
|
190 |
FLAG_SET_DEFAULT(UseBlockZeroing, false); |
|
191 |
} |
|
192 |
||
10512 | 193 |
assert(BlockCopyLowLimit > 0, "invalid value"); |
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194 |
|
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195 |
if (has_blk_zeroing() && cache_line_size > 0) { |
10512 | 196 |
if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
197 |
FLAG_SET_DEFAULT(UseBlockCopy, true); |
|
198 |
} |
|
199 |
} else if (UseBlockCopy) { |
|
200 |
warning("BIS instructions are not available or expensive on this CPU"); |
|
201 |
FLAG_SET_DEFAULT(UseBlockCopy, false); |
|
202 |
} |
|
203 |
||
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204 |
#ifdef COMPILER2 |
10252 | 205 |
if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { |
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206 |
FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
10252 | 207 |
} |
208 |
||
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209 |
// Currently not supported anywhere. |
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210 |
FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
10264 | 211 |
|
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212 |
MaxVectorSize = 8; |
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213 |
|
10264 | 214 |
assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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215 |
#endif |
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216 |
|
10264 | 217 |
assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
218 |
assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
|
219 |
||
1 | 220 |
char buf[512]; |
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221 |
jio_snprintf(buf, sizeof(buf), |
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222 |
"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s" |
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223 |
"%s%s%s%s%s%s%s%s%s" "%s%s%s%s%s%s%s%s%s" |
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224 |
"%s%s%s%s%s%s%s", |
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225 |
(has_v9() ? "v9" : ""), |
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226 |
(has_popc() ? ", popc" : ""), |
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227 |
(has_vis1() ? ", vis1" : ""), |
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228 |
(has_vis2() ? ", vis2" : ""), |
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229 |
(has_blk_init() ? ", blk_init" : ""), |
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230 |
(has_fmaf() ? ", fmaf" : ""), |
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231 |
(has_hpc() ? ", hpc" : ""), |
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232 |
(has_ima() ? ", ima" : ""), |
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|
233 |
(has_aes() ? ", aes" : ""), |
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234 |
(has_des() ? ", des" : ""), |
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|
235 |
(has_kasumi() ? ", kas" : ""), |
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|
236 |
(has_camellia() ? ", cam" : ""), |
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|
237 |
(has_md5() ? ", md5" : ""), |
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|
238 |
(has_sha1() ? ", sha1" : ""), |
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|
239 |
(has_sha256() ? ", sha256" : ""), |
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|
240 |
(has_sha512() ? ", sha512" : ""), |
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|
241 |
(has_mpmul() ? ", mpmul" : ""), |
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|
242 |
(has_mont() ? ", mont" : ""), |
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|
243 |
(has_pause() ? ", pause" : ""), |
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|
244 |
(has_cbcond() ? ", cbcond" : ""), |
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|
245 |
(has_crc32c() ? ", crc32c" : ""), |
1 | 246 |
|
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|
247 |
(has_athena_plus() ? ", athena_plus" : ""), |
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|
248 |
(has_vis3b() ? ", vis3b" : ""), |
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|
249 |
(has_adi() ? ", adi" : ""), |
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|
250 |
(has_sparc5() ? ", sparc5" : ""), |
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|
251 |
(has_mwait() ? ", mwait" : ""), |
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|
252 |
(has_xmpmul() ? ", xmpmul" : ""), |
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|
253 |
(has_xmont() ? ", xmont" : ""), |
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|
254 |
(has_pause_nsec() ? ", pause_nsec" : ""), |
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|
255 |
(has_vamask() ? ", vamask" : ""), |
1 | 256 |
|
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|
257 |
(has_sparc6() ? ", sparc6" : ""), |
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|
258 |
(has_dictunp() ? ", dictunp" : ""), |
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|
259 |
(has_fpcmpshl() ? ", fpcmpshl" : ""), |
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|
260 |
(has_rle() ? ", rle" : ""), |
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|
261 |
(has_sha3() ? ", sha3" : ""), |
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|
262 |
(has_athena_plus2()? ", athena_plus2" : ""), |
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|
263 |
(has_vis3c() ? ", vis3c" : ""), |
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|
264 |
(has_sparc5b() ? ", sparc5b" : ""), |
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|
265 |
(has_mme() ? ", mme" : ""), |
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|
266 |
|
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|
267 |
(has_fast_idiv() ? ", *idiv" : ""), |
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|
268 |
(has_fast_rdpc() ? ", *rdpc" : ""), |
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|
269 |
(has_fast_bis() ? ", *bis" : ""), |
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|
270 |
(has_fast_ld() ? ", *ld" : ""), |
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|
271 |
(has_fast_cmove() ? ", *cmove" : ""), |
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|
272 |
(has_fast_ind_br() ? ", *ind_br" : ""), |
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|
273 |
(has_blk_zeroing() ? ", *blk_zeroing" : "")); |
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|
274 |
|
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|
275 |
assert(strlen(buf) >= 2, "must be"); |
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|
276 |
|
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|
277 |
_features_string = os::strdup(buf); |
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|
278 |
|
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|
279 |
log_info(os, cpu)("SPARC features detected: %s", _features_string); |
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|
280 |
|
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|
281 |
// UseVIS is set to the smallest of what hardware supports and what the command |
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|
282 |
// line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do |
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|
283 |
// not support it. |
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|
284 |
|
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|
285 |
if (UseVIS > 3) UseVIS = 3; |
6e357e2c8143
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changeset
|
286 |
if (UseVIS < 0) UseVIS = 0; |
10027 | 287 |
if (!has_vis3()) // Drop to 2 if no VIS3 support |
46592
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|
288 |
UseVIS = MIN2((intx)2, UseVIS); |
10027 | 289 |
if (!has_vis2()) // Drop to 1 if no VIS2 support |
46592
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|
290 |
UseVIS = MIN2((intx)1, UseVIS); |
10027 | 291 |
if (!has_vis1()) // Drop to 0 if no VIS1 support |
292 |
UseVIS = 0; |
|
293 |
||
22505 | 294 |
if (has_aes()) { |
34176
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8131778: java disables UseAES flag when using VIS=2 on sparc
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diff
changeset
|
295 |
if (FLAG_IS_DEFAULT(UseAES)) { |
c1b52e665b47
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parents:
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|
296 |
FLAG_SET_DEFAULT(UseAES, true); |
c1b52e665b47
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changeset
|
297 |
} |
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changeset
|
298 |
if (!UseAES) { |
c1b52e665b47
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parents:
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changeset
|
299 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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diff
changeset
|
300 |
warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); |
22505 | 301 |
} |
34176
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8131778: java disables UseAES flag when using VIS=2 on sparc
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changeset
|
302 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
c1b52e665b47
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changeset
|
303 |
} else { |
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parents:
34174
diff
changeset
|
304 |
// The AES intrinsic stubs require AES instruction support (of course) |
c1b52e665b47
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parents:
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diff
changeset
|
305 |
// but also require VIS3 mode or higher for instructions it use. |
c1b52e665b47
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parents:
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diff
changeset
|
306 |
if (UseVIS > 2) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
34174
diff
changeset
|
307 |
if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
34174
diff
changeset
|
308 |
FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
309 |
} |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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diff
changeset
|
310 |
} else { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
311 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
312 |
warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
313 |
} |
22505 | 314 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
315 |
} |
|
316 |
} |
|
317 |
} else if (UseAES || UseAESIntrinsics) { |
|
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
318 |
if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
319 |
warning("AES instructions are not available on this CPU"); |
22505 | 320 |
FLAG_SET_DEFAULT(UseAES, false); |
321 |
} |
|
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
322 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
323 |
warning("AES intrinsics are not available on this CPU"); |
22505 | 324 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
325 |
} |
|
326 |
} |
|
327 |
||
35154 | 328 |
if (UseAESCTRIntrinsics) { |
329 |
warning("AES/CTR intrinsics are not available on this CPU"); |
|
330 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); |
|
331 |
} |
|
332 |
||
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
333 |
// GHASH/GCM intrinsics |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
334 |
if (has_vis3() && (UseVIS > 2)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
335 |
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
336 |
UseGHASHIntrinsics = true; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
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diff
changeset
|
337 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
338 |
} else if (UseGHASHIntrinsics) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
339 |
if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) |
31774 | 340 |
warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); |
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
341 |
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
342 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
343 |
|
46597
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46595
diff
changeset
|
344 |
if (has_fmaf()) { |
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46595
diff
changeset
|
345 |
if (FLAG_IS_DEFAULT(UseFMA)) { |
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46595
diff
changeset
|
346 |
UseFMA = true; |
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46595
diff
changeset
|
347 |
} |
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46595
diff
changeset
|
348 |
} else if (UseFMA) { |
41323 | 349 |
warning("FMA instructions are not available on this CPU"); |
350 |
FLAG_SET_DEFAULT(UseFMA, false); |
|
351 |
} |
|
352 |
||
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
353 |
// SHA1, SHA256, and SHA512 instructions were added to SPARC at different times |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
354 |
if (has_sha1() || has_sha256() || has_sha512()) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
355 |
if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
356 |
if (FLAG_IS_DEFAULT(UseSHA)) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
357 |
FLAG_SET_DEFAULT(UseSHA, true); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
358 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
359 |
} else { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
360 |
if (UseSHA) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
361 |
warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
362 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
363 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
364 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
365 |
} else if (UseSHA) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
366 |
warning("SHA instructions are not available on this CPU"); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
367 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
368 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
369 |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
370 |
if (UseSHA && has_sha1()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
371 |
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
372 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
373 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
374 |
} else if (UseSHA1Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
375 |
warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
376 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
377 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
378 |
|
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
379 |
if (UseSHA && has_sha256()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
380 |
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
381 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
382 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
383 |
} else if (UseSHA256Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
384 |
warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
385 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
386 |
} |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
387 |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
388 |
if (UseSHA && has_sha512()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
389 |
if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
390 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
391 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
392 |
} else if (UseSHA512Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
393 |
warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
394 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
395 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
396 |
|
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
397 |
if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
398 |
FLAG_SET_DEFAULT(UseSHA, false); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
399 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
400 |
|
31515 | 401 |
if (has_crc32c()) { |
402 |
if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions |
|
403 |
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { |
|
404 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); |
|
405 |
} |
|
406 |
} else { |
|
407 |
if (UseCRC32CIntrinsics) { |
|
408 |
warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
|
409 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
410 |
} |
|
411 |
} |
|
412 |
} else if (UseCRC32CIntrinsics) { |
|
413 |
warning("CRC32C instruction is not available on this CPU"); |
|
414 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
415 |
} |
|
416 |
||
32581 | 417 |
if (UseVIS > 2) { |
418 |
if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { |
|
419 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); |
|
420 |
} |
|
421 |
} else if (UseAdler32Intrinsics) { |
|
422 |
warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
|
423 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); |
|
424 |
} |
|
425 |
||
34205 | 426 |
if (UseVIS > 2) { |
427 |
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
|
428 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); |
|
429 |
} |
|
430 |
} else if (UseCRC32Intrinsics) { |
|
42580
56304dee97f3
8169711: CDS does not patch entry trampoline if intrinsic method is disabled
thartmann
parents:
42024
diff
changeset
|
431 |
warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled"); |
34205 | 432 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
433 |
} |
|
434 |
||
47561
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
435 |
if (UseVIS > 2) { |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
436 |
if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
437 |
FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, true); |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
438 |
} |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
439 |
} else if (UseMultiplyToLenIntrinsic) { |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
440 |
warning("SPARC multiplyToLen intrinsics require VIS3 instructions support. Intrinsics will be disabled"); |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
441 |
FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
442 |
} |
f59f0e51ef8a
8167199: Add C2 SPARC intrinsic for BigInteger::multiplyToLen() method.
neliasso
parents:
47216
diff
changeset
|
443 |
|
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
444 |
if (UseVectorizedMismatchIntrinsic) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
445 |
warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
446 |
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
447 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
448 |
|
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
449 |
if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
450 |
(cache_line_size > ContendedPaddingWidth)) |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
451 |
ContendedPaddingWidth = cache_line_size; |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
452 |
|
30209
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
453 |
// This machine does not allow unaligned memory accesses |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
454 |
if (UseUnalignedAccesses) { |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
455 |
if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
456 |
warning("Unaligned memory access is not available on this CPU"); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
457 |
FLAG_SET_DEFAULT(UseUnalignedAccesses, false); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
458 |
} |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
459 |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
460 |
if (log_is_enabled(Info, os, cpu)) { |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
461 |
ResourceMark rm; |
46701
f559541c0daa
8181917: Refactor UL LogStreams to avoid using resource area
stuefe
parents:
46597
diff
changeset
|
462 |
LogStream ls(Log(os, cpu)::info()); |
f559541c0daa
8181917: Refactor UL LogStreams to avoid using resource area
stuefe
parents:
46597
diff
changeset
|
463 |
outputStream* log = &ls; |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
464 |
log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
465 |
log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
466 |
log->print("Allocation"); |
1 | 467 |
if (AllocatePrefetchStyle <= 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
468 |
log->print(": no prefetching"); |
1 | 469 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
470 |
log->print(" prefetching: "); |
10267 | 471 |
if (AllocatePrefetchInstr == 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
472 |
log->print("PREFETCH"); |
10267 | 473 |
} else if (AllocatePrefetchInstr == 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
474 |
log->print("BIS"); |
10267 | 475 |
} |
1 | 476 |
if (AllocatePrefetchLines > 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
477 |
log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
1 | 478 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
479 |
log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
1 | 480 |
} |
481 |
} |
|
482 |
if (PrefetchCopyIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
483 |
log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
1 | 484 |
} |
485 |
if (PrefetchScanIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
486 |
log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
1 | 487 |
} |
488 |
if (PrefetchFieldsAhead > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
489 |
log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
1 | 490 |
} |
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
491 |
if (ContendedPaddingWidth > 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
492 |
log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
493 |
} |
1 | 494 |
} |
495 |
} |
|
496 |
||
497 |
void VM_Version::print_features() { |
|
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
498 |
tty->print("ISA features [0x%0" PRIx64 "]:", _features); |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
499 |
if (_features_string != NULL) { |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
500 |
tty->print(" %s", _features_string); |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
501 |
} |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
502 |
tty->cr(); |
1 | 503 |
} |
504 |
||
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
505 |
void VM_Version::determine_features() { |
46593 | 506 |
platform_features(); // platform_features() is os_arch specific. |
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
507 |
|
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
508 |
assert(has_v9(), "must be"); |
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
509 |
|
46593 | 510 |
if (UseNiagaraInstrs) { // Limit code generation to Niagara. |
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
511 |
_features &= niagara1_msk; |
1 | 512 |
} |
513 |
} |
|
514 |
||
35148 | 515 |
static uint64_t saved_features = 0; |
1 | 516 |
|
517 |
void VM_Version::allow_all() { |
|
518 |
saved_features = _features; |
|
46592
6e357e2c8143
8172231: SPARC ISA/CPU feature detection is broken/insufficient (on Solaris)
neliasso
parents:
46591
diff
changeset
|
519 |
_features = full_feature_msk; |
1 | 520 |
} |
521 |
||
522 |
void VM_Version::revert() { |
|
523 |
_features = saved_features; |
|
524 |
} |