author | rraghavan |
Mon, 19 Jun 2017 01:23:58 -0700 | |
changeset 46547 | e1b926a0b23f |
parent 46381 | 020219e46c86 |
child 46560 | 388aa8d67c80 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
46381 | 2 |
* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. |
1 | 3 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
|
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* This code is free software; you can redistribute it and/or modify it |
|
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* under the terms of the GNU General Public License version 2 only, as |
|
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* published by the Free Software Foundation. |
|
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
|
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
|
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* |
|
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include "precompiled.hpp" |
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#include "asm/macroAssembler.inline.hpp" |
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#include "logging/log.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "runtime/java.hpp" |
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#include "runtime/os.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
32 |
#include "vm_version_sparc.hpp" |
|
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|
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unsigned int VM_Version::_L2_data_cache_line_size = 0; |
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|
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void VM_Version::initialize() { |
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assert(_features != 0, "System pre-initialization is not complete."); |
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guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
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|
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if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) { |
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FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, prefetch_copy_interval_in_bytes()); |
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} |
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if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) { |
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FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, prefetch_scan_interval_in_bytes()); |
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} |
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if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) { |
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FLAG_SET_DEFAULT(PrefetchFieldsAhead, prefetch_fields_ahead()); |
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} |
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|
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// Allocation prefetch settings |
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intx cache_line_size = prefetch_data_size(); |
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if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) && |
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(cache_line_size > AllocatePrefetchStepSize)) { |
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FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size); |
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} |
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|
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if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 512); |
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} |
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|
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if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) { |
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assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0"); |
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if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
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warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag."); |
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} |
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0); |
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} |
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|
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if ((AllocatePrefetchInstr == 1) && (!has_blk_init() || cache_line_size <= 0)) { |
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if (!FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable"); |
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} |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
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} |
75 |
||
1 | 76 |
UseSSE = 0; // Only on x86 and x64 |
77 |
||
10267 | 78 |
_supports_cx8 = has_v9(); |
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_supports_atomic_getset4 = true; // swap instruction |
1 | 80 |
|
7704 | 81 |
if (is_niagara()) { |
1 | 82 |
// Indirect branch is the same cost as direct |
83 |
if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
|
2342 | 84 |
FLAG_SET_DEFAULT(UseInlineCaches, false); |
1 | 85 |
} |
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// Align loops on a single instruction boundary. |
87 |
if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
|
88 |
FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
|
89 |
} |
|
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// 32-bit oops don't make sense for the 64-bit VM on sparc |
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// since the 32-bit VM has the same registers and smaller objects. |
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Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
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Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
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#ifdef COMPILER2 |
95 |
// Indirect branch is the same cost as direct |
|
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if (FLAG_IS_DEFAULT(UseJumpTables)) { |
|
2342 | 97 |
FLAG_SET_DEFAULT(UseJumpTables, true); |
1 | 98 |
} |
99 |
// Single-issue, so entry and loop tops are |
|
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// aligned on a single instruction boundary |
|
101 |
if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
|
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FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
1 | 103 |
} |
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if (is_niagara_plus()) { |
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if (has_blk_init() && (cache_line_size > 0) && UseTLAB && |
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FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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if (!has_sparc5_instr()) { |
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// Use BIS instruction for TLAB allocation prefetch |
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// on Niagara plus processors other than those based on CoreS4 |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1); |
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} else { |
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// On CoreS4 processors use prefetch instruction |
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// to avoid partial RAW issue, also use prefetch style 3 |
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FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
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if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
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} |
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118 |
} |
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} |
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if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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if (AllocatePrefetchInstr == 0) { |
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122 |
// Use different prefetch distance without BIS |
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123 |
FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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124 |
} else { |
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// Use smaller prefetch distance with BIS |
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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} |
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128 |
} |
10267 | 129 |
if (is_T4()) { |
130 |
// Double number of prefetched cache lines on T4 |
|
131 |
// since L2 cache line size is smaller (32 bytes). |
|
132 |
if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { |
|
133 |
FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); |
|
134 |
} |
|
135 |
if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { |
|
136 |
FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); |
|
137 |
} |
|
138 |
} |
|
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139 |
} |
10267 | 140 |
|
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141 |
if ((AllocatePrefetchInstr == 1) && (AllocatePrefetchStyle != 3)) { |
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142 |
if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
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143 |
warning("AllocatePrefetchStyle set to 3 because BIS instructions require aligned memory addresses"); |
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144 |
} |
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145 |
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); |
1 | 146 |
} |
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147 |
#endif /* COMPILER2 */ |
1 | 148 |
} |
149 |
||
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// Use hardware population count instruction if available. |
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|
151 |
if (has_hardware_popc()) { |
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|
152 |
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
2342 | 153 |
FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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|
154 |
} |
10252 | 155 |
} else if (UsePopCountInstruction) { |
156 |
warning("POPC instruction is not available on this CPU"); |
|
157 |
FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
|
158 |
} |
|
159 |
||
160 |
// T4 and newer Sparc cpus have new compare and branch instruction. |
|
161 |
if (has_cbcond()) { |
|
162 |
if (FLAG_IS_DEFAULT(UseCBCond)) { |
|
163 |
FLAG_SET_DEFAULT(UseCBCond, true); |
|
164 |
} |
|
165 |
} else if (UseCBCond) { |
|
166 |
warning("CBCOND instruction is not available on this CPU"); |
|
167 |
FLAG_SET_DEFAULT(UseCBCond, false); |
|
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168 |
} |
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169 |
|
10501 | 170 |
assert(BlockZeroingLowLimit > 0, "invalid value"); |
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171 |
if (has_block_zeroing() && cache_line_size > 0) { |
10501 | 172 |
if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
173 |
FLAG_SET_DEFAULT(UseBlockZeroing, true); |
|
174 |
} |
|
175 |
} else if (UseBlockZeroing) { |
|
176 |
warning("BIS zeroing instructions are not available on this CPU"); |
|
177 |
FLAG_SET_DEFAULT(UseBlockZeroing, false); |
|
178 |
} |
|
179 |
||
10512 | 180 |
assert(BlockCopyLowLimit > 0, "invalid value"); |
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|
181 |
if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache |
10512 | 182 |
if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
183 |
FLAG_SET_DEFAULT(UseBlockCopy, true); |
|
184 |
} |
|
185 |
} else if (UseBlockCopy) { |
|
186 |
warning("BIS instructions are not available or expensive on this CPU"); |
|
187 |
FLAG_SET_DEFAULT(UseBlockCopy, false); |
|
188 |
} |
|
189 |
||
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190 |
#ifdef COMPILER2 |
10252 | 191 |
// T4 and newer Sparc cpus have fast RDPC. |
192 |
if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { |
|
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193 |
FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
10252 | 194 |
} |
195 |
||
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// Currently not supported anywhere. |
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|
197 |
FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
10264 | 198 |
|
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|
199 |
MaxVectorSize = 8; |
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|
200 |
|
10264 | 201 |
assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
6272
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|
202 |
#endif |
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|
203 |
|
10264 | 204 |
assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
205 |
assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
|
206 |
||
1 | 207 |
char buf[512]; |
41706
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|
208 |
jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
10252 | 209 |
(has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
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changeset
|
210 |
(has_hardware_popc() ? ", popc" : ""), |
10252 | 211 |
(has_vis1() ? ", vis1" : ""), |
212 |
(has_vis2() ? ", vis2" : ""), |
|
213 |
(has_vis3() ? ", vis3" : ""), |
|
214 |
(has_blk_init() ? ", blk_init" : ""), |
|
215 |
(has_cbcond() ? ", cbcond" : ""), |
|
22505 | 216 |
(has_aes() ? ", aes" : ""), |
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|
217 |
(has_sha1() ? ", sha1" : ""), |
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|
218 |
(has_sha256() ? ", sha256" : ""), |
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|
219 |
(has_sha512() ? ", sha512" : ""), |
31515 | 220 |
(has_crc32c() ? ", crc32c" : ""), |
10252 | 221 |
(is_ultra3() ? ", ultra3" : ""), |
41706
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|
222 |
(has_sparc5_instr() ? ", sparc5" : ""), |
10252 | 223 |
(is_sun4v() ? ", sun4v" : ""), |
224 |
(is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
|
225 |
(is_sparc64() ? ", sparc64" : ""), |
|
2253
30268d00878e
6812587: Use auxv to determine SPARC hardware features on Solaris
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diff
changeset
|
226 |
(!has_hardware_mul32() ? ", no-mul32" : ""), |
30268d00878e
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changeset
|
227 |
(!has_hardware_div32() ? ", no-div32" : ""), |
1 | 228 |
(!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
229 |
||
230 |
// buf is started with ", " or is empty |
|
35148 | 231 |
_features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf); |
1 | 232 |
|
10027 | 233 |
// UseVIS is set to the smallest of what hardware supports and what |
234 |
// the command line requires. I.e., you cannot set UseVIS to 3 on |
|
235 |
// older UltraSparc which do not support it. |
|
236 |
if (UseVIS > 3) UseVIS=3; |
|
237 |
if (UseVIS < 0) UseVIS=0; |
|
238 |
if (!has_vis3()) // Drop to 2 if no VIS3 support |
|
239 |
UseVIS = MIN2((intx)2,UseVIS); |
|
240 |
if (!has_vis2()) // Drop to 1 if no VIS2 support |
|
241 |
UseVIS = MIN2((intx)1,UseVIS); |
|
242 |
if (!has_vis1()) // Drop to 0 if no VIS1 support |
|
243 |
UseVIS = 0; |
|
244 |
||
24328
bddefb356fba
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|
245 |
// SPARC T4 and above should have support for AES instructions |
22505 | 246 |
if (has_aes()) { |
34176
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changeset
|
247 |
if (FLAG_IS_DEFAULT(UseAES)) { |
c1b52e665b47
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|
248 |
FLAG_SET_DEFAULT(UseAES, true); |
c1b52e665b47
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|
249 |
} |
c1b52e665b47
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changeset
|
250 |
if (!UseAES) { |
c1b52e665b47
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changeset
|
251 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
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changeset
|
252 |
warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); |
22505 | 253 |
} |
34176
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|
254 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
c1b52e665b47
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parents:
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changeset
|
255 |
} else { |
c1b52e665b47
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parents:
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diff
changeset
|
256 |
// The AES intrinsic stubs require AES instruction support (of course) |
c1b52e665b47
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changeset
|
257 |
// but also require VIS3 mode or higher for instructions it use. |
c1b52e665b47
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changeset
|
258 |
if (UseVIS > 2) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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changeset
|
259 |
if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
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changeset
|
260 |
FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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diff
changeset
|
261 |
} |
c1b52e665b47
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parents:
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diff
changeset
|
262 |
} else { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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changeset
|
263 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
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changeset
|
264 |
warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
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diff
changeset
|
265 |
} |
22505 | 266 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
267 |
} |
|
268 |
} |
|
269 |
} else if (UseAES || UseAESIntrinsics) { |
|
34176
c1b52e665b47
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changeset
|
270 |
if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { |
c1b52e665b47
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parents:
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changeset
|
271 |
warning("AES instructions are not available on this CPU"); |
22505 | 272 |
FLAG_SET_DEFAULT(UseAES, false); |
273 |
} |
|
34176
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parents:
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diff
changeset
|
274 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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diff
changeset
|
275 |
warning("AES intrinsics are not available on this CPU"); |
22505 | 276 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
277 |
} |
|
278 |
} |
|
279 |
||
35154 | 280 |
if (UseAESCTRIntrinsics) { |
281 |
warning("AES/CTR intrinsics are not available on this CPU"); |
|
282 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); |
|
283 |
} |
|
284 |
||
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
285 |
// GHASH/GCM intrinsics |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
286 |
if (has_vis3() && (UseVIS > 2)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
287 |
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
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diff
changeset
|
288 |
UseGHASHIntrinsics = true; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
289 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
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diff
changeset
|
290 |
} else if (UseGHASHIntrinsics) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
291 |
if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) |
31774 | 292 |
warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); |
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
293 |
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
294 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
295 |
|
41323 | 296 |
if (UseFMA) { |
297 |
warning("FMA instructions are not available on this CPU"); |
|
298 |
FLAG_SET_DEFAULT(UseFMA, false); |
|
299 |
} |
|
300 |
||
24953
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parents:
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diff
changeset
|
301 |
// SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times |
9680119572be
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diff
changeset
|
302 |
if (has_sha1() || has_sha256() || has_sha512()) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
303 |
if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
9680119572be
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parents:
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diff
changeset
|
304 |
if (FLAG_IS_DEFAULT(UseSHA)) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
305 |
FLAG_SET_DEFAULT(UseSHA, true); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
306 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
307 |
} else { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
308 |
if (UseSHA) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
309 |
warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
9680119572be
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parents:
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diff
changeset
|
310 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
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kvn
parents:
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diff
changeset
|
311 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
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diff
changeset
|
312 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
313 |
} else if (UseSHA) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
314 |
warning("SHA instructions are not available on this CPU"); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
315 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
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kvn
parents:
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diff
changeset
|
316 |
} |
9680119572be
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kvn
parents:
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diff
changeset
|
317 |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
318 |
if (UseSHA && has_sha1()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
319 |
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
320 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
321 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
322 |
} else if (UseSHA1Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
323 |
warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
324 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
325 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
326 |
|
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
327 |
if (UseSHA && has_sha256()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
328 |
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
329 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
330 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
331 |
} else if (UseSHA256Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
332 |
warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
333 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
334 |
} |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
335 |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
336 |
if (UseSHA && has_sha512()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
337 |
if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
338 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
339 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
340 |
} else if (UseSHA512Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
341 |
warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
342 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
343 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
344 |
|
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
345 |
if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
346 |
FLAG_SET_DEFAULT(UseSHA, false); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
347 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
348 |
|
31515 | 349 |
// SPARC T4 and above should have support for CRC32C instruction |
350 |
if (has_crc32c()) { |
|
351 |
if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions |
|
352 |
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { |
|
353 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); |
|
354 |
} |
|
355 |
} else { |
|
356 |
if (UseCRC32CIntrinsics) { |
|
357 |
warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
|
358 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
359 |
} |
|
360 |
} |
|
361 |
} else if (UseCRC32CIntrinsics) { |
|
362 |
warning("CRC32C instruction is not available on this CPU"); |
|
363 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
364 |
} |
|
365 |
||
32581 | 366 |
if (UseVIS > 2) { |
367 |
if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { |
|
368 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); |
|
369 |
} |
|
370 |
} else if (UseAdler32Intrinsics) { |
|
371 |
warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
|
372 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); |
|
373 |
} |
|
374 |
||
34205 | 375 |
if (UseVIS > 2) { |
376 |
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
|
377 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); |
|
378 |
} |
|
379 |
} else if (UseCRC32Intrinsics) { |
|
42580
56304dee97f3
8169711: CDS does not patch entry trampoline if intrinsic method is disabled
thartmann
parents:
42024
diff
changeset
|
380 |
warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled"); |
34205 | 381 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
382 |
} |
|
383 |
||
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
384 |
if (UseVectorizedMismatchIntrinsic) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
385 |
warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
386 |
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
387 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
388 |
|
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
389 |
if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
390 |
(cache_line_size > ContendedPaddingWidth)) |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
391 |
ContendedPaddingWidth = cache_line_size; |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
392 |
|
30209
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
393 |
// This machine does not allow unaligned memory accesses |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
394 |
if (UseUnalignedAccesses) { |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
395 |
if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
396 |
warning("Unaligned memory access is not available on this CPU"); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
397 |
FLAG_SET_DEFAULT(UseUnalignedAccesses, false); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
398 |
} |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
399 |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
400 |
if (log_is_enabled(Info, os, cpu)) { |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
401 |
ResourceMark rm; |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
402 |
outputStream* log = Log(os, cpu)::info_stream(); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
403 |
log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
404 |
log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
405 |
log->print("Allocation"); |
1 | 406 |
if (AllocatePrefetchStyle <= 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
407 |
log->print(": no prefetching"); |
1 | 408 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
409 |
log->print(" prefetching: "); |
10267 | 410 |
if (AllocatePrefetchInstr == 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
411 |
log->print("PREFETCH"); |
10267 | 412 |
} else if (AllocatePrefetchInstr == 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
413 |
log->print("BIS"); |
10267 | 414 |
} |
1 | 415 |
if (AllocatePrefetchLines > 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
416 |
log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
1 | 417 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
418 |
log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
1 | 419 |
} |
420 |
} |
|
421 |
if (PrefetchCopyIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
422 |
log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
1 | 423 |
} |
424 |
if (PrefetchScanIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
425 |
log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
1 | 426 |
} |
427 |
if (PrefetchFieldsAhead > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
428 |
log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
1 | 429 |
} |
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
430 |
if (ContendedPaddingWidth > 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
431 |
log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
432 |
} |
1 | 433 |
} |
434 |
} |
|
435 |
||
436 |
void VM_Version::print_features() { |
|
35148 | 437 |
tty->print_cr("Version:%s", _features); |
1 | 438 |
} |
439 |
||
440 |
int VM_Version::determine_features() { |
|
441 |
if (UseV8InstrsOnly) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
442 |
log_info(os, cpu)("Version is Forced-V8"); |
1 | 443 |
return generic_v8_m; |
444 |
} |
|
445 |
||
446 |
int features = platform_features(unknown_m); // platform_features() is os_arch specific |
|
447 |
||
448 |
if (features == unknown_m) { |
|
449 |
features = generic_v9_m; |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
450 |
log_info(os)("Cannot recognize SPARC version. Default to V9"); |
1 | 451 |
} |
452 |
||
7704 | 453 |
assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
454 |
if (UseNiagaraInstrs) { // Force code generation for Niagara |
|
455 |
if (is_T_family(features)) { |
|
1 | 456 |
// Happy to accomodate... |
457 |
} else { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
458 |
log_info(os, cpu)("Version is Forced-Niagara"); |
7704 | 459 |
features |= T_family_m; |
1 | 460 |
} |
461 |
} else { |
|
7704 | 462 |
if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
463 |
log_info(os, cpu)("Version is Forced-Not-Niagara"); |
7704 | 464 |
features &= ~(T_family_m | T1_model_m); |
1 | 465 |
} else { |
466 |
// Happy to accomodate... |
|
467 |
} |
|
468 |
} |
|
469 |
||
470 |
return features; |
|
471 |
} |
|
472 |
||
35148 | 473 |
static uint64_t saved_features = 0; |
1 | 474 |
|
475 |
void VM_Version::allow_all() { |
|
476 |
saved_features = _features; |
|
477 |
_features = all_features_m; |
|
478 |
} |
|
479 |
||
480 |
void VM_Version::revert() { |
|
481 |
_features = saved_features; |
|
482 |
} |
|
183
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
483 |
|
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
484 |
unsigned int VM_Version::calc_parallel_worker_threads() { |
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
485 |
unsigned int result; |
42024
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
486 |
if (is_M_series() || is_S_series()) { |
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
487 |
// for now, use same gc thread calculation for M-series and S-series as for |
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
488 |
// niagara-plus. In future, we may want to tweak parameters for |
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
489 |
// nof_parallel_worker_thread |
13888
93dce24e57e5
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
13886
diff
changeset
|
490 |
result = nof_parallel_worker_threads(5, 16, 8); |
93dce24e57e5
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
13886
diff
changeset
|
491 |
} else if (is_niagara_plus()) { |
183
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
492 |
result = nof_parallel_worker_threads(5, 16, 8); |
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
493 |
} else { |
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
494 |
result = nof_parallel_worker_threads(5, 8, 8); |
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
495 |
} |
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
496 |
return result; |
ba55c7f3fd45
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
1
diff
changeset
|
497 |
} |
36346 | 498 |
|
499 |
||
500 |
int VM_Version::parse_features(const char* implementation) { |
|
501 |
int features = unknown_m; |
|
502 |
// Convert to UPPER case before compare. |
|
503 |
char* impl = os::strdup_check_oom(implementation); |
|
504 |
||
505 |
for (int i = 0; impl[i] != 0; i++) |
|
506 |
impl[i] = (char)toupper((uint)impl[i]); |
|
507 |
||
508 |
if (strstr(impl, "SPARC64") != NULL) { |
|
509 |
features |= sparc64_family_m; |
|
510 |
} else if (strstr(impl, "SPARC-M") != NULL) { |
|
511 |
// M-series SPARC is based on T-series. |
|
512 |
features |= (M_family_m | T_family_m); |
|
42024
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
513 |
} else if (strstr(impl, "SPARC-S") != NULL) { |
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
514 |
// S-series SPARC is based on T-series. |
f3ee61fe224c
8164002: Add a new CPU family (S_family) for SPARC S7 and above processors
mwalsh
parents:
41706
diff
changeset
|
515 |
features |= (S_family_m | T_family_m); |
36346 | 516 |
} else if (strstr(impl, "SPARC-T") != NULL) { |
517 |
features |= T_family_m; |
|
518 |
if (strstr(impl, "SPARC-T1") != NULL) { |
|
519 |
features |= T1_model_m; |
|
520 |
} |
|
41706
eb0fab7b44af
8165482: java in ldoms, with cpu-arch=generic has problems
mwalsh
parents:
41323
diff
changeset
|
521 |
} else if (strstr(impl, "SUN4V-CPU") != NULL) { |
eb0fab7b44af
8165482: java in ldoms, with cpu-arch=generic has problems
mwalsh
parents:
41323
diff
changeset
|
522 |
// Generic or migration class LDOM |
eb0fab7b44af
8165482: java in ldoms, with cpu-arch=generic has problems
mwalsh
parents:
41323
diff
changeset
|
523 |
features |= T_family_m; |
36346 | 524 |
} else { |
41706
eb0fab7b44af
8165482: java in ldoms, with cpu-arch=generic has problems
mwalsh
parents:
41323
diff
changeset
|
525 |
log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl); |
36346 | 526 |
} |
527 |
os::free((void*)impl); |
|
528 |
return features; |
|
529 |
} |