hotspot/src/cpu/sparc/vm/vm_version_sparc.cpp
author kvn
Thu, 21 Jul 2011 11:25:07 -0700
changeset 10252 0981ce1c3eef
parent 10027 20cd71f29262
child 10264 6879f93d268d
permissions -rw-r--r--
7063628: Use cbcond on T4 Summary: Add new short branch instruction to Hotspot sparc assembler. Reviewed-by: never, twisti, jrose
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/*
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 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "assembler_sparc.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "vm_version_sparc.hpp"
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#ifdef TARGET_OS_FAMILY_linux
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# include "os_linux.inline.hpp"
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#endif
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#ifdef TARGET_OS_FAMILY_solaris
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# include "os_solaris.inline.hpp"
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#endif
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int VM_Version::_features = VM_Version::unknown_m;
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const char* VM_Version::_features_str = "";
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void VM_Version::initialize() {
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  _features = determine_features();
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  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
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  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
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  PrefetchFieldsAhead         = prefetch_fields_ahead();
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  // Allocation prefetch settings
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  intx cache_line_size = L1_data_cache_line_size();
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  if( cache_line_size > AllocatePrefetchStepSize )
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    AllocatePrefetchStepSize = cache_line_size;
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  if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
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    AllocatePrefetchLines = 3; // Optimistic value
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  assert( AllocatePrefetchLines > 0, "invalid value");
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  if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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    AllocatePrefetchLines = 1; // Conservative value
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  AllocatePrefetchDistance = allocate_prefetch_distance();
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  AllocatePrefetchStyle    = allocate_prefetch_style();
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  assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
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  if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
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    warning("BIS instructions are not available on this CPU");
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    FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
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  }
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  UseSSE = 0; // Only on x86 and x64
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  _supports_cx8               = has_v9();
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  if (is_niagara()) {
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    // Indirect branch is the same cost as direct
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    if (FLAG_IS_DEFAULT(UseInlineCaches)) {
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      FLAG_SET_DEFAULT(UseInlineCaches, false);
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    }
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    // Align loops on a single instruction boundary.
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    if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
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      FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
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    }
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    // When using CMS, we cannot use memset() in BOT updates because
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    // the sun4v/CMT version in libc_psr uses BIS which exposes
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    // "phantom zeros" to concurrent readers. See 6948537.
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    if (FLAG_IS_DEFAULT(UseMemSetInBOT) && UseConcMarkSweepGC) {
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      FLAG_SET_DEFAULT(UseMemSetInBOT, false);
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    }
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#ifdef _LP64
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    // 32-bit oops don't make sense for the 64-bit VM on sparc
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    // since the 32-bit VM has the same registers and smaller objects.
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    Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
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#endif // _LP64
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#ifdef COMPILER2
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    // Indirect branch is the same cost as direct
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    if (FLAG_IS_DEFAULT(UseJumpTables)) {
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      FLAG_SET_DEFAULT(UseJumpTables, true);
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    }
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    // Single-issue, so entry and loop tops are
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    // aligned on a single instruction boundary
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    if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
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      FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
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    }
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    if (is_niagara_plus()) {
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      if (has_blk_init() && AllocatePrefetchStyle > 0 &&
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          FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
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        // Use BIS instruction for allocation prefetch.
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        FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
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        if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
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          // Use smaller prefetch distance on N2 with BIS
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          FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
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        }
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      }
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      if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
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        // Use different prefetch distance without BIS
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        FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
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      }
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    }
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#endif
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  }
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  // Use hardware population count instruction if available.
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  if (has_hardware_popc()) {
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    if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
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      FLAG_SET_DEFAULT(UsePopCountInstruction, true);
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    }
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  } else if (UsePopCountInstruction) {
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    warning("POPC instruction is not available on this CPU");
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    FLAG_SET_DEFAULT(UsePopCountInstruction, false);
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  }
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  // T4 and newer Sparc cpus have new compare and branch instruction.
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  if (has_cbcond()) {
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    if (FLAG_IS_DEFAULT(UseCBCond)) {
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      FLAG_SET_DEFAULT(UseCBCond, true);
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    }
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  } else if (UseCBCond) {
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    warning("CBCOND instruction is not available on this CPU");
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    FLAG_SET_DEFAULT(UseCBCond, false);
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  }
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#ifdef COMPILER2
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  // T4 and newer Sparc cpus have fast RDPC.
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  if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
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//    FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
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  }
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  // Currently not supported anywhere.
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  FLAG_SET_DEFAULT(UseFPUForSpilling, false);
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#endif
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  char buf[512];
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  jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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               (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
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               (has_hardware_popc() ? ", popc" : ""),
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               (has_vis1() ? ", vis1" : ""),
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               (has_vis2() ? ", vis2" : ""),
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               (has_vis3() ? ", vis3" : ""),
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               (has_blk_init() ? ", blk_init" : ""),
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               (has_cbcond() ? ", cbcond" : ""),
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               (is_ultra3() ? ", ultra3" : ""),
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               (is_sun4v() ? ", sun4v" : ""),
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               (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
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               (is_sparc64() ? ", sparc64" : ""),
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               (!has_hardware_mul32() ? ", no-mul32" : ""),
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               (!has_hardware_div32() ? ", no-div32" : ""),
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               (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
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  // buf is started with ", " or is empty
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  _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
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  // UseVIS is set to the smallest of what hardware supports and what
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  // the command line requires.  I.e., you cannot set UseVIS to 3 on
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  // older UltraSparc which do not support it.
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  if (UseVIS > 3) UseVIS=3;
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  if (UseVIS < 0) UseVIS=0;
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  if (!has_vis3()) // Drop to 2 if no VIS3 support
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    UseVIS = MIN2((intx)2,UseVIS);
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  if (!has_vis2()) // Drop to 1 if no VIS2 support
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    UseVIS = MIN2((intx)1,UseVIS);
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  if (!has_vis1()) // Drop to 0 if no VIS1 support
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    UseVIS = 0;
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1
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#ifndef PRODUCT
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  if (PrintMiscellaneous && Verbose) {
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    tty->print("Allocation: ");
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    if (AllocatePrefetchStyle <= 0) {
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      tty->print_cr("no prefetching");
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    } else {
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      if (AllocatePrefetchLines > 1) {
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        tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
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      } else {
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        tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance);
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      }
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    }
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    if (PrefetchCopyIntervalInBytes > 0) {
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      tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
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    }
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    if (PrefetchScanIntervalInBytes > 0) {
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      tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
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    }
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    if (PrefetchFieldsAhead > 0) {
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      tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
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    }
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  }
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#endif // PRODUCT
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}
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void VM_Version::print_features() {
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  tty->print_cr("Version:%s", cpu_features());
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}
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int VM_Version::determine_features() {
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  if (UseV8InstrsOnly) {
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    NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
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    return generic_v8_m;
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  }
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  int features = platform_features(unknown_m); // platform_features() is os_arch specific
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  if (features == unknown_m) {
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    features = generic_v9_m;
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    warning("Cannot recognize SPARC version. Default to V9");
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  }
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  assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
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  if (UseNiagaraInstrs) { // Force code generation for Niagara
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    if (is_T_family(features)) {
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      // Happy to accomodate...
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    } else {
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      NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
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      features |= T_family_m;
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    }
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  } else {
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    if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
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      NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
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      features &= ~(T_family_m | T1_model_m);
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    } else {
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      // Happy to accomodate...
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    }
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  }
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  return features;
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}
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static int saved_features = 0;
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void VM_Version::allow_all() {
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  saved_features = _features;
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  _features      = all_features_m;
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}
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void VM_Version::revert() {
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  _features = saved_features;
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}
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unsigned int VM_Version::calc_parallel_worker_threads() {
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  unsigned int result;
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  if (is_niagara_plus()) {
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    result = nof_parallel_worker_threads(5, 16, 8);
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  } else {
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    result = nof_parallel_worker_threads(5, 8, 8);
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  }
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  return result;
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}