author | zmajo |
Thu, 21 Apr 2016 09:21:48 +0200 | |
changeset 38054 | 3a22f46fb514 |
parent 37430 | fd743dadef12 |
child 38220 | 8d86b82e0ac7 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
7397 | 25 |
#include "precompiled.hpp" |
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#include "asm/macroAssembler.inline.hpp" |
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#include "logging/log.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "runtime/java.hpp" |
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#include "runtime/os.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
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#include "vm_version_sparc.hpp" |
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|
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unsigned int VM_Version::_L2_data_cache_line_size = 0; |
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void VM_Version::initialize() { |
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assert(_features != 0, "System pre-initialization is not complete."); |
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guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
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|
1 | 40 |
PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
41 |
PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
|
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PrefetchFieldsAhead = prefetch_fields_ahead(); |
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||
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// Allocation prefetch settings |
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10267 | 45 |
intx cache_line_size = prefetch_data_size(); |
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if( cache_line_size > AllocatePrefetchStepSize ) |
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AllocatePrefetchStepSize = cache_line_size; |
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|
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AllocatePrefetchDistance = allocate_prefetch_distance(); |
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AllocatePrefetchStyle = allocate_prefetch_style(); |
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||
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if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
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warning("BIS instructions are not available on this CPU"); |
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FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); |
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} |
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||
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UseSSE = 0; // Only on x86 and x64 |
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||
10267 | 59 |
_supports_cx8 = has_v9(); |
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_supports_atomic_getset4 = true; // swap instruction |
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|
7704 | 62 |
if (is_niagara()) { |
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// Indirect branch is the same cost as direct |
64 |
if (FLAG_IS_DEFAULT(UseInlineCaches)) { |
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2342 | 65 |
FLAG_SET_DEFAULT(UseInlineCaches, false); |
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} |
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// Align loops on a single instruction boundary. |
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if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |
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FLAG_SET_DEFAULT(OptoLoopAlignment, 4); |
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} |
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#ifdef _LP64 |
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// 32-bit oops don't make sense for the 64-bit VM on sparc |
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// since the 32-bit VM has the same registers and smaller objects. |
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Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
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Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
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#endif // _LP64 |
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#ifdef COMPILER2 |
78 |
// Indirect branch is the same cost as direct |
|
79 |
if (FLAG_IS_DEFAULT(UseJumpTables)) { |
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2342 | 80 |
FLAG_SET_DEFAULT(UseJumpTables, true); |
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} |
82 |
// Single-issue, so entry and loop tops are |
|
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// aligned on a single instruction boundary |
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84 |
if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { |
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2342 | 85 |
FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
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} |
7704 | 87 |
if (is_niagara_plus()) { |
10267 | 88 |
if (has_blk_init() && UseTLAB && |
89 |
FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
|
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// Use BIS instruction for TLAB allocation prefetch. |
|
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FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); |
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if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
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FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); |
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} |
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if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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// Use smaller prefetch distance with BIS |
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
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} |
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} |
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if (is_T4()) { |
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// Double number of prefetched cache lines on T4 |
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// since L2 cache line size is smaller (32 bytes). |
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if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { |
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FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); |
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} |
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if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { |
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FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); |
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} |
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} |
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if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
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// Use different prefetch distance without BIS |
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FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
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} |
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if (AllocatePrefetchInstr == 1) { |
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// Need extra space at the end of TLAB for BIS, otherwise prefetching |
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// instructions will fault (due to accessing memory outside of heap). |
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// The amount of space is the max of the number of lines to |
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// prefetch for array and for instance allocations. (Extra space must be |
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// reserved to accomodate both types of allocations.) |
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// +1 for rounding up to next cache line, +1 to be safe |
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int lines = MAX2(AllocatePrefetchLines, AllocateInstancePrefetchLines) + 2; |
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int step_size = AllocatePrefetchStepSize; |
124 |
int distance = AllocatePrefetchDistance; |
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_reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; |
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126 |
} |
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1 | 127 |
} |
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#endif |
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} |
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||
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// Use hardware population count instruction if available. |
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if (has_hardware_popc()) { |
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if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
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} |
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} else if (UsePopCountInstruction) { |
137 |
warning("POPC instruction is not available on this CPU"); |
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138 |
FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
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139 |
} |
|
140 |
||
141 |
// T4 and newer Sparc cpus have new compare and branch instruction. |
|
142 |
if (has_cbcond()) { |
|
143 |
if (FLAG_IS_DEFAULT(UseCBCond)) { |
|
144 |
FLAG_SET_DEFAULT(UseCBCond, true); |
|
145 |
} |
|
146 |
} else if (UseCBCond) { |
|
147 |
warning("CBCOND instruction is not available on this CPU"); |
|
148 |
FLAG_SET_DEFAULT(UseCBCond, false); |
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} |
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10501 | 151 |
assert(BlockZeroingLowLimit > 0, "invalid value"); |
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if (has_block_zeroing() && cache_line_size > 0) { |
10501 | 153 |
if (FLAG_IS_DEFAULT(UseBlockZeroing)) { |
154 |
FLAG_SET_DEFAULT(UseBlockZeroing, true); |
|
155 |
} |
|
156 |
} else if (UseBlockZeroing) { |
|
157 |
warning("BIS zeroing instructions are not available on this CPU"); |
|
158 |
FLAG_SET_DEFAULT(UseBlockZeroing, false); |
|
159 |
} |
|
160 |
||
10512 | 161 |
assert(BlockCopyLowLimit > 0, "invalid value"); |
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162 |
if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache |
10512 | 163 |
if (FLAG_IS_DEFAULT(UseBlockCopy)) { |
164 |
FLAG_SET_DEFAULT(UseBlockCopy, true); |
|
165 |
} |
|
166 |
} else if (UseBlockCopy) { |
|
167 |
warning("BIS instructions are not available or expensive on this CPU"); |
|
168 |
FLAG_SET_DEFAULT(UseBlockCopy, false); |
|
169 |
} |
|
170 |
||
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#ifdef COMPILER2 |
10252 | 172 |
// T4 and newer Sparc cpus have fast RDPC. |
173 |
if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { |
|
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FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
10252 | 175 |
} |
176 |
||
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// Currently not supported anywhere. |
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FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
10264 | 179 |
|
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MaxVectorSize = 8; |
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181 |
|
10264 | 182 |
assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
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#endif |
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|
10264 | 185 |
assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
186 |
assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
|
187 |
||
1 | 188 |
char buf[512]; |
31515 | 189 |
jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
10252 | 190 |
(has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), |
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191 |
(has_hardware_popc() ? ", popc" : ""), |
10252 | 192 |
(has_vis1() ? ", vis1" : ""), |
193 |
(has_vis2() ? ", vis2" : ""), |
|
194 |
(has_vis3() ? ", vis3" : ""), |
|
195 |
(has_blk_init() ? ", blk_init" : ""), |
|
196 |
(has_cbcond() ? ", cbcond" : ""), |
|
22505 | 197 |
(has_aes() ? ", aes" : ""), |
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(has_sha1() ? ", sha1" : ""), |
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(has_sha256() ? ", sha256" : ""), |
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200 |
(has_sha512() ? ", sha512" : ""), |
31515 | 201 |
(has_crc32c() ? ", crc32c" : ""), |
10252 | 202 |
(is_ultra3() ? ", ultra3" : ""), |
203 |
(is_sun4v() ? ", sun4v" : ""), |
|
204 |
(is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), |
|
205 |
(is_sparc64() ? ", sparc64" : ""), |
|
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(!has_hardware_mul32() ? ", no-mul32" : ""), |
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207 |
(!has_hardware_div32() ? ", no-div32" : ""), |
1 | 208 |
(!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
209 |
||
210 |
// buf is started with ", " or is empty |
|
35148 | 211 |
_features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf); |
1 | 212 |
|
10027 | 213 |
// UseVIS is set to the smallest of what hardware supports and what |
214 |
// the command line requires. I.e., you cannot set UseVIS to 3 on |
|
215 |
// older UltraSparc which do not support it. |
|
216 |
if (UseVIS > 3) UseVIS=3; |
|
217 |
if (UseVIS < 0) UseVIS=0; |
|
218 |
if (!has_vis3()) // Drop to 2 if no VIS3 support |
|
219 |
UseVIS = MIN2((intx)2,UseVIS); |
|
220 |
if (!has_vis2()) // Drop to 1 if no VIS2 support |
|
221 |
UseVIS = MIN2((intx)1,UseVIS); |
|
222 |
if (!has_vis1()) // Drop to 0 if no VIS1 support |
|
223 |
UseVIS = 0; |
|
224 |
||
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225 |
// SPARC T4 and above should have support for AES instructions |
22505 | 226 |
if (has_aes()) { |
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227 |
if (FLAG_IS_DEFAULT(UseAES)) { |
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FLAG_SET_DEFAULT(UseAES, true); |
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229 |
} |
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230 |
if (!UseAES) { |
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231 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
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232 |
warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); |
22505 | 233 |
} |
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234 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
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235 |
} else { |
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236 |
// The AES intrinsic stubs require AES instruction support (of course) |
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|
237 |
// but also require VIS3 mode or higher for instructions it use. |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
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parents:
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diff
changeset
|
238 |
if (UseVIS > 2) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
239 |
if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
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diff
changeset
|
240 |
FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
241 |
} |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
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diff
changeset
|
242 |
} else { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
243 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
244 |
warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
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diff
changeset
|
245 |
} |
22505 | 246 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
247 |
} |
|
248 |
} |
|
249 |
} else if (UseAES || UseAESIntrinsics) { |
|
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
250 |
if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
251 |
warning("AES instructions are not available on this CPU"); |
22505 | 252 |
FLAG_SET_DEFAULT(UseAES, false); |
253 |
} |
|
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
254 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34174
diff
changeset
|
255 |
warning("AES intrinsics are not available on this CPU"); |
22505 | 256 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
257 |
} |
|
258 |
} |
|
259 |
||
35154 | 260 |
if (UseAESCTRIntrinsics) { |
261 |
warning("AES/CTR intrinsics are not available on this CPU"); |
|
262 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); |
|
263 |
} |
|
264 |
||
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
265 |
// GHASH/GCM intrinsics |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
266 |
if (has_vis3() && (UseVIS > 2)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
267 |
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
268 |
UseGHASHIntrinsics = true; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
269 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
270 |
} else if (UseGHASHIntrinsics) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
271 |
if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) |
31774 | 272 |
warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); |
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
273 |
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
274 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
30217
diff
changeset
|
275 |
|
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
276 |
// SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
277 |
if (has_sha1() || has_sha256() || has_sha512()) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
278 |
if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
279 |
if (FLAG_IS_DEFAULT(UseSHA)) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
280 |
FLAG_SET_DEFAULT(UseSHA, true); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
281 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
282 |
} else { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
283 |
if (UseSHA) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
284 |
warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
285 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
286 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
287 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
288 |
} else if (UseSHA) { |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
289 |
warning("SHA instructions are not available on this CPU"); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
290 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
291 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
292 |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
293 |
if (UseSHA && has_sha1()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
294 |
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
295 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
296 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
297 |
} else if (UseSHA1Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
298 |
warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
299 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
300 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
301 |
|
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
302 |
if (UseSHA && has_sha256()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
303 |
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
304 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
305 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
306 |
} else if (UseSHA256Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
307 |
warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
308 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
309 |
} |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
310 |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
311 |
if (UseSHA && has_sha512()) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
312 |
if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
313 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
314 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
315 |
} else if (UseSHA512Intrinsics) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
316 |
warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
317 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
318 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
319 |
|
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
320 |
if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31515
diff
changeset
|
321 |
FLAG_SET_DEFAULT(UseSHA, false); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
322 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
323 |
|
31515 | 324 |
// SPARC T4 and above should have support for CRC32C instruction |
325 |
if (has_crc32c()) { |
|
326 |
if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions |
|
327 |
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { |
|
328 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); |
|
329 |
} |
|
330 |
} else { |
|
331 |
if (UseCRC32CIntrinsics) { |
|
332 |
warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
|
333 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
334 |
} |
|
335 |
} |
|
336 |
} else if (UseCRC32CIntrinsics) { |
|
337 |
warning("CRC32C instruction is not available on this CPU"); |
|
338 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
339 |
} |
|
340 |
||
32581 | 341 |
if (UseVIS > 2) { |
342 |
if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { |
|
343 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); |
|
344 |
} |
|
345 |
} else if (UseAdler32Intrinsics) { |
|
346 |
warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); |
|
347 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); |
|
348 |
} |
|
349 |
||
34205 | 350 |
if (UseVIS > 2) { |
351 |
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
|
352 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); |
|
353 |
} |
|
354 |
} else if (UseCRC32Intrinsics) { |
|
355 |
warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled"); |
|
356 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
|
357 |
} |
|
358 |
||
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
359 |
if (UseVectorizedMismatchIntrinsic) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
360 |
warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
361 |
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
362 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34205
diff
changeset
|
363 |
|
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
364 |
if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
365 |
(cache_line_size > ContendedPaddingWidth)) |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
366 |
ContendedPaddingWidth = cache_line_size; |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14631
diff
changeset
|
367 |
|
30209
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
368 |
// This machine does not allow unaligned memory accesses |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
369 |
if (UseUnalignedAccesses) { |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
370 |
if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
371 |
warning("Unaligned memory access is not available on this CPU"); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
372 |
FLAG_SET_DEFAULT(UseUnalignedAccesses, false); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
373 |
} |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
26579
diff
changeset
|
374 |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
375 |
if (log_is_enabled(Info, os, cpu)) { |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
376 |
ResourceMark rm; |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
377 |
outputStream* log = Log(os, cpu)::info_stream(); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
378 |
log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
379 |
log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
380 |
log->print("Allocation"); |
1 | 381 |
if (AllocatePrefetchStyle <= 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
382 |
log->print(": no prefetching"); |
1 | 383 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
384 |
log->print(" prefetching: "); |
10267 | 385 |
if (AllocatePrefetchInstr == 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
386 |
log->print("PREFETCH"); |
10267 | 387 |
} else if (AllocatePrefetchInstr == 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
388 |
log->print("BIS"); |
10267 | 389 |
} |
1 | 390 |
if (AllocatePrefetchLines > 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
391 |
log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
1 | 392 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
393 |
log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
1 | 394 |
} |
395 |
} |
|
396 |
if (PrefetchCopyIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
397 |
log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
1 | 398 |
} |
399 |
if (PrefetchScanIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36346
diff
changeset
|
400 |
log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
1 | 401 |
} |
402 |
if (PrefetchFieldsAhead > 0) { |
|
37430
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403 |
log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
1 | 404 |
} |
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405 |
if (ContendedPaddingWidth > 0) { |
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406 |
log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
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407 |
} |
1 | 408 |
} |
409 |
} |
|
410 |
||
411 |
void VM_Version::print_features() { |
|
35148 | 412 |
tty->print_cr("Version:%s", _features); |
1 | 413 |
} |
414 |
||
415 |
int VM_Version::determine_features() { |
|
416 |
if (UseV8InstrsOnly) { |
|
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417 |
log_info(os, cpu)("Version is Forced-V8"); |
1 | 418 |
return generic_v8_m; |
419 |
} |
|
420 |
||
421 |
int features = platform_features(unknown_m); // platform_features() is os_arch specific |
|
422 |
||
423 |
if (features == unknown_m) { |
|
424 |
features = generic_v9_m; |
|
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425 |
log_info(os)("Cannot recognize SPARC version. Default to V9"); |
1 | 426 |
} |
427 |
||
7704 | 428 |
assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
429 |
if (UseNiagaraInstrs) { // Force code generation for Niagara |
|
430 |
if (is_T_family(features)) { |
|
1 | 431 |
// Happy to accomodate... |
432 |
} else { |
|
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433 |
log_info(os, cpu)("Version is Forced-Niagara"); |
7704 | 434 |
features |= T_family_m; |
1 | 435 |
} |
436 |
} else { |
|
7704 | 437 |
if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
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438 |
log_info(os, cpu)("Version is Forced-Not-Niagara"); |
7704 | 439 |
features &= ~(T_family_m | T1_model_m); |
1 | 440 |
} else { |
441 |
// Happy to accomodate... |
|
442 |
} |
|
443 |
} |
|
444 |
||
445 |
return features; |
|
446 |
} |
|
447 |
||
35148 | 448 |
static uint64_t saved_features = 0; |
1 | 449 |
|
450 |
void VM_Version::allow_all() { |
|
451 |
saved_features = _features; |
|
452 |
_features = all_features_m; |
|
453 |
} |
|
454 |
||
455 |
void VM_Version::revert() { |
|
456 |
_features = saved_features; |
|
457 |
} |
|
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|
458 |
|
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|
459 |
unsigned int VM_Version::calc_parallel_worker_threads() { |
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|
460 |
unsigned int result; |
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|
461 |
if (is_M_series()) { |
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|
462 |
// for now, use same gc thread calculation for M-series as for niagara-plus |
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|
463 |
// in future, we may want to tweak parameters for nof_parallel_worker_thread |
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|
464 |
result = nof_parallel_worker_threads(5, 16, 8); |
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|
465 |
} else if (is_niagara_plus()) { |
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|
466 |
result = nof_parallel_worker_threads(5, 16, 8); |
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|
467 |
} else { |
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|
468 |
result = nof_parallel_worker_threads(5, 8, 8); |
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|
469 |
} |
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|
470 |
return result; |
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|
471 |
} |
36346 | 472 |
|
473 |
||
474 |
int VM_Version::parse_features(const char* implementation) { |
|
475 |
int features = unknown_m; |
|
476 |
// Convert to UPPER case before compare. |
|
477 |
char* impl = os::strdup_check_oom(implementation); |
|
478 |
||
479 |
for (int i = 0; impl[i] != 0; i++) |
|
480 |
impl[i] = (char)toupper((uint)impl[i]); |
|
481 |
||
482 |
if (strstr(impl, "SPARC64") != NULL) { |
|
483 |
features |= sparc64_family_m; |
|
484 |
} else if (strstr(impl, "SPARC-M") != NULL) { |
|
485 |
// M-series SPARC is based on T-series. |
|
486 |
features |= (M_family_m | T_family_m); |
|
487 |
} else if (strstr(impl, "SPARC-T") != NULL) { |
|
488 |
features |= T_family_m; |
|
489 |
if (strstr(impl, "SPARC-T1") != NULL) { |
|
490 |
features |= T1_model_m; |
|
491 |
} |
|
492 |
} else { |
|
493 |
if (strstr(impl, "SPARC") == NULL) { |
|
494 |
#ifndef PRODUCT |
|
495 |
// kstat on Solaris 8 virtual machines (branded zones) |
|
496 |
// returns "(unsupported)" implementation. Solaris 8 is not |
|
497 |
// supported anymore, but include this check to be on the |
|
498 |
// safe side. |
|
499 |
warning("Can't parse CPU implementation = '%s', assume generic SPARC", impl); |
|
500 |
#endif |
|
501 |
} |
|
502 |
} |
|
503 |
os::free((void*)impl); |
|
504 |
return features; |
|
505 |
} |