author | chegar |
Thu, 17 Oct 2019 20:54:25 +0100 | |
branch | datagramsocketimpl-branch |
changeset 58679 | 9c3209ff7550 |
parent 58678 | 9cf78a70fa4f |
parent 58421 | 6fc57e391539 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
52992
diff
changeset
|
2 |
* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
1 | 3 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 |
* |
|
5 |
* This code is free software; you can redistribute it and/or modify it |
|
6 |
* under the terms of the GNU General Public License version 2 only, as |
|
7 |
* published by the Free Software Foundation. |
|
8 |
* |
|
9 |
* This code is distributed in the hope that it will be useful, but WITHOUT |
|
10 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
11 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
|
12 |
* version 2 for more details (a copy is included in the LICENSE file that |
|
13 |
* accompanied this code). |
|
14 |
* |
|
15 |
* You should have received a copy of the GNU General Public License version |
|
16 |
* 2 along with this work; if not, write to the Free Software Foundation, |
|
17 |
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
|
18 |
* |
|
5547
f4b087cbb361
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
5416
diff
changeset
|
19 |
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
f4b087cbb361
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
5416
diff
changeset
|
20 |
* or visit www.oracle.com if you need additional information or have any |
f4b087cbb361
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
5416
diff
changeset
|
21 |
* questions. |
1 | 22 |
* |
23 |
*/ |
|
24 |
||
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
52992
diff
changeset
|
25 |
#ifndef CPU_X86_ASSEMBLER_X86_HPP |
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
52992
diff
changeset
|
26 |
#define CPU_X86_ASSEMBLER_X86_HPP |
7397 | 27 |
|
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
28 |
#include "asm/register.hpp" |
26576
a9429d24d429
8050147: StoreLoad barrier interferes with stack usages
shade
parents:
26434
diff
changeset
|
29 |
#include "vm_version_x86.hpp" |
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
30 |
|
1 | 31 |
class BiasedLockingCounters; |
32 |
||
33 |
// Contains all the definitions needed for x86 assembly code generation. |
|
34 |
||
35 |
// Calling convention |
|
49364
601146c66cad
8173070: Remove ValueObj class for allocation subclassing for runtime code
coleenp
parents:
48309
diff
changeset
|
36 |
class Argument { |
1 | 37 |
public: |
38 |
enum { |
|
39 |
#ifdef _LP64 |
|
40 |
#ifdef _WIN64 |
|
41 |
n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
|
42 |
n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
|
43 |
#else |
|
44 |
n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
|
45 |
n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
|
46 |
#endif // _WIN64 |
|
47 |
n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
|
48 |
n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
|
49 |
#else |
|
50 |
n_register_parameters = 0 // 0 registers used to pass arguments |
|
51 |
#endif // _LP64 |
|
52 |
}; |
|
53 |
}; |
|
54 |
||
55 |
||
56 |
#ifdef _LP64 |
|
57 |
// Symbolically name the register arguments used by the c calling convention. |
|
58 |
// Windows is different from linux/solaris. So much for standards... |
|
59 |
||
60 |
#ifdef _WIN64 |
|
61 |
||
62 |
REGISTER_DECLARATION(Register, c_rarg0, rcx); |
|
63 |
REGISTER_DECLARATION(Register, c_rarg1, rdx); |
|
64 |
REGISTER_DECLARATION(Register, c_rarg2, r8); |
|
65 |
REGISTER_DECLARATION(Register, c_rarg3, r9); |
|
66 |
||
1066 | 67 |
REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
68 |
REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
|
69 |
REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
|
70 |
REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
|
1 | 71 |
|
72 |
#else |
|
73 |
||
74 |
REGISTER_DECLARATION(Register, c_rarg0, rdi); |
|
75 |
REGISTER_DECLARATION(Register, c_rarg1, rsi); |
|
76 |
REGISTER_DECLARATION(Register, c_rarg2, rdx); |
|
77 |
REGISTER_DECLARATION(Register, c_rarg3, rcx); |
|
78 |
REGISTER_DECLARATION(Register, c_rarg4, r8); |
|
79 |
REGISTER_DECLARATION(Register, c_rarg5, r9); |
|
80 |
||
1066 | 81 |
REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
82 |
REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
|
83 |
REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
|
84 |
REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
|
85 |
REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); |
|
86 |
REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); |
|
87 |
REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); |
|
88 |
REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); |
|
1 | 89 |
|
90 |
#endif // _WIN64 |
|
91 |
||
92 |
// Symbolically name the register arguments used by the Java calling convention. |
|
93 |
// We have control over the convention for java so we can do what we please. |
|
94 |
// What pleases us is to offset the java calling convention so that when |
|
95 |
// we call a suitable jni method the arguments are lined up and we don't |
|
96 |
// have to do little shuffling. A suitable jni method is non-static and a |
|
97 |
// small number of arguments (two fewer args on windows) |
|
98 |
// |
|
99 |
// |-------------------------------------------------------| |
|
100 |
// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
|
101 |
// |-------------------------------------------------------| |
|
102 |
// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
|
103 |
// | rdi rsi rdx rcx r8 r9 | solaris/linux |
|
104 |
// |-------------------------------------------------------| |
|
105 |
// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
|
106 |
// |-------------------------------------------------------| |
|
107 |
||
108 |
REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
|
109 |
REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
|
110 |
REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
|
111 |
// Windows runs out of register args here |
|
112 |
#ifdef _WIN64 |
|
113 |
REGISTER_DECLARATION(Register, j_rarg3, rdi); |
|
114 |
REGISTER_DECLARATION(Register, j_rarg4, rsi); |
|
115 |
#else |
|
116 |
REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
|
117 |
REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
|
118 |
#endif /* _WIN64 */ |
|
119 |
REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
|
120 |
||
1066 | 121 |
REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
122 |
REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); |
|
123 |
REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); |
|
124 |
REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); |
|
125 |
REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); |
|
126 |
REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); |
|
127 |
REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); |
|
128 |
REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); |
|
1 | 129 |
|
130 |
REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
|
131 |
REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
|
132 |
||
1066 | 133 |
REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
1 | 134 |
REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
135 |
||
1066 | 136 |
#else |
137 |
// rscratch1 will apear in 32bit code that is dead but of course must compile |
|
138 |
// Using noreg ensures if the dead code is incorrectly live and executed it |
|
139 |
// will cause an assertion failure |
|
140 |
#define rscratch1 noreg |
|
7427 | 141 |
#define rscratch2 noreg |
1066 | 142 |
|
1 | 143 |
#endif // _LP64 |
144 |
||
30305
b92a97e1e9cb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
30211
diff
changeset
|
145 |
// JSR 292 |
b92a97e1e9cb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
30211
diff
changeset
|
146 |
// On x86, the SP does not have to be saved when invoking method handle intrinsics |
b92a97e1e9cb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
30211
diff
changeset
|
147 |
// or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg. |
b92a97e1e9cb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
zmajo
parents:
30211
diff
changeset
|
148 |
REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg); |
5687 | 149 |
|
1 | 150 |
// Address is an abstraction used to represent a memory location |
151 |
// using any of the amd64 addressing modes with one object. |
|
152 |
// |
|
153 |
// Note: A register location is represented via a Register, not |
|
154 |
// via an address for efficiency & simplicity reasons. |
|
155 |
||
156 |
class ArrayAddress; |
|
157 |
||
49364
601146c66cad
8173070: Remove ValueObj class for allocation subclassing for runtime code
coleenp
parents:
48309
diff
changeset
|
158 |
class Address { |
1 | 159 |
public: |
160 |
enum ScaleFactor { |
|
161 |
no_scale = -1, |
|
162 |
times_1 = 0, |
|
163 |
times_2 = 1, |
|
164 |
times_4 = 2, |
|
1066 | 165 |
times_8 = 3, |
166 |
times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) |
|
1 | 167 |
}; |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
168 |
static ScaleFactor times(int size) { |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
169 |
assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
170 |
if (size == 8) return times_8; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
171 |
if (size == 4) return times_4; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
172 |
if (size == 2) return times_2; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
173 |
return times_1; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
174 |
} |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
175 |
static int scale_size(ScaleFactor scale) { |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
176 |
assert(scale != no_scale, ""); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
177 |
assert(((1 << (int)times_1) == 1 && |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
178 |
(1 << (int)times_2) == 2 && |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
179 |
(1 << (int)times_4) == 4 && |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
180 |
(1 << (int)times_8) == 8), ""); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
181 |
return (1 << (int)scale); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
182 |
} |
1 | 183 |
|
184 |
private: |
|
185 |
Register _base; |
|
186 |
Register _index; |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
187 |
XMMRegister _xmmindex; |
1 | 188 |
ScaleFactor _scale; |
189 |
int _disp; |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
190 |
bool _isxmmindex; |
1 | 191 |
RelocationHolder _rspec; |
192 |
||
1066 | 193 |
// Easily misused constructors make them private |
194 |
// %%% can we make these go away? |
|
195 |
NOT_LP64(Address(address loc, RelocationHolder spec);) |
|
196 |
Address(int disp, address loc, relocInfo::relocType rtype); |
|
197 |
Address(int disp, address loc, RelocationHolder spec); |
|
1 | 198 |
|
199 |
public: |
|
1066 | 200 |
|
201 |
int disp() { return _disp; } |
|
1 | 202 |
// creation |
203 |
Address() |
|
204 |
: _base(noreg), |
|
205 |
_index(noreg), |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
206 |
_xmmindex(xnoreg), |
1 | 207 |
_scale(no_scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
208 |
_disp(0), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
209 |
_isxmmindex(false){ |
1 | 210 |
} |
211 |
||
212 |
// No default displacement otherwise Register can be implicitly |
|
213 |
// converted to 0(Register) which is quite a different animal. |
|
214 |
||
215 |
Address(Register base, int disp) |
|
216 |
: _base(base), |
|
217 |
_index(noreg), |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
218 |
_xmmindex(xnoreg), |
1 | 219 |
_scale(no_scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
220 |
_disp(disp), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
221 |
_isxmmindex(false){ |
1 | 222 |
} |
223 |
||
224 |
Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
|
225 |
: _base (base), |
|
226 |
_index(index), |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
227 |
_xmmindex(xnoreg), |
1 | 228 |
_scale(scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
229 |
_disp (disp), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
230 |
_isxmmindex(false) { |
1 | 231 |
assert(!index->is_valid() == (scale == Address::no_scale), |
232 |
"inconsistent address"); |
|
233 |
} |
|
234 |
||
2332
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
235 |
Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
236 |
: _base (base), |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
237 |
_index(index.register_or_noreg()), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
238 |
_xmmindex(xnoreg), |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
239 |
_scale(scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
240 |
_disp (disp + (index.constant_or_zero() * scale_size(scale))), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
241 |
_isxmmindex(false){ |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
242 |
if (!index.is_register()) scale = Address::no_scale; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
243 |
assert(!_index->is_valid() == (scale == Address::no_scale), |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
244 |
"inconsistent address"); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
245 |
} |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
246 |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
247 |
Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0) |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
248 |
: _base (base), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
249 |
_index(noreg), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
250 |
_xmmindex(index), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
251 |
_scale(scale), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
252 |
_disp(disp), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
253 |
_isxmmindex(true) { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
254 |
assert(!index->is_valid() == (scale == Address::no_scale), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
255 |
"inconsistent address"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
256 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
257 |
|
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
258 |
Address plus_disp(int disp) const { |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
259 |
Address a = (*this); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
260 |
a._disp += disp; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
261 |
return a; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
262 |
} |
9630
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
263 |
Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
264 |
Address a = (*this); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
265 |
a._disp += disp.constant_or_zero() * scale_size(scale); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
266 |
if (disp.is_register()) { |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
267 |
assert(!a.index()->is_valid(), "competing indexes"); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
268 |
a._index = disp.as_register(); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
269 |
a._scale = scale; |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
270 |
} |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
271 |
return a; |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
272 |
} |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
273 |
bool is_same_address(Address a) const { |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
274 |
// disregard _rspec |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
275 |
return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
276 |
} |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
277 |
|
1 | 278 |
// The following two overloads are used in connection with the |
279 |
// ByteSize type (see sizes.hpp). They simplify the use of |
|
280 |
// ByteSize'd arguments in assembly code. Note that their equivalent |
|
281 |
// for the optimized build are the member functions with int disp |
|
282 |
// argument since ByteSize is mapped to an int type in that case. |
|
283 |
// |
|
284 |
// Note: DO NOT introduce similar overloaded functions for WordSize |
|
285 |
// arguments as in the optimized mode, both ByteSize and WordSize |
|
286 |
// are mapped to the same type and thus the compiler cannot make a |
|
287 |
// distinction anymore (=> compiler errors). |
|
288 |
||
289 |
#ifdef ASSERT |
|
290 |
Address(Register base, ByteSize disp) |
|
291 |
: _base(base), |
|
292 |
_index(noreg), |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
293 |
_xmmindex(xnoreg), |
1 | 294 |
_scale(no_scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
295 |
_disp(in_bytes(disp)), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
296 |
_isxmmindex(false){ |
1 | 297 |
} |
298 |
||
299 |
Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
|
300 |
: _base(base), |
|
301 |
_index(index), |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
302 |
_xmmindex(xnoreg), |
1 | 303 |
_scale(scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
304 |
_disp(in_bytes(disp)), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
305 |
_isxmmindex(false){ |
1 | 306 |
assert(!index->is_valid() == (scale == Address::no_scale), |
307 |
"inconsistent address"); |
|
308 |
} |
|
2332
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
309 |
Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
310 |
: _base (base), |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
311 |
_index(index.register_or_noreg()), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
312 |
_xmmindex(xnoreg), |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
313 |
_scale(scale), |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
314 |
_disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))), |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
315 |
_isxmmindex(false) { |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
316 |
if (!index.is_register()) scale = Address::no_scale; |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
317 |
assert(!_index->is_valid() == (scale == Address::no_scale), |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
318 |
"inconsistent address"); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
319 |
} |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
320 |
|
1 | 321 |
#endif // ASSERT |
322 |
||
323 |
// accessors |
|
1374
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
324 |
bool uses(Register reg) const { return _base == reg || _index == reg; } |
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
325 |
Register base() const { return _base; } |
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
326 |
Register index() const { return _index; } |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
327 |
XMMRegister xmmindex() const { return _xmmindex; } |
1374
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
328 |
ScaleFactor scale() const { return _scale; } |
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
329 |
int disp() const { return _disp; } |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
330 |
bool isxmmindex() const { return _isxmmindex; } |
1 | 331 |
|
332 |
// Convert the raw encoding form into the form expected by the constructor for |
|
333 |
// Address. An index of 4 (rsp) corresponds to having no index, so convert |
|
334 |
// that to noreg for the Address constructor. |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13485
diff
changeset
|
335 |
static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
1 | 336 |
|
337 |
static Address make_array(ArrayAddress); |
|
338 |
||
339 |
private: |
|
340 |
bool base_needs_rex() const { |
|
341 |
return _base != noreg && _base->encoding() >= 8; |
|
342 |
} |
|
343 |
||
344 |
bool index_needs_rex() const { |
|
345 |
return _index != noreg &&_index->encoding() >= 8; |
|
346 |
} |
|
347 |
||
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
348 |
bool xmmindex_needs_rex() const { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
349 |
return _xmmindex != xnoreg && _xmmindex->encoding() >= 8; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
350 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
351 |
|
1 | 352 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
353 |
||
354 |
friend class Assembler; |
|
355 |
friend class MacroAssembler; |
|
356 |
friend class LIR_Assembler; // base/index/scale/disp |
|
357 |
}; |
|
358 |
||
359 |
// |
|
360 |
// AddressLiteral has been split out from Address because operands of this type |
|
361 |
// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
|
362 |
// the few instructions that need to deal with address literals are unique and the |
|
363 |
// MacroAssembler does not have to implement every instruction in the Assembler |
|
364 |
// in order to search for address literals that may need special handling depending |
|
365 |
// on the instruction and the platform. As small step on the way to merging i486/amd64 |
|
366 |
// directories. |
|
367 |
// |
|
49364
601146c66cad
8173070: Remove ValueObj class for allocation subclassing for runtime code
coleenp
parents:
48309
diff
changeset
|
368 |
class AddressLiteral { |
1 | 369 |
friend class ArrayAddress; |
370 |
RelocationHolder _rspec; |
|
371 |
// Typically we use AddressLiterals we want to use their rval |
|
372 |
// However in some situations we want the lval (effect address) of the item. |
|
373 |
// We provide a special factory for making those lvals. |
|
374 |
bool _is_lval; |
|
375 |
||
376 |
// If the target is far we'll need to load the ea of this to |
|
377 |
// a register to reach it. Otherwise if near we can do rip |
|
378 |
// relative addressing. |
|
379 |
||
380 |
address _target; |
|
381 |
||
382 |
protected: |
|
383 |
// creation |
|
384 |
AddressLiteral() |
|
385 |
: _is_lval(false), |
|
386 |
_target(NULL) |
|
387 |
{} |
|
388 |
||
389 |
public: |
|
390 |
||
391 |
||
392 |
AddressLiteral(address target, relocInfo::relocType rtype); |
|
393 |
||
394 |
AddressLiteral(address target, RelocationHolder const& rspec) |
|
395 |
: _rspec(rspec), |
|
396 |
_is_lval(false), |
|
397 |
_target(target) |
|
398 |
{} |
|
399 |
||
400 |
AddressLiteral addr() { |
|
401 |
AddressLiteral ret = *this; |
|
402 |
ret._is_lval = true; |
|
403 |
return ret; |
|
404 |
} |
|
405 |
||
406 |
||
407 |
private: |
|
408 |
||
409 |
address target() { return _target; } |
|
410 |
bool is_lval() { return _is_lval; } |
|
411 |
||
412 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
|
413 |
const RelocationHolder& rspec() const { return _rspec; } |
|
414 |
||
415 |
friend class Assembler; |
|
416 |
friend class MacroAssembler; |
|
417 |
friend class Address; |
|
418 |
friend class LIR_Assembler; |
|
419 |
}; |
|
420 |
||
421 |
// Convience classes |
|
422 |
class RuntimeAddress: public AddressLiteral { |
|
423 |
||
424 |
public: |
|
425 |
||
426 |
RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
|
427 |
||
428 |
}; |
|
429 |
||
430 |
class ExternalAddress: public AddressLiteral { |
|
9111
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
431 |
private: |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
432 |
static relocInfo::relocType reloc_for_target(address target) { |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
433 |
// Sometimes ExternalAddress is used for values which aren't |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
434 |
// exactly addresses, like the card table base. |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
435 |
// external_word_type can't be used for values in the first page |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
436 |
// so just skip the reloc in that case. |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
437 |
return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
438 |
} |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
439 |
|
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
440 |
public: |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
441 |
|
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
442 |
ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
1 | 443 |
|
444 |
}; |
|
445 |
||
446 |
class InternalAddress: public AddressLiteral { |
|
447 |
||
448 |
public: |
|
449 |
||
450 |
InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
|
451 |
||
452 |
}; |
|
453 |
||
454 |
// x86 can do array addressing as a single operation since disp can be an absolute |
|
455 |
// address amd64 can't. We create a class that expresses the concept but does extra |
|
456 |
// magic on amd64 to get the final result |
|
457 |
||
49364
601146c66cad
8173070: Remove ValueObj class for allocation subclassing for runtime code
coleenp
parents:
48309
diff
changeset
|
458 |
class ArrayAddress { |
1 | 459 |
private: |
460 |
||
461 |
AddressLiteral _base; |
|
462 |
Address _index; |
|
463 |
||
464 |
public: |
|
465 |
||
466 |
ArrayAddress() {}; |
|
467 |
ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
|
468 |
AddressLiteral base() { return _base; } |
|
469 |
Address index() { return _index; } |
|
470 |
||
471 |
}; |
|
472 |
||
34162 | 473 |
class InstructionAttr; |
474 |
||
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
475 |
// 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
476 |
// See fxsave and xsave(EVEX enabled) documentation for layout |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
477 |
const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize); |
1 | 478 |
|
479 |
// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction |
|
480 |
// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write |
|
481 |
// is what you get. The Assembler is generating code into a CodeBuffer. |
|
482 |
||
483 |
class Assembler : public AbstractAssembler { |
|
484 |
friend class AbstractAssembler; // for the non-virtual hack |
|
485 |
friend class LIR_Assembler; // as_Address() |
|
1066 | 486 |
friend class StubGenerator; |
1 | 487 |
|
488 |
public: |
|
489 |
enum Condition { // The x86 condition codes used for conditional jumps/moves. |
|
490 |
zero = 0x4, |
|
491 |
notZero = 0x5, |
|
492 |
equal = 0x4, |
|
493 |
notEqual = 0x5, |
|
494 |
less = 0xc, |
|
495 |
lessEqual = 0xe, |
|
496 |
greater = 0xf, |
|
497 |
greaterEqual = 0xd, |
|
498 |
below = 0x2, |
|
499 |
belowEqual = 0x6, |
|
500 |
above = 0x7, |
|
501 |
aboveEqual = 0x3, |
|
502 |
overflow = 0x0, |
|
503 |
noOverflow = 0x1, |
|
504 |
carrySet = 0x2, |
|
505 |
carryClear = 0x3, |
|
506 |
negative = 0x8, |
|
507 |
positive = 0x9, |
|
508 |
parity = 0xa, |
|
509 |
noParity = 0xb |
|
510 |
}; |
|
511 |
||
512 |
enum Prefix { |
|
513 |
// segment overrides |
|
514 |
CS_segment = 0x2e, |
|
515 |
SS_segment = 0x36, |
|
516 |
DS_segment = 0x3e, |
|
517 |
ES_segment = 0x26, |
|
518 |
FS_segment = 0x64, |
|
519 |
GS_segment = 0x65, |
|
520 |
||
521 |
REX = 0x40, |
|
522 |
||
523 |
REX_B = 0x41, |
|
524 |
REX_X = 0x42, |
|
525 |
REX_XB = 0x43, |
|
526 |
REX_R = 0x44, |
|
527 |
REX_RB = 0x45, |
|
528 |
REX_RX = 0x46, |
|
529 |
REX_RXB = 0x47, |
|
530 |
||
531 |
REX_W = 0x48, |
|
532 |
||
533 |
REX_WB = 0x49, |
|
534 |
REX_WX = 0x4A, |
|
535 |
REX_WXB = 0x4B, |
|
536 |
REX_WR = 0x4C, |
|
537 |
REX_WRB = 0x4D, |
|
538 |
REX_WRX = 0x4E, |
|
11427 | 539 |
REX_WRXB = 0x4F, |
540 |
||
541 |
VEX_3bytes = 0xC4, |
|
30624 | 542 |
VEX_2bytes = 0xC5, |
33066 | 543 |
EVEX_4bytes = 0x62, |
544 |
Prefix_EMPTY = 0x0 |
|
11427 | 545 |
}; |
546 |
||
547 |
enum VexPrefix { |
|
548 |
VEX_B = 0x20, |
|
549 |
VEX_X = 0x40, |
|
550 |
VEX_R = 0x80, |
|
551 |
VEX_W = 0x80 |
|
552 |
}; |
|
553 |
||
30624 | 554 |
enum ExexPrefix { |
555 |
EVEX_F = 0x04, |
|
556 |
EVEX_V = 0x08, |
|
557 |
EVEX_Rb = 0x10, |
|
558 |
EVEX_X = 0x40, |
|
559 |
EVEX_Z = 0x80 |
|
560 |
}; |
|
561 |
||
11427 | 562 |
enum VexSimdPrefix { |
563 |
VEX_SIMD_NONE = 0x0, |
|
564 |
VEX_SIMD_66 = 0x1, |
|
565 |
VEX_SIMD_F3 = 0x2, |
|
566 |
VEX_SIMD_F2 = 0x3 |
|
567 |
}; |
|
568 |
||
569 |
enum VexOpcode { |
|
570 |
VEX_OPCODE_NONE = 0x0, |
|
571 |
VEX_OPCODE_0F = 0x1, |
|
572 |
VEX_OPCODE_0F_38 = 0x2, |
|
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33089
diff
changeset
|
573 |
VEX_OPCODE_0F_3A = 0x3, |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33089
diff
changeset
|
574 |
VEX_OPCODE_MASK = 0x1F |
1 | 575 |
}; |
576 |
||
30624 | 577 |
enum AvxVectorLen { |
578 |
AVX_128bit = 0x0, |
|
579 |
AVX_256bit = 0x1, |
|
580 |
AVX_512bit = 0x2, |
|
581 |
AVX_NoVec = 0x4 |
|
582 |
}; |
|
583 |
||
584 |
enum EvexTupleType { |
|
585 |
EVEX_FV = 0, |
|
586 |
EVEX_HV = 4, |
|
587 |
EVEX_FVM = 6, |
|
588 |
EVEX_T1S = 7, |
|
589 |
EVEX_T1F = 11, |
|
590 |
EVEX_T2 = 13, |
|
591 |
EVEX_T4 = 15, |
|
592 |
EVEX_T8 = 17, |
|
593 |
EVEX_HVM = 18, |
|
594 |
EVEX_QVM = 19, |
|
595 |
EVEX_OVM = 20, |
|
596 |
EVEX_M128 = 21, |
|
597 |
EVEX_DUP = 22, |
|
598 |
EVEX_ETUP = 23 |
|
599 |
}; |
|
600 |
||
601 |
enum EvexInputSizeInBits { |
|
602 |
EVEX_8bit = 0, |
|
603 |
EVEX_16bit = 1, |
|
604 |
EVEX_32bit = 2, |
|
34162 | 605 |
EVEX_64bit = 3, |
606 |
EVEX_NObit = 4 |
|
30624 | 607 |
}; |
608 |
||
1 | 609 |
enum WhichOperand { |
610 |
// input to locate_operand, and format code for relocations |
|
1066 | 611 |
imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
1 | 612 |
disp32_operand = 1, // embedded 32-bit displacement or address |
613 |
call32_operand = 2, // embedded 32-bit self-relative displacement |
|
1066 | 614 |
#ifndef _LP64 |
1 | 615 |
_WhichOperand_limit = 3 |
1066 | 616 |
#else |
617 |
narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop |
|
618 |
_WhichOperand_limit = 4 |
|
619 |
#endif |
|
1 | 620 |
}; |
621 |
||
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
622 |
enum ComparisonPredicate { |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
623 |
eq = 0, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
624 |
lt = 1, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
625 |
le = 2, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
626 |
_false = 3, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
627 |
neq = 4, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
628 |
nlt = 5, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
629 |
nle = 6, |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
630 |
_true = 7 |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
631 |
}; |
1066 | 632 |
|
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
633 |
//---< calculate length of instruction >--- |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
634 |
// As instruction size can't be found out easily on x86/x64, |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
635 |
// we just use '4' for len and maxlen. |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
636 |
// instruction must start at passed address |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
637 |
static unsigned int instr_len(unsigned char *instr) { return 4; } |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
638 |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
639 |
//---< longest instructions >--- |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
640 |
// Max instruction length is not specified in architecture documentation. |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
641 |
// We could use a "safe enough" estimate (15), but just default to |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
642 |
// instruction length guess from above. |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54750
diff
changeset
|
643 |
static unsigned int instr_maxlen() { return 4; } |
1066 | 644 |
|
645 |
// NOTE: The general philopsophy of the declarations here is that 64bit versions |
|
646 |
// of instructions are freely declared without the need for wrapping them an ifdef. |
|
647 |
// (Some dangerous instructions are ifdef's out of inappropriate jvm's.) |
|
648 |
// In the .cpp file the implementations are wrapped so that they are dropped out |
|
15432 | 649 |
// of the resulting jvm. This is done mostly to keep the footprint of MINIMAL |
1066 | 650 |
// to the size it was prior to merging up the 32bit and 64bit assemblers. |
651 |
// |
|
652 |
// This does mean you'll get a linker/runtime error if you use a 64bit only instruction |
|
653 |
// in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. |
|
654 |
||
655 |
private: |
|
656 |
||
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
657 |
bool _legacy_mode_bw; |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
658 |
bool _legacy_mode_dq; |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
659 |
bool _legacy_mode_vl; |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
660 |
bool _legacy_mode_vlbw; |
36837 | 661 |
bool _is_managed; |
38138
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
662 |
bool _vector_masking; // For stub code use only |
34162 | 663 |
|
664 |
class InstructionAttr *_attributes; |
|
1066 | 665 |
|
666 |
// 64bit prefixes |
|
667 |
int prefix_and_encode(int reg_enc, bool byteinst = false); |
|
668 |
int prefixq_and_encode(int reg_enc); |
|
669 |
||
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33089
diff
changeset
|
670 |
int prefix_and_encode(int dst_enc, int src_enc) { |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33089
diff
changeset
|
671 |
return prefix_and_encode(dst_enc, false, src_enc, false); |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33089
diff
changeset
|
672 |
} |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33089
diff
changeset
|
673 |
int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); |
1066 | 674 |
int prefixq_and_encode(int dst_enc, int src_enc); |
675 |
||
676 |
void prefix(Register reg); |
|
33066 | 677 |
void prefix(Register dst, Register src, Prefix p); |
678 |
void prefix(Register dst, Address adr, Prefix p); |
|
1066 | 679 |
void prefix(Address adr); |
680 |
void prefixq(Address adr); |
|
681 |
||
682 |
void prefix(Address adr, Register reg, bool byteinst = false); |
|
11427 | 683 |
void prefix(Address adr, XMMRegister reg); |
1066 | 684 |
void prefixq(Address adr, Register reg); |
11427 | 685 |
void prefixq(Address adr, XMMRegister reg); |
1066 | 686 |
|
687 |
void prefetch_prefix(Address src); |
|
688 |
||
11427 | 689 |
void rex_prefix(Address adr, XMMRegister xreg, |
690 |
VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
|
691 |
int rex_prefix_and_encode(int dst_enc, int src_enc, |
|
692 |
VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
|
693 |
||
34162 | 694 |
void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc); |
30624 | 695 |
|
34162 | 696 |
void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, |
697 |
int nds_enc, VexSimdPrefix pre, VexOpcode opc); |
|
11427 | 698 |
|
699 |
void vex_prefix(Address adr, int nds_enc, int xreg_enc, |
|
700 |
VexSimdPrefix pre, VexOpcode opc, |
|
34162 | 701 |
InstructionAttr *attributes); |
31410 | 702 |
|
11427 | 703 |
int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
704 |
VexSimdPrefix pre, VexOpcode opc, |
|
34162 | 705 |
InstructionAttr *attributes); |
31410 | 706 |
|
34162 | 707 |
void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, |
708 |
VexOpcode opc, InstructionAttr *attributes); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
709 |
|
34162 | 710 |
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, |
711 |
VexOpcode opc, InstructionAttr *attributes); |
|
11427 | 712 |
|
1066 | 713 |
// Helper functions for groups of instructions |
714 |
void emit_arith_b(int op1, int op2, Register dst, int imm8); |
|
715 |
||
716 |
void emit_arith(int op1, int op2, Register dst, int32_t imm32); |
|
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
717 |
// Force generation of a 4 byte immediate value even if it fits into 8bit |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
718 |
void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
1066 | 719 |
void emit_arith(int op1, int op2, Register dst, Register src); |
720 |
||
30624 | 721 |
bool emit_compressed_disp_byte(int &disp); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
722 |
|
1066 | 723 |
void emit_operand(Register reg, |
724 |
Register base, Register index, Address::ScaleFactor scale, |
|
725 |
int disp, |
|
726 |
RelocationHolder const& rspec, |
|
727 |
int rip_relative_correction = 0); |
|
728 |
||
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
729 |
void emit_operand(XMMRegister reg, Register base, XMMRegister index, |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
730 |
Address::ScaleFactor scale, |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
731 |
int disp, RelocationHolder const& rspec); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
732 |
|
1066 | 733 |
void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); |
734 |
||
735 |
// operands that only take the original 32bit registers |
|
736 |
void emit_operand32(Register reg, Address adr); |
|
737 |
||
738 |
void emit_operand(XMMRegister reg, |
|
739 |
Register base, Register index, Address::ScaleFactor scale, |
|
740 |
int disp, |
|
741 |
RelocationHolder const& rspec); |
|
742 |
||
743 |
void emit_operand(XMMRegister reg, Address adr); |
|
744 |
||
745 |
void emit_operand(MMXRegister reg, Address adr); |
|
746 |
||
747 |
// workaround gcc (3.2.1-7) bug |
|
748 |
void emit_operand(Address adr, MMXRegister reg); |
|
749 |
||
750 |
||
751 |
// Immediate-to-memory forms |
|
752 |
void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); |
|
753 |
||
754 |
void emit_farith(int b1, int b2, int i); |
|
755 |
||
756 |
||
757 |
protected: |
|
758 |
#ifdef ASSERT |
|
759 |
void check_relocation(RelocationHolder const& rspec, int format); |
|
760 |
#endif |
|
761 |
||
762 |
void emit_data(jint data, relocInfo::relocType rtype, int format); |
|
763 |
void emit_data(jint data, RelocationHolder const& rspec, int format); |
|
764 |
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
|
765 |
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
|
766 |
||
767 |
bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); |
|
768 |
||
769 |
// These are all easily abused and hence protected |
|
770 |
||
771 |
// 32BIT ONLY SECTION |
|
772 |
#ifndef _LP64 |
|
773 |
// Make these disappear in 64bit mode since they would never be correct |
|
774 |
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
775 |
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
776 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
777 |
void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
1066 | 778 |
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
779 |
||
780 |
void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
781 |
#else |
|
782 |
// 64BIT ONLY SECTION |
|
783 |
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
784 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
785 |
void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
786 |
void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
787 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
788 |
void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
789 |
void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
1066 | 790 |
#endif // _LP64 |
791 |
||
792 |
// These are unique in that we are ensured by the caller that the 32bit |
|
793 |
// relative in these instructions will always be able to reach the potentially |
|
794 |
// 64bit address described by entry. Since they can take a 64bit address they |
|
795 |
// don't have the 32 suffix like the other instructions in this class. |
|
796 |
||
797 |
void call_literal(address entry, RelocationHolder const& rspec); |
|
798 |
void jmp_literal(address entry, RelocationHolder const& rspec); |
|
799 |
||
800 |
// Avoid using directly section |
|
801 |
// Instructions in this section are actually usable by anyone without danger |
|
802 |
// of failure but have performance issues that are addressed my enhanced |
|
803 |
// instructions which will do the proper thing base on the particular cpu. |
|
804 |
// We protect them because we don't trust you... |
|
805 |
||
806 |
// Don't use next inc() and dec() methods directly. INC & DEC instructions |
|
807 |
// could cause a partial flag stall since they don't set CF flag. |
|
808 |
// Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
|
809 |
// which call inc() & dec() or add() & sub() in accordance with |
|
810 |
// the product flag UseIncDec value. |
|
811 |
||
812 |
void decl(Register dst); |
|
813 |
void decl(Address dst); |
|
814 |
void decq(Register dst); |
|
815 |
void decq(Address dst); |
|
816 |
||
817 |
void incl(Register dst); |
|
818 |
void incl(Address dst); |
|
819 |
void incq(Register dst); |
|
820 |
void incq(Address dst); |
|
821 |
||
822 |
// New cpus require use of movsd and movss to avoid partial register stall |
|
823 |
// when loading from memory. But for old Opteron use movlpd instead of movsd. |
|
824 |
// The selection is done in MacroAssembler::movdbl() and movflt(). |
|
825 |
||
826 |
// Move Scalar Single-Precision Floating-Point Values |
|
827 |
void movss(XMMRegister dst, Address src); |
|
828 |
void movss(XMMRegister dst, XMMRegister src); |
|
829 |
void movss(Address dst, XMMRegister src); |
|
830 |
||
831 |
// Move Scalar Double-Precision Floating-Point Values |
|
832 |
void movsd(XMMRegister dst, Address src); |
|
833 |
void movsd(XMMRegister dst, XMMRegister src); |
|
834 |
void movsd(Address dst, XMMRegister src); |
|
835 |
void movlpd(XMMRegister dst, Address src); |
|
836 |
||
837 |
// New cpus require use of movaps and movapd to avoid partial register stall |
|
838 |
// when moving between registers. |
|
839 |
void movaps(XMMRegister dst, XMMRegister src); |
|
840 |
void movapd(XMMRegister dst, XMMRegister src); |
|
841 |
||
842 |
// End avoid using directly |
|
843 |
||
844 |
||
845 |
// Instruction prefixes |
|
846 |
void prefix(Prefix p); |
|
847 |
||
1 | 848 |
public: |
849 |
||
850 |
// Creation |
|
30624 | 851 |
Assembler(CodeBuffer* code) : AbstractAssembler(code) { |
852 |
init_attributes(); |
|
853 |
} |
|
1 | 854 |
|
855 |
// Decoding |
|
856 |
static address locate_operand(address inst, WhichOperand which); |
|
857 |
static address locate_next_instruction(address inst); |
|
858 |
||
1066 | 859 |
// Utilities |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8494
diff
changeset
|
860 |
static bool is_polling_page_far() NOT_LP64({ return false;}); |
30624 | 861 |
static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, |
862 |
int cur_tuple_type, int in_size_in_bits, int cur_encoding); |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8494
diff
changeset
|
863 |
|
1066 | 864 |
// Generic instructions |
865 |
// Does 32bit or 64bit as needed for the platform. In some sense these |
|
866 |
// belong in macro assembler but there is no need for both varieties to exist |
|
867 |
||
30624 | 868 |
void init_attributes(void) { |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
869 |
_legacy_mode_bw = (VM_Version::supports_avx512bw() == false); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
870 |
_legacy_mode_dq = (VM_Version::supports_avx512dq() == false); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
871 |
_legacy_mode_vl = (VM_Version::supports_avx512vl() == false); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
872 |
_legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false); |
36837 | 873 |
_is_managed = false; |
38138
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
874 |
_vector_masking = false; |
34162 | 875 |
_attributes = NULL; |
30624 | 876 |
} |
877 |
||
34162 | 878 |
void set_attributes(InstructionAttr *attributes) { _attributes = attributes; } |
879 |
void clear_attributes(void) { _attributes = NULL; } |
|
880 |
||
36837 | 881 |
void set_managed(void) { _is_managed = true; } |
882 |
void clear_managed(void) { _is_managed = false; } |
|
883 |
bool is_managed(void) { return _is_managed; } |
|
884 |
||
1066 | 885 |
void lea(Register dst, Address src); |
886 |
||
887 |
void mov(Register dst, Register src); |
|
888 |
||
889 |
void pusha(); |
|
890 |
void popa(); |
|
891 |
||
892 |
void pushf(); |
|
893 |
void popf(); |
|
894 |
||
895 |
void push(int32_t imm32); |
|
896 |
||
897 |
void push(Register src); |
|
898 |
||
899 |
void pop(Register dst); |
|
900 |
||
901 |
// These are dummies to prevent surprise implicit conversions to Register |
|
902 |
void push(void* v); |
|
903 |
void pop(void* v); |
|
904 |
||
905 |
// These do register sized moves/scans |
|
906 |
void rep_mov(); |
|
15114
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14631
diff
changeset
|
907 |
void rep_stos(); |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14631
diff
changeset
|
908 |
void rep_stosb(); |
1066 | 909 |
void repne_scan(); |
910 |
#ifdef _LP64 |
|
911 |
void repne_scanl(); |
|
912 |
#endif |
|
913 |
||
914 |
// Vanilla instructions in lexical order |
|
915 |
||
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
916 |
void adcl(Address dst, int32_t imm32); |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
917 |
void adcl(Address dst, Register src); |
1066 | 918 |
void adcl(Register dst, int32_t imm32); |
1 | 919 |
void adcl(Register dst, Address src); |
920 |
void adcl(Register dst, Register src); |
|
921 |
||
1066 | 922 |
void adcq(Register dst, int32_t imm32); |
923 |
void adcq(Register dst, Address src); |
|
924 |
void adcq(Register dst, Register src); |
|
925 |
||
39419
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
926 |
void addb(Address dst, int imm8); |
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
927 |
void addw(Address dst, int imm16); |
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
928 |
|
1066 | 929 |
void addl(Address dst, int32_t imm32); |
1 | 930 |
void addl(Address dst, Register src); |
1066 | 931 |
void addl(Register dst, int32_t imm32); |
1 | 932 |
void addl(Register dst, Address src); |
933 |
void addl(Register dst, Register src); |
|
934 |
||
1066 | 935 |
void addq(Address dst, int32_t imm32); |
936 |
void addq(Address dst, Register src); |
|
937 |
void addq(Register dst, int32_t imm32); |
|
938 |
void addq(Register dst, Address src); |
|
939 |
void addq(Register dst, Register src); |
|
940 |
||
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
941 |
#ifdef _LP64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
942 |
//Add Unsigned Integers with Carry Flag |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
943 |
void adcxq(Register dst, Register src); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
944 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
945 |
//Add Unsigned Integers with Overflow Flag |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
946 |
void adoxq(Register dst, Register src); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
947 |
#endif |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
948 |
|
1 | 949 |
void addr_nop_4(); |
950 |
void addr_nop_5(); |
|
951 |
void addr_nop_7(); |
|
952 |
void addr_nop_8(); |
|
953 |
||
1066 | 954 |
// Add Scalar Double-Precision Floating-Point Values |
955 |
void addsd(XMMRegister dst, Address src); |
|
956 |
void addsd(XMMRegister dst, XMMRegister src); |
|
957 |
||
958 |
// Add Scalar Single-Precision Floating-Point Values |
|
959 |
void addss(XMMRegister dst, Address src); |
|
960 |
void addss(XMMRegister dst, XMMRegister src); |
|
961 |
||
14132 | 962 |
// AES instructions |
963 |
void aesdec(XMMRegister dst, Address src); |
|
964 |
void aesdec(XMMRegister dst, XMMRegister src); |
|
965 |
void aesdeclast(XMMRegister dst, Address src); |
|
966 |
void aesdeclast(XMMRegister dst, XMMRegister src); |
|
967 |
void aesenc(XMMRegister dst, Address src); |
|
968 |
void aesenc(XMMRegister dst, XMMRegister src); |
|
969 |
void aesenclast(XMMRegister dst, Address src); |
|
970 |
void aesenclast(XMMRegister dst, XMMRegister src); |
|
57786
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
54960
diff
changeset
|
971 |
// Vector AES instructions |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
54960
diff
changeset
|
972 |
void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
54960
diff
changeset
|
973 |
void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50577
diff
changeset
|
974 |
void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50577
diff
changeset
|
975 |
void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
14132 | 976 |
|
11427 | 977 |
void andl(Address dst, int32_t imm32); |
1066 | 978 |
void andl(Register dst, int32_t imm32); |
979 |
void andl(Register dst, Address src); |
|
980 |
void andl(Register dst, Register src); |
|
981 |
||
10006 | 982 |
void andq(Address dst, int32_t imm32); |
1066 | 983 |
void andq(Register dst, int32_t imm32); |
984 |
void andq(Register dst, Address src); |
|
985 |
void andq(Register dst, Register src); |
|
986 |
||
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
987 |
// BMI instructions |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
988 |
void andnl(Register dst, Register src1, Register src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
989 |
void andnl(Register dst, Register src1, Address src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
990 |
void andnq(Register dst, Register src1, Register src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
991 |
void andnq(Register dst, Register src1, Address src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
992 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
993 |
void blsil(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
994 |
void blsil(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
995 |
void blsiq(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
996 |
void blsiq(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
997 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
998 |
void blsmskl(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
999 |
void blsmskl(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1000 |
void blsmskq(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1001 |
void blsmskq(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1002 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1003 |
void blsrl(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1004 |
void blsrl(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1005 |
void blsrq(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1006 |
void blsrq(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1007 |
|
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1008 |
void bsfl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1009 |
void bsrl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1010 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1011 |
#ifdef _LP64 |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1012 |
void bsfq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1013 |
void bsrq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1014 |
#endif |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1015 |
|
1066 | 1016 |
void bswapl(Register reg); |
1017 |
||
1018 |
void bswapq(Register reg); |
|
1019 |
||
1 | 1020 |
void call(Label& L, relocInfo::relocType rtype); |
1021 |
void call(Register reg); // push pc; pc <- reg |
|
1022 |
void call(Address adr); // push pc; pc <- adr |
|
1023 |
||
1066 | 1024 |
void cdql(); |
1025 |
||
1026 |
void cdqq(); |
|
1027 |
||
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1028 |
void cld(); |
1066 | 1029 |
|
1030 |
void clflush(Address adr); |
|
57804 | 1031 |
void clflushopt(Address adr); |
1032 |
void clwb(Address adr); |
|
1066 | 1033 |
|
1034 |
void cmovl(Condition cc, Register dst, Register src); |
|
1035 |
void cmovl(Condition cc, Register dst, Address src); |
|
1036 |
||
1037 |
void cmovq(Condition cc, Register dst, Register src); |
|
1038 |
void cmovq(Condition cc, Register dst, Address src); |
|
1039 |
||
1040 |
||
1041 |
void cmpb(Address dst, int imm8); |
|
1042 |
||
1043 |
void cmpl(Address dst, int32_t imm32); |
|
1044 |
||
1045 |
void cmpl(Register dst, int32_t imm32); |
|
1046 |
void cmpl(Register dst, Register src); |
|
1047 |
void cmpl(Register dst, Address src); |
|
1048 |
||
1049 |
void cmpq(Address dst, int32_t imm32); |
|
1050 |
void cmpq(Address dst, Register src); |
|
1051 |
||
1052 |
void cmpq(Register dst, int32_t imm32); |
|
1053 |
void cmpq(Register dst, Register src); |
|
1054 |
void cmpq(Register dst, Address src); |
|
1055 |
||
1056 |
// these are dummies used to catch attempting to convert NULL to Register |
|
1057 |
void cmpl(Register dst, void* junk); // dummy |
|
1058 |
void cmpq(Register dst, void* junk); // dummy |
|
1059 |
||
1060 |
void cmpw(Address dst, int imm16); |
|
1061 |
||
1062 |
void cmpxchg8 (Address adr); |
|
1063 |
||
27691
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26576
diff
changeset
|
1064 |
void cmpxchgb(Register reg, Address adr); |
1066 | 1065 |
void cmpxchgl(Register reg, Address adr); |
1066 |
||
1067 |
void cmpxchgq(Register reg, Address adr); |
|
1068 |
||
1069 |
// Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
|
1070 |
void comisd(XMMRegister dst, Address src); |
|
11427 | 1071 |
void comisd(XMMRegister dst, XMMRegister src); |
1066 | 1072 |
|
1073 |
// Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
|
1074 |
void comiss(XMMRegister dst, Address src); |
|
11427 | 1075 |
void comiss(XMMRegister dst, XMMRegister src); |
1066 | 1076 |
|
1077 |
// Identify processor type and features |
|
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1078 |
void cpuid(); |
1066 | 1079 |
|
33066 | 1080 |
// CRC32C |
1081 |
void crc32(Register crc, Register v, int8_t sizeInBytes); |
|
1082 |
void crc32(Register crc, Address adr, int8_t sizeInBytes); |
|
1083 |
||
1066 | 1084 |
// Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value |
1085 |
void cvtsd2ss(XMMRegister dst, XMMRegister src); |
|
11427 | 1086 |
void cvtsd2ss(XMMRegister dst, Address src); |
1066 | 1087 |
|
1088 |
// Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value |
|
1089 |
void cvtsi2sdl(XMMRegister dst, Register src); |
|
11427 | 1090 |
void cvtsi2sdl(XMMRegister dst, Address src); |
1066 | 1091 |
void cvtsi2sdq(XMMRegister dst, Register src); |
11427 | 1092 |
void cvtsi2sdq(XMMRegister dst, Address src); |
1066 | 1093 |
|
1094 |
// Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value |
|
1095 |
void cvtsi2ssl(XMMRegister dst, Register src); |
|
11427 | 1096 |
void cvtsi2ssl(XMMRegister dst, Address src); |
1066 | 1097 |
void cvtsi2ssq(XMMRegister dst, Register src); |
11427 | 1098 |
void cvtsi2ssq(XMMRegister dst, Address src); |
1066 | 1099 |
|
1100 |
// Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value |
|
1101 |
void cvtdq2pd(XMMRegister dst, XMMRegister src); |
|
1102 |
||
1103 |
// Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value |
|
1104 |
void cvtdq2ps(XMMRegister dst, XMMRegister src); |
|
1105 |
||
1106 |
// Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value |
|
1107 |
void cvtss2sd(XMMRegister dst, XMMRegister src); |
|
11427 | 1108 |
void cvtss2sd(XMMRegister dst, Address src); |
1066 | 1109 |
|
1110 |
// Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer |
|
1111 |
void cvttsd2sil(Register dst, Address src); |
|
1112 |
void cvttsd2sil(Register dst, XMMRegister src); |
|
1113 |
void cvttsd2siq(Register dst, XMMRegister src); |
|
1114 |
||
1115 |
// Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer |
|
1116 |
void cvttss2sil(Register dst, XMMRegister src); |
|
1117 |
void cvttss2siq(Register dst, XMMRegister src); |
|
1118 |
||
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
37293
diff
changeset
|
1119 |
void cvttpd2dq(XMMRegister dst, XMMRegister src); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
37293
diff
changeset
|
1120 |
|
54750 | 1121 |
//Abs of packed Integer values |
1122 |
void pabsb(XMMRegister dst, XMMRegister src); |
|
1123 |
void pabsw(XMMRegister dst, XMMRegister src); |
|
1124 |
void pabsd(XMMRegister dst, XMMRegister src); |
|
1125 |
void vpabsb(XMMRegister dst, XMMRegister src, int vector_len); |
|
1126 |
void vpabsw(XMMRegister dst, XMMRegister src, int vector_len); |
|
1127 |
void vpabsd(XMMRegister dst, XMMRegister src, int vector_len); |
|
1128 |
void evpabsq(XMMRegister dst, XMMRegister src, int vector_len); |
|
1129 |
||
1066 | 1130 |
// Divide Scalar Double-Precision Floating-Point Values |
1131 |
void divsd(XMMRegister dst, Address src); |
|
1132 |
void divsd(XMMRegister dst, XMMRegister src); |
|
1133 |
||
1134 |
// Divide Scalar Single-Precision Floating-Point Values |
|
1135 |
void divss(XMMRegister dst, Address src); |
|
1136 |
void divss(XMMRegister dst, XMMRegister src); |
|
1137 |
||
1138 |
void emms(); |
|
1139 |
||
1140 |
void fabs(); |
|
1141 |
||
1142 |
void fadd(int i); |
|
1143 |
||
1144 |
void fadd_d(Address src); |
|
1145 |
void fadd_s(Address src); |
|
1146 |
||
1147 |
// "Alternate" versions of x87 instructions place result down in FPU |
|
1148 |
// stack instead of on TOS |
|
1149 |
||
1150 |
void fadda(int i); // "alternate" fadd |
|
1151 |
void faddp(int i = 1); |
|
1152 |
||
1153 |
void fchs(); |
|
1154 |
||
1155 |
void fcom(int i); |
|
1156 |
||
1157 |
void fcomp(int i = 1); |
|
1158 |
void fcomp_d(Address src); |
|
1159 |
void fcomp_s(Address src); |
|
1160 |
||
1161 |
void fcompp(); |
|
1162 |
||
1163 |
void fcos(); |
|
1164 |
||
1165 |
void fdecstp(); |
|
1166 |
||
1167 |
void fdiv(int i); |
|
1168 |
void fdiv_d(Address src); |
|
1169 |
void fdivr_s(Address src); |
|
1170 |
void fdiva(int i); // "alternate" fdiv |
|
1171 |
void fdivp(int i = 1); |
|
1172 |
||
1173 |
void fdivr(int i); |
|
1174 |
void fdivr_d(Address src); |
|
1175 |
void fdiv_s(Address src); |
|
1176 |
||
1177 |
void fdivra(int i); // "alternate" reversed fdiv |
|
1178 |
||
1179 |
void fdivrp(int i = 1); |
|
1180 |
||
1181 |
void ffree(int i = 0); |
|
1182 |
||
1183 |
void fild_d(Address adr); |
|
1184 |
void fild_s(Address adr); |
|
1185 |
||
1186 |
void fincstp(); |
|
1187 |
||
1188 |
void finit(); |
|
1189 |
||
1190 |
void fist_s (Address adr); |
|
1191 |
void fistp_d(Address adr); |
|
1192 |
void fistp_s(Address adr); |
|
1193 |
||
1194 |
void fld1(); |
|
1195 |
||
1196 |
void fld_d(Address adr); |
|
1197 |
void fld_s(Address adr); |
|
1198 |
void fld_s(int index); |
|
1199 |
void fld_x(Address adr); // extended-precision (80-bit) format |
|
1200 |
||
1201 |
void fldcw(Address src); |
|
1202 |
||
1203 |
void fldenv(Address src); |
|
1204 |
||
1205 |
void fldlg2(); |
|
1206 |
||
1207 |
void fldln2(); |
|
1208 |
||
1209 |
void fldz(); |
|
1210 |
||
1211 |
void flog(); |
|
1212 |
void flog10(); |
|
1213 |
||
1214 |
void fmul(int i); |
|
1215 |
||
1216 |
void fmul_d(Address src); |
|
1217 |
void fmul_s(Address src); |
|
1218 |
||
1219 |
void fmula(int i); // "alternate" fmul |
|
1220 |
||
1221 |
void fmulp(int i = 1); |
|
1222 |
||
1223 |
void fnsave(Address dst); |
|
1224 |
||
1225 |
void fnstcw(Address src); |
|
1226 |
||
1227 |
void fnstsw_ax(); |
|
1228 |
||
1229 |
void fprem(); |
|
1230 |
void fprem1(); |
|
1231 |
||
1232 |
void frstor(Address src); |
|
1233 |
||
1234 |
void fsin(); |
|
1235 |
||
1236 |
void fsqrt(); |
|
1237 |
||
1238 |
void fst_d(Address adr); |
|
1239 |
void fst_s(Address adr); |
|
1240 |
||
1241 |
void fstp_d(Address adr); |
|
1242 |
void fstp_d(int index); |
|
1243 |
void fstp_s(Address adr); |
|
1244 |
void fstp_x(Address adr); // extended-precision (80-bit) format |
|
1245 |
||
1246 |
void fsub(int i); |
|
1247 |
void fsub_d(Address src); |
|
1248 |
void fsub_s(Address src); |
|
1249 |
||
1250 |
void fsuba(int i); // "alternate" fsub |
|
1251 |
||
1252 |
void fsubp(int i = 1); |
|
1253 |
||
1254 |
void fsubr(int i); |
|
1255 |
void fsubr_d(Address src); |
|
1256 |
void fsubr_s(Address src); |
|
1257 |
||
1258 |
void fsubra(int i); // "alternate" reversed fsub |
|
1259 |
||
1260 |
void fsubrp(int i = 1); |
|
1261 |
||
1262 |
void ftan(); |
|
1263 |
||
1264 |
void ftst(); |
|
1265 |
||
1266 |
void fucomi(int i = 1); |
|
1267 |
void fucomip(int i = 1); |
|
1268 |
||
1269 |
void fwait(); |
|
1270 |
||
1271 |
void fxch(int i = 1); |
|
1272 |
||
1273 |
void fxrstor(Address src); |
|
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1274 |
void xrstor(Address src); |
1066 | 1275 |
|
1276 |
void fxsave(Address dst); |
|
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1277 |
void xsave(Address dst); |
1066 | 1278 |
|
1279 |
void fyl2x(); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11791
diff
changeset
|
1280 |
void frndint(); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11791
diff
changeset
|
1281 |
void f2xm1(); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11791
diff
changeset
|
1282 |
void fldl2e(); |
1066 | 1283 |
|
1284 |
void hlt(); |
|
1285 |
||
1286 |
void idivl(Register src); |
|
7121 | 1287 |
void divl(Register src); // Unsigned division |
1066 | 1288 |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1289 |
#ifdef _LP64 |
1066 | 1290 |
void idivq(Register src); |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1291 |
#endif |
1066 | 1292 |
|
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35154
diff
changeset
|
1293 |
void imull(Register src); |
1066 | 1294 |
void imull(Register dst, Register src); |
1295 |
void imull(Register dst, Register src, int value); |
|
21105
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1296 |
void imull(Register dst, Address src); |
1066 | 1297 |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1298 |
#ifdef _LP64 |
1066 | 1299 |
void imulq(Register dst, Register src); |
1300 |
void imulq(Register dst, Register src, int value); |
|
21105
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1301 |
void imulq(Register dst, Address src); |
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1302 |
#endif |
1066 | 1303 |
|
1 | 1304 |
// jcc is the generic conditional branch generator to run- |
1305 |
// time routines, jcc is used for branches to labels. jcc |
|
1306 |
// takes a branch opcode (cc) and a label (L) and generates |
|
1307 |
// either a backward branch or a forward branch and links it |
|
1308 |
// to the label fixup chain. Usage: |
|
1309 |
// |
|
1310 |
// Label L; // unbound label |
|
1311 |
// jcc(cc, L); // forward branch to unbound label |
|
1312 |
// bind(L); // bind label to the current pc |
|
1313 |
// jcc(cc, L); // backward branch to bound label |
|
1314 |
// bind(L); // illegal: a label may be bound only once |
|
1315 |
// |
|
1316 |
// Note: The same Label can be used for forward and backward branches |
|
1317 |
// but it may be bound only once. |
|
1318 |
||
10264 | 1319 |
void jcc(Condition cc, Label& L, bool maybe_short = true); |
1 | 1320 |
|
1321 |
// Conditional jump to a 8-bit offset to L. |
|
1322 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
1323 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
1324 |
// will occur. |
|
51633
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1325 |
|
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1326 |
// Use macro to record file and line number. |
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1327 |
#define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__) |
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1328 |
|
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1329 |
void jccb_0(Condition cc, Label& L, const char* file, int line); |
1 | 1330 |
|
1066 | 1331 |
void jmp(Address entry); // pc <- entry |
1332 |
||
1333 |
// Label operations & relative jumps (PPUM Appendix D) |
|
10264 | 1334 |
void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
1066 | 1335 |
|
1336 |
void jmp(Register entry); // pc <- entry |
|
1337 |
||
1338 |
// Unconditional 8-bit offset jump to L. |
|
1339 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
1340 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
1341 |
// will occur. |
|
51633
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1342 |
|
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1343 |
// Use macro to record file and line number. |
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1344 |
#define jmpb(L) jmpb_0(L, __FILE__, __LINE__) |
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1345 |
|
21154cb84d2a
8209594: guarantee(this->is8bit(imm8)) failed: Short forward jump exceeds 8-bit offset
kvn
parents:
51333
diff
changeset
|
1346 |
void jmpb_0(Label& L, const char* file, int line); |
1066 | 1347 |
|
1348 |
void ldmxcsr( Address src ); |
|
1349 |
||
1350 |
void leal(Register dst, Address src); |
|
1351 |
||
1352 |
void leaq(Register dst, Address src); |
|
1353 |
||
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1354 |
void lfence(); |
1066 | 1355 |
|
1356 |
void lock(); |
|
1357 |
||
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1358 |
void lzcntl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1359 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1360 |
#ifdef _LP64 |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1361 |
void lzcntq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1362 |
#endif |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1363 |
|
1066 | 1364 |
enum Membar_mask_bits { |
1365 |
StoreStore = 1 << 3, |
|
1366 |
LoadStore = 1 << 2, |
|
1367 |
StoreLoad = 1 << 1, |
|
1368 |
LoadLoad = 1 << 0 |
|
1369 |
}; |
|
1370 |
||
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1371 |
// Serializes memory and blows flags |
1066 | 1372 |
void membar(Membar_mask_bits order_constraint) { |
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1373 |
// We only have to handle StoreLoad |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1374 |
if (order_constraint & StoreLoad) { |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1375 |
// All usable chips support "locked" instructions which suffice |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1376 |
// as barriers, and are much faster than the alternative of |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1377 |
// using cpuid instruction. We use here a locked add [esp-C],0. |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1378 |
// This is conveniently otherwise a no-op except for blowing |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1379 |
// flags, and introducing a false dependency on target memory |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1380 |
// location. We can't do anything with flags, but we can avoid |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1381 |
// memory dependencies in the current method by locked-adding |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1382 |
// somewhere else on the stack. Doing [esp+C] will collide with |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1383 |
// something on stack in current method, hence we go for [esp-C]. |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1384 |
// It is convenient since it is almost always in data cache, for |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1385 |
// any small C. We need to step back from SP to avoid data |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1386 |
// dependencies with other things on below SP (callee-saves, for |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1387 |
// example). Without a clear way to figure out the minimal safe |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1388 |
// distance from SP, it makes sense to step back the complete |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1389 |
// cache line, as this will also avoid possible second-order effects |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1390 |
// with locked ops against the cache line. Our choice of offset |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1391 |
// is bounded by x86 operand encoding, which should stay within |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1392 |
// [-128; +127] to have the 8-byte displacement encoding. |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1393 |
// |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1394 |
// Any change to this code may need to revisit other places in |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1395 |
// the code where this idiom is used, in particular the |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1396 |
// orderAccess code. |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1397 |
|
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1398 |
int offset = -VM_Version::L1_line_size(); |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1399 |
if (offset < -128) { |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1400 |
offset = -128; |
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1401 |
} |
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1402 |
|
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1403 |
lock(); |
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
1404 |
addl(Address(rsp, offset), 0);// Assert the lock# signal here |
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1405 |
} |
1066 | 1406 |
} |
1407 |
||
1408 |
void mfence(); |
|
57804 | 1409 |
void sfence(); |
1066 | 1410 |
|
1411 |
// Moves |
|
1412 |
||
1413 |
void mov64(Register dst, int64_t imm64); |
|
1414 |
||
1415 |
void movb(Address dst, Register src); |
|
1416 |
void movb(Address dst, int imm8); |
|
1417 |
void movb(Register dst, Address src); |
|
1418 |
||
33465 | 1419 |
void movddup(XMMRegister dst, XMMRegister src); |
1420 |
||
35113 | 1421 |
void kmovbl(KRegister dst, Register src); |
1422 |
void kmovbl(Register dst, KRegister src); |
|
34203 | 1423 |
void kmovwl(KRegister dst, Register src); |
38049 | 1424 |
void kmovwl(KRegister dst, Address src); |
35113 | 1425 |
void kmovwl(Register dst, KRegister src); |
34203 | 1426 |
void kmovdl(KRegister dst, Register src); |
35113 | 1427 |
void kmovdl(Register dst, KRegister src); |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1428 |
void kmovql(KRegister dst, KRegister src); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1429 |
void kmovql(Address dst, KRegister src); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1430 |
void kmovql(KRegister dst, Address src); |
35113 | 1431 |
void kmovql(KRegister dst, Register src); |
1432 |
void kmovql(Register dst, KRegister src); |
|
30624 | 1433 |
|
38049 | 1434 |
void knotwl(KRegister dst, KRegister src); |
1435 |
||
34203 | 1436 |
void kortestbl(KRegister dst, KRegister src); |
1437 |
void kortestwl(KRegister dst, KRegister src); |
|
1438 |
void kortestdl(KRegister dst, KRegister src); |
|
1439 |
void kortestql(KRegister dst, KRegister src); |
|
1440 |
||
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1441 |
void ktestq(KRegister src1, KRegister src2); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1442 |
void ktestd(KRegister src1, KRegister src2); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1443 |
|
38138
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
1444 |
void ktestql(KRegister dst, KRegister src); |
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
1445 |
|
1066 | 1446 |
void movdl(XMMRegister dst, Register src); |
1447 |
void movdl(Register dst, XMMRegister src); |
|
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1448 |
void movdl(XMMRegister dst, Address src); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1449 |
void movdl(Address dst, XMMRegister src); |
1066 | 1450 |
|
1451 |
// Move Double Quadword |
|
1452 |
void movdq(XMMRegister dst, Register src); |
|
1453 |
void movdq(Register dst, XMMRegister src); |
|
1454 |
||
1455 |
// Move Aligned Double Quadword |
|
1456 |
void movdqa(XMMRegister dst, XMMRegister src); |
|
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1457 |
void movdqa(XMMRegister dst, Address src); |
1066 | 1458 |
|
1437 | 1459 |
// Move Unaligned Double Quadword |
1460 |
void movdqu(Address dst, XMMRegister src); |
|
1461 |
void movdqu(XMMRegister dst, Address src); |
|
1462 |
void movdqu(XMMRegister dst, XMMRegister src); |
|
1463 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1464 |
// Move Unaligned 256bit Vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1465 |
void vmovdqu(Address dst, XMMRegister src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1466 |
void vmovdqu(XMMRegister dst, Address src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1467 |
void vmovdqu(XMMRegister dst, XMMRegister src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1468 |
|
30624 | 1469 |
// Move Unaligned 512bit Vector |
34203 | 1470 |
void evmovdqub(Address dst, XMMRegister src, int vector_len); |
1471 |
void evmovdqub(XMMRegister dst, Address src, int vector_len); |
|
1472 |
void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len); |
|
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1473 |
void evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len); |
34203 | 1474 |
void evmovdquw(Address dst, XMMRegister src, int vector_len); |
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1475 |
void evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len); |
34203 | 1476 |
void evmovdquw(XMMRegister dst, Address src, int vector_len); |
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1477 |
void evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len); |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1478 |
void evmovdqul(Address dst, XMMRegister src, int vector_len); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1479 |
void evmovdqul(XMMRegister dst, Address src, int vector_len); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1480 |
void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1481 |
void evmovdquq(Address dst, XMMRegister src, int vector_len); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1482 |
void evmovdquq(XMMRegister dst, Address src, int vector_len); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1483 |
void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len); |
30624 | 1484 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1485 |
// Move lower 64bit to high 64bit in 128bit register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1486 |
void movlhps(XMMRegister dst, XMMRegister src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1487 |
|
1066 | 1488 |
void movl(Register dst, int32_t imm32); |
1489 |
void movl(Address dst, int32_t imm32); |
|
1490 |
void movl(Register dst, Register src); |
|
1491 |
void movl(Register dst, Address src); |
|
1492 |
void movl(Address dst, Register src); |
|
1493 |
||
1494 |
// These dummies prevent using movl from converting a zero (like NULL) into Register |
|
1495 |
// by giving the compiler two choices it can't resolve |
|
1496 |
||
1497 |
void movl(Address dst, void* junk); |
|
1498 |
void movl(Register dst, void* junk); |
|
1499 |
||
1500 |
#ifdef _LP64 |
|
1501 |
void movq(Register dst, Register src); |
|
1502 |
void movq(Register dst, Address src); |
|
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
1503 |
void movq(Address dst, Register src); |
1066 | 1504 |
#endif |
1505 |
||
1506 |
void movq(Address dst, MMXRegister src ); |
|
1507 |
void movq(MMXRegister dst, Address src ); |
|
1508 |
||
1509 |
#ifdef _LP64 |
|
1510 |
// These dummies prevent using movq from converting a zero (like NULL) into Register |
|
1511 |
// by giving the compiler two choices it can't resolve |
|
1512 |
||
1513 |
void movq(Address dst, void* dummy); |
|
1514 |
void movq(Register dst, void* dummy); |
|
1515 |
#endif |
|
1516 |
||
1517 |
// Move Quadword |
|
1518 |
void movq(Address dst, XMMRegister src); |
|
1519 |
void movq(XMMRegister dst, Address src); |
|
1520 |
||
1521 |
void movsbl(Register dst, Address src); |
|
1522 |
void movsbl(Register dst, Register src); |
|
1523 |
||
1524 |
#ifdef _LP64 |
|
2150 | 1525 |
void movsbq(Register dst, Address src); |
1526 |
void movsbq(Register dst, Register src); |
|
1527 |
||
1066 | 1528 |
// Move signed 32bit immediate to 64bit extending sign |
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
1529 |
void movslq(Address dst, int32_t imm64); |
1066 | 1530 |
void movslq(Register dst, int32_t imm64); |
1531 |
||
1532 |
void movslq(Register dst, Address src); |
|
1533 |
void movslq(Register dst, Register src); |
|
1534 |
void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous |
|
1535 |
#endif |
|
1536 |
||
1537 |
void movswl(Register dst, Address src); |
|
1538 |
void movswl(Register dst, Register src); |
|
1539 |
||
2150 | 1540 |
#ifdef _LP64 |
1541 |
void movswq(Register dst, Address src); |
|
1542 |
void movswq(Register dst, Register src); |
|
1543 |
#endif |
|
1544 |
||
1066 | 1545 |
void movw(Address dst, int imm16); |
1546 |
void movw(Register dst, Address src); |
|
1547 |
void movw(Address dst, Register src); |
|
1548 |
||
1549 |
void movzbl(Register dst, Address src); |
|
1550 |
void movzbl(Register dst, Register src); |
|
1551 |
||
2150 | 1552 |
#ifdef _LP64 |
1553 |
void movzbq(Register dst, Address src); |
|
1554 |
void movzbq(Register dst, Register src); |
|
1555 |
#endif |
|
1556 |
||
1066 | 1557 |
void movzwl(Register dst, Address src); |
1558 |
void movzwl(Register dst, Register src); |
|
1559 |
||
2150 | 1560 |
#ifdef _LP64 |
1561 |
void movzwq(Register dst, Address src); |
|
1562 |
void movzwq(Register dst, Register src); |
|
1563 |
#endif |
|
1564 |
||
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1565 |
// Unsigned multiply with RAX destination register |
1066 | 1566 |
void mull(Address src); |
1567 |
void mull(Register src); |
|
1568 |
||
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1569 |
#ifdef _LP64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1570 |
void mulq(Address src); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1571 |
void mulq(Register src); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1572 |
void mulxq(Register dst1, Register dst2, Register src); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1573 |
#endif |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1574 |
|
1066 | 1575 |
// Multiply Scalar Double-Precision Floating-Point Values |
1576 |
void mulsd(XMMRegister dst, Address src); |
|
1577 |
void mulsd(XMMRegister dst, XMMRegister src); |
|
1578 |
||
1579 |
// Multiply Scalar Single-Precision Floating-Point Values |
|
1580 |
void mulss(XMMRegister dst, Address src); |
|
1581 |
void mulss(XMMRegister dst, XMMRegister src); |
|
1582 |
||
1583 |
void negl(Register dst); |
|
1584 |
||
1585 |
#ifdef _LP64 |
|
1586 |
void negq(Register dst); |
|
1587 |
#endif |
|
1588 |
||
1589 |
void nop(int i = 1); |
|
1590 |
||
1591 |
void notl(Register dst); |
|
1592 |
||
1593 |
#ifdef _LP64 |
|
1594 |
void notq(Register dst); |
|
1595 |
#endif |
|
1596 |
||
1597 |
void orl(Address dst, int32_t imm32); |
|
1598 |
void orl(Register dst, int32_t imm32); |
|
1599 |
void orl(Register dst, Address src); |
|
1600 |
void orl(Register dst, Register src); |
|
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1601 |
void orl(Address dst, Register src); |
1066 | 1602 |
|
50577
bf7e2684cd0a
8204240: Extend MDO to allow more reasons to be recorded per bci
roland
parents:
50103
diff
changeset
|
1603 |
void orb(Address dst, int imm8); |
bf7e2684cd0a
8204240: Extend MDO to allow more reasons to be recorded per bci
roland
parents:
50103
diff
changeset
|
1604 |
|
1066 | 1605 |
void orq(Address dst, int32_t imm32); |
1606 |
void orq(Register dst, int32_t imm32); |
|
1607 |
void orq(Register dst, Address src); |
|
1608 |
void orq(Register dst, Register src); |
|
1609 |
||
11427 | 1610 |
// Pack with unsigned saturation |
1611 |
void packuswb(XMMRegister dst, XMMRegister src); |
|
1612 |
void packuswb(XMMRegister dst, Address src); |
|
30624 | 1613 |
void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
15242
695bb216be99
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
15117
diff
changeset
|
1614 |
|
695bb216be99
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
15117
diff
changeset
|
1615 |
// Pemutation of 64bit words |
30624 | 1616 |
void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len); |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32723
diff
changeset
|
1617 |
void vpermq(XMMRegister dst, XMMRegister src, int imm8); |
54750 | 1618 |
void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38049
diff
changeset
|
1619 |
void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); |
42039 | 1620 |
void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
1621 |
void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
11427 | 1622 |
|
23491 | 1623 |
void pause(); |
1624 |
||
46525
3a5c833a43de
8176506: C2: loop unswitching and unsafe accesses cause crash
roland
parents:
42039
diff
changeset
|
1625 |
// Undefined Instruction |
3a5c833a43de
8176506: C2: loop unswitching and unsafe accesses cause crash
roland
parents:
42039
diff
changeset
|
1626 |
void ud2(); |
3a5c833a43de
8176506: C2: loop unswitching and unsafe accesses cause crash
roland
parents:
42039
diff
changeset
|
1627 |
|
2348 | 1628 |
// SSE4.2 string instructions |
1629 |
void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); |
|
1630 |
void pcmpestri(XMMRegister xmm1, Address src, int imm8); |
|
1631 |
||
34203 | 1632 |
void pcmpeqb(XMMRegister dst, XMMRegister src); |
1633 |
void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1634 |
void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); |
|
35113 | 1635 |
void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len); |
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1636 |
void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1637 |
|
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1638 |
void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1639 |
void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1640 |
|
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1641 |
void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1642 |
void evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate of, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1643 |
void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len); |
34203 | 1644 |
|
33628 | 1645 |
void pcmpeqw(XMMRegister dst, XMMRegister src); |
1646 |
void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
34203 | 1647 |
void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); |
35113 | 1648 |
void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len); |
34203 | 1649 |
|
1650 |
void pcmpeqd(XMMRegister dst, XMMRegister src); |
|
1651 |
void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1652 |
void evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); |
|
35113 | 1653 |
void evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len); |
34203 | 1654 |
|
1655 |
void pcmpeqq(XMMRegister dst, XMMRegister src); |
|
1656 |
void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1657 |
void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1658 |
void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len); |
|
33628 | 1659 |
|
1660 |
void pmovmskb(Register dst, XMMRegister src); |
|
1661 |
void vpmovmskb(Register dst, XMMRegister src); |
|
1662 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1663 |
// SSE 4.1 extract |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1664 |
void pextrd(Register dst, XMMRegister src, int imm8); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1665 |
void pextrq(Register dst, XMMRegister src, int imm8); |
35154 | 1666 |
void pextrd(Address dst, XMMRegister src, int imm8); |
1667 |
void pextrq(Address dst, XMMRegister src, int imm8); |
|
1668 |
void pextrb(Address dst, XMMRegister src, int imm8); |
|
33089 | 1669 |
// SSE 2 extract |
1670 |
void pextrw(Register dst, XMMRegister src, int imm8); |
|
35154 | 1671 |
void pextrw(Address dst, XMMRegister src, int imm8); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1672 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1673 |
// SSE 4.1 insert |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1674 |
void pinsrd(XMMRegister dst, Register src, int imm8); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1675 |
void pinsrq(XMMRegister dst, Register src, int imm8); |
35154 | 1676 |
void pinsrd(XMMRegister dst, Address src, int imm8); |
1677 |
void pinsrq(XMMRegister dst, Address src, int imm8); |
|
1678 |
void pinsrb(XMMRegister dst, Address src, int imm8); |
|
33089 | 1679 |
// SSE 2 insert |
1680 |
void pinsrw(XMMRegister dst, Register src, int imm8); |
|
35154 | 1681 |
void pinsrw(XMMRegister dst, Address src, int imm8); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1682 |
|
11427 | 1683 |
// SSE4.1 packed move |
1684 |
void pmovzxbw(XMMRegister dst, XMMRegister src); |
|
1685 |
void pmovzxbw(XMMRegister dst, Address src); |
|
1686 |
||
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1687 |
void vpmovzxbw( XMMRegister dst, Address src, int vector_len); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
1688 |
void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len); |
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1689 |
void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1690 |
|
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1691 |
void evpmovwb(Address dst, XMMRegister src, int vector_len); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1692 |
void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len); |
33628 | 1693 |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
1694 |
void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
1695 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
1696 |
void evpmovdb(Address dst, XMMRegister src, int vector_len); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
1697 |
|
54750 | 1698 |
// Sign extend moves |
1699 |
void pmovsxbw(XMMRegister dst, XMMRegister src); |
|
1700 |
void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len); |
|
1701 |
||
52992 | 1702 |
// Multiply add |
1703 |
void pmaddwd(XMMRegister dst, XMMRegister src); |
|
1704 |
void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1705 |
// Multiply add accumulate |
|
1706 |
void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1707 |
||
4430 | 1708 |
#ifndef _LP64 // no 32bit push/pop on amd64 |
1066 | 1709 |
void popl(Address dst); |
4430 | 1710 |
#endif |
1066 | 1711 |
|
1712 |
#ifdef _LP64 |
|
1713 |
void popq(Address dst); |
|
1714 |
#endif |
|
1715 |
||
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1716 |
void popcntl(Register dst, Address src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1717 |
void popcntl(Register dst, Register src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1718 |
|
49396
647ee5457fd1
8199603: Build failures after JDK-8199421 "Add support for vector popcount"
shade
parents:
49384
diff
changeset
|
1719 |
void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len); |
647ee5457fd1
8199603: Build failures after JDK-8199421 "Add support for vector popcount"
shade
parents:
49384
diff
changeset
|
1720 |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1721 |
#ifdef _LP64 |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1722 |
void popcntq(Register dst, Address src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1723 |
void popcntq(Register dst, Register src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1724 |
#endif |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1725 |
|
1066 | 1726 |
// Prefetches (SSE, SSE2, 3DNOW only) |
1727 |
||
1728 |
void prefetchnta(Address src); |
|
1729 |
void prefetchr(Address src); |
|
1730 |
void prefetcht0(Address src); |
|
1731 |
void prefetcht1(Address src); |
|
1732 |
void prefetcht2(Address src); |
|
1733 |
void prefetchw(Address src); |
|
1734 |
||
14132 | 1735 |
// Shuffle Bytes |
1736 |
void pshufb(XMMRegister dst, XMMRegister src); |
|
1737 |
void pshufb(XMMRegister dst, Address src); |
|
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38049
diff
changeset
|
1738 |
void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
14132 | 1739 |
|
1066 | 1740 |
// Shuffle Packed Doublewords |
1741 |
void pshufd(XMMRegister dst, XMMRegister src, int mode); |
|
1742 |
void pshufd(XMMRegister dst, Address src, int mode); |
|
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38049
diff
changeset
|
1743 |
void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len); |
1066 | 1744 |
|
1745 |
// Shuffle Packed Low Words |
|
1746 |
void pshuflw(XMMRegister dst, XMMRegister src, int mode); |
|
1747 |
void pshuflw(XMMRegister dst, Address src, int mode); |
|
1748 |
||
49614
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
1749 |
// Shuffle packed values at 128 bit granularity |
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
1750 |
void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len); |
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
1751 |
|
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1752 |
// Shift Right by bytes Logical DoubleQuadword Immediate |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1753 |
void psrldq(XMMRegister dst, int shift); |
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
1754 |
// Shift Left by bytes Logical DoubleQuadword Immediate |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
1755 |
void pslldq(XMMRegister dst, int shift); |
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1756 |
|
15117
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1757 |
// Logical Compare 128bit |
2348 | 1758 |
void ptest(XMMRegister dst, XMMRegister src); |
1759 |
void ptest(XMMRegister dst, Address src); |
|
15117
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1760 |
// Logical Compare 256bit |
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1761 |
void vptest(XMMRegister dst, XMMRegister src); |
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1762 |
void vptest(XMMRegister dst, Address src); |
2348 | 1763 |
|
1066 | 1764 |
// Interleave Low Bytes |
1765 |
void punpcklbw(XMMRegister dst, XMMRegister src); |
|
11427 | 1766 |
void punpcklbw(XMMRegister dst, Address src); |
1767 |
||
1768 |
// Interleave Low Doublewords |
|
1769 |
void punpckldq(XMMRegister dst, XMMRegister src); |
|
1770 |
void punpckldq(XMMRegister dst, Address src); |
|
1066 | 1771 |
|
13294 | 1772 |
// Interleave Low Quadwords |
1773 |
void punpcklqdq(XMMRegister dst, XMMRegister src); |
|
1774 |
||
4430 | 1775 |
#ifndef _LP64 // no 32bit push/pop on amd64 |
1066 | 1776 |
void pushl(Address src); |
4430 | 1777 |
#endif |
1066 | 1778 |
|
1779 |
void pushq(Address src); |
|
1780 |
||
1781 |
void rcll(Register dst, int imm8); |
|
1782 |
||
1783 |
void rclq(Register dst, int imm8); |
|
1784 |
||
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1785 |
void rcrq(Register dst, int imm8); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1786 |
|
33465 | 1787 |
void rcpps(XMMRegister dst, XMMRegister src); |
1788 |
||
1789 |
void rcpss(XMMRegister dst, XMMRegister src); |
|
1790 |
||
23491 | 1791 |
void rdtsc(); |
1792 |
||
1066 | 1793 |
void ret(int imm16); |
1 | 1794 |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1795 |
#ifdef _LP64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1796 |
void rorq(Register dst, int imm8); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1797 |
void rorxq(Register dst, Register src, int imm8); |
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38049
diff
changeset
|
1798 |
void rorxd(Register dst, Register src, int imm8); |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1799 |
#endif |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
25932
diff
changeset
|
1800 |
|
1 | 1801 |
void sahf(); |
1802 |
||
1066 | 1803 |
void sarl(Register dst, int imm8); |
1804 |
void sarl(Register dst); |
|
1805 |
||
1806 |
void sarq(Register dst, int imm8); |
|
1807 |
void sarq(Register dst); |
|
1808 |
||
1809 |
void sbbl(Address dst, int32_t imm32); |
|
1810 |
void sbbl(Register dst, int32_t imm32); |
|
1811 |
void sbbl(Register dst, Address src); |
|
1812 |
void sbbl(Register dst, Register src); |
|
1813 |
||
1814 |
void sbbq(Address dst, int32_t imm32); |
|
1815 |
void sbbq(Register dst, int32_t imm32); |
|
1816 |
void sbbq(Register dst, Address src); |
|
1817 |
void sbbq(Register dst, Register src); |
|
1818 |
||
1819 |
void setb(Condition cc, Register dst); |
|
1820 |
||
36555 | 1821 |
void palignr(XMMRegister dst, XMMRegister src, int imm8); |
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38049
diff
changeset
|
1822 |
void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len); |
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50577
diff
changeset
|
1823 |
void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38049
diff
changeset
|
1824 |
|
36555 | 1825 |
void pblendw(XMMRegister dst, XMMRegister src, int imm8); |
1826 |
||
1827 |
void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8); |
|
1828 |
void sha1nexte(XMMRegister dst, XMMRegister src); |
|
1829 |
void sha1msg1(XMMRegister dst, XMMRegister src); |
|
1830 |
void sha1msg2(XMMRegister dst, XMMRegister src); |
|
1831 |
// xmm0 is implicit additional source to the following instruction. |
|
1832 |
void sha256rnds2(XMMRegister dst, XMMRegister src); |
|
1833 |
void sha256msg1(XMMRegister dst, XMMRegister src); |
|
1834 |
void sha256msg2(XMMRegister dst, XMMRegister src); |
|
1835 |
||
1066 | 1836 |
void shldl(Register dst, Register src); |
33066 | 1837 |
void shldl(Register dst, Register src, int8_t imm8); |
1066 | 1838 |
|
1839 |
void shll(Register dst, int imm8); |
|
1840 |
void shll(Register dst); |
|
1841 |
||
1842 |
void shlq(Register dst, int imm8); |
|
1843 |
void shlq(Register dst); |
|
1844 |
||
1845 |
void shrdl(Register dst, Register src); |
|
1846 |
||
1847 |
void shrl(Register dst, int imm8); |
|
1848 |
void shrl(Register dst); |
|
1849 |
||
1850 |
void shrq(Register dst, int imm8); |
|
1851 |
void shrq(Register dst); |
|
1852 |
||
1853 |
void smovl(); // QQQ generic? |
|
1854 |
||
1855 |
// Compute Square Root of Scalar Double-Precision Floating-Point Value |
|
1856 |
void sqrtsd(XMMRegister dst, Address src); |
|
1857 |
void sqrtsd(XMMRegister dst, XMMRegister src); |
|
1858 |
||
58421
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
1859 |
void roundsd(XMMRegister dst, Address src, int32_t rmode); |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
1860 |
void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode); |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
1861 |
|
7433 | 1862 |
// Compute Square Root of Scalar Single-Precision Floating-Point Value |
1863 |
void sqrtss(XMMRegister dst, Address src); |
|
1864 |
void sqrtss(XMMRegister dst, XMMRegister src); |
|
1865 |
||
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1866 |
void std(); |
1066 | 1867 |
|
1868 |
void stmxcsr( Address dst ); |
|
1869 |
||
1870 |
void subl(Address dst, int32_t imm32); |
|
1871 |
void subl(Address dst, Register src); |
|
1872 |
void subl(Register dst, int32_t imm32); |
|
1873 |
void subl(Register dst, Address src); |
|
1874 |
void subl(Register dst, Register src); |
|
1875 |
||
1876 |
void subq(Address dst, int32_t imm32); |
|
1877 |
void subq(Address dst, Register src); |
|
1878 |
void subq(Register dst, int32_t imm32); |
|
1879 |
void subq(Register dst, Address src); |
|
1880 |
void subq(Register dst, Register src); |
|
1881 |
||
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
1882 |
// Force generation of a 4 byte immediate value even if it fits into 8bit |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
1883 |
void subl_imm32(Register dst, int32_t imm32); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
1884 |
void subq_imm32(Register dst, int32_t imm32); |
1066 | 1885 |
|
1886 |
// Subtract Scalar Double-Precision Floating-Point Values |
|
1887 |
void subsd(XMMRegister dst, Address src); |
|
1 | 1888 |
void subsd(XMMRegister dst, XMMRegister src); |
1889 |
||
1066 | 1890 |
// Subtract Scalar Single-Precision Floating-Point Values |
1891 |
void subss(XMMRegister dst, Address src); |
|
1892 |
void subss(XMMRegister dst, XMMRegister src); |
|
1893 |
||
1894 |
void testb(Register dst, int imm8); |
|
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35154
diff
changeset
|
1895 |
void testb(Address dst, int imm8); |
1066 | 1896 |
|
1897 |
void testl(Register dst, int32_t imm32); |
|
1898 |
void testl(Register dst, Register src); |
|
1899 |
void testl(Register dst, Address src); |
|
1900 |
||
1901 |
void testq(Register dst, int32_t imm32); |
|
1902 |
void testq(Register dst, Register src); |
|
50103
b99e90f885bf
8202993: Add support for x86 testptr/testq with register and address
pliden
parents:
49614
diff
changeset
|
1903 |
void testq(Register dst, Address src); |
1066 | 1904 |
|
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1905 |
// BMI - count trailing zeros |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1906 |
void tzcntl(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1907 |
void tzcntq(Register dst, Register src); |
1066 | 1908 |
|
1909 |
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
|
1910 |
void ucomisd(XMMRegister dst, Address src); |
|
1 | 1911 |
void ucomisd(XMMRegister dst, XMMRegister src); |
1912 |
||
1066 | 1913 |
// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1914 |
void ucomiss(XMMRegister dst, Address src); |
|
1915 |
void ucomiss(XMMRegister dst, XMMRegister src); |
|
1916 |
||
23491 | 1917 |
void xabort(int8_t imm8); |
1918 |
||
39419
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
1919 |
void xaddb(Address dst, Register src); |
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
1920 |
void xaddw(Address dst, Register src); |
1066 | 1921 |
void xaddl(Address dst, Register src); |
1922 |
void xaddq(Address dst, Register src); |
|
1923 |
||
23491 | 1924 |
void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); |
1925 |
||
39419
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
1926 |
void xchgb(Register reg, Address adr); |
cc993a4ab581
8157726: VarHandles/Unsafe should support sub-word atomic ops
shade
parents:
38239
diff
changeset
|
1927 |
void xchgw(Register reg, Address adr); |
1066 | 1928 |
void xchgl(Register reg, Address adr); |
1929 |
void xchgl(Register dst, Register src); |
|
1930 |
||
1931 |
void xchgq(Register reg, Address adr); |
|
1932 |
void xchgq(Register dst, Register src); |
|
1933 |
||
23491 | 1934 |
void xend(); |
1935 |
||
11427 | 1936 |
// Get Value of Extended Control Register |
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1937 |
void xgetbv(); |
11427 | 1938 |
|
1066 | 1939 |
void xorl(Register dst, int32_t imm32); |
1940 |
void xorl(Register dst, Address src); |
|
1941 |
void xorl(Register dst, Register src); |
|
1942 |
||
35154 | 1943 |
void xorb(Register dst, Address src); |
1944 |
||
1066 | 1945 |
void xorq(Register dst, Address src); |
1946 |
void xorq(Register dst, Register src); |
|
1947 |
||
1948 |
void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 |
|
11427 | 1949 |
|
13294 | 1950 |
// AVX 3-operands scalar instructions (encoded with VEX prefix) |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1951 |
|
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1952 |
void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1953 |
void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1954 |
void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1955 |
void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1956 |
void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1957 |
void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1958 |
void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1959 |
void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
41323 | 1960 |
void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
1961 |
void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
|
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1962 |
void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1963 |
void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1964 |
void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1965 |
void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1966 |
void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1967 |
void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1968 |
void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1969 |
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1970 |
|
54022
ff399127078a
8217561: X86: Add floating-point Math.min/max intrinsics
bsrbnd
parents:
53244
diff
changeset
|
1971 |
void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
ff399127078a
8217561: X86: Add floating-point Math.min/max intrinsics
bsrbnd
parents:
53244
diff
changeset
|
1972 |
void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
ff399127078a
8217561: X86: Add floating-point Math.min/max intrinsics
bsrbnd
parents:
53244
diff
changeset
|
1973 |
void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
ff399127078a
8217561: X86: Add floating-point Math.min/max intrinsics
bsrbnd
parents:
53244
diff
changeset
|
1974 |
void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
ff399127078a
8217561: X86: Add floating-point Math.min/max intrinsics
bsrbnd
parents:
53244
diff
changeset
|
1975 |
|
38239
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1976 |
void shlxl(Register dst, Register src1, Register src2); |
4d8b8ba74fea
8154974: AVX-512 equipped inflate, has_negatives & compress intrinsics
kvn
parents:
38138
diff
changeset
|
1977 |
void shlxq(Register dst, Register src1, Register src2); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1978 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1979 |
//====================VECTOR ARITHMETIC===================================== |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1980 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1981 |
// Add Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1982 |
void addpd(XMMRegister dst, XMMRegister src); |
35146 | 1983 |
void addpd(XMMRegister dst, Address src); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1984 |
void addps(XMMRegister dst, XMMRegister src); |
30624 | 1985 |
void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
1986 |
void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1987 |
void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
1988 |
void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1989 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1990 |
// Subtract Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1991 |
void subpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1992 |
void subps(XMMRegister dst, XMMRegister src); |
30624 | 1993 |
void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
1994 |
void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
1995 |
void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
1996 |
void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1997 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1998 |
// Multiply Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1999 |
void mulpd(XMMRegister dst, XMMRegister src); |
33089 | 2000 |
void mulpd(XMMRegister dst, Address src); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2001 |
void mulps(XMMRegister dst, XMMRegister src); |
30624 | 2002 |
void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2003 |
void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2004 |
void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2005 |
void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2006 |
|
46528 | 2007 |
void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2008 |
void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2009 |
void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2010 |
void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2011 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2012 |
// Divide Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2013 |
void divpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2014 |
void divps(XMMRegister dst, XMMRegister src); |
30624 | 2015 |
void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2016 |
void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2017 |
void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2018 |
void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2019 |
|
48089
22c9856fc2c2
8190800: Support vectorization of Math.sqrt() on floats
rlupusoru
parents:
47216
diff
changeset
|
2020 |
// Sqrt Packed Floating-Point Values |
32723
56534fb3d71a
8135028: support for vectorizing double precision sqrt
mcberg
parents:
31410
diff
changeset
|
2021 |
void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len); |
56534fb3d71a
8135028: support for vectorizing double precision sqrt
mcberg
parents:
31410
diff
changeset
|
2022 |
void vsqrtpd(XMMRegister dst, Address src, int vector_len); |
48089
22c9856fc2c2
8190800: Support vectorization of Math.sqrt() on floats
rlupusoru
parents:
47216
diff
changeset
|
2023 |
void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len); |
22c9856fc2c2
8190800: Support vectorization of Math.sqrt() on floats
rlupusoru
parents:
47216
diff
changeset
|
2024 |
void vsqrtps(XMMRegister dst, Address src, int vector_len); |
32723
56534fb3d71a
8135028: support for vectorizing double precision sqrt
mcberg
parents:
31410
diff
changeset
|
2025 |
|
58421
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
2026 |
// Round Packed Double precision value. |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
2027 |
void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
2028 |
void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len); |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
2029 |
void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
2030 |
void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len); |
6fc57e391539
8226721: Missing intrinsics for Math.ceil, floor, rint
neliasso
parents:
57804
diff
changeset
|
2031 |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2032 |
// Bitwise Logical AND of Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2033 |
void andpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2034 |
void andps(XMMRegister dst, XMMRegister src); |
30624 | 2035 |
void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2036 |
void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2037 |
void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2038 |
void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2039 |
|
33089 | 2040 |
void unpckhpd(XMMRegister dst, XMMRegister src); |
2041 |
void unpcklpd(XMMRegister dst, XMMRegister src); |
|
2042 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2043 |
// Bitwise Logical XOR of Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2044 |
void xorpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2045 |
void xorps(XMMRegister dst, XMMRegister src); |
30624 | 2046 |
void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2047 |
void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2048 |
void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2049 |
void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2050 |
|
30211 | 2051 |
// Add horizontal packed integers |
30624 | 2052 |
void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2053 |
void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
30211 | 2054 |
void phaddw(XMMRegister dst, XMMRegister src); |
2055 |
void phaddd(XMMRegister dst, XMMRegister src); |
|
2056 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2057 |
// Add packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2058 |
void paddb(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2059 |
void paddw(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2060 |
void paddd(XMMRegister dst, XMMRegister src); |
36555 | 2061 |
void paddd(XMMRegister dst, Address src); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2062 |
void paddq(XMMRegister dst, XMMRegister src); |
30624 | 2063 |
void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2064 |
void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2065 |
void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2066 |
void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2067 |
void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2068 |
void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2069 |
void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2070 |
void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2071 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2072 |
// Sub packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2073 |
void psubb(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2074 |
void psubw(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2075 |
void psubd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2076 |
void psubq(XMMRegister dst, XMMRegister src); |
30624 | 2077 |
void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2078 |
void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2079 |
void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2080 |
void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2081 |
void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2082 |
void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2083 |
void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2084 |
void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2085 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2086 |
// Multiply packed integers (only shorts and ints) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2087 |
void pmullw(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2088 |
void pmulld(XMMRegister dst, XMMRegister src); |
30624 | 2089 |
void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2090 |
void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2091 |
void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
|
2092 |
void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2093 |
void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
2094 |
void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2095 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2096 |
// Shift left packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2097 |
void psllw(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2098 |
void pslld(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2099 |
void psllq(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2100 |
void psllw(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2101 |
void pslld(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2102 |
void psllq(XMMRegister dst, XMMRegister shift); |
30624 | 2103 |
void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
2104 |
void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
|
2105 |
void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
|
2106 |
void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
2107 |
void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
2108 |
void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
52990
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
51996
diff
changeset
|
2109 |
void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2110 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2111 |
// Logical shift right packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2112 |
void psrlw(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2113 |
void psrld(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2114 |
void psrlq(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2115 |
void psrlw(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2116 |
void psrld(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2117 |
void psrlq(XMMRegister dst, XMMRegister shift); |
30624 | 2118 |
void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
2119 |
void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
|
2120 |
void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
|
2121 |
void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
2122 |
void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
2123 |
void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
52990
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
51996
diff
changeset
|
2124 |
void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
2125 |
void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
2126 |
void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2127 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2128 |
// Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2129 |
void psraw(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2130 |
void psrad(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2131 |
void psraw(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2132 |
void psrad(XMMRegister dst, XMMRegister shift); |
30624 | 2133 |
void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
2134 |
void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
|
2135 |
void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
2136 |
void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
54750 | 2137 |
void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len); |
2138 |
void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2139 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2140 |
// And packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2141 |
void pand(XMMRegister dst, XMMRegister src); |
30624 | 2142 |
void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2143 |
void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
2144 |
void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2145 |
|
33089 | 2146 |
// Andn packed integers |
2147 |
void pandn(XMMRegister dst, XMMRegister src); |
|
51857 | 2148 |
void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
33089 | 2149 |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2150 |
// Or packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2151 |
void por(XMMRegister dst, XMMRegister src); |
30624 | 2152 |
void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2153 |
void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
2154 |
void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2155 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2156 |
// Xor packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2157 |
void pxor(XMMRegister dst, XMMRegister src); |
30624 | 2158 |
void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
2159 |
void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
|
49614
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
2160 |
void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); |
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
2161 |
void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); |
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
2162 |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
2163 |
|
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2164 |
// vinserti forms |
36561
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
2165 |
void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
2166 |
void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); |
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2167 |
void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2168 |
void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2169 |
void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2170 |
|
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2171 |
// vinsertf forms |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2172 |
void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2173 |
void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2174 |
void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2175 |
void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2176 |
void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2177 |
void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2178 |
|
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2179 |
// vextracti forms |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2180 |
void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8); |
36561
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
2181 |
void vextracti128(Address dst, XMMRegister src, uint8_t imm8); |
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2182 |
void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2183 |
void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2184 |
void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8); |
36561
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
2185 |
void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8); |
51857 | 2186 |
void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8); |
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2187 |
|
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2188 |
// vextractf forms |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2189 |
void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2190 |
void vextractf128(Address dst, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2191 |
void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2192 |
void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8); |
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2193 |
void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8); |
36561
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
2194 |
void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8); |
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
2195 |
void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8); |
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2196 |
|
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2197 |
// xmm/mem sourced byte/word/dword/qword replicate |
51857 | 2198 |
void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len); |
2199 |
void vpbroadcastb(XMMRegister dst, Address src, int vector_len); |
|
2200 |
void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len); |
|
2201 |
void vpbroadcastw(XMMRegister dst, Address src, int vector_len); |
|
2202 |
void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len); |
|
2203 |
void vpbroadcastd(XMMRegister dst, Address src, int vector_len); |
|
2204 |
void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len); |
|
2205 |
void vpbroadcastq(XMMRegister dst, Address src, int vector_len); |
|
31410 | 2206 |
|
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50577
diff
changeset
|
2207 |
void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50577
diff
changeset
|
2208 |
void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50577
diff
changeset
|
2209 |
|
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2210 |
// scalar single/double precision replicate |
51857 | 2211 |
void vpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len); |
2212 |
void vpbroadcastss(XMMRegister dst, Address src, int vector_len); |
|
2213 |
void vpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len); |
|
2214 |
void vpbroadcastsd(XMMRegister dst, Address src, int vector_len); |
|
31410 | 2215 |
|
37293
c010188d360f
8151003: Remove nds->is_valid() checks from assembler_x86.cpp
mcberg
parents:
36837
diff
changeset
|
2216 |
// gpr sourced byte/word/dword/qword replicate |
31410 | 2217 |
void evpbroadcastb(XMMRegister dst, Register src, int vector_len); |
2218 |
void evpbroadcastw(XMMRegister dst, Register src, int vector_len); |
|
2219 |
void evpbroadcastd(XMMRegister dst, Register src, int vector_len); |
|
2220 |
void evpbroadcastq(XMMRegister dst, Register src, int vector_len); |
|
30624 | 2221 |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
2222 |
void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
2223 |
|
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
2224 |
// Carry-Less Multiplication Quadword |
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
23491
diff
changeset
|
2225 |
void pclmulqdq(XMMRegister dst, XMMRegister src, int mask); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
2226 |
void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); |
49614
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49396
diff
changeset
|
2227 |
void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
2228 |
// AVX instruction which is used to clear upper 128 bits of YMM registers and |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
2229 |
// to avoid transaction penalty between AVX and SSE states. There is no |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
2230 |
// penalty if legacy SSE instructions are encoded using VEX prefix because |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
2231 |
// they always clear upper 128 bits. It should be used before calling |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
2232 |
// runtime code and native libraries. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
2233 |
void vzeroupper(); |
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2234 |
|
48309 | 2235 |
// AVX support for vectorized conditional move (float/double). The following two instructions used only coupled. |
33469
30f4811eded0
8139340: SuperWord enhancement to support vector conditional move (CMovVD) on Intel AVX cpu
iveresov
parents:
33465
diff
changeset
|
2236 |
void cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len); |
42039 | 2237 |
void blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); |
48309 | 2238 |
void cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len); |
2239 |
void blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); |
|
42039 | 2240 |
void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len); |
33469
30f4811eded0
8139340: SuperWord enhancement to support vector conditional move (CMovVD) on Intel AVX cpu
iveresov
parents:
33465
diff
changeset
|
2241 |
|
11427 | 2242 |
protected: |
2243 |
// Next instructions require address alignment 16 bytes SSE mode. |
|
2244 |
// They should be called only from corresponding MacroAssembler instructions. |
|
2245 |
void andpd(XMMRegister dst, Address src); |
|
2246 |
void andps(XMMRegister dst, Address src); |
|
2247 |
void xorpd(XMMRegister dst, Address src); |
|
2248 |
void xorps(XMMRegister dst, Address src); |
|
2249 |
||
1 | 2250 |
}; |
2251 |
||
34162 | 2252 |
// The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions. |
2253 |
// Specific set functions are for specialized use, else defaults or whatever was supplied to object construction |
|
2254 |
// are applied. |
|
2255 |
class InstructionAttr { |
|
2256 |
public: |
|
2257 |
InstructionAttr( |
|
36066 | 2258 |
int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX |
2259 |
bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true |
|
2260 |
bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX |
|
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51857
diff
changeset
|
2261 |
bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used |
36066 | 2262 |
bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX |
34162 | 2263 |
: |
2264 |
_avx_vector_len(vector_len), |
|
2265 |
_rex_vex_w(rex_vex_w), |
|
38049 | 2266 |
_rex_vex_w_reverted(false), |
34162 | 2267 |
_legacy_mode(legacy_mode), |
2268 |
_no_reg_mask(no_reg_mask), |
|
2269 |
_uses_vl(uses_vl), |
|
2270 |
_tuple_type(Assembler::EVEX_ETUP), |
|
2271 |
_input_size_in_bits(Assembler::EVEX_NObit), |
|
2272 |
_is_evex_instruction(false), |
|
2273 |
_evex_encoding(0), |
|
42014
cc32438a1003
8167987: change merge context to clear for mask register usage model
mcberg
parents:
41323
diff
changeset
|
2274 |
_is_clear_context(true), |
34162 | 2275 |
_is_extended_context(false), |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51857
diff
changeset
|
2276 |
_embedded_opmask_register_specifier(0), // hard code k0 |
51333
f6641fcf7b7e
8208670: Compiler changes to allow enabling -Wreorder
tschatzl
parents:
50860
diff
changeset
|
2277 |
_current_assembler(NULL) { |
34162 | 2278 |
if (UseAVX < 3) _legacy_mode = true; |
2279 |
} |
|
2280 |
||
2281 |
~InstructionAttr() { |
|
2282 |
if (_current_assembler != NULL) { |
|
2283 |
_current_assembler->clear_attributes(); |
|
2284 |
} |
|
2285 |
_current_assembler = NULL; |
|
2286 |
} |
|
2287 |
||
2288 |
private: |
|
2289 |
int _avx_vector_len; |
|
2290 |
bool _rex_vex_w; |
|
38049 | 2291 |
bool _rex_vex_w_reverted; |
34162 | 2292 |
bool _legacy_mode; |
2293 |
bool _no_reg_mask; |
|
2294 |
bool _uses_vl; |
|
2295 |
int _tuple_type; |
|
2296 |
int _input_size_in_bits; |
|
2297 |
bool _is_evex_instruction; |
|
2298 |
int _evex_encoding; |
|
2299 |
bool _is_clear_context; |
|
2300 |
bool _is_extended_context; |
|
38138
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2301 |
int _embedded_opmask_register_specifier; |
34162 | 2302 |
|
2303 |
Assembler *_current_assembler; |
|
2304 |
||
2305 |
public: |
|
2306 |
// query functions for field accessors |
|
2307 |
int get_vector_len(void) const { return _avx_vector_len; } |
|
2308 |
bool is_rex_vex_w(void) const { return _rex_vex_w; } |
|
38049 | 2309 |
bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; } |
34162 | 2310 |
bool is_legacy_mode(void) const { return _legacy_mode; } |
2311 |
bool is_no_reg_mask(void) const { return _no_reg_mask; } |
|
2312 |
bool uses_vl(void) const { return _uses_vl; } |
|
2313 |
int get_tuple_type(void) const { return _tuple_type; } |
|
2314 |
int get_input_size(void) const { return _input_size_in_bits; } |
|
2315 |
int is_evex_instruction(void) const { return _is_evex_instruction; } |
|
2316 |
int get_evex_encoding(void) const { return _evex_encoding; } |
|
2317 |
bool is_clear_context(void) const { return _is_clear_context; } |
|
2318 |
bool is_extended_context(void) const { return _is_extended_context; } |
|
38138
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2319 |
int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; } |
34162 | 2320 |
|
2321 |
// Set the vector len manually |
|
2322 |
void set_vector_len(int vector_len) { _avx_vector_len = vector_len; } |
|
2323 |
||
38049 | 2324 |
// Set revert rex_vex_w for avx encoding |
2325 |
void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; } |
|
2326 |
||
2327 |
// Set rex_vex_w based on state |
|
2328 |
void set_rex_vex_w(bool state) { _rex_vex_w = state; } |
|
2329 |
||
34162 | 2330 |
// Set the instruction to be encoded in AVX mode |
2331 |
void set_is_legacy_mode(void) { _legacy_mode = true; } |
|
2332 |
||
2333 |
// Set the current instuction to be encoded as an EVEX instuction |
|
2334 |
void set_is_evex_instruction(void) { _is_evex_instruction = true; } |
|
2335 |
||
2336 |
// Internal encoding data used in compressed immediate offset programming |
|
2337 |
void set_evex_encoding(int value) { _evex_encoding = value; } |
|
2338 |
||
2339 |
// Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components |
|
42014
cc32438a1003
8167987: change merge context to clear for mask register usage model
mcberg
parents:
41323
diff
changeset
|
2340 |
void reset_is_clear_context(void) { _is_clear_context = false; } |
34162 | 2341 |
|
2342 |
// Map back to current asembler so that we can manage object level assocation |
|
2343 |
void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; } |
|
2344 |
||
2345 |
// Address modifiers used for compressed displacement calculation |
|
2346 |
void set_address_attributes(int tuple_type, int input_size_in_bits) { |
|
2347 |
if (VM_Version::supports_evex()) { |
|
2348 |
_tuple_type = tuple_type; |
|
2349 |
_input_size_in_bits = input_size_in_bits; |
|
2350 |
} |
|
2351 |
} |
|
2352 |
||
38138
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2353 |
// Set embedded opmask register specifier. |
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2354 |
void set_embedded_opmask_register_specifier(KRegister mask) { |
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2355 |
_embedded_opmask_register_specifier = (*mask).encoding() & 0x7; |
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2356 |
} |
8514e24123c8
8154975: Update for vectorizedMismatch with AVX512
vdeshpande
parents:
38135
diff
changeset
|
2357 |
|
34162 | 2358 |
}; |
2359 |
||
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
52992
diff
changeset
|
2360 |
#endif // CPU_X86_ASSEMBLER_X86_HPP |