author | iveresov |
Wed, 12 Mar 2014 11:24:26 -0700 | |
changeset 23220 | fc827339dc37 |
parent 21105 | 47618ee96ed5 |
child 23491 | f690330b10b9 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
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#define CPU_X86_VM_ASSEMBLER_X86_HPP |
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#include "asm/register.hpp" |
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class BiasedLockingCounters; |
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||
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// Contains all the definitions needed for x86 assembly code generation. |
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||
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// Calling convention |
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class Argument VALUE_OBJ_CLASS_SPEC { |
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public: |
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enum { |
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#ifdef _LP64 |
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#ifdef _WIN64 |
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n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
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#else |
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n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
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#endif // _WIN64 |
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n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
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n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
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#else |
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n_register_parameters = 0 // 0 registers used to pass arguments |
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#endif // _LP64 |
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}; |
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}; |
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||
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||
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#ifdef _LP64 |
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// Symbolically name the register arguments used by the c calling convention. |
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// Windows is different from linux/solaris. So much for standards... |
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||
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#ifdef _WIN64 |
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||
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REGISTER_DECLARATION(Register, c_rarg0, rcx); |
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REGISTER_DECLARATION(Register, c_rarg1, rdx); |
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REGISTER_DECLARATION(Register, c_rarg2, r8); |
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REGISTER_DECLARATION(Register, c_rarg3, r9); |
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||
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REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
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#else |
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||
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REGISTER_DECLARATION(Register, c_rarg0, rdi); |
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REGISTER_DECLARATION(Register, c_rarg1, rsi); |
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REGISTER_DECLARATION(Register, c_rarg2, rdx); |
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REGISTER_DECLARATION(Register, c_rarg3, rcx); |
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REGISTER_DECLARATION(Register, c_rarg4, r8); |
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REGISTER_DECLARATION(Register, c_rarg5, r9); |
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REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
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REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); |
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REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); |
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REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); |
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REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); |
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#endif // _WIN64 |
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||
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// Symbolically name the register arguments used by the Java calling convention. |
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// We have control over the convention for java so we can do what we please. |
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// What pleases us is to offset the java calling convention so that when |
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// we call a suitable jni method the arguments are lined up and we don't |
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// have to do little shuffling. A suitable jni method is non-static and a |
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// small number of arguments (two fewer args on windows) |
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// |
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// |-------------------------------------------------------| |
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// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
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// |-------------------------------------------------------| |
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// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
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// | rdi rsi rdx rcx r8 r9 | solaris/linux |
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// |-------------------------------------------------------| |
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// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
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// |-------------------------------------------------------| |
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||
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REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
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REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
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REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
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// Windows runs out of register args here |
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#ifdef _WIN64 |
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REGISTER_DECLARATION(Register, j_rarg3, rdi); |
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REGISTER_DECLARATION(Register, j_rarg4, rsi); |
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#else |
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REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
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REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
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#endif /* _WIN64 */ |
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REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
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REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); |
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REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); |
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REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); |
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REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); |
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REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); |
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REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
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REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
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REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
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REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
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#else |
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// rscratch1 will apear in 32bit code that is dead but of course must compile |
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// Using noreg ensures if the dead code is incorrectly live and executed it |
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// will cause an assertion failure |
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#define rscratch1 noreg |
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#define rscratch2 noreg |
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#endif // _LP64 |
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// JSR 292 fixed register usages: |
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REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); |
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// Address is an abstraction used to represent a memory location |
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// using any of the amd64 addressing modes with one object. |
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// |
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// Note: A register location is represented via a Register, not |
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// via an address for efficiency & simplicity reasons. |
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class ArrayAddress; |
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||
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class Address VALUE_OBJ_CLASS_SPEC { |
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public: |
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enum ScaleFactor { |
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no_scale = -1, |
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times_1 = 0, |
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times_2 = 1, |
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times_4 = 2, |
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times_8 = 3, |
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times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) |
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}; |
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static ScaleFactor times(int size) { |
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assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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if (size == 8) return times_8; |
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if (size == 4) return times_4; |
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if (size == 2) return times_2; |
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return times_1; |
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} |
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static int scale_size(ScaleFactor scale) { |
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assert(scale != no_scale, ""); |
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assert(((1 << (int)times_1) == 1 && |
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(1 << (int)times_2) == 2 && |
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(1 << (int)times_4) == 4 && |
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(1 << (int)times_8) == 8), ""); |
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return (1 << (int)scale); |
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} |
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private: |
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Register _base; |
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Register _index; |
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ScaleFactor _scale; |
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int _disp; |
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RelocationHolder _rspec; |
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// Easily misused constructors make them private |
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// %%% can we make these go away? |
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NOT_LP64(Address(address loc, RelocationHolder spec);) |
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Address(int disp, address loc, relocInfo::relocType rtype); |
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Address(int disp, address loc, RelocationHolder spec); |
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public: |
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int disp() { return _disp; } |
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// creation |
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Address() |
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: _base(noreg), |
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_index(noreg), |
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_scale(no_scale), |
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_disp(0) { |
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} |
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// No default displacement otherwise Register can be implicitly |
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// converted to 0(Register) which is quite a different animal. |
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208 |
Address(Register base, int disp) |
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: _base(base), |
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_index(noreg), |
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_scale(no_scale), |
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_disp(disp) { |
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} |
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Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
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: _base (base), |
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_index(index), |
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_scale(scale), |
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_disp (disp) { |
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assert(!index->is_valid() == (scale == Address::no_scale), |
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"inconsistent address"); |
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} |
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Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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: _base (base), |
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_index(index.register_or_noreg()), |
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_scale(scale), |
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_disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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if (!index.is_register()) scale = Address::no_scale; |
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assert(!_index->is_valid() == (scale == Address::no_scale), |
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"inconsistent address"); |
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} |
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Address plus_disp(int disp) const { |
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Address a = (*this); |
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a._disp += disp; |
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return a; |
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} |
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Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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Address a = (*this); |
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a._disp += disp.constant_or_zero() * scale_size(scale); |
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242 |
if (disp.is_register()) { |
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assert(!a.index()->is_valid(), "competing indexes"); |
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a._index = disp.as_register(); |
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a._scale = scale; |
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} |
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return a; |
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} |
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bool is_same_address(Address a) const { |
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// disregard _rspec |
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return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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} |
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1 | 254 |
// The following two overloads are used in connection with the |
255 |
// ByteSize type (see sizes.hpp). They simplify the use of |
|
256 |
// ByteSize'd arguments in assembly code. Note that their equivalent |
|
257 |
// for the optimized build are the member functions with int disp |
|
258 |
// argument since ByteSize is mapped to an int type in that case. |
|
259 |
// |
|
260 |
// Note: DO NOT introduce similar overloaded functions for WordSize |
|
261 |
// arguments as in the optimized mode, both ByteSize and WordSize |
|
262 |
// are mapped to the same type and thus the compiler cannot make a |
|
263 |
// distinction anymore (=> compiler errors). |
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264 |
||
265 |
#ifdef ASSERT |
|
266 |
Address(Register base, ByteSize disp) |
|
267 |
: _base(base), |
|
268 |
_index(noreg), |
|
269 |
_scale(no_scale), |
|
270 |
_disp(in_bytes(disp)) { |
|
271 |
} |
|
272 |
||
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Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
|
274 |
: _base(base), |
|
275 |
_index(index), |
|
276 |
_scale(scale), |
|
277 |
_disp(in_bytes(disp)) { |
|
278 |
assert(!index->is_valid() == (scale == Address::no_scale), |
|
279 |
"inconsistent address"); |
|
280 |
} |
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Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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|
283 |
: _base (base), |
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|
284 |
_index(index.register_or_noreg()), |
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|
285 |
_scale(scale), |
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diff
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|
286 |
_disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
09c7f703773b
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|
287 |
if (!index.is_register()) scale = Address::no_scale; |
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|
288 |
assert(!_index->is_valid() == (scale == Address::no_scale), |
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|
289 |
"inconsistent address"); |
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|
290 |
} |
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|
291 |
|
1 | 292 |
#endif // ASSERT |
293 |
||
294 |
// accessors |
|
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|
295 |
bool uses(Register reg) const { return _base == reg || _index == reg; } |
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|
296 |
Register base() const { return _base; } |
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|
297 |
Register index() const { return _index; } |
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|
298 |
ScaleFactor scale() const { return _scale; } |
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|
299 |
int disp() const { return _disp; } |
1 | 300 |
|
301 |
// Convert the raw encoding form into the form expected by the constructor for |
|
302 |
// Address. An index of 4 (rsp) corresponds to having no index, so convert |
|
303 |
// that to noreg for the Address constructor. |
|
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|
304 |
static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); |
1 | 305 |
|
306 |
static Address make_array(ArrayAddress); |
|
307 |
||
308 |
private: |
|
309 |
bool base_needs_rex() const { |
|
310 |
return _base != noreg && _base->encoding() >= 8; |
|
311 |
} |
|
312 |
||
313 |
bool index_needs_rex() const { |
|
314 |
return _index != noreg &&_index->encoding() >= 8; |
|
315 |
} |
|
316 |
||
317 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
|
318 |
||
319 |
friend class Assembler; |
|
320 |
friend class MacroAssembler; |
|
321 |
friend class LIR_Assembler; // base/index/scale/disp |
|
322 |
}; |
|
323 |
||
324 |
// |
|
325 |
// AddressLiteral has been split out from Address because operands of this type |
|
326 |
// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
|
327 |
// the few instructions that need to deal with address literals are unique and the |
|
328 |
// MacroAssembler does not have to implement every instruction in the Assembler |
|
329 |
// in order to search for address literals that may need special handling depending |
|
330 |
// on the instruction and the platform. As small step on the way to merging i486/amd64 |
|
331 |
// directories. |
|
332 |
// |
|
333 |
class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
|
334 |
friend class ArrayAddress; |
|
335 |
RelocationHolder _rspec; |
|
336 |
// Typically we use AddressLiterals we want to use their rval |
|
337 |
// However in some situations we want the lval (effect address) of the item. |
|
338 |
// We provide a special factory for making those lvals. |
|
339 |
bool _is_lval; |
|
340 |
||
341 |
// If the target is far we'll need to load the ea of this to |
|
342 |
// a register to reach it. Otherwise if near we can do rip |
|
343 |
// relative addressing. |
|
344 |
||
345 |
address _target; |
|
346 |
||
347 |
protected: |
|
348 |
// creation |
|
349 |
AddressLiteral() |
|
350 |
: _is_lval(false), |
|
351 |
_target(NULL) |
|
352 |
{} |
|
353 |
||
354 |
public: |
|
355 |
||
356 |
||
357 |
AddressLiteral(address target, relocInfo::relocType rtype); |
|
358 |
||
359 |
AddressLiteral(address target, RelocationHolder const& rspec) |
|
360 |
: _rspec(rspec), |
|
361 |
_is_lval(false), |
|
362 |
_target(target) |
|
363 |
{} |
|
364 |
||
365 |
AddressLiteral addr() { |
|
366 |
AddressLiteral ret = *this; |
|
367 |
ret._is_lval = true; |
|
368 |
return ret; |
|
369 |
} |
|
370 |
||
371 |
||
372 |
private: |
|
373 |
||
374 |
address target() { return _target; } |
|
375 |
bool is_lval() { return _is_lval; } |
|
376 |
||
377 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
|
378 |
const RelocationHolder& rspec() const { return _rspec; } |
|
379 |
||
380 |
friend class Assembler; |
|
381 |
friend class MacroAssembler; |
|
382 |
friend class Address; |
|
383 |
friend class LIR_Assembler; |
|
384 |
}; |
|
385 |
||
386 |
// Convience classes |
|
387 |
class RuntimeAddress: public AddressLiteral { |
|
388 |
||
389 |
public: |
|
390 |
||
391 |
RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
|
392 |
||
393 |
}; |
|
394 |
||
395 |
class ExternalAddress: public AddressLiteral { |
|
9111
c100c09c66f2
6777083: assert(target != __null,"must not be null")
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parents:
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|
396 |
private: |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
397 |
static relocInfo::relocType reloc_for_target(address target) { |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
398 |
// Sometimes ExternalAddress is used for values which aren't |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
399 |
// exactly addresses, like the card table base. |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
400 |
// external_word_type can't be used for values in the first page |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
401 |
// so just skip the reloc in that case. |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
402 |
return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
403 |
} |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
404 |
|
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
405 |
public: |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
406 |
|
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
407 |
ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
1 | 408 |
|
409 |
}; |
|
410 |
||
411 |
class InternalAddress: public AddressLiteral { |
|
412 |
||
413 |
public: |
|
414 |
||
415 |
InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
|
416 |
||
417 |
}; |
|
418 |
||
419 |
// x86 can do array addressing as a single operation since disp can be an absolute |
|
420 |
// address amd64 can't. We create a class that expresses the concept but does extra |
|
421 |
// magic on amd64 to get the final result |
|
422 |
||
423 |
class ArrayAddress VALUE_OBJ_CLASS_SPEC { |
|
424 |
private: |
|
425 |
||
426 |
AddressLiteral _base; |
|
427 |
Address _index; |
|
428 |
||
429 |
public: |
|
430 |
||
431 |
ArrayAddress() {}; |
|
432 |
ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
|
433 |
AddressLiteral base() { return _base; } |
|
434 |
Address index() { return _index; } |
|
435 |
||
436 |
}; |
|
437 |
||
1066 | 438 |
const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
1 | 439 |
|
440 |
// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction |
|
441 |
// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write |
|
442 |
// is what you get. The Assembler is generating code into a CodeBuffer. |
|
443 |
||
444 |
class Assembler : public AbstractAssembler { |
|
445 |
friend class AbstractAssembler; // for the non-virtual hack |
|
446 |
friend class LIR_Assembler; // as_Address() |
|
1066 | 447 |
friend class StubGenerator; |
1 | 448 |
|
449 |
public: |
|
450 |
enum Condition { // The x86 condition codes used for conditional jumps/moves. |
|
451 |
zero = 0x4, |
|
452 |
notZero = 0x5, |
|
453 |
equal = 0x4, |
|
454 |
notEqual = 0x5, |
|
455 |
less = 0xc, |
|
456 |
lessEqual = 0xe, |
|
457 |
greater = 0xf, |
|
458 |
greaterEqual = 0xd, |
|
459 |
below = 0x2, |
|
460 |
belowEqual = 0x6, |
|
461 |
above = 0x7, |
|
462 |
aboveEqual = 0x3, |
|
463 |
overflow = 0x0, |
|
464 |
noOverflow = 0x1, |
|
465 |
carrySet = 0x2, |
|
466 |
carryClear = 0x3, |
|
467 |
negative = 0x8, |
|
468 |
positive = 0x9, |
|
469 |
parity = 0xa, |
|
470 |
noParity = 0xb |
|
471 |
}; |
|
472 |
||
473 |
enum Prefix { |
|
474 |
// segment overrides |
|
475 |
CS_segment = 0x2e, |
|
476 |
SS_segment = 0x36, |
|
477 |
DS_segment = 0x3e, |
|
478 |
ES_segment = 0x26, |
|
479 |
FS_segment = 0x64, |
|
480 |
GS_segment = 0x65, |
|
481 |
||
482 |
REX = 0x40, |
|
483 |
||
484 |
REX_B = 0x41, |
|
485 |
REX_X = 0x42, |
|
486 |
REX_XB = 0x43, |
|
487 |
REX_R = 0x44, |
|
488 |
REX_RB = 0x45, |
|
489 |
REX_RX = 0x46, |
|
490 |
REX_RXB = 0x47, |
|
491 |
||
492 |
REX_W = 0x48, |
|
493 |
||
494 |
REX_WB = 0x49, |
|
495 |
REX_WX = 0x4A, |
|
496 |
REX_WXB = 0x4B, |
|
497 |
REX_WR = 0x4C, |
|
498 |
REX_WRB = 0x4D, |
|
499 |
REX_WRX = 0x4E, |
|
11427 | 500 |
REX_WRXB = 0x4F, |
501 |
||
502 |
VEX_3bytes = 0xC4, |
|
503 |
VEX_2bytes = 0xC5 |
|
504 |
}; |
|
505 |
||
506 |
enum VexPrefix { |
|
507 |
VEX_B = 0x20, |
|
508 |
VEX_X = 0x40, |
|
509 |
VEX_R = 0x80, |
|
510 |
VEX_W = 0x80 |
|
511 |
}; |
|
512 |
||
513 |
enum VexSimdPrefix { |
|
514 |
VEX_SIMD_NONE = 0x0, |
|
515 |
VEX_SIMD_66 = 0x1, |
|
516 |
VEX_SIMD_F3 = 0x2, |
|
517 |
VEX_SIMD_F2 = 0x3 |
|
518 |
}; |
|
519 |
||
520 |
enum VexOpcode { |
|
521 |
VEX_OPCODE_NONE = 0x0, |
|
522 |
VEX_OPCODE_0F = 0x1, |
|
523 |
VEX_OPCODE_0F_38 = 0x2, |
|
524 |
VEX_OPCODE_0F_3A = 0x3 |
|
1 | 525 |
}; |
526 |
||
527 |
enum WhichOperand { |
|
528 |
// input to locate_operand, and format code for relocations |
|
1066 | 529 |
imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
1 | 530 |
disp32_operand = 1, // embedded 32-bit displacement or address |
531 |
call32_operand = 2, // embedded 32-bit self-relative displacement |
|
1066 | 532 |
#ifndef _LP64 |
1 | 533 |
_WhichOperand_limit = 3 |
1066 | 534 |
#else |
535 |
narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop |
|
536 |
_WhichOperand_limit = 4 |
|
537 |
#endif |
|
1 | 538 |
}; |
539 |
||
1066 | 540 |
|
541 |
||
542 |
// NOTE: The general philopsophy of the declarations here is that 64bit versions |
|
543 |
// of instructions are freely declared without the need for wrapping them an ifdef. |
|
544 |
// (Some dangerous instructions are ifdef's out of inappropriate jvm's.) |
|
545 |
// In the .cpp file the implementations are wrapped so that they are dropped out |
|
15432 | 546 |
// of the resulting jvm. This is done mostly to keep the footprint of MINIMAL |
1066 | 547 |
// to the size it was prior to merging up the 32bit and 64bit assemblers. |
548 |
// |
|
549 |
// This does mean you'll get a linker/runtime error if you use a 64bit only instruction |
|
550 |
// in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. |
|
551 |
||
552 |
private: |
|
553 |
||
554 |
||
555 |
// 64bit prefixes |
|
556 |
int prefix_and_encode(int reg_enc, bool byteinst = false); |
|
557 |
int prefixq_and_encode(int reg_enc); |
|
558 |
||
559 |
int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); |
|
560 |
int prefixq_and_encode(int dst_enc, int src_enc); |
|
561 |
||
562 |
void prefix(Register reg); |
|
563 |
void prefix(Address adr); |
|
564 |
void prefixq(Address adr); |
|
565 |
||
566 |
void prefix(Address adr, Register reg, bool byteinst = false); |
|
11427 | 567 |
void prefix(Address adr, XMMRegister reg); |
1066 | 568 |
void prefixq(Address adr, Register reg); |
11427 | 569 |
void prefixq(Address adr, XMMRegister reg); |
1066 | 570 |
|
571 |
void prefetch_prefix(Address src); |
|
572 |
||
11427 | 573 |
void rex_prefix(Address adr, XMMRegister xreg, |
574 |
VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
|
575 |
int rex_prefix_and_encode(int dst_enc, int src_enc, |
|
576 |
VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
|
577 |
||
578 |
void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, |
|
579 |
int nds_enc, VexSimdPrefix pre, VexOpcode opc, |
|
580 |
bool vector256); |
|
581 |
||
582 |
void vex_prefix(Address adr, int nds_enc, int xreg_enc, |
|
583 |
VexSimdPrefix pre, VexOpcode opc, |
|
584 |
bool vex_w, bool vector256); |
|
585 |
||
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
586 |
void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
587 |
VexSimdPrefix pre, bool vector256 = false) { |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
588 |
int dst_enc = dst->encoding(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
589 |
int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
590 |
vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); |
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
591 |
} |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
592 |
|
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
593 |
void vex_prefix_0F38(Register dst, Register nds, Address src) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
594 |
bool vex_w = false; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
595 |
bool vector256 = false; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
596 |
vex_prefix(src, nds->encoding(), dst->encoding(), |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
597 |
VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
598 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
599 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
600 |
void vex_prefix_0F38_q(Register dst, Register nds, Address src) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
601 |
bool vex_w = true; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
602 |
bool vector256 = false; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
603 |
vex_prefix(src, nds->encoding(), dst->encoding(), |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
604 |
VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
605 |
} |
11427 | 606 |
int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
607 |
VexSimdPrefix pre, VexOpcode opc, |
|
608 |
bool vex_w, bool vector256); |
|
609 |
||
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
610 |
int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
611 |
bool vex_w = false; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
612 |
bool vector256 = false; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
613 |
return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
614 |
VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
615 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
616 |
int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
617 |
bool vex_w = true; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
618 |
bool vector256 = false; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
619 |
return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
620 |
VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
621 |
} |
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
622 |
int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
623 |
VexSimdPrefix pre, bool vector256 = false, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
624 |
VexOpcode opc = VEX_OPCODE_0F) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
625 |
int src_enc = src->encoding(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
626 |
int dst_enc = dst->encoding(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
627 |
int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
628 |
return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); |
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
629 |
} |
11427 | 630 |
|
631 |
void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, |
|
632 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, |
|
633 |
bool rex_w = false, bool vector256 = false); |
|
634 |
||
635 |
void simd_prefix(XMMRegister dst, Address src, |
|
636 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
637 |
simd_prefix(dst, xnoreg, src, pre, opc); |
|
638 |
} |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
639 |
|
11427 | 640 |
void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
641 |
simd_prefix(src, dst, pre); |
|
642 |
} |
|
643 |
void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, |
|
644 |
VexSimdPrefix pre) { |
|
645 |
bool rex_w = true; |
|
646 |
simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); |
|
647 |
} |
|
648 |
||
649 |
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
|
650 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, |
|
651 |
bool rex_w = false, bool vector256 = false); |
|
652 |
||
653 |
// Move/convert 32-bit integer value. |
|
654 |
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, |
|
655 |
VexSimdPrefix pre) { |
|
656 |
// It is OK to cast from Register to XMMRegister to pass argument here |
|
657 |
// since only encoding is used in simd_prefix_and_encode() and number of |
|
658 |
// Gen and Xmm registers are the same. |
|
659 |
return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); |
|
660 |
} |
|
661 |
int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { |
|
662 |
return simd_prefix_and_encode(dst, xnoreg, src, pre); |
|
663 |
} |
|
664 |
int simd_prefix_and_encode(Register dst, XMMRegister src, |
|
665 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
666 |
return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); |
|
667 |
} |
|
668 |
||
669 |
// Move/convert 64-bit integer value. |
|
670 |
int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, |
|
671 |
VexSimdPrefix pre) { |
|
672 |
bool rex_w = true; |
|
673 |
return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); |
|
674 |
} |
|
675 |
int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { |
|
676 |
return simd_prefix_and_encode_q(dst, xnoreg, src, pre); |
|
677 |
} |
|
678 |
int simd_prefix_and_encode_q(Register dst, XMMRegister src, |
|
679 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
680 |
bool rex_w = true; |
|
681 |
return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); |
|
682 |
} |
|
683 |
||
1066 | 684 |
// Helper functions for groups of instructions |
685 |
void emit_arith_b(int op1, int op2, Register dst, int imm8); |
|
686 |
||
687 |
void emit_arith(int op1, int op2, Register dst, int32_t imm32); |
|
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
688 |
// Force generation of a 4 byte immediate value even if it fits into 8bit |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
689 |
void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); |
1066 | 690 |
void emit_arith(int op1, int op2, Register dst, Register src); |
691 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
692 |
void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
693 |
void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
694 |
void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
695 |
void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
696 |
void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
697 |
Address src, VexSimdPrefix pre, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
698 |
void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
699 |
XMMRegister src, VexSimdPrefix pre, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
700 |
|
1066 | 701 |
void emit_operand(Register reg, |
702 |
Register base, Register index, Address::ScaleFactor scale, |
|
703 |
int disp, |
|
704 |
RelocationHolder const& rspec, |
|
705 |
int rip_relative_correction = 0); |
|
706 |
||
707 |
void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); |
|
708 |
||
709 |
// operands that only take the original 32bit registers |
|
710 |
void emit_operand32(Register reg, Address adr); |
|
711 |
||
712 |
void emit_operand(XMMRegister reg, |
|
713 |
Register base, Register index, Address::ScaleFactor scale, |
|
714 |
int disp, |
|
715 |
RelocationHolder const& rspec); |
|
716 |
||
717 |
void emit_operand(XMMRegister reg, Address adr); |
|
718 |
||
719 |
void emit_operand(MMXRegister reg, Address adr); |
|
720 |
||
721 |
// workaround gcc (3.2.1-7) bug |
|
722 |
void emit_operand(Address adr, MMXRegister reg); |
|
723 |
||
724 |
||
725 |
// Immediate-to-memory forms |
|
726 |
void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); |
|
727 |
||
728 |
void emit_farith(int b1, int b2, int i); |
|
729 |
||
730 |
||
731 |
protected: |
|
732 |
#ifdef ASSERT |
|
733 |
void check_relocation(RelocationHolder const& rspec, int format); |
|
734 |
#endif |
|
735 |
||
736 |
void emit_data(jint data, relocInfo::relocType rtype, int format); |
|
737 |
void emit_data(jint data, RelocationHolder const& rspec, int format); |
|
738 |
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
|
739 |
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
|
740 |
||
741 |
bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); |
|
742 |
||
743 |
// These are all easily abused and hence protected |
|
744 |
||
745 |
// 32BIT ONLY SECTION |
|
746 |
#ifndef _LP64 |
|
747 |
// Make these disappear in 64bit mode since they would never be correct |
|
748 |
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
749 |
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
750 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
751 |
void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
1066 | 752 |
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
753 |
||
754 |
void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
755 |
#else |
|
756 |
// 64BIT ONLY SECTION |
|
757 |
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
758 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
759 |
void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
760 |
void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
761 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
762 |
void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
763 |
void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
1066 | 764 |
#endif // _LP64 |
765 |
||
766 |
// These are unique in that we are ensured by the caller that the 32bit |
|
767 |
// relative in these instructions will always be able to reach the potentially |
|
768 |
// 64bit address described by entry. Since they can take a 64bit address they |
|
769 |
// don't have the 32 suffix like the other instructions in this class. |
|
770 |
||
771 |
void call_literal(address entry, RelocationHolder const& rspec); |
|
772 |
void jmp_literal(address entry, RelocationHolder const& rspec); |
|
773 |
||
774 |
// Avoid using directly section |
|
775 |
// Instructions in this section are actually usable by anyone without danger |
|
776 |
// of failure but have performance issues that are addressed my enhanced |
|
777 |
// instructions which will do the proper thing base on the particular cpu. |
|
778 |
// We protect them because we don't trust you... |
|
779 |
||
780 |
// Don't use next inc() and dec() methods directly. INC & DEC instructions |
|
781 |
// could cause a partial flag stall since they don't set CF flag. |
|
782 |
// Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
|
783 |
// which call inc() & dec() or add() & sub() in accordance with |
|
784 |
// the product flag UseIncDec value. |
|
785 |
||
786 |
void decl(Register dst); |
|
787 |
void decl(Address dst); |
|
788 |
void decq(Register dst); |
|
789 |
void decq(Address dst); |
|
790 |
||
791 |
void incl(Register dst); |
|
792 |
void incl(Address dst); |
|
793 |
void incq(Register dst); |
|
794 |
void incq(Address dst); |
|
795 |
||
796 |
// New cpus require use of movsd and movss to avoid partial register stall |
|
797 |
// when loading from memory. But for old Opteron use movlpd instead of movsd. |
|
798 |
// The selection is done in MacroAssembler::movdbl() and movflt(). |
|
799 |
||
800 |
// Move Scalar Single-Precision Floating-Point Values |
|
801 |
void movss(XMMRegister dst, Address src); |
|
802 |
void movss(XMMRegister dst, XMMRegister src); |
|
803 |
void movss(Address dst, XMMRegister src); |
|
804 |
||
805 |
// Move Scalar Double-Precision Floating-Point Values |
|
806 |
void movsd(XMMRegister dst, Address src); |
|
807 |
void movsd(XMMRegister dst, XMMRegister src); |
|
808 |
void movsd(Address dst, XMMRegister src); |
|
809 |
void movlpd(XMMRegister dst, Address src); |
|
810 |
||
811 |
// New cpus require use of movaps and movapd to avoid partial register stall |
|
812 |
// when moving between registers. |
|
813 |
void movaps(XMMRegister dst, XMMRegister src); |
|
814 |
void movapd(XMMRegister dst, XMMRegister src); |
|
815 |
||
816 |
// End avoid using directly |
|
817 |
||
818 |
||
819 |
// Instruction prefixes |
|
820 |
void prefix(Prefix p); |
|
821 |
||
1 | 822 |
public: |
823 |
||
824 |
// Creation |
|
825 |
Assembler(CodeBuffer* code) : AbstractAssembler(code) {} |
|
826 |
||
827 |
// Decoding |
|
828 |
static address locate_operand(address inst, WhichOperand which); |
|
829 |
static address locate_next_instruction(address inst); |
|
830 |
||
1066 | 831 |
// Utilities |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8494
diff
changeset
|
832 |
static bool is_polling_page_far() NOT_LP64({ return false;}); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8494
diff
changeset
|
833 |
|
1066 | 834 |
// Generic instructions |
835 |
// Does 32bit or 64bit as needed for the platform. In some sense these |
|
836 |
// belong in macro assembler but there is no need for both varieties to exist |
|
837 |
||
838 |
void lea(Register dst, Address src); |
|
839 |
||
840 |
void mov(Register dst, Register src); |
|
841 |
||
842 |
void pusha(); |
|
843 |
void popa(); |
|
844 |
||
845 |
void pushf(); |
|
846 |
void popf(); |
|
847 |
||
848 |
void push(int32_t imm32); |
|
849 |
||
850 |
void push(Register src); |
|
851 |
||
852 |
void pop(Register dst); |
|
853 |
||
854 |
// These are dummies to prevent surprise implicit conversions to Register |
|
855 |
void push(void* v); |
|
856 |
void pop(void* v); |
|
857 |
||
858 |
// These do register sized moves/scans |
|
859 |
void rep_mov(); |
|
15114
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14631
diff
changeset
|
860 |
void rep_stos(); |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14631
diff
changeset
|
861 |
void rep_stosb(); |
1066 | 862 |
void repne_scan(); |
863 |
#ifdef _LP64 |
|
864 |
void repne_scanl(); |
|
865 |
#endif |
|
866 |
||
867 |
// Vanilla instructions in lexical order |
|
868 |
||
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
869 |
void adcl(Address dst, int32_t imm32); |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
870 |
void adcl(Address dst, Register src); |
1066 | 871 |
void adcl(Register dst, int32_t imm32); |
1 | 872 |
void adcl(Register dst, Address src); |
873 |
void adcl(Register dst, Register src); |
|
874 |
||
1066 | 875 |
void adcq(Register dst, int32_t imm32); |
876 |
void adcq(Register dst, Address src); |
|
877 |
void adcq(Register dst, Register src); |
|
878 |
||
879 |
void addl(Address dst, int32_t imm32); |
|
1 | 880 |
void addl(Address dst, Register src); |
1066 | 881 |
void addl(Register dst, int32_t imm32); |
1 | 882 |
void addl(Register dst, Address src); |
883 |
void addl(Register dst, Register src); |
|
884 |
||
1066 | 885 |
void addq(Address dst, int32_t imm32); |
886 |
void addq(Address dst, Register src); |
|
887 |
void addq(Register dst, int32_t imm32); |
|
888 |
void addq(Register dst, Address src); |
|
889 |
void addq(Register dst, Register src); |
|
890 |
||
1 | 891 |
void addr_nop_4(); |
892 |
void addr_nop_5(); |
|
893 |
void addr_nop_7(); |
|
894 |
void addr_nop_8(); |
|
895 |
||
1066 | 896 |
// Add Scalar Double-Precision Floating-Point Values |
897 |
void addsd(XMMRegister dst, Address src); |
|
898 |
void addsd(XMMRegister dst, XMMRegister src); |
|
899 |
||
900 |
// Add Scalar Single-Precision Floating-Point Values |
|
901 |
void addss(XMMRegister dst, Address src); |
|
902 |
void addss(XMMRegister dst, XMMRegister src); |
|
903 |
||
14132 | 904 |
// AES instructions |
905 |
void aesdec(XMMRegister dst, Address src); |
|
906 |
void aesdec(XMMRegister dst, XMMRegister src); |
|
907 |
void aesdeclast(XMMRegister dst, Address src); |
|
908 |
void aesdeclast(XMMRegister dst, XMMRegister src); |
|
909 |
void aesenc(XMMRegister dst, Address src); |
|
910 |
void aesenc(XMMRegister dst, XMMRegister src); |
|
911 |
void aesenclast(XMMRegister dst, Address src); |
|
912 |
void aesenclast(XMMRegister dst, XMMRegister src); |
|
913 |
||
914 |
||
11427 | 915 |
void andl(Address dst, int32_t imm32); |
1066 | 916 |
void andl(Register dst, int32_t imm32); |
917 |
void andl(Register dst, Address src); |
|
918 |
void andl(Register dst, Register src); |
|
919 |
||
10006 | 920 |
void andq(Address dst, int32_t imm32); |
1066 | 921 |
void andq(Register dst, int32_t imm32); |
922 |
void andq(Register dst, Address src); |
|
923 |
void andq(Register dst, Register src); |
|
924 |
||
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
925 |
// BMI instructions |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
926 |
void andnl(Register dst, Register src1, Register src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
927 |
void andnl(Register dst, Register src1, Address src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
928 |
void andnq(Register dst, Register src1, Register src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
929 |
void andnq(Register dst, Register src1, Address src2); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
930 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
931 |
void blsil(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
932 |
void blsil(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
933 |
void blsiq(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
934 |
void blsiq(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
935 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
936 |
void blsmskl(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
937 |
void blsmskl(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
938 |
void blsmskq(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
939 |
void blsmskq(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
940 |
|
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
941 |
void blsrl(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
942 |
void blsrl(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
943 |
void blsrq(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
944 |
void blsrq(Register dst, Address src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
945 |
|
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
946 |
void bsfl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
947 |
void bsrl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
948 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
949 |
#ifdef _LP64 |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
950 |
void bsfq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
951 |
void bsrq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
952 |
#endif |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
953 |
|
1066 | 954 |
void bswapl(Register reg); |
955 |
||
956 |
void bswapq(Register reg); |
|
957 |
||
1 | 958 |
void call(Label& L, relocInfo::relocType rtype); |
959 |
void call(Register reg); // push pc; pc <- reg |
|
960 |
void call(Address adr); // push pc; pc <- adr |
|
961 |
||
1066 | 962 |
void cdql(); |
963 |
||
964 |
void cdqq(); |
|
965 |
||
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
966 |
void cld(); |
1066 | 967 |
|
968 |
void clflush(Address adr); |
|
969 |
||
970 |
void cmovl(Condition cc, Register dst, Register src); |
|
971 |
void cmovl(Condition cc, Register dst, Address src); |
|
972 |
||
973 |
void cmovq(Condition cc, Register dst, Register src); |
|
974 |
void cmovq(Condition cc, Register dst, Address src); |
|
975 |
||
976 |
||
977 |
void cmpb(Address dst, int imm8); |
|
978 |
||
979 |
void cmpl(Address dst, int32_t imm32); |
|
980 |
||
981 |
void cmpl(Register dst, int32_t imm32); |
|
982 |
void cmpl(Register dst, Register src); |
|
983 |
void cmpl(Register dst, Address src); |
|
984 |
||
985 |
void cmpq(Address dst, int32_t imm32); |
|
986 |
void cmpq(Address dst, Register src); |
|
987 |
||
988 |
void cmpq(Register dst, int32_t imm32); |
|
989 |
void cmpq(Register dst, Register src); |
|
990 |
void cmpq(Register dst, Address src); |
|
991 |
||
992 |
// these are dummies used to catch attempting to convert NULL to Register |
|
993 |
void cmpl(Register dst, void* junk); // dummy |
|
994 |
void cmpq(Register dst, void* junk); // dummy |
|
995 |
||
996 |
void cmpw(Address dst, int imm16); |
|
997 |
||
998 |
void cmpxchg8 (Address adr); |
|
999 |
||
1000 |
void cmpxchgl(Register reg, Address adr); |
|
1001 |
||
1002 |
void cmpxchgq(Register reg, Address adr); |
|
1003 |
||
1004 |
// Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
|
1005 |
void comisd(XMMRegister dst, Address src); |
|
11427 | 1006 |
void comisd(XMMRegister dst, XMMRegister src); |
1066 | 1007 |
|
1008 |
// Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
|
1009 |
void comiss(XMMRegister dst, Address src); |
|
11427 | 1010 |
void comiss(XMMRegister dst, XMMRegister src); |
1066 | 1011 |
|
1012 |
// Identify processor type and features |
|
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1013 |
void cpuid(); |
1066 | 1014 |
|
1015 |
// Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value |
|
1016 |
void cvtsd2ss(XMMRegister dst, XMMRegister src); |
|
11427 | 1017 |
void cvtsd2ss(XMMRegister dst, Address src); |
1066 | 1018 |
|
1019 |
// Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value |
|
1020 |
void cvtsi2sdl(XMMRegister dst, Register src); |
|
11427 | 1021 |
void cvtsi2sdl(XMMRegister dst, Address src); |
1066 | 1022 |
void cvtsi2sdq(XMMRegister dst, Register src); |
11427 | 1023 |
void cvtsi2sdq(XMMRegister dst, Address src); |
1066 | 1024 |
|
1025 |
// Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value |
|
1026 |
void cvtsi2ssl(XMMRegister dst, Register src); |
|
11427 | 1027 |
void cvtsi2ssl(XMMRegister dst, Address src); |
1066 | 1028 |
void cvtsi2ssq(XMMRegister dst, Register src); |
11427 | 1029 |
void cvtsi2ssq(XMMRegister dst, Address src); |
1066 | 1030 |
|
1031 |
// Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value |
|
1032 |
void cvtdq2pd(XMMRegister dst, XMMRegister src); |
|
1033 |
||
1034 |
// Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value |
|
1035 |
void cvtdq2ps(XMMRegister dst, XMMRegister src); |
|
1036 |
||
1037 |
// Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value |
|
1038 |
void cvtss2sd(XMMRegister dst, XMMRegister src); |
|
11427 | 1039 |
void cvtss2sd(XMMRegister dst, Address src); |
1066 | 1040 |
|
1041 |
// Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer |
|
1042 |
void cvttsd2sil(Register dst, Address src); |
|
1043 |
void cvttsd2sil(Register dst, XMMRegister src); |
|
1044 |
void cvttsd2siq(Register dst, XMMRegister src); |
|
1045 |
||
1046 |
// Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer |
|
1047 |
void cvttss2sil(Register dst, XMMRegister src); |
|
1048 |
void cvttss2siq(Register dst, XMMRegister src); |
|
1049 |
||
1050 |
// Divide Scalar Double-Precision Floating-Point Values |
|
1051 |
void divsd(XMMRegister dst, Address src); |
|
1052 |
void divsd(XMMRegister dst, XMMRegister src); |
|
1053 |
||
1054 |
// Divide Scalar Single-Precision Floating-Point Values |
|
1055 |
void divss(XMMRegister dst, Address src); |
|
1056 |
void divss(XMMRegister dst, XMMRegister src); |
|
1057 |
||
1058 |
void emms(); |
|
1059 |
||
1060 |
void fabs(); |
|
1061 |
||
1062 |
void fadd(int i); |
|
1063 |
||
1064 |
void fadd_d(Address src); |
|
1065 |
void fadd_s(Address src); |
|
1066 |
||
1067 |
// "Alternate" versions of x87 instructions place result down in FPU |
|
1068 |
// stack instead of on TOS |
|
1069 |
||
1070 |
void fadda(int i); // "alternate" fadd |
|
1071 |
void faddp(int i = 1); |
|
1072 |
||
1073 |
void fchs(); |
|
1074 |
||
1075 |
void fcom(int i); |
|
1076 |
||
1077 |
void fcomp(int i = 1); |
|
1078 |
void fcomp_d(Address src); |
|
1079 |
void fcomp_s(Address src); |
|
1080 |
||
1081 |
void fcompp(); |
|
1082 |
||
1083 |
void fcos(); |
|
1084 |
||
1085 |
void fdecstp(); |
|
1086 |
||
1087 |
void fdiv(int i); |
|
1088 |
void fdiv_d(Address src); |
|
1089 |
void fdivr_s(Address src); |
|
1090 |
void fdiva(int i); // "alternate" fdiv |
|
1091 |
void fdivp(int i = 1); |
|
1092 |
||
1093 |
void fdivr(int i); |
|
1094 |
void fdivr_d(Address src); |
|
1095 |
void fdiv_s(Address src); |
|
1096 |
||
1097 |
void fdivra(int i); // "alternate" reversed fdiv |
|
1098 |
||
1099 |
void fdivrp(int i = 1); |
|
1100 |
||
1101 |
void ffree(int i = 0); |
|
1102 |
||
1103 |
void fild_d(Address adr); |
|
1104 |
void fild_s(Address adr); |
|
1105 |
||
1106 |
void fincstp(); |
|
1107 |
||
1108 |
void finit(); |
|
1109 |
||
1110 |
void fist_s (Address adr); |
|
1111 |
void fistp_d(Address adr); |
|
1112 |
void fistp_s(Address adr); |
|
1113 |
||
1114 |
void fld1(); |
|
1115 |
||
1116 |
void fld_d(Address adr); |
|
1117 |
void fld_s(Address adr); |
|
1118 |
void fld_s(int index); |
|
1119 |
void fld_x(Address adr); // extended-precision (80-bit) format |
|
1120 |
||
1121 |
void fldcw(Address src); |
|
1122 |
||
1123 |
void fldenv(Address src); |
|
1124 |
||
1125 |
void fldlg2(); |
|
1126 |
||
1127 |
void fldln2(); |
|
1128 |
||
1129 |
void fldz(); |
|
1130 |
||
1131 |
void flog(); |
|
1132 |
void flog10(); |
|
1133 |
||
1134 |
void fmul(int i); |
|
1135 |
||
1136 |
void fmul_d(Address src); |
|
1137 |
void fmul_s(Address src); |
|
1138 |
||
1139 |
void fmula(int i); // "alternate" fmul |
|
1140 |
||
1141 |
void fmulp(int i = 1); |
|
1142 |
||
1143 |
void fnsave(Address dst); |
|
1144 |
||
1145 |
void fnstcw(Address src); |
|
1146 |
||
1147 |
void fnstsw_ax(); |
|
1148 |
||
1149 |
void fprem(); |
|
1150 |
void fprem1(); |
|
1151 |
||
1152 |
void frstor(Address src); |
|
1153 |
||
1154 |
void fsin(); |
|
1155 |
||
1156 |
void fsqrt(); |
|
1157 |
||
1158 |
void fst_d(Address adr); |
|
1159 |
void fst_s(Address adr); |
|
1160 |
||
1161 |
void fstp_d(Address adr); |
|
1162 |
void fstp_d(int index); |
|
1163 |
void fstp_s(Address adr); |
|
1164 |
void fstp_x(Address adr); // extended-precision (80-bit) format |
|
1165 |
||
1166 |
void fsub(int i); |
|
1167 |
void fsub_d(Address src); |
|
1168 |
void fsub_s(Address src); |
|
1169 |
||
1170 |
void fsuba(int i); // "alternate" fsub |
|
1171 |
||
1172 |
void fsubp(int i = 1); |
|
1173 |
||
1174 |
void fsubr(int i); |
|
1175 |
void fsubr_d(Address src); |
|
1176 |
void fsubr_s(Address src); |
|
1177 |
||
1178 |
void fsubra(int i); // "alternate" reversed fsub |
|
1179 |
||
1180 |
void fsubrp(int i = 1); |
|
1181 |
||
1182 |
void ftan(); |
|
1183 |
||
1184 |
void ftst(); |
|
1185 |
||
1186 |
void fucomi(int i = 1); |
|
1187 |
void fucomip(int i = 1); |
|
1188 |
||
1189 |
void fwait(); |
|
1190 |
||
1191 |
void fxch(int i = 1); |
|
1192 |
||
1193 |
void fxrstor(Address src); |
|
1194 |
||
1195 |
void fxsave(Address dst); |
|
1196 |
||
1197 |
void fyl2x(); |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11791
diff
changeset
|
1198 |
void frndint(); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11791
diff
changeset
|
1199 |
void f2xm1(); |
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
11791
diff
changeset
|
1200 |
void fldl2e(); |
1066 | 1201 |
|
1202 |
void hlt(); |
|
1203 |
||
1204 |
void idivl(Register src); |
|
7121 | 1205 |
void divl(Register src); // Unsigned division |
1066 | 1206 |
|
1207 |
void idivq(Register src); |
|
1208 |
||
1209 |
void imull(Register dst, Register src); |
|
1210 |
void imull(Register dst, Register src, int value); |
|
21105
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1211 |
void imull(Register dst, Address src); |
1066 | 1212 |
|
1213 |
void imulq(Register dst, Register src); |
|
1214 |
void imulq(Register dst, Register src, int value); |
|
21105
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1215 |
#ifdef _LP64 |
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1216 |
void imulq(Register dst, Address src); |
47618ee96ed5
8026844: Various Math functions needs intrinsification
rbackman
parents:
18507
diff
changeset
|
1217 |
#endif |
1066 | 1218 |
|
1 | 1219 |
|
1220 |
// jcc is the generic conditional branch generator to run- |
|
1221 |
// time routines, jcc is used for branches to labels. jcc |
|
1222 |
// takes a branch opcode (cc) and a label (L) and generates |
|
1223 |
// either a backward branch or a forward branch and links it |
|
1224 |
// to the label fixup chain. Usage: |
|
1225 |
// |
|
1226 |
// Label L; // unbound label |
|
1227 |
// jcc(cc, L); // forward branch to unbound label |
|
1228 |
// bind(L); // bind label to the current pc |
|
1229 |
// jcc(cc, L); // backward branch to bound label |
|
1230 |
// bind(L); // illegal: a label may be bound only once |
|
1231 |
// |
|
1232 |
// Note: The same Label can be used for forward and backward branches |
|
1233 |
// but it may be bound only once. |
|
1234 |
||
10264 | 1235 |
void jcc(Condition cc, Label& L, bool maybe_short = true); |
1 | 1236 |
|
1237 |
// Conditional jump to a 8-bit offset to L. |
|
1238 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
1239 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
1240 |
// will occur. |
|
1241 |
void jccb(Condition cc, Label& L); |
|
1242 |
||
1066 | 1243 |
void jmp(Address entry); // pc <- entry |
1244 |
||
1245 |
// Label operations & relative jumps (PPUM Appendix D) |
|
10264 | 1246 |
void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
1066 | 1247 |
|
1248 |
void jmp(Register entry); // pc <- entry |
|
1249 |
||
1250 |
// Unconditional 8-bit offset jump to L. |
|
1251 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
1252 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
1253 |
// will occur. |
|
1254 |
void jmpb(Label& L); |
|
1255 |
||
1256 |
void ldmxcsr( Address src ); |
|
1257 |
||
1258 |
void leal(Register dst, Address src); |
|
1259 |
||
1260 |
void leaq(Register dst, Address src); |
|
1261 |
||
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1262 |
void lfence(); |
1066 | 1263 |
|
1264 |
void lock(); |
|
1265 |
||
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1266 |
void lzcntl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1267 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1268 |
#ifdef _LP64 |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1269 |
void lzcntq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1270 |
#endif |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1271 |
|
1066 | 1272 |
enum Membar_mask_bits { |
1273 |
StoreStore = 1 << 3, |
|
1274 |
LoadStore = 1 << 2, |
|
1275 |
StoreLoad = 1 << 1, |
|
1276 |
LoadLoad = 1 << 0 |
|
1277 |
}; |
|
1278 |
||
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1279 |
// Serializes memory and blows flags |
1066 | 1280 |
void membar(Membar_mask_bits order_constraint) { |
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1281 |
if (os::is_MP()) { |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1282 |
// We only have to handle StoreLoad |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1283 |
if (order_constraint & StoreLoad) { |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1284 |
// All usable chips support "locked" instructions which suffice |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1285 |
// as barriers, and are much faster than the alternative of |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1286 |
// using cpuid instruction. We use here a locked add [esp],0. |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1287 |
// This is conveniently otherwise a no-op except for blowing |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1288 |
// flags. |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1289 |
// Any change to this code may need to revisit other places in |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1290 |
// the code where this idiom is used, in particular the |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1291 |
// orderAccess code. |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1292 |
lock(); |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1293 |
addl(Address(rsp, 0), 0);// Assert the lock# signal here |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1294 |
} |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1295 |
} |
1066 | 1296 |
} |
1297 |
||
1298 |
void mfence(); |
|
1299 |
||
1300 |
// Moves |
|
1301 |
||
1302 |
void mov64(Register dst, int64_t imm64); |
|
1303 |
||
1304 |
void movb(Address dst, Register src); |
|
1305 |
void movb(Address dst, int imm8); |
|
1306 |
void movb(Register dst, Address src); |
|
1307 |
||
1308 |
void movdl(XMMRegister dst, Register src); |
|
1309 |
void movdl(Register dst, XMMRegister src); |
|
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1310 |
void movdl(XMMRegister dst, Address src); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1311 |
void movdl(Address dst, XMMRegister src); |
1066 | 1312 |
|
1313 |
// Move Double Quadword |
|
1314 |
void movdq(XMMRegister dst, Register src); |
|
1315 |
void movdq(Register dst, XMMRegister src); |
|
1316 |
||
1317 |
// Move Aligned Double Quadword |
|
1318 |
void movdqa(XMMRegister dst, XMMRegister src); |
|
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1319 |
void movdqa(XMMRegister dst, Address src); |
1066 | 1320 |
|
1437 | 1321 |
// Move Unaligned Double Quadword |
1322 |
void movdqu(Address dst, XMMRegister src); |
|
1323 |
void movdqu(XMMRegister dst, Address src); |
|
1324 |
void movdqu(XMMRegister dst, XMMRegister src); |
|
1325 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1326 |
// Move Unaligned 256bit Vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1327 |
void vmovdqu(Address dst, XMMRegister src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1328 |
void vmovdqu(XMMRegister dst, Address src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1329 |
void vmovdqu(XMMRegister dst, XMMRegister src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1330 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1331 |
// Move lower 64bit to high 64bit in 128bit register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1332 |
void movlhps(XMMRegister dst, XMMRegister src); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1333 |
|
1066 | 1334 |
void movl(Register dst, int32_t imm32); |
1335 |
void movl(Address dst, int32_t imm32); |
|
1336 |
void movl(Register dst, Register src); |
|
1337 |
void movl(Register dst, Address src); |
|
1338 |
void movl(Address dst, Register src); |
|
1339 |
||
1340 |
// These dummies prevent using movl from converting a zero (like NULL) into Register |
|
1341 |
// by giving the compiler two choices it can't resolve |
|
1342 |
||
1343 |
void movl(Address dst, void* junk); |
|
1344 |
void movl(Register dst, void* junk); |
|
1345 |
||
1346 |
#ifdef _LP64 |
|
1347 |
void movq(Register dst, Register src); |
|
1348 |
void movq(Register dst, Address src); |
|
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
1349 |
void movq(Address dst, Register src); |
1066 | 1350 |
#endif |
1351 |
||
1352 |
void movq(Address dst, MMXRegister src ); |
|
1353 |
void movq(MMXRegister dst, Address src ); |
|
1354 |
||
1355 |
#ifdef _LP64 |
|
1356 |
// These dummies prevent using movq from converting a zero (like NULL) into Register |
|
1357 |
// by giving the compiler two choices it can't resolve |
|
1358 |
||
1359 |
void movq(Address dst, void* dummy); |
|
1360 |
void movq(Register dst, void* dummy); |
|
1361 |
#endif |
|
1362 |
||
1363 |
// Move Quadword |
|
1364 |
void movq(Address dst, XMMRegister src); |
|
1365 |
void movq(XMMRegister dst, Address src); |
|
1366 |
||
1367 |
void movsbl(Register dst, Address src); |
|
1368 |
void movsbl(Register dst, Register src); |
|
1369 |
||
1370 |
#ifdef _LP64 |
|
2150 | 1371 |
void movsbq(Register dst, Address src); |
1372 |
void movsbq(Register dst, Register src); |
|
1373 |
||
1066 | 1374 |
// Move signed 32bit immediate to 64bit extending sign |
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
1375 |
void movslq(Address dst, int32_t imm64); |
1066 | 1376 |
void movslq(Register dst, int32_t imm64); |
1377 |
||
1378 |
void movslq(Register dst, Address src); |
|
1379 |
void movslq(Register dst, Register src); |
|
1380 |
void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous |
|
1381 |
#endif |
|
1382 |
||
1383 |
void movswl(Register dst, Address src); |
|
1384 |
void movswl(Register dst, Register src); |
|
1385 |
||
2150 | 1386 |
#ifdef _LP64 |
1387 |
void movswq(Register dst, Address src); |
|
1388 |
void movswq(Register dst, Register src); |
|
1389 |
#endif |
|
1390 |
||
1066 | 1391 |
void movw(Address dst, int imm16); |
1392 |
void movw(Register dst, Address src); |
|
1393 |
void movw(Address dst, Register src); |
|
1394 |
||
1395 |
void movzbl(Register dst, Address src); |
|
1396 |
void movzbl(Register dst, Register src); |
|
1397 |
||
2150 | 1398 |
#ifdef _LP64 |
1399 |
void movzbq(Register dst, Address src); |
|
1400 |
void movzbq(Register dst, Register src); |
|
1401 |
#endif |
|
1402 |
||
1066 | 1403 |
void movzwl(Register dst, Address src); |
1404 |
void movzwl(Register dst, Register src); |
|
1405 |
||
2150 | 1406 |
#ifdef _LP64 |
1407 |
void movzwq(Register dst, Address src); |
|
1408 |
void movzwq(Register dst, Register src); |
|
1409 |
#endif |
|
1410 |
||
1066 | 1411 |
void mull(Address src); |
1412 |
void mull(Register src); |
|
1413 |
||
1414 |
// Multiply Scalar Double-Precision Floating-Point Values |
|
1415 |
void mulsd(XMMRegister dst, Address src); |
|
1416 |
void mulsd(XMMRegister dst, XMMRegister src); |
|
1417 |
||
1418 |
// Multiply Scalar Single-Precision Floating-Point Values |
|
1419 |
void mulss(XMMRegister dst, Address src); |
|
1420 |
void mulss(XMMRegister dst, XMMRegister src); |
|
1421 |
||
1422 |
void negl(Register dst); |
|
1423 |
||
1424 |
#ifdef _LP64 |
|
1425 |
void negq(Register dst); |
|
1426 |
#endif |
|
1427 |
||
1428 |
void nop(int i = 1); |
|
1429 |
||
1430 |
void notl(Register dst); |
|
1431 |
||
1432 |
#ifdef _LP64 |
|
1433 |
void notq(Register dst); |
|
1434 |
#endif |
|
1435 |
||
1436 |
void orl(Address dst, int32_t imm32); |
|
1437 |
void orl(Register dst, int32_t imm32); |
|
1438 |
void orl(Register dst, Address src); |
|
1439 |
void orl(Register dst, Register src); |
|
1440 |
||
1441 |
void orq(Address dst, int32_t imm32); |
|
1442 |
void orq(Register dst, int32_t imm32); |
|
1443 |
void orq(Register dst, Address src); |
|
1444 |
void orq(Register dst, Register src); |
|
1445 |
||
11427 | 1446 |
// Pack with unsigned saturation |
1447 |
void packuswb(XMMRegister dst, XMMRegister src); |
|
1448 |
void packuswb(XMMRegister dst, Address src); |
|
15242
695bb216be99
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
15117
diff
changeset
|
1449 |
void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
695bb216be99
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
15117
diff
changeset
|
1450 |
|
695bb216be99
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
15117
diff
changeset
|
1451 |
// Pemutation of 64bit words |
695bb216be99
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
15117
diff
changeset
|
1452 |
void vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256); |
11427 | 1453 |
|
2348 | 1454 |
// SSE4.2 string instructions |
1455 |
void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); |
|
1456 |
void pcmpestri(XMMRegister xmm1, Address src, int imm8); |
|
1457 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1458 |
// SSE 4.1 extract |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1459 |
void pextrd(Register dst, XMMRegister src, int imm8); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1460 |
void pextrq(Register dst, XMMRegister src, int imm8); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1461 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1462 |
// SSE 4.1 insert |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1463 |
void pinsrd(XMMRegister dst, Register src, int imm8); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1464 |
void pinsrq(XMMRegister dst, Register src, int imm8); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1465 |
|
11427 | 1466 |
// SSE4.1 packed move |
1467 |
void pmovzxbw(XMMRegister dst, XMMRegister src); |
|
1468 |
void pmovzxbw(XMMRegister dst, Address src); |
|
1469 |
||
4430 | 1470 |
#ifndef _LP64 // no 32bit push/pop on amd64 |
1066 | 1471 |
void popl(Address dst); |
4430 | 1472 |
#endif |
1066 | 1473 |
|
1474 |
#ifdef _LP64 |
|
1475 |
void popq(Address dst); |
|
1476 |
#endif |
|
1477 |
||
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1478 |
void popcntl(Register dst, Address src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1479 |
void popcntl(Register dst, Register src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1480 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1481 |
#ifdef _LP64 |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1482 |
void popcntq(Register dst, Address src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1483 |
void popcntq(Register dst, Register src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1484 |
#endif |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1485 |
|
1066 | 1486 |
// Prefetches (SSE, SSE2, 3DNOW only) |
1487 |
||
1488 |
void prefetchnta(Address src); |
|
1489 |
void prefetchr(Address src); |
|
1490 |
void prefetcht0(Address src); |
|
1491 |
void prefetcht1(Address src); |
|
1492 |
void prefetcht2(Address src); |
|
1493 |
void prefetchw(Address src); |
|
1494 |
||
14132 | 1495 |
// Shuffle Bytes |
1496 |
void pshufb(XMMRegister dst, XMMRegister src); |
|
1497 |
void pshufb(XMMRegister dst, Address src); |
|
1498 |
||
1066 | 1499 |
// Shuffle Packed Doublewords |
1500 |
void pshufd(XMMRegister dst, XMMRegister src, int mode); |
|
1501 |
void pshufd(XMMRegister dst, Address src, int mode); |
|
1502 |
||
1503 |
// Shuffle Packed Low Words |
|
1504 |
void pshuflw(XMMRegister dst, XMMRegister src, int mode); |
|
1505 |
void pshuflw(XMMRegister dst, Address src, int mode); |
|
1506 |
||
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1507 |
// Shift Right by bytes Logical DoubleQuadword Immediate |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1508 |
void psrldq(XMMRegister dst, int shift); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1509 |
|
15117
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1510 |
// Logical Compare 128bit |
2348 | 1511 |
void ptest(XMMRegister dst, XMMRegister src); |
1512 |
void ptest(XMMRegister dst, Address src); |
|
15117
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1513 |
// Logical Compare 256bit |
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1514 |
void vptest(XMMRegister dst, XMMRegister src); |
625397df6f4f
8005419: Improve intrinsics code performance on x86 by using AVX2
kvn
parents:
15115
diff
changeset
|
1515 |
void vptest(XMMRegister dst, Address src); |
2348 | 1516 |
|
1066 | 1517 |
// Interleave Low Bytes |
1518 |
void punpcklbw(XMMRegister dst, XMMRegister src); |
|
11427 | 1519 |
void punpcklbw(XMMRegister dst, Address src); |
1520 |
||
1521 |
// Interleave Low Doublewords |
|
1522 |
void punpckldq(XMMRegister dst, XMMRegister src); |
|
1523 |
void punpckldq(XMMRegister dst, Address src); |
|
1066 | 1524 |
|
13294 | 1525 |
// Interleave Low Quadwords |
1526 |
void punpcklqdq(XMMRegister dst, XMMRegister src); |
|
1527 |
||
4430 | 1528 |
#ifndef _LP64 // no 32bit push/pop on amd64 |
1066 | 1529 |
void pushl(Address src); |
4430 | 1530 |
#endif |
1066 | 1531 |
|
1532 |
void pushq(Address src); |
|
1533 |
||
1534 |
void rcll(Register dst, int imm8); |
|
1535 |
||
1536 |
void rclq(Register dst, int imm8); |
|
1537 |
||
1538 |
void ret(int imm16); |
|
1 | 1539 |
|
1540 |
void sahf(); |
|
1541 |
||
1066 | 1542 |
void sarl(Register dst, int imm8); |
1543 |
void sarl(Register dst); |
|
1544 |
||
1545 |
void sarq(Register dst, int imm8); |
|
1546 |
void sarq(Register dst); |
|
1547 |
||
1548 |
void sbbl(Address dst, int32_t imm32); |
|
1549 |
void sbbl(Register dst, int32_t imm32); |
|
1550 |
void sbbl(Register dst, Address src); |
|
1551 |
void sbbl(Register dst, Register src); |
|
1552 |
||
1553 |
void sbbq(Address dst, int32_t imm32); |
|
1554 |
void sbbq(Register dst, int32_t imm32); |
|
1555 |
void sbbq(Register dst, Address src); |
|
1556 |
void sbbq(Register dst, Register src); |
|
1557 |
||
1558 |
void setb(Condition cc, Register dst); |
|
1559 |
||
1560 |
void shldl(Register dst, Register src); |
|
1561 |
||
1562 |
void shll(Register dst, int imm8); |
|
1563 |
void shll(Register dst); |
|
1564 |
||
1565 |
void shlq(Register dst, int imm8); |
|
1566 |
void shlq(Register dst); |
|
1567 |
||
1568 |
void shrdl(Register dst, Register src); |
|
1569 |
||
1570 |
void shrl(Register dst, int imm8); |
|
1571 |
void shrl(Register dst); |
|
1572 |
||
1573 |
void shrq(Register dst, int imm8); |
|
1574 |
void shrq(Register dst); |
|
1575 |
||
1576 |
void smovl(); // QQQ generic? |
|
1577 |
||
1578 |
// Compute Square Root of Scalar Double-Precision Floating-Point Value |
|
1579 |
void sqrtsd(XMMRegister dst, Address src); |
|
1580 |
void sqrtsd(XMMRegister dst, XMMRegister src); |
|
1581 |
||
7433 | 1582 |
// Compute Square Root of Scalar Single-Precision Floating-Point Value |
1583 |
void sqrtss(XMMRegister dst, Address src); |
|
1584 |
void sqrtss(XMMRegister dst, XMMRegister src); |
|
1585 |
||
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1586 |
void std(); |
1066 | 1587 |
|
1588 |
void stmxcsr( Address dst ); |
|
1589 |
||
1590 |
void subl(Address dst, int32_t imm32); |
|
1591 |
void subl(Address dst, Register src); |
|
1592 |
void subl(Register dst, int32_t imm32); |
|
1593 |
void subl(Register dst, Address src); |
|
1594 |
void subl(Register dst, Register src); |
|
1595 |
||
1596 |
void subq(Address dst, int32_t imm32); |
|
1597 |
void subq(Address dst, Register src); |
|
1598 |
void subq(Register dst, int32_t imm32); |
|
1599 |
void subq(Register dst, Address src); |
|
1600 |
void subq(Register dst, Register src); |
|
1601 |
||
11791
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
1602 |
// Force generation of a 4 byte immediate value even if it fits into 8bit |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
1603 |
void subl_imm32(Register dst, int32_t imm32); |
3be8cae67887
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents:
11429
diff
changeset
|
1604 |
void subq_imm32(Register dst, int32_t imm32); |
1066 | 1605 |
|
1606 |
// Subtract Scalar Double-Precision Floating-Point Values |
|
1607 |
void subsd(XMMRegister dst, Address src); |
|
1 | 1608 |
void subsd(XMMRegister dst, XMMRegister src); |
1609 |
||
1066 | 1610 |
// Subtract Scalar Single-Precision Floating-Point Values |
1611 |
void subss(XMMRegister dst, Address src); |
|
1612 |
void subss(XMMRegister dst, XMMRegister src); |
|
1613 |
||
1614 |
void testb(Register dst, int imm8); |
|
1615 |
||
1616 |
void testl(Register dst, int32_t imm32); |
|
1617 |
void testl(Register dst, Register src); |
|
1618 |
void testl(Register dst, Address src); |
|
1619 |
||
1620 |
void testq(Register dst, int32_t imm32); |
|
1621 |
void testq(Register dst, Register src); |
|
1622 |
||
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1623 |
// BMI - count trailing zeros |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1624 |
void tzcntl(Register dst, Register src); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
21105
diff
changeset
|
1625 |
void tzcntq(Register dst, Register src); |
1066 | 1626 |
|
1627 |
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
|
1628 |
void ucomisd(XMMRegister dst, Address src); |
|
1 | 1629 |
void ucomisd(XMMRegister dst, XMMRegister src); |
1630 |
||
1066 | 1631 |
// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1632 |
void ucomiss(XMMRegister dst, Address src); |
|
1633 |
void ucomiss(XMMRegister dst, XMMRegister src); |
|
1634 |
||
1635 |
void xaddl(Address dst, Register src); |
|
1636 |
||
1637 |
void xaddq(Address dst, Register src); |
|
1638 |
||
1639 |
void xchgl(Register reg, Address adr); |
|
1640 |
void xchgl(Register dst, Register src); |
|
1641 |
||
1642 |
void xchgq(Register reg, Address adr); |
|
1643 |
void xchgq(Register dst, Register src); |
|
1644 |
||
11427 | 1645 |
// Get Value of Extended Control Register |
14626
0cf4eccf130f
8003240: x86: move MacroAssembler into separate file
twisti
parents:
14625
diff
changeset
|
1646 |
void xgetbv(); |
11427 | 1647 |
|
1066 | 1648 |
void xorl(Register dst, int32_t imm32); |
1649 |
void xorl(Register dst, Address src); |
|
1650 |
void xorl(Register dst, Register src); |
|
1651 |
||
1652 |
void xorq(Register dst, Address src); |
|
1653 |
void xorq(Register dst, Register src); |
|
1654 |
||
1655 |
void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 |
|
11427 | 1656 |
|
13294 | 1657 |
// AVX 3-operands scalar instructions (encoded with VEX prefix) |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1658 |
|
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1659 |
void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1660 |
void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1661 |
void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1662 |
void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1663 |
void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1664 |
void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1665 |
void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1666 |
void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1667 |
void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1668 |
void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1669 |
void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1670 |
void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1671 |
void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1672 |
void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1673 |
void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1674 |
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1675 |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1676 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1677 |
//====================VECTOR ARITHMETIC===================================== |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1678 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1679 |
// Add Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1680 |
void addpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1681 |
void addps(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1682 |
void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1683 |
void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1684 |
void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1685 |
void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1686 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1687 |
// Subtract Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1688 |
void subpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1689 |
void subps(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1690 |
void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1691 |
void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1692 |
void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1693 |
void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1694 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1695 |
// Multiply Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1696 |
void mulpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1697 |
void mulps(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1698 |
void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1699 |
void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1700 |
void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1701 |
void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1702 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1703 |
// Divide Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1704 |
void divpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1705 |
void divps(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1706 |
void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1707 |
void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1708 |
void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1709 |
void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1710 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1711 |
// Bitwise Logical AND of Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1712 |
void andpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1713 |
void andps(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1714 |
void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1715 |
void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1716 |
void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1717 |
void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1718 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1719 |
// Bitwise Logical XOR of Packed Floating-Point Values |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1720 |
void xorpd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1721 |
void xorps(XMMRegister dst, XMMRegister src); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1722 |
void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1723 |
void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1724 |
void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1725 |
void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1726 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1727 |
// Add packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1728 |
void paddb(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1729 |
void paddw(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1730 |
void paddd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1731 |
void paddq(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1732 |
void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1733 |
void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1734 |
void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1735 |
void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1736 |
void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1737 |
void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1738 |
void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1739 |
void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1740 |
|
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diff
changeset
|
1741 |
// Sub packed integers |
6c7faa516fc6
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diff
changeset
|
1742 |
void psubb(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1743 |
void psubw(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1744 |
void psubd(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1745 |
void psubq(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1746 |
void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1747 |
void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1748 |
void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1749 |
void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1750 |
void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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diff
changeset
|
1751 |
void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
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diff
changeset
|
1752 |
void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1753 |
void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1754 |
|
6c7faa516fc6
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diff
changeset
|
1755 |
// Multiply packed integers (only shorts and ints) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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13391
diff
changeset
|
1756 |
void pmullw(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1757 |
void pmulld(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1758 |
void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1759 |
void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1760 |
void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1761 |
void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1762 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1763 |
// Shift left packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1764 |
void psllw(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1765 |
void pslld(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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13391
diff
changeset
|
1766 |
void psllq(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1767 |
void psllw(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1768 |
void pslld(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1769 |
void psllq(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1770 |
void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1771 |
void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1772 |
void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1773 |
void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1774 |
void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1775 |
void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1776 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1777 |
// Logical shift right packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1778 |
void psrlw(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1779 |
void psrld(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1780 |
void psrlq(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1781 |
void psrlw(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1782 |
void psrld(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1783 |
void psrlq(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1784 |
void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1785 |
void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1786 |
void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1787 |
void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1788 |
void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1789 |
void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1790 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
13391
diff
changeset
|
1791 |
// Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1792 |
void psraw(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1793 |
void psrad(XMMRegister dst, int shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1794 |
void psraw(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1795 |
void psrad(XMMRegister dst, XMMRegister shift); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1796 |
void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1797 |
void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
1798 |
void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1799 |
void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1800 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1801 |
// And packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
1802 |
void pand(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1803 |
void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
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diff
changeset
|
1804 |
void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1805 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1806 |
// Or packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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parents:
13391
diff
changeset
|
1807 |
void por(XMMRegister dst, XMMRegister src); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1808 |
void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1809 |
void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
1810 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1811 |
// Xor packed integers |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1812 |
void pxor(XMMRegister dst, XMMRegister src); |
13294 | 1813 |
void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
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13391
diff
changeset
|
1814 |
void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1815 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13391
diff
changeset
|
1816 |
// Copy low 128bit into high 128bit of YMM registers. |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1817 |
void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
13294 | 1818 |
void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1819 |
|
13883
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13743
diff
changeset
|
1820 |
// Load/store high 128bit of YMM registers which does not destroy other half. |
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13743
diff
changeset
|
1821 |
void vinsertf128h(XMMRegister dst, Address src); |
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13743
diff
changeset
|
1822 |
void vinserti128h(XMMRegister dst, Address src); |
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13743
diff
changeset
|
1823 |
void vextractf128h(Address dst, XMMRegister src); |
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13743
diff
changeset
|
1824 |
void vextracti128h(Address dst, XMMRegister src); |
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13743
diff
changeset
|
1825 |
|
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
15114
diff
changeset
|
1826 |
// duplicate 4-bytes integer data from src into 8 locations in dest |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
15114
diff
changeset
|
1827 |
void vpbroadcastd(XMMRegister dst, XMMRegister src); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
15114
diff
changeset
|
1828 |
|
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1829 |
// Carry-Less Multiplication Quadword |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1830 |
void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15436
diff
changeset
|
1831 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1832 |
// AVX instruction which is used to clear upper 128 bits of YMM registers and |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1833 |
// to avoid transaction penalty between AVX and SSE states. There is no |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1834 |
// penalty if legacy SSE instructions are encoded using VEX prefix because |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1835 |
// they always clear upper 128 bits. It should be used before calling |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1836 |
// runtime code and native libraries. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
12955
diff
changeset
|
1837 |
void vzeroupper(); |
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1838 |
|
11427 | 1839 |
protected: |
1840 |
// Next instructions require address alignment 16 bytes SSE mode. |
|
1841 |
// They should be called only from corresponding MacroAssembler instructions. |
|
1842 |
void andpd(XMMRegister dst, Address src); |
|
1843 |
void andps(XMMRegister dst, Address src); |
|
1844 |
void xorpd(XMMRegister dst, Address src); |
|
1845 |
void xorps(XMMRegister dst, Address src); |
|
1846 |
||
1 | 1847 |
}; |
1848 |
||
7397 | 1849 |
#endif // CPU_X86_VM_ASSEMBLER_X86_HPP |