/*

 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "c1/c1_Compilation.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_MacroAssembler.hpp"

#include "c1/c1_Runtime1.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciArrayKlass.hpp"

#include "ci/ciInstance.hpp"

#include "gc/shared/barrierSet.hpp"

#include "gc/shared/cardTableModRefBS.hpp"

#include "gc/shared/collectedHeap.hpp"

#include "nativeInst_sparc.hpp"

#include "oops/objArrayKlass.hpp"

#include "runtime/sharedRuntime.hpp"

#define __ _masm->

//------------------------------------------------------------

bool LIR_Assembler::is_small_constant(LIR_Opr opr) {

  if (opr->is_constant()) {

    LIR_Const* constant = opr->as_constant_ptr();

    switch (constant->type()) {

      case T_INT: {

        jint value = constant->as_jint();

        return Assembler::is_simm13(value);

      }

      default:

        return false;

    }

  }

  return false;

}

bool LIR_Assembler::is_single_instruction(LIR_Op* op) {

  switch (op->code()) {

    case lir_null_check:

    return true;

    case lir_add:

    case lir_ushr:

    case lir_shr:

    case lir_shl:

      // integer shifts and adds are always one instruction

      return op->result_opr()->is_single_cpu();

    case lir_move: {

      LIR_Op1* op1 = op->as_Op1();

      LIR_Opr src = op1->in_opr();

      LIR_Opr dst = op1->result_opr();

      if (src == dst) {

        NEEDS_CLEANUP;

        // this works around a problem where moves with the same src and dst

        // end up in the delay slot and then the assembler swallows the mov

        // since it has no effect and then it complains because the delay slot

        // is empty.  returning false stops the optimizer from putting this in

        // the delay slot

        return false;

      }

      // don't put moves involving oops into the delay slot since the VerifyOops code

      // will make it much larger than a single instruction.

      if (VerifyOops) {

        return false;

      }

      if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||

          ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {

        return false;

      }

      if (UseCompressedOops) {

        if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false;

        if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false;

      }

      if (UseCompressedClassPointers) {

        if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS &&

            src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false;

      }

      if (dst->is_register()) {

        if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {

          return !PatchALot;

        } else if (src->is_single_stack()) {

          return true;

        }

      }

      if (src->is_register()) {

        if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {

          return !PatchALot;

        } else if (dst->is_single_stack()) {

          return true;

        }

      }

      if (dst->is_register() &&

          ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||

           (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {

        return true;

      }

      return false;

    }

    default:

      return false;

  }

  ShouldNotReachHere();

}

LIR_Opr LIR_Assembler::receiverOpr() {

  return FrameMap::O0_oop_opr;

}

LIR_Opr LIR_Assembler::osrBufferPointer() {

  return FrameMap::I0_opr;

}

int LIR_Assembler::initial_frame_size_in_bytes() const {

  return in_bytes(frame_map()->framesize_in_bytes());

}

// inline cache check: the inline cached class is in G5_inline_cache_reg(G5);

// we fetch the class of the receiver (O0) and compare it with the cached class.

// If they do not match we jump to slow case.

int LIR_Assembler::check_icache() {

  int offset = __ offset();

  __ inline_cache_check(O0, G5_inline_cache_reg);

  return offset;

}

void LIR_Assembler::osr_entry() {

  // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):

  //

  //   1. Create a new compiled activation.

  //   2. Initialize local variables in the compiled activation.  The expression stack must be empty

  //      at the osr_bci; it is not initialized.

  //   3. Jump to the continuation address in compiled code to resume execution.

  // OSR entry point

  offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());

  BlockBegin* osr_entry = compilation()->hir()->osr_entry();

  ValueStack* entry_state = osr_entry->end()->state();

  int number_of_locks = entry_state->locks_size();

  // Create a frame for the compiled activation.

  __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());

  // OSR buffer is

  //

  // locals[nlocals-1..0]

  // monitors[number_of_locks-1..0]

  //

  // locals is a direct copy of the interpreter frame so in the osr buffer

  // so first slot in the local array is the last local from the interpreter

  // and last slot is local[0] (receiver) from the interpreter

  //

  // Similarly with locks. The first lock slot in the osr buffer is the nth lock

  // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock

  // in the interpreter frame (the method lock if a sync method)

  // Initialize monitors in the compiled activation.

  //   I0: pointer to osr buffer

  //

  // All other registers are dead at this point and the locals will be

  // copied into place by code emitted in the IR.

  Register OSR_buf = osrBufferPointer()->as_register();

  { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");

    int monitor_offset = BytesPerWord * method()->max_locals() +

      (2 * BytesPerWord) * (number_of_locks - 1);

    // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in

    // the OSR buffer using 2 word entries: first the lock and then

    // the oop.

    for (int i = 0; i < number_of_locks; i++) {

      int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);

#ifdef ASSERT

      // verify the interpreter's monitor has a non-null object

      {

        Label L;

        __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);

        __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L);

        __ stop("locked object is NULL");

        __ bind(L);

      }

#endif // ASSERT

      // Copy the lock field into the compiled activation.

      __ ld_ptr(OSR_buf, slot_offset + 0, O7);

      __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));

      __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);

      __ st_ptr(O7, frame_map()->address_for_monitor_object(i));

    }

  }

}

// --------------------------------------------------------------------------------------------

void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {

  if (!GenerateSynchronizationCode) return;

  Register obj_reg = obj_opr->as_register();

  Register lock_reg = lock_opr->as_register();

  Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);

  Register reg = mon_addr.base();

  int offset = mon_addr.disp();

  // compute pointer to BasicLock

  if (mon_addr.is_simm13()) {

    __ add(reg, offset, lock_reg);

  }

  else {

    __ set(offset, lock_reg);

    __ add(reg, lock_reg, lock_reg);

  }

  // unlock object

  MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);

  // _slow_case_stubs->append(slow_case);

  // temporary fix: must be created after exceptionhandler, therefore as call stub

  _slow_case_stubs->append(slow_case);

  if (UseFastLocking) {

    // try inlined fast unlocking first, revert to slow locking if it fails

    // note: lock_reg points to the displaced header since the displaced header offset is 0!

    assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");

    __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());

  } else {

    // always do slow unlocking

    // note: the slow unlocking code could be inlined here, however if we use

    //       slow unlocking, speed doesn't matter anyway and this solution is

    //       simpler and requires less duplicated code - additionally, the

    //       slow unlocking code is the same in either case which simplifies

    //       debugging

    __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());

    __ delayed()->nop();

  }

  // done

  __ bind(*slow_case->continuation());

}

int LIR_Assembler::emit_exception_handler() {

  // if the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci => add a nop

  // (was bug 5/14/1999 - gri)

  __ nop();

  // generate code for exception handler

  ciMethod* method = compilation()->method();

  address handler_base = __ start_a_stub(exception_handler_size());

  if (handler_base == NULL) {

    // not enough space left for the handler

    bailout("exception handler overflow");

    return -1;

  }

  int offset = code_offset();

  __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);

  __ delayed()->nop();

  __ should_not_reach_here();

  guarantee(code_offset() - offset <= exception_handler_size(), "overflow");

  __ end_a_stub();

  return offset;

}

// Emit the code to remove the frame from the stack in the exception

// unwind path.

int LIR_Assembler::emit_unwind_handler() {

#ifndef PRODUCT

  if (CommentedAssembly) {

    _masm->block_comment("Unwind handler");

  }

#endif

  int offset = code_offset();

  // Fetch the exception from TLS and clear out exception related thread state

  __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0);

  __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));

  __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset()));

  __ bind(_unwind_handler_entry);

  __ verify_not_null_oop(O0);

  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

    __ mov(O0, I0);  // Preserve the exception

  }

  // Preform needed unlocking

  MonitorExitStub* stub = NULL;

  if (method()->is_synchronized()) {

    monitor_address(0, FrameMap::I1_opr);

    stub = new MonitorExitStub(FrameMap::I1_opr, true, 0);

    __ unlock_object(I3, I2, I1, *stub->entry());

    __ bind(*stub->continuation());

  }

  if (compilation()->env()->dtrace_method_probes()) {

    __ mov(G2_thread, O0);

    __ save_thread(I1); // need to preserve thread in G2 across

                        // runtime call

    metadata2reg(method()->constant_encoding(), O1);

    __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type);

    __ delayed()->nop();

    __ restore_thread(I1);

  }

  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

    __ mov(I0, O0);  // Restore the exception

  }

  // dispatch to the unwind logic

  __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);

  __ delayed()->nop();

  // Emit the slow path assembly

  if (stub != NULL) {

    stub->emit_code(this);

  }

  return offset;

}

int LIR_Assembler::emit_deopt_handler() {

  // if the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci => add a nop

  // (was bug 5/14/1999 - gri)

  __ nop();

  // generate code for deopt handler

  ciMethod* method = compilation()->method();

  address handler_base = __ start_a_stub(deopt_handler_size());

  if (handler_base == NULL) {

    // not enough space left for the handler

    bailout("deopt handler overflow");

    return -1;

  }

  int offset = code_offset();

  AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());

  __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp

  __ delayed()->nop();

  guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");

  __ end_a_stub();

  return offset;

}

void LIR_Assembler::jobject2reg(jobject o, Register reg) {

  if (o == NULL) {

    __ set(NULL_WORD, reg);

  } else {

    int oop_index = __ oop_recorder()->find_index(o);

    assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop");

    RelocationHolder rspec = oop_Relocation::spec(oop_index);

    __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created

  }

}

void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {

  // Allocate a new index in table to hold the object once it's been patched

  int oop_index = __ oop_recorder()->allocate_oop_index(NULL);

  PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);

  AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));

  assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");

  // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the

  // NULL will be dynamically patched later and the patched value may be large.  We must

  // therefore generate the sethi/add as a placeholders

  __ patchable_set(addrlit, reg);

  patching_epilog(patch, lir_patch_normal, reg, info);

}

void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {

  __ set_metadata_constant(o, reg);

}

void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {

  // Allocate a new index in table to hold the klass once it's been patched

  int index = __ oop_recorder()->allocate_metadata_index(NULL);

  PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);

  AddressLiteral addrlit(NULL, metadata_Relocation::spec(index));

  assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");

  // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the

  // NULL will be dynamically patched later and the patched value may be large.  We must

  // therefore generate the sethi/add as a placeholders

  __ patchable_set(addrlit, reg);

  patching_epilog(patch, lir_patch_normal, reg, info);

}

void LIR_Assembler::emit_op3(LIR_Op3* op) {

  switch (op->code()) {

    case lir_idiv:

    case lir_irem:  // Both idiv & irem are handled after the switch (below).

      break;

    case lir_fmaf:

      __ fmadd(FloatRegisterImpl::S,

               op->in_opr1()->as_float_reg(),

               op->in_opr2()->as_float_reg(),

               op->in_opr3()->as_float_reg(),

               op->result_opr()->as_float_reg());

      return;

    case lir_fmad:

      __ fmadd(FloatRegisterImpl::D,

               op->in_opr1()->as_double_reg(),

               op->in_opr2()->as_double_reg(),

               op->in_opr3()->as_double_reg(),

               op->result_opr()->as_double_reg());

      return;

    default:

      ShouldNotReachHere();

      break;

  }

  // Handle idiv & irem:

  Register Rdividend = op->in_opr1()->as_register();

  Register Rdivisor  = noreg;

  Register Rscratch  = op->in_opr3()->as_register();

  Register Rresult   = op->result_opr()->as_register();

  int divisor = -1;

  if (op->in_opr2()->is_register()) {

    Rdivisor = op->in_opr2()->as_register();

  } else {

    divisor = op->in_opr2()->as_constant_ptr()->as_jint();

    assert(Assembler::is_simm13(divisor), "can only handle simm13");

  }

  assert(Rdividend != Rscratch, "");

  assert(Rdivisor  != Rscratch, "");

  assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");

  if (Rdivisor == noreg && is_power_of_2(divisor)) {

    // convert division by a power of two into some shifts and logical operations

    if (op->code() == lir_idiv) {

      if (divisor == 2) {

        __ srl(Rdividend, 31, Rscratch);

      } else {

        __ sra(Rdividend, 31, Rscratch);

        __ and3(Rscratch, divisor - 1, Rscratch);

      }

      __ add(Rdividend, Rscratch, Rscratch);

      __ sra(Rscratch, log2_intptr(divisor), Rresult);

      return;

    } else {

      if (divisor == 2) {

        __ srl(Rdividend, 31, Rscratch);

      } else {

        __ sra(Rdividend, 31, Rscratch);

        __ and3(Rscratch, divisor - 1,Rscratch);

      }

      __ add(Rdividend, Rscratch, Rscratch);

      __ andn(Rscratch, divisor - 1,Rscratch);

      __ sub(Rdividend, Rscratch, Rresult);

      return;

    }

  }

  __ sra(Rdividend, 31, Rscratch);