/*

 * Copyright 2000-2010 Sun Microsystems, Inc.  All Rights Reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

 * CA 95054 USA or visit www.sun.com if you need additional information or

 * have any questions.

 *

 */

# include "incls/_precompiled.incl"

# include "incls/_c1_LIRAssembler_sparc.cpp.incl"

#define __ _masm->

//------------------------------------------------------------

bool LIR_Assembler::is_small_constant(LIR_Opr opr) {

  if (opr->is_constant()) {

    LIR_Const* constant = opr->as_constant_ptr();

    switch (constant->type()) {

      case T_INT: {

        jint value = constant->as_jint();

        return Assembler::is_simm13(value);

      }

      default:

        return false;

    }

  }

  return false;

}

bool LIR_Assembler::is_single_instruction(LIR_Op* op) {

  switch (op->code()) {

    case lir_null_check:

    return true;

    case lir_add:

    case lir_ushr:

    case lir_shr:

    case lir_shl:

      // integer shifts and adds are always one instruction

      return op->result_opr()->is_single_cpu();

    case lir_move: {

      LIR_Op1* op1 = op->as_Op1();

      LIR_Opr src = op1->in_opr();

      LIR_Opr dst = op1->result_opr();

      if (src == dst) {

        NEEDS_CLEANUP;

        // this works around a problem where moves with the same src and dst

        // end up in the delay slot and then the assembler swallows the mov

        // since it has no effect and then it complains because the delay slot

        // is empty.  returning false stops the optimizer from putting this in

        // the delay slot

        return false;

      }

      // don't put moves involving oops into the delay slot since the VerifyOops code

      // will make it much larger than a single instruction.

      if (VerifyOops) {

        return false;

      }

      if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||

          ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {

        return false;

      }

      if (dst->is_register()) {

        if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {

          return !PatchALot;

        } else if (src->is_single_stack()) {

          return true;

        }

      }

      if (src->is_register()) {

        if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {

          return !PatchALot;

        } else if (dst->is_single_stack()) {

          return true;

        }

      }

      if (dst->is_register() &&

          ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||

           (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {

        return true;

      }

      return false;

    }

    default:

      return false;

  }

  ShouldNotReachHere();

}

LIR_Opr LIR_Assembler::receiverOpr() {

  return FrameMap::O0_oop_opr;

}

LIR_Opr LIR_Assembler::incomingReceiverOpr() {

  return FrameMap::I0_oop_opr;

}

LIR_Opr LIR_Assembler::osrBufferPointer() {

  return FrameMap::I0_opr;

}

int LIR_Assembler::initial_frame_size_in_bytes() {

  return in_bytes(frame_map()->framesize_in_bytes());

}

// inline cache check: the inline cached class is in G5_inline_cache_reg(G5);

// we fetch the class of the receiver (O0) and compare it with the cached class.

// If they do not match we jump to slow case.

int LIR_Assembler::check_icache() {

  int offset = __ offset();

  __ inline_cache_check(O0, G5_inline_cache_reg);

  return offset;

}

void LIR_Assembler::osr_entry() {

  // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):

  //

  //   1. Create a new compiled activation.

  //   2. Initialize local variables in the compiled activation.  The expression stack must be empty

  //      at the osr_bci; it is not initialized.

  //   3. Jump to the continuation address in compiled code to resume execution.

  // OSR entry point

  offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());

  BlockBegin* osr_entry = compilation()->hir()->osr_entry();

  ValueStack* entry_state = osr_entry->end()->state();

  int number_of_locks = entry_state->locks_size();

  // Create a frame for the compiled activation.

  __ build_frame(initial_frame_size_in_bytes());

  // OSR buffer is

  //

  // locals[nlocals-1..0]

  // monitors[number_of_locks-1..0]

  //

  // locals is a direct copy of the interpreter frame so in the osr buffer

  // so first slot in the local array is the last local from the interpreter

  // and last slot is local[0] (receiver) from the interpreter

  //

  // Similarly with locks. The first lock slot in the osr buffer is the nth lock

  // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock

  // in the interpreter frame (the method lock if a sync method)

  // Initialize monitors in the compiled activation.

  //   I0: pointer to osr buffer

  //

  // All other registers are dead at this point and the locals will be

  // copied into place by code emitted in the IR.

  Register OSR_buf = osrBufferPointer()->as_register();

  { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");

    int monitor_offset = BytesPerWord * method()->max_locals() +

      (2 * BytesPerWord) * (number_of_locks - 1);

    // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in

    // the OSR buffer using 2 word entries: first the lock and then

    // the oop.

    for (int i = 0; i < number_of_locks; i++) {

      int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);

#ifdef ASSERT

      // verify the interpreter's monitor has a non-null object

      {

        Label L;

        __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);

        __ cmp(G0, O7);

        __ br(Assembler::notEqual, false, Assembler::pt, L);

        __ delayed()->nop();

        __ stop("locked object is NULL");

        __ bind(L);

      }

#endif // ASSERT

      // Copy the lock field into the compiled activation.

      __ ld_ptr(OSR_buf, slot_offset + 0, O7);

      __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));

      __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);

      __ st_ptr(O7, frame_map()->address_for_monitor_object(i));

    }

  }

}

// Optimized Library calls

// This is the fast version of java.lang.String.compare; it has not

// OSR-entry and therefore, we generate a slow version for OSR's

void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {

  Register str0 = left->as_register();

  Register str1 = right->as_register();

  Label Ldone;

  Register result = dst->as_register();

  {

    // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0

    // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1

    // Also, get string0.count-string1.count in o7 and get the condition code set

    // Note: some instructions have been hoisted for better instruction scheduling

    Register tmp0 = L0;

    Register tmp1 = L1;

    Register tmp2 = L2;

    int  value_offset = java_lang_String:: value_offset_in_bytes(); // char array

    int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position

    int  count_offset = java_lang_String:: count_offset_in_bytes();

    __ ld_ptr(str0, value_offset, tmp0);

    __ ld(str0, offset_offset, tmp2);

    __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);

    __ ld(str0, count_offset, str0);

    __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);

    // str1 may be null

    add_debug_info_for_null_check_here(info);

    __ ld_ptr(str1, value_offset, tmp1);

    __ add(tmp0, tmp2, tmp0);

    __ ld(str1, offset_offset, tmp2);

    __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);

    __ ld(str1, count_offset, str1);

    __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);

    __ subcc(str0, str1, O7);

    __ add(tmp1, tmp2, tmp1);

  }

  {

    // Compute the minimum of the string lengths, scale it and store it in limit

    Register count0 = I0;

    Register count1 = I1;

    Register limit  = L3;

    Label Lskip;

    __ sll(count0, exact_log2(sizeof(jchar)), limit);             // string0 is shorter

    __ br(Assembler::greater, true, Assembler::pt, Lskip);

    __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit);  // string1 is shorter

    __ bind(Lskip);

    // If either string is empty (or both of them) the result is the difference in lengths

    __ cmp(limit, 0);

    __ br(Assembler::equal, true, Assembler::pn, Ldone);

    __ delayed()->mov(O7, result);  // result is difference in lengths

  }

  {

    // Neither string is empty

    Label Lloop;

    Register base0 = L0;

    Register base1 = L1;

    Register chr0  = I0;

    Register chr1  = I1;

    Register limit = L3;

    // Shift base0 and base1 to the end of the arrays, negate limit

    __ add(base0, limit, base0);

    __ add(base1, limit, base1);

    __ neg(limit);  // limit = -min{string0.count, strin1.count}

    __ lduh(base0, limit, chr0);

    __ bind(Lloop);

    __ lduh(base1, limit, chr1);

    __ subcc(chr0, chr1, chr0);

    __ br(Assembler::notZero, false, Assembler::pn, Ldone);

    assert(chr0 == result, "result must be pre-placed");

    __ delayed()->inccc(limit, sizeof(jchar));

    __ br(Assembler::notZero, true, Assembler::pt, Lloop);

    __ delayed()->lduh(base0, limit, chr0);

  }

  // If strings are equal up to min length, return the length difference.

  __ mov(O7, result);

  // Otherwise, return the difference between the first mismatched chars.

  __ bind(Ldone);

}

// --------------------------------------------------------------------------------------------

void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {

  if (!GenerateSynchronizationCode) return;

  Register obj_reg = obj_opr->as_register();

  Register lock_reg = lock_opr->as_register();

  Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);

  Register reg = mon_addr.base();

  int offset = mon_addr.disp();

  // compute pointer to BasicLock

  if (mon_addr.is_simm13()) {

    __ add(reg, offset, lock_reg);

  }

  else {

    __ set(offset, lock_reg);

    __ add(reg, lock_reg, lock_reg);

  }

  // unlock object

  MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);

  // _slow_case_stubs->append(slow_case);

  // temporary fix: must be created after exceptionhandler, therefore as call stub

  _slow_case_stubs->append(slow_case);

  if (UseFastLocking) {

    // try inlined fast unlocking first, revert to slow locking if it fails

    // note: lock_reg points to the displaced header since the displaced header offset is 0!

    assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");

    __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());

  } else {

    // always do slow unlocking

    // note: the slow unlocking code could be inlined here, however if we use

    //       slow unlocking, speed doesn't matter anyway and this solution is

    //       simpler and requires less duplicated code - additionally, the

    //       slow unlocking code is the same in either case which simplifies

    //       debugging

    __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());

    __ delayed()->nop();

  }

  // done

  __ bind(*slow_case->continuation());

}

int LIR_Assembler::emit_exception_handler() {

  // if the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci => add a nop

  // (was bug 5/14/1999 - gri)

  __ nop();

  // generate code for exception handler

  ciMethod* method = compilation()->method();

  address handler_base = __ start_a_stub(exception_handler_size);

  if (handler_base == NULL) {

    // not enough space left for the handler

    bailout("exception handler overflow");

    return -1;

  }

  int offset = code_offset();

  __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);

  __ delayed()->nop();

  debug_only(__ stop("should have gone to the caller");)

  assert(code_offset() - offset <= exception_handler_size, "overflow");

  __ end_a_stub();

  return offset;

}

int LIR_Assembler::emit_deopt_handler() {

  // if the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci => add a nop

  // (was bug 5/14/1999 - gri)

  __ nop();

  // generate code for deopt handler

  ciMethod* method = compilation()->method();

  address handler_base = __ start_a_stub(deopt_handler_size);

  if (handler_base == NULL) {

    // not enough space left for the handler

    bailout("deopt handler overflow");

    return -1;

  }

  int offset = code_offset();

  AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());

  __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp

  __ delayed()->nop();

  assert(code_offset() - offset <= deopt_handler_size, "overflow");

  debug_only(__ stop("should have gone to the caller");)

  __ end_a_stub();

  return offset;

}

void LIR_Assembler::jobject2reg(jobject o, Register reg) {

  if (o == NULL) {

    __ set(NULL_WORD, reg);

  } else {

    int oop_index = __ oop_recorder()->find_index(o);

    RelocationHolder rspec = oop_Relocation::spec(oop_index);

    __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created

  }

}

void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {

  // Allocate a new index in oop table to hold the oop once it's been patched

  int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);

  PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);

  AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));

  assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");

  // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the

  // NULL will be dynamically patched later and the patched value may be large.  We must

  // therefore generate the sethi/add as a placeholders

  __ patchable_set(addrlit, reg);

  patching_epilog(patch, lir_patch_normal, reg, info);

}

void LIR_Assembler::emit_op3(LIR_Op3* op) {

  Register Rdividend = op->in_opr1()->as_register();

  Register Rdivisor  = noreg;

  Register Rscratch  = op->in_opr3()->as_register();

  Register Rresult   = op->result_opr()->as_register();

  int divisor = -1;

  if (op->in_opr2()->is_register()) {

    Rdivisor = op->in_opr2()->as_register();

  } else {

    divisor = op->in_opr2()->as_constant_ptr()->as_jint();

    assert(Assembler::is_simm13(divisor), "can only handle simm13");

  }

  assert(Rdividend != Rscratch, "");

  assert(Rdivisor  != Rscratch, "");

  assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");

  if (Rdivisor == noreg && is_power_of_2(divisor)) {

    // convert division by a power of two into some shifts and logical operations

    if (op->code() == lir_idiv) {

      if (divisor == 2) {

        __ srl(Rdividend, 31, Rscratch);

      } else {

        __ sra(Rdividend, 31, Rscratch);

        __ and3(Rscratch, divisor - 1, Rscratch);

      }

      __ add(Rdividend, Rscratch, Rscratch);

      __ sra(Rscratch, log2_intptr(divisor), Rresult);

      return;

    } else {

      if (divisor == 2) {

        __ srl(Rdividend, 31, Rscratch);

      } else {

        __ sra(Rdividend, 31, Rscratch);

        __ and3(Rscratch, divisor - 1,Rscratch);

      }

      __ add(Rdividend, Rscratch, Rscratch);

      __ andn(Rscratch, divisor - 1,Rscratch);

      __ sub(Rdividend, Rscratch, Rresult);

      return;

    }

  }

  __ sra(Rdividend, 31, Rscratch);

  __ wry(Rscratch);

  if (!VM_Version::v9_instructions_work()) {

    // v9 doesn't require these nops

    __ nop();

    __ nop();

    __ nop();

    __ nop();

  }

  add_debug_info_for_div0_here(op->info());

  if (Rdivisor != noreg) {

    __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));

  } else {

    assert(Assembler::is_simm13(divisor), "can only handle simm13");

    __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));

  }

  Label skip;

  __ br(Assembler::overflowSet, true, Assembler::pn, skip);

  __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));

  __ bind(skip);

  if (op->code() == lir_irem) {

    if (Rdivisor != noreg) {

      __ smul(Rscratch, Rdivisor, Rscratch);

    } else {

      __ smul(Rscratch, divisor, Rscratch);

    }

    __ sub(Rdividend, Rscratch, Rresult);

  }

}