--- a/hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp	Tue Apr 05 20:32:54 2016 +0000
+++ b/hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp	Wed Mar 30 17:04:14 2016 +0200
@@ -3313,6 +3313,9 @@
   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
 }
 
+void LIR_Assembler::on_spin_wait() {
+  Unimplemented();
+}
 
 // Pack two sequential registers containing 32 bit values
 // into a single 64 bit register.