/*

 * Copyright (c) 2009, 2018, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 */

package org.graalvm.compiler.asm.amd64;

import static jdk.vm.ci.amd64.AMD64.CPU;

import static jdk.vm.ci.amd64.AMD64.MASK;

import static jdk.vm.ci.amd64.AMD64.XMM;

import static jdk.vm.ci.code.MemoryBarriers.STORE_LOAD;

import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseAddressNop;

import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseNormalNop;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.ADD;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.AND;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.CMP;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.OR;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SBB;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SUB;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.XOR;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.DEC;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.INC;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NEG;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NOT;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.B0;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.Z0;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.Z1;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.BYTE;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.DWORD;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.PD;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.PS;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.QWORD;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.SD;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.SS;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.WORD;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.L128;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.L256;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.LZ;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.M_0F;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.M_0F38;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.M_0F3A;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_66;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_F2;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_F3;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.W0;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.W1;

import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.WIG;

import static org.graalvm.compiler.core.common.NumUtil.isByte;

import static org.graalvm.compiler.core.common.NumUtil.isInt;

import static org.graalvm.compiler.core.common.NumUtil.isShiftCount;

import static org.graalvm.compiler.core.common.NumUtil.isUByte;

import java.util.EnumSet;

import org.graalvm.compiler.asm.Label;

import org.graalvm.compiler.asm.amd64.AMD64Address.Scale;

import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize;

import org.graalvm.compiler.core.common.NumUtil;

import org.graalvm.compiler.core.common.calc.Condition;

import org.graalvm.compiler.debug.GraalError;

import jdk.vm.ci.amd64.AMD64;

import jdk.vm.ci.amd64.AMD64.CPUFeature;

import jdk.vm.ci.code.Register;

import jdk.vm.ci.code.Register.RegisterCategory;

import jdk.vm.ci.code.TargetDescription;

/**

 * This class implements an assembler that can encode most X86 instructions.

 */

public class AMD64Assembler extends AMD64BaseAssembler {

    /**

     * Constructs an assembler for the AMD64 architecture.

     */

    public AMD64Assembler(TargetDescription target) {

        super(target);

    }

    /**

     * The x86 condition codes used for conditional jumps/moves.

     */

    public enum ConditionFlag {

        Zero(0x4, "|zero|"),

        NotZero(0x5, "|nzero|"),

        Equal(0x4, "="),

        NotEqual(0x5, "!="),

        Less(0xc, "<"),

        LessEqual(0xe, "<="),

        Greater(0xf, ">"),

        GreaterEqual(0xd, ">="),

        Below(0x2, "|<|"),

        BelowEqual(0x6, "|<=|"),

        Above(0x7, "|>|"),

        AboveEqual(0x3, "|>=|"),

        Overflow(0x0, "|of|"),

        NoOverflow(0x1, "|nof|"),

        CarrySet(0x2, "|carry|"),

        CarryClear(0x3, "|ncarry|"),

        Negative(0x8, "|neg|"),

        Positive(0x9, "|pos|"),

        Parity(0xa, "|par|"),

        NoParity(0xb, "|npar|");

        private final int value;

        private final String operator;

        ConditionFlag(int value, String operator) {

            this.value = value;

            this.operator = operator;

        }

        public ConditionFlag negate() {

            switch (this) {

                case Zero:

                    return NotZero;

                case NotZero:

                    return Zero;

                case Equal:

                    return NotEqual;

                case NotEqual:

                    return Equal;

                case Less:

                    return GreaterEqual;

                case LessEqual:

                    return Greater;

                case Greater:

                    return LessEqual;

                case GreaterEqual:

                    return Less;

                case Below:

                    return AboveEqual;

                case BelowEqual:

                    return Above;

                case Above:

                    return BelowEqual;

                case AboveEqual:

                    return Below;

                case Overflow:

                    return NoOverflow;

                case NoOverflow:

                    return Overflow;

                case CarrySet:

                    return CarryClear;

                case CarryClear:

                    return CarrySet;

                case Negative:

                    return Positive;

                case Positive:

                    return Negative;

                case Parity:

                    return NoParity;

                case NoParity:

                    return Parity;

            }

            throw new IllegalArgumentException();

        }

        public int getValue() {

            return value;

        }

        @Override

        public String toString() {

            return operator;

        }

    }

    /**

     * Operand size and register type constraints.

     */

    private enum OpAssertion {

        ByteAssertion(CPU, CPU, BYTE),

        ByteOrLargerAssertion(CPU, CPU, BYTE, WORD, DWORD, QWORD),

        WordOrLargerAssertion(CPU, CPU, WORD, DWORD, QWORD),

        DwordOrLargerAssertion(CPU, CPU, DWORD, QWORD),

        WordOrDwordAssertion(CPU, CPU, WORD, QWORD),

        QwordAssertion(CPU, CPU, QWORD),

        FloatAssertion(XMM, XMM, SS, SD, PS, PD),

        PackedFloatAssertion(XMM, XMM, PS, PD),

        SingleAssertion(XMM, XMM, SS),

        DoubleAssertion(XMM, XMM, SD),

        PackedDoubleAssertion(XMM, XMM, PD),

        IntToFloatAssertion(XMM, CPU, DWORD, QWORD),

        FloatToIntAssertion(CPU, XMM, DWORD, QWORD);

        private final RegisterCategory resultCategory;

        private final RegisterCategory inputCategory;

        private final OperandSize[] allowedSizes;

        OpAssertion(RegisterCategory resultCategory, RegisterCategory inputCategory, OperandSize... allowedSizes) {

            this.resultCategory = resultCategory;

            this.inputCategory = inputCategory;

            this.allowedSizes = allowedSizes;

        }

        protected boolean checkOperands(AMD64Op op, OperandSize size, Register resultReg, Register inputReg) {

            assert resultReg == null || resultCategory.equals(resultReg.getRegisterCategory()) : "invalid result register " + resultReg + " used in " + op;

            assert inputReg == null || inputCategory.equals(inputReg.getRegisterCategory()) : "invalid input register " + inputReg + " used in " + op;

            for (OperandSize s : allowedSizes) {

                if (size == s) {

                    return true;

                }

            }

            assert false : "invalid operand size " + size + " used in " + op;

            return false;

        }

    }

    protected static final int P_0F = 0x0F;

    protected static final int P_0F38 = 0x380F;

    protected static final int P_0F3A = 0x3A0F;

    /**

     * Base class for AMD64 opcodes.

     */

    public static class AMD64Op {

        private final String opcode;

        protected final int prefix1;

        protected final int prefix2;

        protected final int op;

        private final boolean dstIsByte;

        private final boolean srcIsByte;

        private final OpAssertion assertion;

        private final CPUFeature feature;

        protected AMD64Op(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {

            this(opcode, prefix1, prefix2, op, assertion == OpAssertion.ByteAssertion, assertion == OpAssertion.ByteAssertion, assertion, feature);

        }

        protected AMD64Op(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {

            this.opcode = opcode;

            this.prefix1 = prefix1;

            this.prefix2 = prefix2;

            this.op = op;

            this.dstIsByte = dstIsByte;

            this.srcIsByte = srcIsByte;

            this.assertion = assertion;

            this.feature = feature;

        }

        protected final void emitOpcode(AMD64Assembler asm, OperandSize size, int rxb, int dstEnc, int srcEnc) {

            if (prefix1 != 0) {

                asm.emitByte(prefix1);

            }

            if (size.getSizePrefix() != 0) {

                asm.emitByte(size.getSizePrefix());

            }

            int rexPrefix = 0x40 | rxb;

            if (size == QWORD) {

                rexPrefix |= 0x08;

            }

            if (rexPrefix != 0x40 || (dstIsByte && dstEnc >= 4) || (srcIsByte && srcEnc >= 4)) {

                asm.emitByte(rexPrefix);

            }

            if (prefix2 > 0xFF) {

                asm.emitShort(prefix2);

            } else if (prefix2 > 0) {

                asm.emitByte(prefix2);

            }

            asm.emitByte(op);

        }

        protected final boolean verify(AMD64Assembler asm, OperandSize size, Register resultReg, Register inputReg) {

            assert feature == null || asm.supports(feature) : String.format("unsupported feature %s required for %s", feature, opcode);

            assert assertion.checkOperands(this, size, resultReg, inputReg);

            return true;

        }

        public OperandSize[] getAllowedSizes() {

            return assertion.allowedSizes;

        }

        protected final boolean isSSEInstruction() {

            if (feature == null) {

                return false;

            }

            switch (feature) {

                case SSE:

                case SSE2:

                case SSE3:

                case SSSE3:

                case SSE4A:

                case SSE4_1:

                case SSE4_2:

                    return true;

                default:

                    return false;

            }

        }

        public final OpAssertion getAssertion() {

            return assertion;

        }

        @Override

        public String toString() {

            return opcode;

        }

    }

    /**

     * Base class for AMD64 opcodes with immediate operands.

     */

    public static class AMD64ImmOp extends AMD64Op {

        private final boolean immIsByte;

        protected AMD64ImmOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion) {

            this(opcode, immIsByte, prefix, op, assertion, null);

        }

        protected AMD64ImmOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion, CPUFeature feature) {

            super(opcode, 0, prefix, op, assertion, feature);

            this.immIsByte = immIsByte;

        }

        protected final void emitImmediate(AMD64Assembler asm, OperandSize size, int imm) {

            if (immIsByte) {

                assert imm == (byte) imm;

                asm.emitByte(imm);

            } else {

                size.emitImmediate(asm, imm);

            }

        }

        protected final int immediateSize(OperandSize size) {

            if (immIsByte) {

                return 1;

            } else {

                return size.getBytes();

            }

        }

    }

    /**

     * Opcode with operand order of either RM or MR for 2 address forms.

     */

    public abstract static class AMD64RROp extends AMD64Op {

        protected AMD64RROp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {

            super(opcode, prefix1, prefix2, op, assertion, feature);

        }

        protected AMD64RROp(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {

            super(opcode, prefix1, prefix2, op, dstIsByte, srcIsByte, assertion, feature);

        }

        public abstract void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src);

    }

    /**

     * Opcode with operand order of RM.

     */

    public static class AMD64RMOp extends AMD64RROp {

        // @formatter:off

        public static final AMD64RMOp IMUL   = new AMD64RMOp("IMUL",         P_0F, 0xAF, OpAssertion.ByteOrLargerAssertion);

        public static final AMD64RMOp BSF    = new AMD64RMOp("BSF",          P_0F, 0xBC);

        public static final AMD64RMOp BSR    = new AMD64RMOp("BSR",          P_0F, 0xBD);

        // POPCNT, TZCNT, and LZCNT support word operation. However, the legacy size prefix should

        // be emitted before the mandatory prefix 0xF3. Since we are not emitting bit count for

        // 16-bit operands, here we simply use DwordOrLargerAssertion.

        public static final AMD64RMOp POPCNT = new AMD64RMOp("POPCNT", 0xF3, P_0F, 0xB8, OpAssertion.DwordOrLargerAssertion, CPUFeature.POPCNT);

        public static final AMD64RMOp TZCNT  = new AMD64RMOp("TZCNT",  0xF3, P_0F, 0xBC, OpAssertion.DwordOrLargerAssertion, CPUFeature.BMI1);

        public static final AMD64RMOp LZCNT  = new AMD64RMOp("LZCNT",  0xF3, P_0F, 0xBD, OpAssertion.DwordOrLargerAssertion, CPUFeature.LZCNT);

        public static final AMD64RMOp MOVZXB = new AMD64RMOp("MOVZXB",       P_0F, 0xB6, false, true, OpAssertion.WordOrLargerAssertion);

        public static final AMD64RMOp MOVZX  = new AMD64RMOp("MOVZX",        P_0F, 0xB7, OpAssertion.DwordOrLargerAssertion);

        public static final AMD64RMOp MOVSXB = new AMD64RMOp("MOVSXB",       P_0F, 0xBE, false, true, OpAssertion.WordOrLargerAssertion);

        public static final AMD64RMOp MOVSX  = new AMD64RMOp("MOVSX",        P_0F, 0xBF, OpAssertion.DwordOrLargerAssertion);

        public static final AMD64RMOp MOVSXD = new AMD64RMOp("MOVSXD",             0x63, OpAssertion.QwordAssertion);

        public static final AMD64RMOp MOVB   = new AMD64RMOp("MOVB",               0x8A, OpAssertion.ByteAssertion);

        public static final AMD64RMOp MOV    = new AMD64RMOp("MOV",                0x8B);

        public static final AMD64RMOp CMP    = new AMD64RMOp("CMP",                0x3B);

        // MOVD/MOVQ and MOVSS/MOVSD are the same opcode, just with different operand size prefix

        public static final AMD64RMOp MOVD   = new AMD64RMOp("MOVD",   0x66, P_0F, 0x6E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);

        public static final AMD64RMOp MOVQ   = new AMD64RMOp("MOVQ",   0x66, P_0F, 0x6E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);

        public static final AMD64RMOp MOVSS  = new AMD64RMOp("MOVSS",        P_0F, 0x10, OpAssertion.FloatAssertion, CPUFeature.SSE);

        public static final AMD64RMOp MOVSD  = new AMD64RMOp("MOVSD",        P_0F, 0x10, OpAssertion.FloatAssertion, CPUFeature.SSE);

        // TEST is documented as MR operation, but it's symmetric, and using it as RM operation is more convenient.

        public static final AMD64RMOp TESTB  = new AMD64RMOp("TEST",               0x84, OpAssertion.ByteAssertion);

        public static final AMD64RMOp TEST   = new AMD64RMOp("TEST",               0x85);

        // @formatter:on

        protected AMD64RMOp(String opcode, int op) {

            this(opcode, 0, op);

        }

        protected AMD64RMOp(String opcode, int op, OpAssertion assertion) {

            this(opcode, 0, op, assertion);

        }

        protected AMD64RMOp(String opcode, int prefix, int op) {

            this(opcode, 0, prefix, op, null);

        }

        protected AMD64RMOp(String opcode, int prefix, int op, OpAssertion assertion) {

            this(opcode, 0, prefix, op, assertion, null);

        }

        protected AMD64RMOp(String opcode, int prefix, int op, OpAssertion assertion, CPUFeature feature) {

            this(opcode, 0, prefix, op, assertion, feature);

        }

        protected AMD64RMOp(String opcode, int prefix, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion) {

            super(opcode, 0, prefix, op, dstIsByte, srcIsByte, assertion, null);

        }

        protected AMD64RMOp(String opcode, int prefix1, int prefix2, int op, CPUFeature feature) {

            this(opcode, prefix1, prefix2, op, OpAssertion.WordOrLargerAssertion, feature);

        }

        protected AMD64RMOp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {

            super(opcode, prefix1, prefix2, op, assertion, feature);

        }

        @Override

        public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src) {

            assert verify(asm, size, dst, src);

            if (isSSEInstruction()) {

                Register nds = Register.None;

                switch (op) {

                    case 0x10:

                    case 0x51:

                        if ((size == SS) || (size == SD)) {

                            nds = dst;

                        }

                        break;

                    case 0x2A:

                    case 0x54:

                    case 0x55:

                    case 0x56:

                    case 0x57:

                    case 0x58:

                    case 0x59:

                    case 0x5A:

                    case 0x5C:

                    case 0x5D:

                    case 0x5E:

                    case 0x5F:

                        nds = dst;

                        break;

                    default:

                        break;

                }

                asm.simdPrefix(dst, nds, src, size, prefix1, prefix2, size == QWORD);

                asm.emitByte(op);

                asm.emitModRM(dst, src);

            } else {

                emitOpcode(asm, size, getRXB(dst, src), dst.encoding, src.encoding);

                asm.emitModRM(dst, src);

            }

        }

        public final void emit(AMD64Assembler asm, OperandSize size, Register dst, AMD64Address src) {

            assert verify(asm, size, dst, null);

            if (isSSEInstruction()) {

                Register nds = Register.None;

                switch (op) {

                    case 0x51:

                        if ((size == SS) || (size == SD)) {

                            nds = dst;

                        }

                        break;

                    case 0x2A:

                    case 0x54:

                    case 0x55:

                    case 0x56:

                    case 0x57:

                    case 0x58:

                    case 0x59:

                    case 0x5A:

                    case 0x5C:

                    case 0x5D:

                    case 0x5E:

                    case 0x5F:

                        nds = dst;

                        break;

                    default:

                        break;

                }

                asm.simdPrefix(dst, nds, src, size, prefix1, prefix2, size == QWORD);

                asm.emitByte(op);