--- a/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/AMD64Assembler.java Fri Feb 02 10:37:48 2018 -0500
+++ b/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/AMD64Assembler.java Fri Feb 02 17:28:17 2018 -0800
@@ -208,7 +208,6 @@
}
private static class VexOpcode {
- private static final int VEX_OPCODE_NONE = 0x0;
private static final int VEX_OPCODE_0F = 0x1;
private static final int VEX_OPCODE_0F_38 = 0x2;
private static final int VEX_OPCODE_0F_3A = 0x3;
@@ -861,9 +860,26 @@
break;
}
+ int opc = 0;
+ if (isSimd) {
+ switch (prefix2) {
+ case P_0F:
+ opc = VexOpcode.VEX_OPCODE_0F;
+ break;
+ case P_0F38:
+ opc = VexOpcode.VEX_OPCODE_0F_38;
+ break;
+ case P_0F3A:
+ opc = VexOpcode.VEX_OPCODE_0F_3A;
+ break;
+ default:
+ isSimd = false;
+ break;
+ }
+ }
+
if (isSimd) {
int pre;
- int opc;
boolean rexVexW = (size == QWORD) ? true : false;
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
int curPrefix = size.sizePrefix | prefix1;
@@ -881,20 +897,6 @@
pre = VexSimdPrefix.VEX_SIMD_NONE;
break;
}
- switch (prefix2) {
- case P_0F:
- opc = VexOpcode.VEX_OPCODE_0F;
- break;
- case P_0F38:
- opc = VexOpcode.VEX_OPCODE_0F_38;
- break;
- case P_0F3A:
- opc = VexOpcode.VEX_OPCODE_0F_3A;
- break;
- default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
- }
int encode;
if (noNds) {
encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes);
@@ -938,9 +940,26 @@
break;
}
+ int opc = 0;
+ if (isSimd) {
+ switch (prefix2) {
+ case P_0F:
+ opc = VexOpcode.VEX_OPCODE_0F;
+ break;
+ case P_0F38:
+ opc = VexOpcode.VEX_OPCODE_0F_38;
+ break;
+ case P_0F3A:
+ opc = VexOpcode.VEX_OPCODE_0F_3A;
+ break;
+ default:
+ isSimd = false;
+ break;
+ }
+ }
+
if (isSimd) {
int pre;
- int opc;
boolean rexVexW = (size == QWORD) ? true : false;
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
int curPrefix = size.sizePrefix | prefix1;
@@ -958,20 +977,6 @@
pre = VexSimdPrefix.VEX_SIMD_NONE;
break;
}
- switch (prefix2) {
- case P_0F:
- opc = VexOpcode.VEX_OPCODE_0F;
- break;
- case P_0F38:
- opc = VexOpcode.VEX_OPCODE_0F_38;
- break;
- case P_0F3A:
- opc = VexOpcode.VEX_OPCODE_0F_3A;
- break;
- default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
- }
if (noNds) {
asm.simdPrefix(dst, Register.None, src, pre, opc, attributes);
} else {
@@ -1055,8 +1060,7 @@
opc = VexOpcode.VEX_OPCODE_0F_3A;
break;
default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
+ throw GraalError.shouldNotReachHere("invalid VEX instruction prefix");
}
int encode;
encode = asm.simdPrefixAndEncode(dst, nds, src, pre, opc, attributes);
@@ -1096,8 +1100,7 @@
opc = VexOpcode.VEX_OPCODE_0F_3A;
break;
default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
+ throw GraalError.shouldNotReachHere("invalid VEX instruction prefix");
}
asm.simdPrefix(dst, nds, src, pre, opc, attributes);
asm.emitByte(op);
@@ -1163,9 +1166,26 @@
break;
}
+ int opc = 0;
+ if (isSimd) {
+ switch (prefix2) {
+ case P_0F:
+ opc = VexOpcode.VEX_OPCODE_0F;
+ break;
+ case P_0F38:
+ opc = VexOpcode.VEX_OPCODE_0F_38;
+ break;
+ case P_0F3A:
+ opc = VexOpcode.VEX_OPCODE_0F_3A;
+ break;
+ default:
+ isSimd = false;
+ break;
+ }
+ }
+
if (isSimd) {
int pre;
- int opc;
boolean rexVexW = (size == QWORD) ? true : false;
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
int curPrefix = size.sizePrefix | prefix1;
@@ -1183,20 +1203,6 @@
pre = VexSimdPrefix.VEX_SIMD_NONE;
break;
}
- switch (prefix2) {
- case P_0F:
- opc = VexOpcode.VEX_OPCODE_0F;
- break;
- case P_0F38:
- opc = VexOpcode.VEX_OPCODE_0F_38;
- break;
- case P_0F3A:
- opc = VexOpcode.VEX_OPCODE_0F_3A;
- break;
- default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
- }
int encode;
if (noNds) {
encode = asm.simdPrefixAndEncode(src, Register.None, dst, pre, opc, attributes);
@@ -1222,9 +1228,26 @@
break;
}
+ int opc = 0;
+ if (isSimd) {
+ switch (prefix2) {
+ case P_0F:
+ opc = VexOpcode.VEX_OPCODE_0F;
+ break;
+ case P_0F38:
+ opc = VexOpcode.VEX_OPCODE_0F_38;
+ break;
+ case P_0F3A:
+ opc = VexOpcode.VEX_OPCODE_0F_3A;
+ break;
+ default:
+ isSimd = false;
+ break;
+ }
+ }
+
if (isSimd) {
int pre;
- int opc;
boolean rexVexW = (size == QWORD) ? true : false;
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
int curPrefix = size.sizePrefix | prefix1;
@@ -1242,20 +1265,6 @@
pre = VexSimdPrefix.VEX_SIMD_NONE;
break;
}
- switch (prefix2) {
- case P_0F:
- opc = VexOpcode.VEX_OPCODE_0F;
- break;
- case P_0F38:
- opc = VexOpcode.VEX_OPCODE_0F_38;
- break;
- case P_0F3A:
- opc = VexOpcode.VEX_OPCODE_0F_3A;
- break;
- default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
- }
asm.simdPrefix(src, Register.None, dst, pre, opc, attributes);
asm.emitByte(op);
asm.emitOperandHelper(src, dst, 0);
@@ -1390,9 +1399,26 @@
break;
}
+ int opc = 0;
+ if (isSimd) {
+ switch (prefix2) {
+ case P_0F:
+ opc = VexOpcode.VEX_OPCODE_0F;
+ break;
+ case P_0F38:
+ opc = VexOpcode.VEX_OPCODE_0F_38;
+ break;
+ case P_0F3A:
+ opc = VexOpcode.VEX_OPCODE_0F_3A;
+ break;
+ default:
+ isSimd = false;
+ break;
+ }
+ }
+
if (isSimd) {
int pre;
- int opc;
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
int curPrefix = size.sizePrefix | prefix1;
switch (curPrefix) {
@@ -1409,20 +1435,6 @@
pre = VexSimdPrefix.VEX_SIMD_NONE;
break;
}
- switch (prefix2) {
- case P_0F:
- opc = VexOpcode.VEX_OPCODE_0F;
- break;
- case P_0F38:
- opc = VexOpcode.VEX_OPCODE_0F_38;
- break;
- case P_0F3A:
- opc = VexOpcode.VEX_OPCODE_0F_3A;
- break;
- default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
- }
int encode;
if (noNds) {
encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes);
@@ -1453,9 +1465,26 @@
break;
}
+ int opc = 0;
+ if (isSimd) {
+ switch (prefix2) {
+ case P_0F:
+ opc = VexOpcode.VEX_OPCODE_0F;
+ break;
+ case P_0F38:
+ opc = VexOpcode.VEX_OPCODE_0F_38;
+ break;
+ case P_0F3A:
+ opc = VexOpcode.VEX_OPCODE_0F_3A;
+ break;
+ default:
+ isSimd = false;
+ break;
+ }
+ }
+
if (isSimd) {
int pre;
- int opc;
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
int curPrefix = size.sizePrefix | prefix1;
switch (curPrefix) {
@@ -1472,21 +1501,6 @@
pre = VexSimdPrefix.VEX_SIMD_NONE;
break;
}
- switch (prefix2) {
- case P_0F:
- opc = VexOpcode.VEX_OPCODE_0F;
- break;
- case P_0F38:
- opc = VexOpcode.VEX_OPCODE_0F_38;
- break;
- case P_0F3A:
- opc = VexOpcode.VEX_OPCODE_0F_3A;
- break;
- default:
- opc = VexOpcode.VEX_OPCODE_NONE;
- break;
- }
-
if (noNds) {
asm.simdPrefix(dst, Register.None, src, pre, opc, attributes);
} else {