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/*
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* Copyright (c) 2009, 2016, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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package org.graalvm.compiler.asm.amd64;
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import static jdk.vm.ci.amd64.AMD64.CPU;
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import static jdk.vm.ci.amd64.AMD64.XMM;
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import static jdk.vm.ci.amd64.AMD64.r12;
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import static jdk.vm.ci.amd64.AMD64.r13;
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import static jdk.vm.ci.amd64.AMD64.rbp;
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import static jdk.vm.ci.amd64.AMD64.rip;
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import static jdk.vm.ci.amd64.AMD64.rsp;
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import static jdk.vm.ci.code.MemoryBarriers.STORE_LOAD;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseAddressNop;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseNormalNop;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.ADD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.AND;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.CMP;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.OR;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SBB;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SUB;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.XOR;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.DEC;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.INC;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NEG;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NOT;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.BYTE;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.DWORD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.PD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.PS;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.QWORD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.SD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.SS;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.WORD;
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import static org.graalvm.compiler.core.common.NumUtil.isByte;
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import static org.graalvm.compiler.core.common.NumUtil.isInt;
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import static org.graalvm.compiler.core.common.NumUtil.isShiftCount;
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import static org.graalvm.compiler.core.common.NumUtil.isUByte;
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import org.graalvm.compiler.asm.Assembler;
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import org.graalvm.compiler.asm.Label;
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import org.graalvm.compiler.asm.amd64.AMD64Address.Scale;
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import org.graalvm.compiler.core.common.NumUtil;
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import org.graalvm.compiler.debug.GraalError;
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import jdk.vm.ci.amd64.AMD64;
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import jdk.vm.ci.amd64.AMD64.CPUFeature;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.code.Register.RegisterCategory;
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import jdk.vm.ci.code.TargetDescription;
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import jdk.vm.ci.meta.PlatformKind;
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/**
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* This class implements an assembler that can encode most X86 instructions.
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*/
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public class AMD64Assembler extends Assembler {
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private static final int MinEncodingNeedsRex = 8;
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/**
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* The x86 condition codes used for conditional jumps/moves.
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*/
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public enum ConditionFlag {
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Zero(0x4, "|zero|"),
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NotZero(0x5, "|nzero|"),
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Equal(0x4, "="),
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NotEqual(0x5, "!="),
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Less(0xc, "<"),
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LessEqual(0xe, "<="),
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Greater(0xf, ">"),
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GreaterEqual(0xd, ">="),
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Below(0x2, "|<|"),
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BelowEqual(0x6, "|<=|"),
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Above(0x7, "|>|"),
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AboveEqual(0x3, "|>=|"),
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Overflow(0x0, "|of|"),
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NoOverflow(0x1, "|nof|"),
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CarrySet(0x2, "|carry|"),
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CarryClear(0x3, "|ncarry|"),
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Negative(0x8, "|neg|"),
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Positive(0x9, "|pos|"),
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Parity(0xa, "|par|"),
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NoParity(0xb, "|npar|");
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private final int value;
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private final String operator;
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ConditionFlag(int value, String operator) {
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this.value = value;
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this.operator = operator;
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}
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public ConditionFlag negate() {
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switch (this) {
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case Zero:
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return NotZero;
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case NotZero:
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return Zero;
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case Equal:
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return NotEqual;
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case NotEqual:
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return Equal;
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case Less:
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return GreaterEqual;
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case LessEqual:
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return Greater;
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case Greater:
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return LessEqual;
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case GreaterEqual:
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return Less;
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case Below:
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return AboveEqual;
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case BelowEqual:
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return Above;
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case Above:
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return BelowEqual;
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case AboveEqual:
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return Below;
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case Overflow:
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return NoOverflow;
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case NoOverflow:
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return Overflow;
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case CarrySet:
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return CarryClear;
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case CarryClear:
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return CarrySet;
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case Negative:
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return Positive;
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case Positive:
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return Negative;
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case Parity:
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return NoParity;
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case NoParity:
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return Parity;
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}
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throw new IllegalArgumentException();
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}
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public int getValue() {
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return value;
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}
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@Override
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public String toString() {
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return operator;
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}
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}
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/**
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* Constants for X86 prefix bytes.
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*/
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private static class Prefix {
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private static final int REX = 0x40;
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private static final int REXB = 0x41;
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private static final int REXX = 0x42;
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private static final int REXXB = 0x43;
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private static final int REXR = 0x44;
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private static final int REXRB = 0x45;
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private static final int REXRX = 0x46;
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private static final int REXRXB = 0x47;
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private static final int REXW = 0x48;
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private static final int REXWB = 0x49;
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private static final int REXWX = 0x4A;
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private static final int REXWXB = 0x4B;
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private static final int REXWR = 0x4C;
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private static final int REXWRB = 0x4D;
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private static final int REXWRX = 0x4E;
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private static final int REXWRXB = 0x4F;
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private static final int VEX_3BYTES = 0xC4;
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private static final int VEX_2BYTES = 0xC5;
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}
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private static class VexPrefix {
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private static final int VEX_R = 0x80;
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private static final int VEX_W = 0x80;
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}
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private static class AvxVectorLen {
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private static final int AVX_128bit = 0x0;
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private static final int AVX_256bit = 0x1;
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}
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private static class VexSimdPrefix {
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private static final int VEX_SIMD_NONE = 0x0;
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private static final int VEX_SIMD_66 = 0x1;
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private static final int VEX_SIMD_F3 = 0x2;
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private static final int VEX_SIMD_F2 = 0x3;
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}
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private static class VexOpcode {
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private static final int VEX_OPCODE_NONE = 0x0;
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private static final int VEX_OPCODE_0F = 0x1;
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private static final int VEX_OPCODE_0F_38 = 0x2;
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private static final int VEX_OPCODE_0F_3A = 0x3;
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}
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private AMD64InstructionAttr curAttributes;
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AMD64InstructionAttr getCurAttributes() {
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return curAttributes;
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}
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void setCurAttributes(AMD64InstructionAttr attributes) {
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curAttributes = attributes;
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}
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/**
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* The x86 operand sizes.
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*/
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public enum OperandSize {
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BYTE(1, AMD64Kind.BYTE) {
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@Override
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protected void emitImmediate(AMD64Assembler asm, int imm) {
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assert imm == (byte) imm;
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asm.emitByte(imm);
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}
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@Override
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protected int immediateSize() {
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return 1;
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}
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},
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WORD(2, AMD64Kind.WORD, 0x66) {
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@Override
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protected void emitImmediate(AMD64Assembler asm, int imm) {
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assert imm == (short) imm;
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asm.emitShort(imm);
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}
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@Override
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protected int immediateSize() {
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return 2;
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}
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},
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DWORD(4, AMD64Kind.DWORD) {
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@Override
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protected void emitImmediate(AMD64Assembler asm, int imm) {
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asm.emitInt(imm);
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}
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@Override
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protected int immediateSize() {
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return 4;
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}
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},
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QWORD(8, AMD64Kind.QWORD) {
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@Override
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protected void emitImmediate(AMD64Assembler asm, int imm) {
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asm.emitInt(imm);
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}
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@Override
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protected int immediateSize() {
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return 4;
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}
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},
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SS(4, AMD64Kind.SINGLE, 0xF3, true),
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SD(8, AMD64Kind.DOUBLE, 0xF2, true),
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PS(16, AMD64Kind.V128_SINGLE, true),
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PD(16, AMD64Kind.V128_DOUBLE, 0x66, true);
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private final int sizePrefix;
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private final int bytes;
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private final boolean xmm;
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private final AMD64Kind kind;
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OperandSize(int bytes, AMD64Kind kind) {
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this(bytes, kind, 0);
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}
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OperandSize(int bytes, AMD64Kind kind, int sizePrefix) {
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this(bytes, kind, sizePrefix, false);
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}
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OperandSize(int bytes, AMD64Kind kind, boolean xmm) {
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this(bytes, kind, 0, xmm);
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}
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OperandSize(int bytes, AMD64Kind kind, int sizePrefix, boolean xmm) {
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this.sizePrefix = sizePrefix;
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this.bytes = bytes;
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this.kind = kind;
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this.xmm = xmm;
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}
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public int getBytes() {
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return bytes;
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}
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public boolean isXmmType() {
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return xmm;
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}
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public AMD64Kind getKind() {
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return kind;
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}
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public static OperandSize get(PlatformKind kind) {
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for (OperandSize operandSize : OperandSize.values()) {
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if (operandSize.kind.equals(kind)) {
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return operandSize;
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}
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}
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throw GraalError.shouldNotReachHere("Unexpected kind: " + kind.toString());
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}
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/**
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* Emit an immediate of this size. Note that immediate {@link #QWORD} operands are encoded
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* as sign-extended 32-bit values.
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*
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* @param asm
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* @param imm
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*/
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protected void emitImmediate(AMD64Assembler asm, int imm) {
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throw new UnsupportedOperationException();
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}
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protected int immediateSize() {
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throw new UnsupportedOperationException();
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}
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}
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/**
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* Operand size and register type constraints.
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*/
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private enum OpAssertion {
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ByteAssertion(CPU, CPU, BYTE),
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ByteOrLargerAssertion(CPU, CPU, BYTE, WORD, DWORD, QWORD),
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WordOrLargerAssertion(CPU, CPU, WORD, DWORD, QWORD),
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DwordOrLargerAssertion(CPU, CPU, DWORD, QWORD),
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WordOrDwordAssertion(CPU, CPU, WORD, QWORD),
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QwordAssertion(CPU, CPU, QWORD),
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FloatAssertion(XMM, XMM, SS, SD, PS, PD),
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PackedFloatAssertion(XMM, XMM, PS, PD),
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SingleAssertion(XMM, XMM, SS),
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DoubleAssertion(XMM, XMM, SD),
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PackedDoubleAssertion(XMM, XMM, PD),
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IntToFloatAssertion(XMM, CPU, DWORD, QWORD),
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FloatToIntAssertion(CPU, XMM, DWORD, QWORD);
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private final RegisterCategory resultCategory;
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private final RegisterCategory inputCategory;
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private final OperandSize[] allowedSizes;
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OpAssertion(RegisterCategory resultCategory, RegisterCategory inputCategory, OperandSize... allowedSizes) {
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this.resultCategory = resultCategory;
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this.inputCategory = inputCategory;
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this.allowedSizes = allowedSizes;
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}
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protected boolean checkOperands(AMD64Op op, OperandSize size, Register resultReg, Register inputReg) {
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assert resultReg == null || resultCategory.equals(resultReg.getRegisterCategory()) : "invalid result register " + resultReg + " used in " + op;
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assert inputReg == null || inputCategory.equals(inputReg.getRegisterCategory()) : "invalid input register " + inputReg + " used in " + op;
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for (OperandSize s : allowedSizes) {
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if (size == s) {
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return true;
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}
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}
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assert false : "invalid operand size " + size + " used in " + op;
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return false;
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}
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}
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public abstract static class OperandDataAnnotation extends CodeAnnotation {
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/**
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|
395 |
* The position (bytes from the beginning of the method) of the operand.
|
|
396 |
*/
|
|
397 |
public final int operandPosition;
|
|
398 |
/**
|
|
399 |
* The size of the operand, in bytes.
|
|
400 |
*/
|
|
401 |
public final int operandSize;
|
|
402 |
/**
|
|
403 |
* The position (bytes from the beginning of the method) of the next instruction. On AMD64,
|
|
404 |
* RIP-relative operands are relative to this position.
|
|
405 |
*/
|
|
406 |
public final int nextInstructionPosition;
|
|
407 |
|
|
408 |
OperandDataAnnotation(int instructionPosition, int operandPosition, int operandSize, int nextInstructionPosition) {
|
|
409 |
super(instructionPosition);
|
|
410 |
|
|
411 |
this.operandPosition = operandPosition;
|
|
412 |
this.operandSize = operandSize;
|
|
413 |
this.nextInstructionPosition = nextInstructionPosition;
|
|
414 |
}
|
|
415 |
|
|
416 |
@Override
|
|
417 |
public String toString() {
|
|
418 |
return getClass().getSimpleName() + " instruction [" + instructionPosition + ", " + nextInstructionPosition + "[ operand at " + operandPosition + " size " + operandSize;
|
|
419 |
}
|
|
420 |
}
|
|
421 |
|
|
422 |
/**
|
|
423 |
* Annotation that stores additional information about the displacement of a
|
|
424 |
* {@link Assembler#getPlaceholder placeholder address} that needs patching.
|
|
425 |
*/
|
|
426 |
public static class AddressDisplacementAnnotation extends OperandDataAnnotation {
|
|
427 |
AddressDisplacementAnnotation(int instructionPosition, int operandPosition, int operndSize, int nextInstructionPosition) {
|
|
428 |
super(instructionPosition, operandPosition, operndSize, nextInstructionPosition);
|
|
429 |
}
|
|
430 |
}
|
|
431 |
|
|
432 |
/**
|
|
433 |
* Annotation that stores additional information about the immediate operand, e.g., of a call
|
|
434 |
* instruction, that needs patching.
|
|
435 |
*/
|
|
436 |
public static class ImmediateOperandAnnotation extends OperandDataAnnotation {
|
|
437 |
ImmediateOperandAnnotation(int instructionPosition, int operandPosition, int operndSize, int nextInstructionPosition) {
|
|
438 |
super(instructionPosition, operandPosition, operndSize, nextInstructionPosition);
|
|
439 |
}
|
|
440 |
}
|
|
441 |
|
|
442 |
/**
|
|
443 |
* Constructs an assembler for the AMD64 architecture.
|
|
444 |
*/
|
|
445 |
public AMD64Assembler(TargetDescription target) {
|
|
446 |
super(target);
|
|
447 |
}
|
|
448 |
|
|
449 |
public boolean supports(CPUFeature feature) {
|
|
450 |
return ((AMD64) target.arch).getFeatures().contains(feature);
|
|
451 |
}
|
|
452 |
|
|
453 |
private static int encode(Register r) {
|
|
454 |
assert r.encoding < 16 && r.encoding >= 0 : "encoding out of range: " + r.encoding;
|
|
455 |
return r.encoding & 0x7;
|
|
456 |
}
|
|
457 |
|
|
458 |
/**
|
|
459 |
* Get RXB bits for register-register instruction. In that encoding, ModRM.rm contains a
|
|
460 |
* register index. The R bit extends the ModRM.reg field and the B bit extends the ModRM.rm
|
|
461 |
* field. The X bit must be 0.
|
|
462 |
*/
|
|
463 |
protected static int getRXB(Register reg, Register rm) {
|
|
464 |
int rxb = (reg == null ? 0 : reg.encoding & 0x08) >> 1;
|
|
465 |
rxb |= (rm == null ? 0 : rm.encoding & 0x08) >> 3;
|
|
466 |
return rxb;
|
|
467 |
}
|
|
468 |
|
|
469 |
/**
|
|
470 |
* Get RXB bits for register-memory instruction. The R bit extends the ModRM.reg field. There
|
|
471 |
* are two cases for the memory operand:<br>
|
|
472 |
* ModRM.rm contains the base register: In that case, B extends the ModRM.rm field and X = 0.
|
|
473 |
* <br>
|
|
474 |
* There is an SIB byte: In that case, X extends SIB.index and B extends SIB.base.
|
|
475 |
*/
|
|
476 |
protected static int getRXB(Register reg, AMD64Address rm) {
|
|
477 |
int rxb = (reg == null ? 0 : reg.encoding & 0x08) >> 1;
|
|
478 |
if (!rm.getIndex().equals(Register.None)) {
|
|
479 |
rxb |= (rm.getIndex().encoding & 0x08) >> 2;
|
|
480 |
}
|
|
481 |
if (!rm.getBase().equals(Register.None)) {
|
|
482 |
rxb |= (rm.getBase().encoding & 0x08) >> 3;
|
|
483 |
}
|
|
484 |
return rxb;
|
|
485 |
}
|
|
486 |
|
|
487 |
/**
|
|
488 |
* Emit the ModR/M byte for one register operand and an opcode extension in the R field.
|
|
489 |
* <p>
|
|
490 |
* Format: [ 11 reg r/m ]
|
|
491 |
*/
|
|
492 |
protected void emitModRM(int reg, Register rm) {
|
|
493 |
assert (reg & 0x07) == reg;
|
|
494 |
emitByte(0xC0 | (reg << 3) | (rm.encoding & 0x07));
|
|
495 |
}
|
|
496 |
|
|
497 |
/**
|
|
498 |
* Emit the ModR/M byte for two register operands.
|
|
499 |
* <p>
|
|
500 |
* Format: [ 11 reg r/m ]
|
|
501 |
*/
|
|
502 |
protected void emitModRM(Register reg, Register rm) {
|
|
503 |
emitModRM(reg.encoding & 0x07, rm);
|
|
504 |
}
|
|
505 |
|
|
506 |
protected void emitOperandHelper(Register reg, AMD64Address addr, int additionalInstructionSize) {
|
|
507 |
assert !reg.equals(Register.None);
|
|
508 |
emitOperandHelper(encode(reg), addr, false, additionalInstructionSize);
|
|
509 |
}
|
|
510 |
|
|
511 |
/**
|
|
512 |
* Emits the ModR/M byte and optionally the SIB byte for one register and one memory operand.
|
|
513 |
*
|
|
514 |
* @param force4Byte use 4 byte encoding for displacements that would normally fit in a byte
|
|
515 |
*/
|
|
516 |
protected void emitOperandHelper(Register reg, AMD64Address addr, boolean force4Byte, int additionalInstructionSize) {
|
|
517 |
assert !reg.equals(Register.None);
|
|
518 |
emitOperandHelper(encode(reg), addr, force4Byte, additionalInstructionSize);
|
|
519 |
}
|
|
520 |
|
|
521 |
protected void emitOperandHelper(int reg, AMD64Address addr, int additionalInstructionSize) {
|
|
522 |
emitOperandHelper(reg, addr, false, additionalInstructionSize);
|
|
523 |
}
|
|
524 |
|
|
525 |
/**
|
|
526 |
* Emits the ModR/M byte and optionally the SIB byte for one memory operand and an opcode
|
|
527 |
* extension in the R field.
|
|
528 |
*
|
|
529 |
* @param force4Byte use 4 byte encoding for displacements that would normally fit in a byte
|
|
530 |
* @param additionalInstructionSize the number of bytes that will be emitted after the operand,
|
|
531 |
* so that the start position of the next instruction can be computed even though
|
|
532 |
* this instruction has not been completely emitted yet.
|
|
533 |
*/
|
|
534 |
protected void emitOperandHelper(int reg, AMD64Address addr, boolean force4Byte, int additionalInstructionSize) {
|
|
535 |
assert (reg & 0x07) == reg;
|
|
536 |
int regenc = reg << 3;
|
|
537 |
|
|
538 |
Register base = addr.getBase();
|
|
539 |
Register index = addr.getIndex();
|
|
540 |
|
|
541 |
AMD64Address.Scale scale = addr.getScale();
|
|
542 |
int disp = addr.getDisplacement();
|
|
543 |
|
|
544 |
if (base.equals(AMD64.rip)) { // also matches addresses returned by getPlaceholder()
|
|
545 |
// [00 000 101] disp32
|
|
546 |
assert index.equals(Register.None) : "cannot use RIP relative addressing with index register";
|
|
547 |
emitByte(0x05 | regenc);
|
|
548 |
if (codePatchingAnnotationConsumer != null && addr.instructionStartPosition >= 0) {
|
|
549 |
codePatchingAnnotationConsumer.accept(new AddressDisplacementAnnotation(addr.instructionStartPosition, position(), 4, position() + 4 + additionalInstructionSize));
|
|
550 |
}
|
|
551 |
emitInt(disp);
|
|
552 |
} else if (base.isValid()) {
|
|
553 |
int baseenc = base.isValid() ? encode(base) : 0;
|
|
554 |
if (index.isValid()) {
|
|
555 |
int indexenc = encode(index) << 3;
|
|
556 |
// [base + indexscale + disp]
|
|
557 |
if (disp == 0 && !base.equals(rbp) && !base.equals(r13)) {
|
|
558 |
// [base + indexscale]
|
|
559 |
// [00 reg 100][ss index base]
|
|
560 |
assert !index.equals(rsp) : "illegal addressing mode";
|
|
561 |
emitByte(0x04 | regenc);
|
|
562 |
emitByte(scale.log2 << 6 | indexenc | baseenc);
|
|
563 |
} else if (isByte(disp) && !force4Byte) {
|
|
564 |
// [base + indexscale + imm8]
|
|
565 |
// [01 reg 100][ss index base] imm8
|
|
566 |
assert !index.equals(rsp) : "illegal addressing mode";
|
|
567 |
emitByte(0x44 | regenc);
|
|
568 |
emitByte(scale.log2 << 6 | indexenc | baseenc);
|
|
569 |
emitByte(disp & 0xFF);
|
|
570 |
} else {
|
|
571 |
// [base + indexscale + disp32]
|
|
572 |
// [10 reg 100][ss index base] disp32
|
|
573 |
assert !index.equals(rsp) : "illegal addressing mode";
|
|
574 |
emitByte(0x84 | regenc);
|
|
575 |
emitByte(scale.log2 << 6 | indexenc | baseenc);
|
|
576 |
emitInt(disp);
|
|
577 |
}
|
|
578 |
} else if (base.equals(rsp) || base.equals(r12)) {
|
|
579 |
// [rsp + disp]
|
|
580 |
if (disp == 0) {
|
|
581 |
// [rsp]
|
|
582 |
// [00 reg 100][00 100 100]
|
|
583 |
emitByte(0x04 | regenc);
|
|
584 |
emitByte(0x24);
|
|
585 |
} else if (isByte(disp) && !force4Byte) {
|
|
586 |
// [rsp + imm8]
|
|
587 |
// [01 reg 100][00 100 100] disp8
|
|
588 |
emitByte(0x44 | regenc);
|
|
589 |
emitByte(0x24);
|
|
590 |
emitByte(disp & 0xFF);
|
|
591 |
} else {
|
|
592 |
// [rsp + imm32]
|
|
593 |
// [10 reg 100][00 100 100] disp32
|
|
594 |
emitByte(0x84 | regenc);
|
|
595 |
emitByte(0x24);
|
|
596 |
emitInt(disp);
|
|
597 |
}
|
|
598 |
} else {
|
|
599 |
// [base + disp]
|
|
600 |
assert !base.equals(rsp) && !base.equals(r12) : "illegal addressing mode";
|
|
601 |
if (disp == 0 && !base.equals(rbp) && !base.equals(r13)) {
|
|
602 |
// [base]
|
|
603 |
// [00 reg base]
|
|
604 |
emitByte(0x00 | regenc | baseenc);
|
|
605 |
} else if (isByte(disp) && !force4Byte) {
|
|
606 |
// [base + disp8]
|
|
607 |
// [01 reg base] disp8
|
|
608 |
emitByte(0x40 | regenc | baseenc);
|
|
609 |
emitByte(disp & 0xFF);
|
|
610 |
} else {
|
|
611 |
// [base + disp32]
|
|
612 |
// [10 reg base] disp32
|
|
613 |
emitByte(0x80 | regenc | baseenc);
|
|
614 |
emitInt(disp);
|
|
615 |
}
|
|
616 |
}
|
|
617 |
} else {
|
|
618 |
if (index.isValid()) {
|
|
619 |
int indexenc = encode(index) << 3;
|
|
620 |
// [indexscale + disp]
|
|
621 |
// [00 reg 100][ss index 101] disp32
|
|
622 |
assert !index.equals(rsp) : "illegal addressing mode";
|
|
623 |
emitByte(0x04 | regenc);
|
|
624 |
emitByte(scale.log2 << 6 | indexenc | 0x05);
|
|
625 |
emitInt(disp);
|
|
626 |
} else {
|
|
627 |
// [disp] ABSOLUTE
|
|
628 |
// [00 reg 100][00 100 101] disp32
|
|
629 |
emitByte(0x04 | regenc);
|
|
630 |
emitByte(0x25);
|
|
631 |
emitInt(disp);
|
|
632 |
}
|
|
633 |
}
|
|
634 |
setCurAttributes(null);
|
|
635 |
}
|
|
636 |
|
|
637 |
/**
|
|
638 |
* Base class for AMD64 opcodes.
|
|
639 |
*/
|
|
640 |
public static class AMD64Op {
|
|
641 |
|
|
642 |
protected static final int P_0F = 0x0F;
|
|
643 |
protected static final int P_0F38 = 0x380F;
|
|
644 |
protected static final int P_0F3A = 0x3A0F;
|
|
645 |
|
|
646 |
private final String opcode;
|
|
647 |
|
|
648 |
protected final int prefix1;
|
|
649 |
protected final int prefix2;
|
|
650 |
protected final int op;
|
|
651 |
|
|
652 |
private final boolean dstIsByte;
|
|
653 |
private final boolean srcIsByte;
|
|
654 |
|
|
655 |
private final OpAssertion assertion;
|
|
656 |
private final CPUFeature feature;
|
|
657 |
|
|
658 |
protected AMD64Op(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
659 |
this(opcode, prefix1, prefix2, op, assertion == OpAssertion.ByteAssertion, assertion == OpAssertion.ByteAssertion, assertion, feature);
|
|
660 |
}
|
|
661 |
|
|
662 |
protected AMD64Op(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {
|
|
663 |
this.opcode = opcode;
|
|
664 |
this.prefix1 = prefix1;
|
|
665 |
this.prefix2 = prefix2;
|
|
666 |
this.op = op;
|
|
667 |
|
|
668 |
this.dstIsByte = dstIsByte;
|
|
669 |
this.srcIsByte = srcIsByte;
|
|
670 |
|
|
671 |
this.assertion = assertion;
|
|
672 |
this.feature = feature;
|
|
673 |
}
|
|
674 |
|
|
675 |
protected final void emitOpcode(AMD64Assembler asm, OperandSize size, int rxb, int dstEnc, int srcEnc) {
|
|
676 |
if (prefix1 != 0) {
|
|
677 |
asm.emitByte(prefix1);
|
|
678 |
}
|
|
679 |
if (size.sizePrefix != 0) {
|
|
680 |
asm.emitByte(size.sizePrefix);
|
|
681 |
}
|
|
682 |
int rexPrefix = 0x40 | rxb;
|
|
683 |
if (size == QWORD) {
|
|
684 |
rexPrefix |= 0x08;
|
|
685 |
}
|
|
686 |
if (rexPrefix != 0x40 || (dstIsByte && dstEnc >= 4) || (srcIsByte && srcEnc >= 4)) {
|
|
687 |
asm.emitByte(rexPrefix);
|
|
688 |
}
|
|
689 |
if (prefix2 > 0xFF) {
|
|
690 |
asm.emitShort(prefix2);
|
|
691 |
} else if (prefix2 > 0) {
|
|
692 |
asm.emitByte(prefix2);
|
|
693 |
}
|
|
694 |
asm.emitByte(op);
|
|
695 |
}
|
|
696 |
|
|
697 |
protected final boolean verify(AMD64Assembler asm, OperandSize size, Register resultReg, Register inputReg) {
|
|
698 |
assert feature == null || asm.supports(feature) : String.format("unsupported feature %s required for %s", feature, opcode);
|
|
699 |
assert assertion.checkOperands(this, size, resultReg, inputReg);
|
|
700 |
return true;
|
|
701 |
}
|
|
702 |
|
|
703 |
@Override
|
|
704 |
public String toString() {
|
|
705 |
return opcode;
|
|
706 |
}
|
|
707 |
}
|
|
708 |
|
|
709 |
/**
|
|
710 |
* Base class for AMD64 opcodes with immediate operands.
|
|
711 |
*/
|
|
712 |
public static class AMD64ImmOp extends AMD64Op {
|
|
713 |
|
|
714 |
private final boolean immIsByte;
|
|
715 |
|
|
716 |
protected AMD64ImmOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion) {
|
|
717 |
super(opcode, 0, prefix, op, assertion, null);
|
|
718 |
this.immIsByte = immIsByte;
|
|
719 |
}
|
|
720 |
|
|
721 |
protected final void emitImmediate(AMD64Assembler asm, OperandSize size, int imm) {
|
|
722 |
if (immIsByte) {
|
|
723 |
assert imm == (byte) imm;
|
|
724 |
asm.emitByte(imm);
|
|
725 |
} else {
|
|
726 |
size.emitImmediate(asm, imm);
|
|
727 |
}
|
|
728 |
}
|
|
729 |
|
|
730 |
protected final int immediateSize(OperandSize size) {
|
|
731 |
if (immIsByte) {
|
|
732 |
return 1;
|
|
733 |
} else {
|
|
734 |
return size.bytes;
|
|
735 |
}
|
|
736 |
}
|
|
737 |
}
|
|
738 |
|
|
739 |
/**
|
|
740 |
* Opcode with operand order of either RM or MR for 2 address forms.
|
|
741 |
*/
|
|
742 |
public abstract static class AMD64RROp extends AMD64Op {
|
|
743 |
|
|
744 |
protected AMD64RROp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
745 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
746 |
}
|
|
747 |
|
|
748 |
protected AMD64RROp(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {
|
|
749 |
super(opcode, prefix1, prefix2, op, dstIsByte, srcIsByte, assertion, feature);
|
|
750 |
}
|
|
751 |
|
|
752 |
public abstract void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src);
|
|
753 |
}
|
|
754 |
|
|
755 |
/**
|
|
756 |
* Opcode with operand order of either RM or MR for 3 address forms.
|
|
757 |
*/
|
|
758 |
public abstract static class AMD64RRROp extends AMD64Op {
|
|
759 |
|
|
760 |
protected AMD64RRROp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
761 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
762 |
}
|
|
763 |
|
|
764 |
protected AMD64RRROp(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {
|
|
765 |
super(opcode, prefix1, prefix2, op, dstIsByte, srcIsByte, assertion, feature);
|
|
766 |
}
|
|
767 |
|
|
768 |
public abstract void emit(AMD64Assembler asm, OperandSize size, Register dst, Register nds, Register src);
|
|
769 |
}
|
|
770 |
|
|
771 |
/**
|
|
772 |
* Opcode with operand order of RM.
|
|
773 |
*/
|
|
774 |
public static class AMD64RMOp extends AMD64RROp {
|
|
775 |
// @formatter:off
|
48190
|
776 |
public static final AMD64RMOp IMUL = new AMD64RMOp("IMUL", P_0F, 0xAF, OpAssertion.ByteOrLargerAssertion);
|
43972
|
777 |
public static final AMD64RMOp BSF = new AMD64RMOp("BSF", P_0F, 0xBC);
|
|
778 |
public static final AMD64RMOp BSR = new AMD64RMOp("BSR", P_0F, 0xBD);
|
|
779 |
public static final AMD64RMOp POPCNT = new AMD64RMOp("POPCNT", 0xF3, P_0F, 0xB8, CPUFeature.POPCNT);
|
|
780 |
public static final AMD64RMOp TZCNT = new AMD64RMOp("TZCNT", 0xF3, P_0F, 0xBC, CPUFeature.BMI1);
|
|
781 |
public static final AMD64RMOp LZCNT = new AMD64RMOp("LZCNT", 0xF3, P_0F, 0xBD, CPUFeature.LZCNT);
|
48190
|
782 |
public static final AMD64RMOp MOVZXB = new AMD64RMOp("MOVZXB", P_0F, 0xB6, false, true, OpAssertion.WordOrLargerAssertion);
|
|
783 |
public static final AMD64RMOp MOVZX = new AMD64RMOp("MOVZX", P_0F, 0xB7, OpAssertion.DwordOrLargerAssertion);
|
|
784 |
public static final AMD64RMOp MOVSXB = new AMD64RMOp("MOVSXB", P_0F, 0xBE, false, true, OpAssertion.WordOrLargerAssertion);
|
|
785 |
public static final AMD64RMOp MOVSX = new AMD64RMOp("MOVSX", P_0F, 0xBF, OpAssertion.DwordOrLargerAssertion);
|
|
786 |
public static final AMD64RMOp MOVSXD = new AMD64RMOp("MOVSXD", 0x63, OpAssertion.QwordAssertion);
|
43972
|
787 |
public static final AMD64RMOp MOVB = new AMD64RMOp("MOVB", 0x8A, OpAssertion.ByteAssertion);
|
|
788 |
public static final AMD64RMOp MOV = new AMD64RMOp("MOV", 0x8B);
|
|
789 |
|
|
790 |
// MOVD/MOVQ and MOVSS/MOVSD are the same opcode, just with different operand size prefix
|
48190
|
791 |
public static final AMD64RMOp MOVD = new AMD64RMOp("MOVD", 0x66, P_0F, 0x6E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
792 |
public static final AMD64RMOp MOVQ = new AMD64RMOp("MOVQ", 0x66, P_0F, 0x6E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
793 |
public static final AMD64RMOp MOVSS = new AMD64RMOp("MOVSS", P_0F, 0x10, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
|
794 |
public static final AMD64RMOp MOVSD = new AMD64RMOp("MOVSD", P_0F, 0x10, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
43972
|
795 |
|
|
796 |
// TEST is documented as MR operation, but it's symmetric, and using it as RM operation is more convenient.
|
|
797 |
public static final AMD64RMOp TESTB = new AMD64RMOp("TEST", 0x84, OpAssertion.ByteAssertion);
|
|
798 |
public static final AMD64RMOp TEST = new AMD64RMOp("TEST", 0x85);
|
|
799 |
// @formatter:on
|
|
800 |
|
|
801 |
protected AMD64RMOp(String opcode, int op) {
|
|
802 |
this(opcode, 0, op);
|
|
803 |
}
|
|
804 |
|
|
805 |
protected AMD64RMOp(String opcode, int op, OpAssertion assertion) {
|
|
806 |
this(opcode, 0, op, assertion);
|
|
807 |
}
|
|
808 |
|
|
809 |
protected AMD64RMOp(String opcode, int prefix, int op) {
|
|
810 |
this(opcode, 0, prefix, op, null);
|
|
811 |
}
|
|
812 |
|
|
813 |
protected AMD64RMOp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
814 |
this(opcode, 0, prefix, op, assertion, null);
|
|
815 |
}
|
|
816 |
|
|
817 |
protected AMD64RMOp(String opcode, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
818 |
this(opcode, 0, prefix, op, assertion, feature);
|
|
819 |
}
|
|
820 |
|
|
821 |
protected AMD64RMOp(String opcode, int prefix, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion) {
|
|
822 |
super(opcode, 0, prefix, op, dstIsByte, srcIsByte, assertion, null);
|
|
823 |
}
|
|
824 |
|
|
825 |
protected AMD64RMOp(String opcode, int prefix1, int prefix2, int op, CPUFeature feature) {
|
48190
|
826 |
this(opcode, prefix1, prefix2, op, OpAssertion.WordOrLargerAssertion, feature);
|
43972
|
827 |
}
|
|
828 |
|
|
829 |
protected AMD64RMOp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
830 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
831 |
}
|
|
832 |
|
|
833 |
@Override
|
|
834 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src) {
|
|
835 |
assert verify(asm, size, dst, src);
|
|
836 |
boolean isSimd = false;
|
|
837 |
boolean noNds = false;
|
|
838 |
|
|
839 |
switch (op) {
|
|
840 |
case 0x2A:
|
|
841 |
case 0x2C:
|
|
842 |
case 0x2E:
|
|
843 |
case 0x5A:
|
|
844 |
case 0x6E:
|
|
845 |
isSimd = true;
|
|
846 |
noNds = true;
|
|
847 |
break;
|
|
848 |
case 0x10:
|
|
849 |
case 0x51:
|
|
850 |
case 0x54:
|
|
851 |
case 0x55:
|
|
852 |
case 0x56:
|
|
853 |
case 0x57:
|
|
854 |
case 0x58:
|
|
855 |
case 0x59:
|
|
856 |
case 0x5C:
|
|
857 |
case 0x5D:
|
|
858 |
case 0x5E:
|
|
859 |
case 0x5F:
|
|
860 |
isSimd = true;
|
|
861 |
break;
|
|
862 |
}
|
|
863 |
|
|
864 |
if (isSimd) {
|
|
865 |
int pre;
|
|
866 |
int opc;
|
|
867 |
boolean rexVexW = (size == QWORD) ? true : false;
|
|
868 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
869 |
int curPrefix = size.sizePrefix | prefix1;
|
|
870 |
switch (curPrefix) {
|
|
871 |
case 0x66:
|
|
872 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
873 |
break;
|
|
874 |
case 0xF2:
|
|
875 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
876 |
break;
|
|
877 |
case 0xF3:
|
|
878 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
879 |
break;
|
|
880 |
default:
|
|
881 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
882 |
break;
|
|
883 |
}
|
|
884 |
switch (prefix2) {
|
|
885 |
case P_0F:
|
|
886 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
887 |
break;
|
|
888 |
case P_0F38:
|
|
889 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
890 |
break;
|
|
891 |
case P_0F3A:
|
|
892 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
893 |
break;
|
|
894 |
default:
|
|
895 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
896 |
break;
|
|
897 |
}
|
|
898 |
int encode;
|
|
899 |
if (noNds) {
|
|
900 |
encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes);
|
|
901 |
} else {
|
|
902 |
encode = asm.simdPrefixAndEncode(dst, dst, src, pre, opc, attributes);
|
|
903 |
}
|
|
904 |
asm.emitByte(op);
|
|
905 |
asm.emitByte(0xC0 | encode);
|
|
906 |
} else {
|
|
907 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, src.encoding);
|
|
908 |
asm.emitModRM(dst, src);
|
|
909 |
}
|
|
910 |
}
|
|
911 |
|
|
912 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, AMD64Address src) {
|
|
913 |
assert verify(asm, size, dst, null);
|
|
914 |
boolean isSimd = false;
|
|
915 |
boolean noNds = false;
|
|
916 |
|
|
917 |
switch (op) {
|
|
918 |
case 0x10:
|
|
919 |
case 0x2A:
|
|
920 |
case 0x2C:
|
|
921 |
case 0x2E:
|
|
922 |
case 0x6E:
|
|
923 |
isSimd = true;
|
|
924 |
noNds = true;
|
|
925 |
break;
|
|
926 |
case 0x51:
|
|
927 |
case 0x54:
|
|
928 |
case 0x55:
|
|
929 |
case 0x56:
|
|
930 |
case 0x57:
|
|
931 |
case 0x58:
|
|
932 |
case 0x59:
|
|
933 |
case 0x5C:
|
|
934 |
case 0x5D:
|
|
935 |
case 0x5E:
|
|
936 |
case 0x5F:
|
|
937 |
isSimd = true;
|
|
938 |
break;
|
|
939 |
}
|
|
940 |
|
|
941 |
if (isSimd) {
|
|
942 |
int pre;
|
|
943 |
int opc;
|
|
944 |
boolean rexVexW = (size == QWORD) ? true : false;
|
|
945 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
946 |
int curPrefix = size.sizePrefix | prefix1;
|
|
947 |
switch (curPrefix) {
|
|
948 |
case 0x66:
|
|
949 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
950 |
break;
|
|
951 |
case 0xF2:
|
|
952 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
953 |
break;
|
|
954 |
case 0xF3:
|
|
955 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
956 |
break;
|
|
957 |
default:
|
|
958 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
959 |
break;
|
|
960 |
}
|
|
961 |
switch (prefix2) {
|
|
962 |
case P_0F:
|
|
963 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
964 |
break;
|
|
965 |
case P_0F38:
|
|
966 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
967 |
break;
|
|
968 |
case P_0F3A:
|
|
969 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
970 |
break;
|
|
971 |
default:
|
|
972 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
973 |
break;
|
|
974 |
}
|
|
975 |
if (noNds) {
|
|
976 |
asm.simdPrefix(dst, Register.None, src, pre, opc, attributes);
|
|
977 |
} else {
|
|
978 |
asm.simdPrefix(dst, dst, src, pre, opc, attributes);
|
|
979 |
}
|
|
980 |
asm.emitByte(op);
|
|
981 |
asm.emitOperandHelper(dst, src, 0);
|
|
982 |
} else {
|
|
983 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, 0);
|
|
984 |
asm.emitOperandHelper(dst, src, 0);
|
|
985 |
}
|
|
986 |
}
|
|
987 |
}
|
|
988 |
|
|
989 |
/**
|
|
990 |
* Opcode with operand order of RM.
|
|
991 |
*/
|
|
992 |
public static class AMD64RRMOp extends AMD64RRROp {
|
|
993 |
protected AMD64RRMOp(String opcode, int op) {
|
|
994 |
this(opcode, 0, op);
|
|
995 |
}
|
|
996 |
|
|
997 |
protected AMD64RRMOp(String opcode, int op, OpAssertion assertion) {
|
|
998 |
this(opcode, 0, op, assertion);
|
|
999 |
}
|
|
1000 |
|
|
1001 |
protected AMD64RRMOp(String opcode, int prefix, int op) {
|
|
1002 |
this(opcode, 0, prefix, op, null);
|
|
1003 |
}
|
|
1004 |
|
|
1005 |
protected AMD64RRMOp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
1006 |
this(opcode, 0, prefix, op, assertion, null);
|
|
1007 |
}
|
|
1008 |
|
|
1009 |
protected AMD64RRMOp(String opcode, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
1010 |
this(opcode, 0, prefix, op, assertion, feature);
|
|
1011 |
}
|
|
1012 |
|
|
1013 |
protected AMD64RRMOp(String opcode, int prefix, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion) {
|
|
1014 |
super(opcode, 0, prefix, op, dstIsByte, srcIsByte, assertion, null);
|
|
1015 |
}
|
|
1016 |
|
|
1017 |
protected AMD64RRMOp(String opcode, int prefix1, int prefix2, int op, CPUFeature feature) {
|
48190
|
1018 |
this(opcode, prefix1, prefix2, op, OpAssertion.WordOrLargerAssertion, feature);
|
43972
|
1019 |
}
|
|
1020 |
|
|
1021 |
protected AMD64RRMOp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
1022 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
1023 |
}
|
|
1024 |
|
|
1025 |
@Override
|
|
1026 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register nds, Register src) {
|
|
1027 |
assert verify(asm, size, dst, src);
|
|
1028 |
int pre;
|
|
1029 |
int opc;
|
|
1030 |
boolean rexVexW = (size == QWORD) ? true : false;
|
|
1031 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
1032 |
int curPrefix = size.sizePrefix | prefix1;
|
|
1033 |
switch (curPrefix) {
|
|
1034 |
case 0x66:
|
|
1035 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
1036 |
break;
|
|
1037 |
case 0xF2:
|
|
1038 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
1039 |
break;
|
|
1040 |
case 0xF3:
|
|
1041 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
1042 |
break;
|
|
1043 |
default:
|
|
1044 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
1045 |
break;
|
|
1046 |
}
|
|
1047 |
switch (prefix2) {
|
|
1048 |
case P_0F:
|
|
1049 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
1050 |
break;
|
|
1051 |
case P_0F38:
|
|
1052 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
1053 |
break;
|
|
1054 |
case P_0F3A:
|
|
1055 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
1056 |
break;
|
|
1057 |
default:
|
|
1058 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
1059 |
break;
|
|
1060 |
}
|
|
1061 |
int encode;
|
|
1062 |
encode = asm.simdPrefixAndEncode(dst, nds, src, pre, opc, attributes);
|
|
1063 |
asm.emitByte(op);
|
|
1064 |
asm.emitByte(0xC0 | encode);
|
|
1065 |
}
|
|
1066 |
|
|
1067 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register nds, AMD64Address src) {
|
|
1068 |
assert verify(asm, size, dst, null);
|
|
1069 |
int pre;
|
|
1070 |
int opc;
|
|
1071 |
boolean rexVexW = (size == QWORD) ? true : false;
|
|
1072 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
1073 |
int curPrefix = size.sizePrefix | prefix1;
|
|
1074 |
switch (curPrefix) {
|
|
1075 |
case 0x66:
|
|
1076 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
1077 |
break;
|
|
1078 |
case 0xF2:
|
|
1079 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
1080 |
break;
|
|
1081 |
case 0xF3:
|
|
1082 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
1083 |
break;
|
|
1084 |
default:
|
|
1085 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
1086 |
break;
|
|
1087 |
}
|
|
1088 |
switch (prefix2) {
|
|
1089 |
case P_0F:
|
|
1090 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
1091 |
break;
|
|
1092 |
case P_0F38:
|
|
1093 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
1094 |
break;
|
|
1095 |
case P_0F3A:
|
|
1096 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
1097 |
break;
|
|
1098 |
default:
|
|
1099 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
1100 |
break;
|
|
1101 |
}
|
|
1102 |
asm.simdPrefix(dst, nds, src, pre, opc, attributes);
|
|
1103 |
asm.emitByte(op);
|
|
1104 |
asm.emitOperandHelper(dst, src, 0);
|
|
1105 |
}
|
|
1106 |
}
|
|
1107 |
|
|
1108 |
/**
|
|
1109 |
* Opcode with operand order of MR.
|
|
1110 |
*/
|
|
1111 |
public static class AMD64MROp extends AMD64RROp {
|
|
1112 |
// @formatter:off
|
|
1113 |
public static final AMD64MROp MOVB = new AMD64MROp("MOVB", 0x88, OpAssertion.ByteAssertion);
|
|
1114 |
public static final AMD64MROp MOV = new AMD64MROp("MOV", 0x89);
|
|
1115 |
|
|
1116 |
// MOVD and MOVQ are the same opcode, just with different operand size prefix
|
|
1117 |
// Note that as MR opcodes, they have reverse operand order, so the IntToFloatingAssertion must be used.
|
48190
|
1118 |
public static final AMD64MROp MOVD = new AMD64MROp("MOVD", 0x66, P_0F, 0x7E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
1119 |
public static final AMD64MROp MOVQ = new AMD64MROp("MOVQ", 0x66, P_0F, 0x7E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
43972
|
1120 |
|
|
1121 |
// MOVSS and MOVSD are the same opcode, just with different operand size prefix
|
48190
|
1122 |
public static final AMD64MROp MOVSS = new AMD64MROp("MOVSS", P_0F, 0x11, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
|
1123 |
public static final AMD64MROp MOVSD = new AMD64MROp("MOVSD", P_0F, 0x11, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
43972
|
1124 |
// @formatter:on
|
|
1125 |
|
|
1126 |
protected AMD64MROp(String opcode, int op) {
|
|
1127 |
this(opcode, 0, op);
|
|
1128 |
}
|
|
1129 |
|
|
1130 |
protected AMD64MROp(String opcode, int op, OpAssertion assertion) {
|
|
1131 |
this(opcode, 0, op, assertion);
|
|
1132 |
}
|
|
1133 |
|
|
1134 |
protected AMD64MROp(String opcode, int prefix, int op) {
|
48190
|
1135 |
this(opcode, prefix, op, OpAssertion.WordOrLargerAssertion);
|
43972
|
1136 |
}
|
|
1137 |
|
|
1138 |
protected AMD64MROp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
1139 |
this(opcode, prefix, op, assertion, null);
|
|
1140 |
}
|
|
1141 |
|
|
1142 |
protected AMD64MROp(String opcode, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
1143 |
this(opcode, 0, prefix, op, assertion, feature);
|
|
1144 |
}
|
|
1145 |
|
|
1146 |
protected AMD64MROp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
1147 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
1148 |
}
|
|
1149 |
|
|
1150 |
@Override
|
|
1151 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src) {
|
|
1152 |
assert verify(asm, size, src, dst);
|
|
1153 |
boolean isSimd = false;
|
|
1154 |
boolean noNds = false;
|
|
1155 |
|
|
1156 |
switch (op) {
|
|
1157 |
case 0x7E:
|
|
1158 |
isSimd = true;
|
|
1159 |
noNds = true;
|
|
1160 |
break;
|
|
1161 |
case 0x11:
|
|
1162 |
isSimd = true;
|
|
1163 |
break;
|
|
1164 |
}
|
|
1165 |
|
|
1166 |
if (isSimd) {
|
|
1167 |
int pre;
|
|
1168 |
int opc;
|
|
1169 |
boolean rexVexW = (size == QWORD) ? true : false;
|
|
1170 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
1171 |
int curPrefix = size.sizePrefix | prefix1;
|
|
1172 |
switch (curPrefix) {
|
|
1173 |
case 0x66:
|
|
1174 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
1175 |
break;
|
|
1176 |
case 0xF2:
|
|
1177 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
1178 |
break;
|
|
1179 |
case 0xF3:
|
|
1180 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
1181 |
break;
|
|
1182 |
default:
|
|
1183 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
1184 |
break;
|
|
1185 |
}
|
|
1186 |
switch (prefix2) {
|
|
1187 |
case P_0F:
|
|
1188 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
1189 |
break;
|
|
1190 |
case P_0F38:
|
|
1191 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
1192 |
break;
|
|
1193 |
case P_0F3A:
|
|
1194 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
1195 |
break;
|
|
1196 |
default:
|
|
1197 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
1198 |
break;
|
|
1199 |
}
|
|
1200 |
int encode;
|
|
1201 |
if (noNds) {
|
|
1202 |
encode = asm.simdPrefixAndEncode(src, Register.None, dst, pre, opc, attributes);
|
|
1203 |
} else {
|
|
1204 |
encode = asm.simdPrefixAndEncode(src, src, dst, pre, opc, attributes);
|
|
1205 |
}
|
|
1206 |
asm.emitByte(op);
|
|
1207 |
asm.emitByte(0xC0 | encode);
|
|
1208 |
} else {
|
|
1209 |
emitOpcode(asm, size, getRXB(src, dst), src.encoding, dst.encoding);
|
|
1210 |
asm.emitModRM(src, dst);
|
|
1211 |
}
|
|
1212 |
}
|
|
1213 |
|
|
1214 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, Register src) {
|
|
1215 |
assert verify(asm, size, null, src);
|
|
1216 |
boolean isSimd = false;
|
|
1217 |
|
|
1218 |
switch (op) {
|
|
1219 |
case 0x7E:
|
|
1220 |
case 0x11:
|
|
1221 |
isSimd = true;
|
|
1222 |
break;
|
|
1223 |
}
|
|
1224 |
|
|
1225 |
if (isSimd) {
|
|
1226 |
int pre;
|
|
1227 |
int opc;
|
|
1228 |
boolean rexVexW = (size == QWORD) ? true : false;
|
|
1229 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, rexVexW, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
1230 |
int curPrefix = size.sizePrefix | prefix1;
|
|
1231 |
switch (curPrefix) {
|
|
1232 |
case 0x66:
|
|
1233 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
1234 |
break;
|
|
1235 |
case 0xF2:
|
|
1236 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
1237 |
break;
|
|
1238 |
case 0xF3:
|
|
1239 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
1240 |
break;
|
|
1241 |
default:
|
|
1242 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
1243 |
break;
|
|
1244 |
}
|
|
1245 |
switch (prefix2) {
|
|
1246 |
case P_0F:
|
|
1247 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
1248 |
break;
|
|
1249 |
case P_0F38:
|
|
1250 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
1251 |
break;
|
|
1252 |
case P_0F3A:
|
|
1253 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
1254 |
break;
|
|
1255 |
default:
|
|
1256 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
1257 |
break;
|
|
1258 |
}
|
|
1259 |
asm.simdPrefix(src, Register.None, dst, pre, opc, attributes);
|
|
1260 |
asm.emitByte(op);
|
|
1261 |
asm.emitOperandHelper(src, dst, 0);
|
|
1262 |
} else {
|
|
1263 |
emitOpcode(asm, size, getRXB(src, dst), src.encoding, 0);
|
|
1264 |
asm.emitOperandHelper(src, dst, 0);
|
|
1265 |
}
|
|
1266 |
}
|
|
1267 |
}
|
|
1268 |
|
|
1269 |
/**
|
|
1270 |
* Opcodes with operand order of M.
|
|
1271 |
*/
|
|
1272 |
public static class AMD64MOp extends AMD64Op {
|
|
1273 |
// @formatter:off
|
|
1274 |
public static final AMD64MOp NOT = new AMD64MOp("NOT", 0xF7, 2);
|
|
1275 |
public static final AMD64MOp NEG = new AMD64MOp("NEG", 0xF7, 3);
|
|
1276 |
public static final AMD64MOp MUL = new AMD64MOp("MUL", 0xF7, 4);
|
|
1277 |
public static final AMD64MOp IMUL = new AMD64MOp("IMUL", 0xF7, 5);
|
|
1278 |
public static final AMD64MOp DIV = new AMD64MOp("DIV", 0xF7, 6);
|
|
1279 |
public static final AMD64MOp IDIV = new AMD64MOp("IDIV", 0xF7, 7);
|
|
1280 |
public static final AMD64MOp INC = new AMD64MOp("INC", 0xFF, 0);
|
|
1281 |
public static final AMD64MOp DEC = new AMD64MOp("DEC", 0xFF, 1);
|
|
1282 |
public static final AMD64MOp PUSH = new AMD64MOp("PUSH", 0xFF, 6);
|
48190
|
1283 |
public static final AMD64MOp POP = new AMD64MOp("POP", 0x8F, 0, OpAssertion.WordOrDwordAssertion);
|
43972
|
1284 |
// @formatter:on
|
|
1285 |
|
|
1286 |
private final int ext;
|
|
1287 |
|
|
1288 |
protected AMD64MOp(String opcode, int op, int ext) {
|
|
1289 |
this(opcode, 0, op, ext);
|
|
1290 |
}
|
|
1291 |
|
|
1292 |
protected AMD64MOp(String opcode, int prefix, int op, int ext) {
|
48190
|
1293 |
this(opcode, prefix, op, ext, OpAssertion.WordOrLargerAssertion);
|
43972
|
1294 |
}
|
|
1295 |
|
|
1296 |
protected AMD64MOp(String opcode, int op, int ext, OpAssertion assertion) {
|
|
1297 |
this(opcode, 0, op, ext, assertion);
|
|
1298 |
}
|
|
1299 |
|
|
1300 |
protected AMD64MOp(String opcode, int prefix, int op, int ext, OpAssertion assertion) {
|
|
1301 |
super(opcode, 0, prefix, op, assertion, null);
|
|
1302 |
this.ext = ext;
|
|
1303 |
}
|
|
1304 |
|
|
1305 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst) {
|
|
1306 |
assert verify(asm, size, dst, null);
|
|
1307 |
emitOpcode(asm, size, getRXB(null, dst), 0, dst.encoding);
|
|
1308 |
asm.emitModRM(ext, dst);
|
|
1309 |
}
|
|
1310 |
|
|
1311 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst) {
|
|
1312 |
assert verify(asm, size, null, null);
|
|
1313 |
emitOpcode(asm, size, getRXB(null, dst), 0, 0);
|
|
1314 |
asm.emitOperandHelper(ext, dst, 0);
|
|
1315 |
}
|
|
1316 |
}
|
|
1317 |
|
|
1318 |
/**
|
|
1319 |
* Opcodes with operand order of MI.
|
|
1320 |
*/
|
|
1321 |
public static class AMD64MIOp extends AMD64ImmOp {
|
|
1322 |
// @formatter:off
|
|
1323 |
public static final AMD64MIOp MOVB = new AMD64MIOp("MOVB", true, 0xC6, 0, OpAssertion.ByteAssertion);
|
|
1324 |
public static final AMD64MIOp MOV = new AMD64MIOp("MOV", false, 0xC7, 0);
|
|
1325 |
public static final AMD64MIOp TEST = new AMD64MIOp("TEST", false, 0xF7, 0);
|
|
1326 |
// @formatter:on
|
|
1327 |
|
|
1328 |
private final int ext;
|
|
1329 |
|
|
1330 |
protected AMD64MIOp(String opcode, boolean immIsByte, int op, int ext) {
|
48190
|
1331 |
this(opcode, immIsByte, op, ext, OpAssertion.WordOrLargerAssertion);
|
43972
|
1332 |
}
|
|
1333 |
|
|
1334 |
protected AMD64MIOp(String opcode, boolean immIsByte, int op, int ext, OpAssertion assertion) {
|
|
1335 |
this(opcode, immIsByte, 0, op, ext, assertion);
|
|
1336 |
}
|
|
1337 |
|
|
1338 |
protected AMD64MIOp(String opcode, boolean immIsByte, int prefix, int op, int ext, OpAssertion assertion) {
|
|
1339 |
super(opcode, immIsByte, prefix, op, assertion);
|
|
1340 |
this.ext = ext;
|
|
1341 |
}
|
|
1342 |
|
|
1343 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, int imm) {
|
|
1344 |
assert verify(asm, size, dst, null);
|
|
1345 |
emitOpcode(asm, size, getRXB(null, dst), 0, dst.encoding);
|
|
1346 |
asm.emitModRM(ext, dst);
|
|
1347 |
emitImmediate(asm, size, imm);
|
|
1348 |
}
|
|
1349 |
|
|
1350 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, int imm) {
|
|
1351 |
assert verify(asm, size, null, null);
|
|
1352 |
emitOpcode(asm, size, getRXB(null, dst), 0, 0);
|
|
1353 |
asm.emitOperandHelper(ext, dst, immediateSize(size));
|
|
1354 |
emitImmediate(asm, size, imm);
|
|
1355 |
}
|
|
1356 |
}
|
|
1357 |
|
|
1358 |
/**
|
|
1359 |
* Opcodes with operand order of RMI.
|
|
1360 |
*
|
|
1361 |
* We only have one form of round as the operation is always treated with single variant input,
|
|
1362 |
* making its extension to 3 address forms redundant.
|
|
1363 |
*/
|
|
1364 |
public static class AMD64RMIOp extends AMD64ImmOp {
|
|
1365 |
// @formatter:off
|
|
1366 |
public static final AMD64RMIOp IMUL = new AMD64RMIOp("IMUL", false, 0x69);
|
|
1367 |
public static final AMD64RMIOp IMUL_SX = new AMD64RMIOp("IMUL", true, 0x6B);
|
|
1368 |
public static final AMD64RMIOp ROUNDSS = new AMD64RMIOp("ROUNDSS", true, P_0F3A, 0x0A, OpAssertion.PackedDoubleAssertion);
|
|
1369 |
public static final AMD64RMIOp ROUNDSD = new AMD64RMIOp("ROUNDSD", true, P_0F3A, 0x0B, OpAssertion.PackedDoubleAssertion);
|
|
1370 |
// @formatter:on
|
|
1371 |
|
|
1372 |
protected AMD64RMIOp(String opcode, boolean immIsByte, int op) {
|
48190
|
1373 |
this(opcode, immIsByte, 0, op, OpAssertion.WordOrLargerAssertion);
|
43972
|
1374 |
}
|
|
1375 |
|
|
1376 |
protected AMD64RMIOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion) {
|
|
1377 |
super(opcode, immIsByte, prefix, op, assertion);
|
|
1378 |
}
|
|
1379 |
|
|
1380 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src, int imm) {
|
|
1381 |
assert verify(asm, size, dst, src);
|
|
1382 |
boolean isSimd = false;
|
|
1383 |
boolean noNds = false;
|
|
1384 |
|
|
1385 |
switch (op) {
|
|
1386 |
case 0x0A:
|
|
1387 |
case 0x0B:
|
|
1388 |
isSimd = true;
|
|
1389 |
noNds = true;
|
|
1390 |
break;
|
|
1391 |
}
|
|
1392 |
|
|
1393 |
if (isSimd) {
|
|
1394 |
int pre;
|
|
1395 |
int opc;
|
|
1396 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
1397 |
int curPrefix = size.sizePrefix | prefix1;
|
|
1398 |
switch (curPrefix) {
|
|
1399 |
case 0x66:
|
|
1400 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
1401 |
break;
|
|
1402 |
case 0xF2:
|
|
1403 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
1404 |
break;
|
|
1405 |
case 0xF3:
|
|
1406 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
1407 |
break;
|
|
1408 |
default:
|
|
1409 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
1410 |
break;
|
|
1411 |
}
|
|
1412 |
switch (prefix2) {
|
|
1413 |
case P_0F:
|
|
1414 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
1415 |
break;
|
|
1416 |
case P_0F38:
|
|
1417 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
1418 |
break;
|
|
1419 |
case P_0F3A:
|
|
1420 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
1421 |
break;
|
|
1422 |
default:
|
|
1423 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
1424 |
break;
|
|
1425 |
}
|
|
1426 |
int encode;
|
|
1427 |
if (noNds) {
|
|
1428 |
encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes);
|
|
1429 |
} else {
|
|
1430 |
encode = asm.simdPrefixAndEncode(dst, dst, src, pre, opc, attributes);
|
|
1431 |
}
|
|
1432 |
asm.emitByte(op);
|
|
1433 |
asm.emitByte(0xC0 | encode);
|
|
1434 |
emitImmediate(asm, size, imm);
|
|
1435 |
} else {
|
|
1436 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, src.encoding);
|
|
1437 |
asm.emitModRM(dst, src);
|
|
1438 |
emitImmediate(asm, size, imm);
|
|
1439 |
}
|
|
1440 |
}
|
|
1441 |
|
|
1442 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, AMD64Address src, int imm) {
|
|
1443 |
assert verify(asm, size, dst, null);
|
|
1444 |
|
|
1445 |
boolean isSimd = false;
|
|
1446 |
boolean noNds = false;
|
|
1447 |
|
|
1448 |
switch (op) {
|
|
1449 |
case 0x0A:
|
|
1450 |
case 0x0B:
|
|
1451 |
isSimd = true;
|
|
1452 |
noNds = true;
|
|
1453 |
break;
|
|
1454 |
}
|
|
1455 |
|
|
1456 |
if (isSimd) {
|
|
1457 |
int pre;
|
|
1458 |
int opc;
|
|
1459 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, asm.target);
|
|
1460 |
int curPrefix = size.sizePrefix | prefix1;
|
|
1461 |
switch (curPrefix) {
|
|
1462 |
case 0x66:
|
|
1463 |
pre = VexSimdPrefix.VEX_SIMD_66;
|
|
1464 |
break;
|
|
1465 |
case 0xF2:
|
|
1466 |
pre = VexSimdPrefix.VEX_SIMD_F2;
|
|
1467 |
break;
|
|
1468 |
case 0xF3:
|
|
1469 |
pre = VexSimdPrefix.VEX_SIMD_F3;
|
|
1470 |
break;
|
|
1471 |
default:
|
|
1472 |
pre = VexSimdPrefix.VEX_SIMD_NONE;
|
|
1473 |
break;
|
|
1474 |
}
|
|
1475 |
switch (prefix2) {
|
|
1476 |
case P_0F:
|
|
1477 |
opc = VexOpcode.VEX_OPCODE_0F;
|
|
1478 |
break;
|
|
1479 |
case P_0F38:
|
|
1480 |
opc = VexOpcode.VEX_OPCODE_0F_38;
|
|
1481 |
break;
|
|
1482 |
case P_0F3A:
|
|
1483 |
opc = VexOpcode.VEX_OPCODE_0F_3A;
|
|
1484 |
break;
|
|
1485 |
default:
|
|
1486 |
opc = VexOpcode.VEX_OPCODE_NONE;
|
|
1487 |
break;
|
|
1488 |
}
|
|
1489 |
|
|
1490 |
if (noNds) {
|
|
1491 |
asm.simdPrefix(dst, Register.None, src, pre, opc, attributes);
|
|
1492 |
} else {
|
|
1493 |
asm.simdPrefix(dst, dst, src, pre, opc, attributes);
|
|
1494 |
}
|
|
1495 |
asm.emitByte(op);
|
|
1496 |
asm.emitOperandHelper(dst, src, immediateSize(size));
|
|
1497 |
emitImmediate(asm, size, imm);
|
|
1498 |
} else {
|
|
1499 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, 0);
|
|
1500 |
asm.emitOperandHelper(dst, src, immediateSize(size));
|
|
1501 |
emitImmediate(asm, size, imm);
|
|
1502 |
}
|
|
1503 |
}
|
|
1504 |
}
|
|
1505 |
|
|
1506 |
public static class SSEOp extends AMD64RMOp {
|
|
1507 |
// @formatter:off
|
48190
|
1508 |
public static final SSEOp CVTSI2SS = new SSEOp("CVTSI2SS", 0xF3, P_0F, 0x2A, OpAssertion.IntToFloatAssertion);
|
|
1509 |
public static final SSEOp CVTSI2SD = new SSEOp("CVTSI2SS", 0xF2, P_0F, 0x2A, OpAssertion.IntToFloatAssertion);
|
|
1510 |
public static final SSEOp CVTTSS2SI = new SSEOp("CVTTSS2SI", 0xF3, P_0F, 0x2C, OpAssertion.FloatToIntAssertion);
|
|
1511 |
public static final SSEOp CVTTSD2SI = new SSEOp("CVTTSD2SI", 0xF2, P_0F, 0x2C, OpAssertion.FloatToIntAssertion);
|
|
1512 |
public static final SSEOp UCOMIS = new SSEOp("UCOMIS", P_0F, 0x2E, OpAssertion.PackedFloatAssertion);
|
43972
|
1513 |
public static final SSEOp SQRT = new SSEOp("SQRT", P_0F, 0x51);
|
48190
|
1514 |
public static final SSEOp AND = new SSEOp("AND", P_0F, 0x54, OpAssertion.PackedFloatAssertion);
|
|
1515 |
public static final SSEOp ANDN = new SSEOp("ANDN", P_0F, 0x55, OpAssertion.PackedFloatAssertion);
|
|
1516 |
public static final SSEOp OR = new SSEOp("OR", P_0F, 0x56, OpAssertion.PackedFloatAssertion);
|
|
1517 |
public static final SSEOp XOR = new SSEOp("XOR", P_0F, 0x57, OpAssertion.PackedFloatAssertion);
|
43972
|
1518 |
public static final SSEOp ADD = new SSEOp("ADD", P_0F, 0x58);
|
|
1519 |
public static final SSEOp MUL = new SSEOp("MUL", P_0F, 0x59);
|
|
1520 |
public static final SSEOp CVTSS2SD = new SSEOp("CVTSS2SD", P_0F, 0x5A, OpAssertion.SingleAssertion);
|
|
1521 |
public static final SSEOp CVTSD2SS = new SSEOp("CVTSD2SS", P_0F, 0x5A, OpAssertion.DoubleAssertion);
|
|
1522 |
public static final SSEOp SUB = new SSEOp("SUB", P_0F, 0x5C);
|
|
1523 |
public static final SSEOp MIN = new SSEOp("MIN", P_0F, 0x5D);
|
|
1524 |
public static final SSEOp DIV = new SSEOp("DIV", P_0F, 0x5E);
|
|
1525 |
public static final SSEOp MAX = new SSEOp("MAX", P_0F, 0x5F);
|
|
1526 |
// @formatter:on
|
|
1527 |
|
|
1528 |
protected SSEOp(String opcode, int prefix, int op) {
|
48190
|
1529 |
this(opcode, prefix, op, OpAssertion.FloatAssertion);
|
43972
|
1530 |
}
|
|
1531 |
|
|
1532 |
protected SSEOp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
1533 |
this(opcode, 0, prefix, op, assertion);
|
|
1534 |
}
|
|
1535 |
|
|
1536 |
protected SSEOp(String opcode, int mandatoryPrefix, int prefix, int op, OpAssertion assertion) {
|
|
1537 |
super(opcode, mandatoryPrefix, prefix, op, assertion, CPUFeature.SSE2);
|
|
1538 |
}
|
|
1539 |
}
|
|
1540 |
|
|
1541 |
public static class AVXOp extends AMD64RRMOp {
|
|
1542 |
// @formatter:off
|
48190
|
1543 |
public static final AVXOp AND = new AVXOp("AND", P_0F, 0x54, OpAssertion.PackedFloatAssertion);
|
|
1544 |
public static final AVXOp ANDN = new AVXOp("ANDN", P_0F, 0x55, OpAssertion.PackedFloatAssertion);
|
|
1545 |
public static final AVXOp OR = new AVXOp("OR", P_0F, 0x56, OpAssertion.PackedFloatAssertion);
|
|
1546 |
public static final AVXOp XOR = new AVXOp("XOR", P_0F, 0x57, OpAssertion.PackedFloatAssertion);
|
43972
|
1547 |
public static final AVXOp ADD = new AVXOp("ADD", P_0F, 0x58);
|
|
1548 |
public static final AVXOp MUL = new AVXOp("MUL", P_0F, 0x59);
|
|
1549 |
public static final AVXOp SUB = new AVXOp("SUB", P_0F, 0x5C);
|
|
1550 |
public static final AVXOp MIN = new AVXOp("MIN", P_0F, 0x5D);
|
|
1551 |
public static final AVXOp DIV = new AVXOp("DIV", P_0F, 0x5E);
|
|
1552 |
public static final AVXOp MAX = new AVXOp("MAX", P_0F, 0x5F);
|
|
1553 |
// @formatter:on
|
|
1554 |
|
|
1555 |
protected AVXOp(String opcode, int prefix, int op) {
|
48190
|
1556 |
this(opcode, prefix, op, OpAssertion.FloatAssertion);
|
43972
|
1557 |
}
|
|
1558 |
|
|
1559 |
protected AVXOp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
1560 |
this(opcode, 0, prefix, op, assertion);
|
|
1561 |
}
|
|
1562 |
|
|
1563 |
protected AVXOp(String opcode, int mandatoryPrefix, int prefix, int op, OpAssertion assertion) {
|
|
1564 |
super(opcode, mandatoryPrefix, prefix, op, assertion, CPUFeature.AVX);
|
|
1565 |
}
|
|
1566 |
}
|
|
1567 |
|
|
1568 |
/**
|
|
1569 |
* Arithmetic operation with operand order of RM, MR or MI.
|
|
1570 |
*/
|
|
1571 |
public static final class AMD64BinaryArithmetic {
|
|
1572 |
// @formatter:off
|
|
1573 |
public static final AMD64BinaryArithmetic ADD = new AMD64BinaryArithmetic("ADD", 0);
|
|
1574 |
public static final AMD64BinaryArithmetic OR = new AMD64BinaryArithmetic("OR", 1);
|
|
1575 |
public static final AMD64BinaryArithmetic ADC = new AMD64BinaryArithmetic("ADC", 2);
|
|
1576 |
public static final AMD64BinaryArithmetic SBB = new AMD64BinaryArithmetic("SBB", 3);
|
|
1577 |
public static final AMD64BinaryArithmetic AND = new AMD64BinaryArithmetic("AND", 4);
|
|
1578 |
public static final AMD64BinaryArithmetic SUB = new AMD64BinaryArithmetic("SUB", 5);
|
|
1579 |
public static final AMD64BinaryArithmetic XOR = new AMD64BinaryArithmetic("XOR", 6);
|
|
1580 |
public static final AMD64BinaryArithmetic CMP = new AMD64BinaryArithmetic("CMP", 7);
|
|
1581 |
// @formatter:on
|
|
1582 |
|
|
1583 |
private final AMD64MIOp byteImmOp;
|
|
1584 |
private final AMD64MROp byteMrOp;
|
|
1585 |
private final AMD64RMOp byteRmOp;
|
|
1586 |
|
|
1587 |
private final AMD64MIOp immOp;
|
|
1588 |
private final AMD64MIOp immSxOp;
|
|
1589 |
private final AMD64MROp mrOp;
|
|
1590 |
private final AMD64RMOp rmOp;
|
|
1591 |
|
|
1592 |
private AMD64BinaryArithmetic(String opcode, int code) {
|
|
1593 |
int baseOp = code << 3;
|
|
1594 |
|
|
1595 |
byteImmOp = new AMD64MIOp(opcode, true, 0, 0x80, code, OpAssertion.ByteAssertion);
|
|
1596 |
byteMrOp = new AMD64MROp(opcode, 0, baseOp, OpAssertion.ByteAssertion);
|
|
1597 |
byteRmOp = new AMD64RMOp(opcode, 0, baseOp | 0x02, OpAssertion.ByteAssertion);
|
|
1598 |
|
48190
|
1599 |
immOp = new AMD64MIOp(opcode, false, 0, 0x81, code, OpAssertion.WordOrLargerAssertion);
|
|
1600 |
immSxOp = new AMD64MIOp(opcode, true, 0, 0x83, code, OpAssertion.WordOrLargerAssertion);
|
|
1601 |
mrOp = new AMD64MROp(opcode, 0, baseOp | 0x01, OpAssertion.WordOrLargerAssertion);
|
|
1602 |
rmOp = new AMD64RMOp(opcode, 0, baseOp | 0x03, OpAssertion.WordOrLargerAssertion);
|
43972
|
1603 |
}
|
|
1604 |
|
|
1605 |
public AMD64MIOp getMIOpcode(OperandSize size, boolean sx) {
|
|
1606 |
if (size == BYTE) {
|
|
1607 |
return byteImmOp;
|
|
1608 |
} else if (sx) {
|
|
1609 |
return immSxOp;
|
|
1610 |
} else {
|
|
1611 |
return immOp;
|
|
1612 |
}
|
|
1613 |
}
|
|
1614 |
|
|
1615 |
public AMD64MROp getMROpcode(OperandSize size) {
|
|
1616 |
if (size == BYTE) {
|
|
1617 |
return byteMrOp;
|
|
1618 |
} else {
|
|
1619 |
return mrOp;
|
|
1620 |
}
|
|
1621 |
}
|
|
1622 |
|
|
1623 |
public AMD64RMOp getRMOpcode(OperandSize size) {
|
|
1624 |
if (size == BYTE) {
|
|
1625 |
return byteRmOp;
|
|
1626 |
} else {
|
|
1627 |
return rmOp;
|
|
1628 |
}
|
|
1629 |
}
|
|
1630 |
}
|
|
1631 |
|
|
1632 |
/**
|
|
1633 |
* Shift operation with operand order of M1, MC or MI.
|
|
1634 |
*/
|
|
1635 |
public static final class AMD64Shift {
|
|
1636 |
// @formatter:off
|
|
1637 |
public static final AMD64Shift ROL = new AMD64Shift("ROL", 0);
|
|
1638 |
public static final AMD64Shift ROR = new AMD64Shift("ROR", 1);
|
|
1639 |
public static final AMD64Shift RCL = new AMD64Shift("RCL", 2);
|
|
1640 |
public static final AMD64Shift RCR = new AMD64Shift("RCR", 3);
|
|
1641 |
public static final AMD64Shift SHL = new AMD64Shift("SHL", 4);
|
|
1642 |
public static final AMD64Shift SHR = new AMD64Shift("SHR", 5);
|
|
1643 |
public static final AMD64Shift SAR = new AMD64Shift("SAR", 7);
|
|
1644 |
// @formatter:on
|
|
1645 |
|
|
1646 |
public final AMD64MOp m1Op;
|
|
1647 |
public final AMD64MOp mcOp;
|
|
1648 |
public final AMD64MIOp miOp;
|
|
1649 |
|
|
1650 |
private AMD64Shift(String opcode, int code) {
|
48190
|
1651 |
m1Op = new AMD64MOp(opcode, 0, 0xD1, code, OpAssertion.WordOrLargerAssertion);
|
|
1652 |
mcOp = new AMD64MOp(opcode, 0, 0xD3, code, OpAssertion.WordOrLargerAssertion);
|
|
1653 |
miOp = new AMD64MIOp(opcode, true, 0, 0xC1, code, OpAssertion.WordOrLargerAssertion);
|
43972
|
1654 |
}
|
|
1655 |
}
|
|
1656 |
|
|
1657 |
public final void addl(AMD64Address dst, int imm32) {
|
|
1658 |
ADD.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
1659 |
}
|
|
1660 |
|
|
1661 |
public final void addl(Register dst, int imm32) {
|
|
1662 |
ADD.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
1663 |
}
|
|
1664 |
|
|
1665 |
public final void addl(Register dst, Register src) {
|
|
1666 |
ADD.rmOp.emit(this, DWORD, dst, src);
|
|
1667 |
}
|
|
1668 |
|
|
1669 |
public final void addpd(Register dst, Register src) {
|
|
1670 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
1671 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1672 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1673 |
emitByte(0x58);
|
|
1674 |
emitByte(0xC0 | encode);
|
|
1675 |
}
|
|
1676 |
|
|
1677 |
public final void addpd(Register dst, AMD64Address src) {
|
|
1678 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
1679 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1680 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1681 |
emitByte(0x58);
|
|
1682 |
emitOperandHelper(dst, src, 0);
|
|
1683 |
}
|
|
1684 |
|
|
1685 |
public final void addsd(Register dst, Register src) {
|
|
1686 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
1687 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1688 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1689 |
emitByte(0x58);
|
|
1690 |
emitByte(0xC0 | encode);
|
|
1691 |
}
|
|
1692 |
|
|
1693 |
public final void addsd(Register dst, AMD64Address src) {
|
|
1694 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
1695 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1696 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1697 |
emitByte(0x58);
|
|
1698 |
emitOperandHelper(dst, src, 0);
|
|
1699 |
}
|
|
1700 |
|
|
1701 |
private void addrNop4() {
|
|
1702 |
// 4 bytes: NOP DWORD PTR [EAX+0]
|
|
1703 |
emitByte(0x0F);
|
|
1704 |
emitByte(0x1F);
|
|
1705 |
emitByte(0x40); // emitRm(cbuf, 0x1, EAXEnc, EAXEnc);
|
|
1706 |
emitByte(0); // 8-bits offset (1 byte)
|
|
1707 |
}
|
|
1708 |
|
|
1709 |
private void addrNop5() {
|
|
1710 |
// 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
|
|
1711 |
emitByte(0x0F);
|
|
1712 |
emitByte(0x1F);
|
|
1713 |
emitByte(0x44); // emitRm(cbuf, 0x1, EAXEnc, 0x4);
|
|
1714 |
emitByte(0x00); // emitRm(cbuf, 0x0, EAXEnc, EAXEnc);
|
|
1715 |
emitByte(0); // 8-bits offset (1 byte)
|
|
1716 |
}
|
|
1717 |
|
|
1718 |
private void addrNop7() {
|
|
1719 |
// 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
|
|
1720 |
emitByte(0x0F);
|
|
1721 |
emitByte(0x1F);
|
|
1722 |
emitByte(0x80); // emitRm(cbuf, 0x2, EAXEnc, EAXEnc);
|
|
1723 |
emitInt(0); // 32-bits offset (4 bytes)
|
|
1724 |
}
|
|
1725 |
|
|
1726 |
private void addrNop8() {
|
|
1727 |
// 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
|
|
1728 |
emitByte(0x0F);
|
|
1729 |
emitByte(0x1F);
|
|
1730 |
emitByte(0x84); // emitRm(cbuf, 0x2, EAXEnc, 0x4);
|
|
1731 |
emitByte(0x00); // emitRm(cbuf, 0x0, EAXEnc, EAXEnc);
|
|
1732 |
emitInt(0); // 32-bits offset (4 bytes)
|
|
1733 |
}
|
|
1734 |
|
|
1735 |
public final void andl(Register dst, int imm32) {
|
|
1736 |
AND.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
1737 |
}
|
|
1738 |
|
|
1739 |
public final void andl(Register dst, Register src) {
|
|
1740 |
AND.rmOp.emit(this, DWORD, dst, src);
|
|
1741 |
}
|
|
1742 |
|
|
1743 |
public final void andpd(Register dst, Register src) {
|
|
1744 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
1745 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1746 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1747 |
emitByte(0x54);
|
|
1748 |
emitByte(0xC0 | encode);
|
|
1749 |
}
|
|
1750 |
|
|
1751 |
public final void andpd(Register dst, AMD64Address src) {
|
|
1752 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
1753 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1754 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1755 |
emitByte(0x54);
|
|
1756 |
emitOperandHelper(dst, src, 0);
|
|
1757 |
}
|
|
1758 |
|
|
1759 |
public final void bsrl(Register dst, Register src) {
|
|
1760 |
int encode = prefixAndEncode(dst.encoding(), src.encoding());
|
|
1761 |
emitByte(0x0F);
|
|
1762 |
emitByte(0xBD);
|
|
1763 |
emitByte(0xC0 | encode);
|
|
1764 |
}
|
|
1765 |
|
|
1766 |
public final void bswapl(Register reg) {
|
|
1767 |
int encode = prefixAndEncode(reg.encoding);
|
|
1768 |
emitByte(0x0F);
|
|
1769 |
emitByte(0xC8 | encode);
|
|
1770 |
}
|
|
1771 |
|
|
1772 |
public final void cdql() {
|
|
1773 |
emitByte(0x99);
|
|
1774 |
}
|
|
1775 |
|
|
1776 |
public final void cmovl(ConditionFlag cc, Register dst, Register src) {
|
|
1777 |
int encode = prefixAndEncode(dst.encoding, src.encoding);
|
|
1778 |
emitByte(0x0F);
|
|
1779 |
emitByte(0x40 | cc.getValue());
|
|
1780 |
emitByte(0xC0 | encode);
|
|
1781 |
}
|
|
1782 |
|
|
1783 |
public final void cmovl(ConditionFlag cc, Register dst, AMD64Address src) {
|
|
1784 |
prefix(src, dst);
|
|
1785 |
emitByte(0x0F);
|
|
1786 |
emitByte(0x40 | cc.getValue());
|
|
1787 |
emitOperandHelper(dst, src, 0);
|
|
1788 |
}
|
|
1789 |
|
|
1790 |
public final void cmpl(Register dst, int imm32) {
|
|
1791 |
CMP.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
1792 |
}
|
|
1793 |
|
|
1794 |
public final void cmpl(Register dst, Register src) {
|
|
1795 |
CMP.rmOp.emit(this, DWORD, dst, src);
|
|
1796 |
}
|
|
1797 |
|
|
1798 |
public final void cmpl(Register dst, AMD64Address src) {
|
|
1799 |
CMP.rmOp.emit(this, DWORD, dst, src);
|
|
1800 |
}
|
|
1801 |
|
|
1802 |
public final void cmpl(AMD64Address dst, int imm32) {
|
|
1803 |
CMP.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
1804 |
}
|
|
1805 |
|
|
1806 |
// The 32-bit cmpxchg compares the value at adr with the contents of X86.rax,
|
|
1807 |
// and stores reg into adr if so; otherwise, the value at adr is loaded into X86.rax,.
|
|
1808 |
// The ZF is set if the compared values were equal, and cleared otherwise.
|
|
1809 |
public final void cmpxchgl(Register reg, AMD64Address adr) { // cmpxchg
|
|
1810 |
prefix(adr, reg);
|
|
1811 |
emitByte(0x0F);
|
|
1812 |
emitByte(0xB1);
|
|
1813 |
emitOperandHelper(reg, adr, 0);
|
|
1814 |
}
|
|
1815 |
|
|
1816 |
public final void cvtsi2sdl(Register dst, Register src) {
|
|
1817 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.CPU);
|
|
1818 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1819 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1820 |
emitByte(0x2A);
|
|
1821 |
emitByte(0xC0 | encode);
|
|
1822 |
}
|
|
1823 |
|
|
1824 |
public final void cvttsd2sil(Register dst, Register src) {
|
|
1825 |
assert dst.getRegisterCategory().equals(AMD64.CPU) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
1826 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1827 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1828 |
emitByte(0x2C);
|
|
1829 |
emitByte(0xC0 | encode);
|
|
1830 |
}
|
|
1831 |
|
|
1832 |
protected final void decl(AMD64Address dst) {
|
|
1833 |
prefix(dst);
|
|
1834 |
emitByte(0xFF);
|
|
1835 |
emitOperandHelper(1, dst, 0);
|
|
1836 |
}
|
|
1837 |
|
|
1838 |
public final void divsd(Register dst, Register src) {
|
|
1839 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
1840 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1841 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1842 |
emitByte(0x5E);
|
|
1843 |
emitByte(0xC0 | encode);
|
|
1844 |
}
|
|
1845 |
|
|
1846 |
public final void hlt() {
|
|
1847 |
emitByte(0xF4);
|
|
1848 |
}
|
|
1849 |
|
|
1850 |
public final void imull(Register dst, Register src, int value) {
|
|
1851 |
if (isByte(value)) {
|
|
1852 |
AMD64RMIOp.IMUL_SX.emit(this, DWORD, dst, src, value);
|
|
1853 |
} else {
|
|
1854 |
AMD64RMIOp.IMUL.emit(this, DWORD, dst, src, value);
|
|
1855 |
}
|
|
1856 |
}
|
|
1857 |
|
|
1858 |
protected final void incl(AMD64Address dst) {
|
|
1859 |
prefix(dst);
|
|
1860 |
emitByte(0xFF);
|
|
1861 |
emitOperandHelper(0, dst, 0);
|
|
1862 |
}
|
|
1863 |
|
|
1864 |
public void jcc(ConditionFlag cc, int jumpTarget, boolean forceDisp32) {
|
|
1865 |
int shortSize = 2;
|
|
1866 |
int longSize = 6;
|
|
1867 |
long disp = jumpTarget - position();
|
|
1868 |
if (!forceDisp32 && isByte(disp - shortSize)) {
|
|
1869 |
// 0111 tttn #8-bit disp
|
|
1870 |
emitByte(0x70 | cc.getValue());
|
|
1871 |
emitByte((int) ((disp - shortSize) & 0xFF));
|
|
1872 |
} else {
|
|
1873 |
// 0000 1111 1000 tttn #32-bit disp
|
|
1874 |
assert isInt(disp - longSize) : "must be 32bit offset (call4)";
|
|
1875 |
emitByte(0x0F);
|
|
1876 |
emitByte(0x80 | cc.getValue());
|
|
1877 |
emitInt((int) (disp - longSize));
|
|
1878 |
}
|
|
1879 |
}
|
|
1880 |
|
|
1881 |
public final void jcc(ConditionFlag cc, Label l) {
|
|
1882 |
assert (0 <= cc.getValue()) && (cc.getValue() < 16) : "illegal cc";
|
|
1883 |
if (l.isBound()) {
|
|
1884 |
jcc(cc, l.position(), false);
|
|
1885 |
} else {
|
|
1886 |
// Note: could eliminate cond. jumps to this jump if condition
|
|
1887 |
// is the same however, seems to be rather unlikely case.
|
|
1888 |
// Note: use jccb() if label to be bound is very close to get
|
|
1889 |
// an 8-bit displacement
|
|
1890 |
l.addPatchAt(position());
|
|
1891 |
emitByte(0x0F);
|
|
1892 |
emitByte(0x80 | cc.getValue());
|
|
1893 |
emitInt(0);
|
|
1894 |
}
|
|
1895 |
|
|
1896 |
}
|
|
1897 |
|
|
1898 |
public final void jccb(ConditionFlag cc, Label l) {
|
|
1899 |
if (l.isBound()) {
|
|
1900 |
int shortSize = 2;
|
|
1901 |
int entry = l.position();
|
|
1902 |
assert isByte(entry - (position() + shortSize)) : "Dispacement too large for a short jmp";
|
|
1903 |
long disp = entry - position();
|
|
1904 |
// 0111 tttn #8-bit disp
|
|
1905 |
emitByte(0x70 | cc.getValue());
|
|
1906 |
emitByte((int) ((disp - shortSize) & 0xFF));
|
|
1907 |
} else {
|
|
1908 |
l.addPatchAt(position());
|
|
1909 |
emitByte(0x70 | cc.getValue());
|
|
1910 |
emitByte(0);
|
|
1911 |
}
|
|
1912 |
}
|
|
1913 |
|
|
1914 |
public final void jmp(int jumpTarget, boolean forceDisp32) {
|
|
1915 |
int shortSize = 2;
|
|
1916 |
int longSize = 5;
|
|
1917 |
long disp = jumpTarget - position();
|
|
1918 |
if (!forceDisp32 && isByte(disp - shortSize)) {
|
|
1919 |
emitByte(0xEB);
|
|
1920 |
emitByte((int) ((disp - shortSize) & 0xFF));
|
|
1921 |
} else {
|
|
1922 |
emitByte(0xE9);
|
|
1923 |
emitInt((int) (disp - longSize));
|
|
1924 |
}
|
|
1925 |
}
|
|
1926 |
|
|
1927 |
@Override
|
|
1928 |
public final void jmp(Label l) {
|
|
1929 |
if (l.isBound()) {
|
|
1930 |
jmp(l.position(), false);
|
|
1931 |
} else {
|
|
1932 |
// By default, forward jumps are always 32-bit displacements, since
|
|
1933 |
// we can't yet know where the label will be bound. If you're sure that
|
|
1934 |
// the forward jump will not run beyond 256 bytes, use jmpb to
|
|
1935 |
// force an 8-bit displacement.
|
|
1936 |
|
|
1937 |
l.addPatchAt(position());
|
|
1938 |
emitByte(0xE9);
|
|
1939 |
emitInt(0);
|
|
1940 |
}
|
|
1941 |
}
|
|
1942 |
|
|
1943 |
public final void jmp(Register entry) {
|
|
1944 |
int encode = prefixAndEncode(entry.encoding);
|
|
1945 |
emitByte(0xFF);
|
|
1946 |
emitByte(0xE0 | encode);
|
|
1947 |
}
|
|
1948 |
|
|
1949 |
public final void jmp(AMD64Address adr) {
|
|
1950 |
prefix(adr);
|
|
1951 |
emitByte(0xFF);
|
|
1952 |
emitOperandHelper(rsp, adr, 0);
|
|
1953 |
}
|
|
1954 |
|
|
1955 |
public final void jmpb(Label l) {
|
|
1956 |
if (l.isBound()) {
|
|
1957 |
int shortSize = 2;
|
|
1958 |
int entry = l.position();
|
|
1959 |
assert isByte((entry - position()) + shortSize) : "Dispacement too large for a short jmp";
|
|
1960 |
long offs = entry - position();
|
|
1961 |
emitByte(0xEB);
|
|
1962 |
emitByte((int) ((offs - shortSize) & 0xFF));
|
|
1963 |
} else {
|
|
1964 |
|
|
1965 |
l.addPatchAt(position());
|
|
1966 |
emitByte(0xEB);
|
|
1967 |
emitByte(0);
|
|
1968 |
}
|
|
1969 |
}
|
|
1970 |
|
48190
|
1971 |
public final void lead(Register dst, AMD64Address src) {
|
|
1972 |
prefix(src, dst);
|
|
1973 |
emitByte(0x8D);
|
|
1974 |
emitOperandHelper(dst, src, 0);
|
|
1975 |
}
|
|
1976 |
|
43972
|
1977 |
public final void leaq(Register dst, AMD64Address src) {
|
|
1978 |
prefixq(src, dst);
|
|
1979 |
emitByte(0x8D);
|
|
1980 |
emitOperandHelper(dst, src, 0);
|
|
1981 |
}
|
|
1982 |
|
|
1983 |
public final void leave() {
|
|
1984 |
emitByte(0xC9);
|
|
1985 |
}
|
|
1986 |
|
|
1987 |
public final void lock() {
|
|
1988 |
emitByte(0xF0);
|
|
1989 |
}
|
|
1990 |
|
|
1991 |
public final void movapd(Register dst, Register src) {
|
|
1992 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
1993 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
1994 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
1995 |
emitByte(0x28);
|
|
1996 |
emitByte(0xC0 | encode);
|
|
1997 |
}
|
|
1998 |
|
|
1999 |
public final void movaps(Register dst, Register src) {
|
|
2000 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2001 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2002 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_NONE, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2003 |
emitByte(0x28);
|
|
2004 |
emitByte(0xC0 | encode);
|
|
2005 |
}
|
|
2006 |
|
|
2007 |
public final void movb(AMD64Address dst, int imm8) {
|
|
2008 |
prefix(dst);
|
|
2009 |
emitByte(0xC6);
|
|
2010 |
emitOperandHelper(0, dst, 1);
|
|
2011 |
emitByte(imm8);
|
|
2012 |
}
|
|
2013 |
|
|
2014 |
public final void movb(AMD64Address dst, Register src) {
|
|
2015 |
assert src.getRegisterCategory().equals(AMD64.CPU) : "must have byte register";
|
|
2016 |
prefix(dst, src, true);
|
|
2017 |
emitByte(0x88);
|
|
2018 |
emitOperandHelper(src, dst, 0);
|
|
2019 |
}
|
|
2020 |
|
|
2021 |
public final void movl(Register dst, int imm32) {
|
|
2022 |
int encode = prefixAndEncode(dst.encoding);
|
|
2023 |
emitByte(0xB8 | encode);
|
|
2024 |
emitInt(imm32);
|
|
2025 |
}
|
|
2026 |
|
|
2027 |
public final void movl(Register dst, Register src) {
|
|
2028 |
int encode = prefixAndEncode(dst.encoding, src.encoding);
|
|
2029 |
emitByte(0x8B);
|
|
2030 |
emitByte(0xC0 | encode);
|
|
2031 |
}
|
|
2032 |
|
|
2033 |
public final void movl(Register dst, AMD64Address src) {
|
|
2034 |
prefix(src, dst);
|
|
2035 |
emitByte(0x8B);
|
|
2036 |
emitOperandHelper(dst, src, 0);
|
|
2037 |
}
|
|
2038 |
|
|
2039 |
public final void movl(AMD64Address dst, int imm32) {
|
|
2040 |
prefix(dst);
|
|
2041 |
emitByte(0xC7);
|
|
2042 |
emitOperandHelper(0, dst, 4);
|
|
2043 |
emitInt(imm32);
|
|
2044 |
}
|
|
2045 |
|
|
2046 |
public final void movl(AMD64Address dst, Register src) {
|
|
2047 |
prefix(dst, src);
|
|
2048 |
emitByte(0x89);
|
|
2049 |
emitOperandHelper(src, dst, 0);
|
|
2050 |
}
|
|
2051 |
|
|
2052 |
/**
|
|
2053 |
* New CPUs require use of movsd and movss to avoid partial register stall when loading from
|
|
2054 |
* memory. But for old Opteron use movlpd instead of movsd. The selection is done in
|
|
2055 |
* {@link AMD64MacroAssembler#movdbl(Register, AMD64Address)} and
|
|
2056 |
* {@link AMD64MacroAssembler#movflt(Register, Register)}.
|
|
2057 |
*/
|
|
2058 |
public final void movlpd(Register dst, AMD64Address src) {
|
|
2059 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2060 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2061 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2062 |
emitByte(0x12);
|
|
2063 |
emitOperandHelper(dst, src, 0);
|
|
2064 |
}
|
|
2065 |
|
|
2066 |
public final void movlhps(Register dst, Register src) {
|
|
2067 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2068 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2069 |
int encode = simdPrefixAndEncode(dst, src, src, VexSimdPrefix.VEX_SIMD_NONE, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2070 |
emitByte(0x16);
|
|
2071 |
emitByte(0xC0 | encode);
|
|
2072 |
}
|
|
2073 |
|
|
2074 |
public final void movq(Register dst, AMD64Address src) {
|
|
2075 |
movq(dst, src, false);
|
|
2076 |
}
|
|
2077 |
|
|
2078 |
public final void movq(Register dst, AMD64Address src, boolean wide) {
|
|
2079 |
if (dst.getRegisterCategory().equals(AMD64.XMM)) {
|
|
2080 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ wide, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2081 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2082 |
emitByte(0x7E);
|
|
2083 |
emitOperandHelper(dst, src, wide, 0);
|
|
2084 |
} else {
|
|
2085 |
// gpr version of movq
|
|
2086 |
prefixq(src, dst);
|
|
2087 |
emitByte(0x8B);
|
|
2088 |
emitOperandHelper(dst, src, wide, 0);
|
|
2089 |
}
|
|
2090 |
}
|
|
2091 |
|
|
2092 |
public final void movq(Register dst, Register src) {
|
|
2093 |
int encode = prefixqAndEncode(dst.encoding, src.encoding);
|
|
2094 |
emitByte(0x8B);
|
|
2095 |
emitByte(0xC0 | encode);
|
|
2096 |
}
|
|
2097 |
|
|
2098 |
public final void movq(AMD64Address dst, Register src) {
|
|
2099 |
if (src.getRegisterCategory().equals(AMD64.XMM)) {
|
|
2100 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2101 |
simdPrefix(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2102 |
emitByte(0xD6);
|
|
2103 |
emitOperandHelper(src, dst, 0);
|
|
2104 |
} else {
|
|
2105 |
// gpr version of movq
|
|
2106 |
prefixq(dst, src);
|
|
2107 |
emitByte(0x89);
|
|
2108 |
emitOperandHelper(src, dst, 0);
|
|
2109 |
}
|
|
2110 |
}
|
|
2111 |
|
|
2112 |
public final void movsbl(Register dst, AMD64Address src) {
|
|
2113 |
prefix(src, dst);
|
|
2114 |
emitByte(0x0F);
|
|
2115 |
emitByte(0xBE);
|
|
2116 |
emitOperandHelper(dst, src, 0);
|
|
2117 |
}
|
|
2118 |
|
|
2119 |
public final void movsbl(Register dst, Register src) {
|
|
2120 |
int encode = prefixAndEncode(dst.encoding, false, src.encoding, true);
|
|
2121 |
emitByte(0x0F);
|
|
2122 |
emitByte(0xBE);
|
|
2123 |
emitByte(0xC0 | encode);
|
|
2124 |
}
|
|
2125 |
|
|
2126 |
public final void movsbq(Register dst, AMD64Address src) {
|
|
2127 |
prefixq(src, dst);
|
|
2128 |
emitByte(0x0F);
|
|
2129 |
emitByte(0xBE);
|
|
2130 |
emitOperandHelper(dst, src, 0);
|
|
2131 |
}
|
|
2132 |
|
|
2133 |
public final void movsbq(Register dst, Register src) {
|
|
2134 |
int encode = prefixqAndEncode(dst.encoding, src.encoding);
|
|
2135 |
emitByte(0x0F);
|
|
2136 |
emitByte(0xBE);
|
|
2137 |
emitByte(0xC0 | encode);
|
|
2138 |
}
|
|
2139 |
|
|
2140 |
public final void movsd(Register dst, Register src) {
|
|
2141 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2142 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2143 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2144 |
emitByte(0x10);
|
|
2145 |
emitByte(0xC0 | encode);
|
|
2146 |
}
|
|
2147 |
|
|
2148 |
public final void movsd(Register dst, AMD64Address src) {
|
|
2149 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2150 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2151 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2152 |
emitByte(0x10);
|
|
2153 |
emitOperandHelper(dst, src, 0);
|
|
2154 |
}
|
|
2155 |
|
|
2156 |
public final void movsd(AMD64Address dst, Register src) {
|
|
2157 |
assert src.getRegisterCategory().equals(AMD64.XMM);
|
|
2158 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2159 |
simdPrefix(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2160 |
emitByte(0x11);
|
|
2161 |
emitOperandHelper(src, dst, 0);
|
|
2162 |
}
|
|
2163 |
|
|
2164 |
public final void movss(Register dst, Register src) {
|
|
2165 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2166 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2167 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2168 |
emitByte(0x10);
|
|
2169 |
emitByte(0xC0 | encode);
|
|
2170 |
}
|
|
2171 |
|
|
2172 |
public final void movss(Register dst, AMD64Address src) {
|
|
2173 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2174 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2175 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2176 |
emitByte(0x10);
|
|
2177 |
emitOperandHelper(dst, src, 0);
|
|
2178 |
}
|
|
2179 |
|
|
2180 |
public final void movss(AMD64Address dst, Register src) {
|
|
2181 |
assert src.getRegisterCategory().equals(AMD64.XMM);
|
|
2182 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2183 |
simdPrefix(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2184 |
emitByte(0x11);
|
|
2185 |
emitOperandHelper(src, dst, 0);
|
|
2186 |
}
|
|
2187 |
|
|
2188 |
public final void mulpd(Register dst, Register src) {
|
|
2189 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2190 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2191 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2192 |
emitByte(0x59);
|
|
2193 |
emitByte(0xC0 | encode);
|
|
2194 |
}
|
|
2195 |
|
|
2196 |
public final void mulpd(Register dst, AMD64Address src) {
|
|
2197 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2198 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2199 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2200 |
emitByte(0x59);
|
|
2201 |
emitOperandHelper(dst, src, 0);
|
|
2202 |
}
|
|
2203 |
|
|
2204 |
public final void mulsd(Register dst, Register src) {
|
|
2205 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2206 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2207 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2208 |
emitByte(0x59);
|
|
2209 |
emitByte(0xC0 | encode);
|
|
2210 |
}
|
|
2211 |
|
|
2212 |
public final void mulsd(Register dst, AMD64Address src) {
|
|
2213 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2214 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2215 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2216 |
emitByte(0x59);
|
|
2217 |
emitOperandHelper(dst, src, 0);
|
|
2218 |
}
|
|
2219 |
|
|
2220 |
public final void mulss(Register dst, Register src) {
|
|
2221 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2222 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2223 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2224 |
emitByte(0x59);
|
|
2225 |
emitByte(0xC0 | encode);
|
|
2226 |
}
|
|
2227 |
|
|
2228 |
public final void movswl(Register dst, AMD64Address src) {
|
|
2229 |
prefix(src, dst);
|
|
2230 |
emitByte(0x0F);
|
|
2231 |
emitByte(0xBF);
|
|
2232 |
emitOperandHelper(dst, src, 0);
|
|
2233 |
}
|
|
2234 |
|
|
2235 |
public final void movw(AMD64Address dst, int imm16) {
|
|
2236 |
emitByte(0x66); // switch to 16-bit mode
|
|
2237 |
prefix(dst);
|
|
2238 |
emitByte(0xC7);
|
|
2239 |
emitOperandHelper(0, dst, 2);
|
|
2240 |
emitShort(imm16);
|
|
2241 |
}
|
|
2242 |
|
|
2243 |
public final void movw(AMD64Address dst, Register src) {
|
|
2244 |
emitByte(0x66);
|
|
2245 |
prefix(dst, src);
|
|
2246 |
emitByte(0x89);
|
|
2247 |
emitOperandHelper(src, dst, 0);
|
|
2248 |
}
|
|
2249 |
|
|
2250 |
public final void movzbl(Register dst, AMD64Address src) {
|
|
2251 |
prefix(src, dst);
|
|
2252 |
emitByte(0x0F);
|
|
2253 |
emitByte(0xB6);
|
|
2254 |
emitOperandHelper(dst, src, 0);
|
|
2255 |
}
|
|
2256 |
|
47798
|
2257 |
public final void movzbl(Register dst, Register src) {
|
|
2258 |
AMD64RMOp.MOVZXB.emit(this, OperandSize.DWORD, dst, src);
|
|
2259 |
}
|
|
2260 |
|
|
2261 |
public final void movzbq(Register dst, Register src) {
|
|
2262 |
AMD64RMOp.MOVZXB.emit(this, OperandSize.QWORD, dst, src);
|
|
2263 |
}
|
|
2264 |
|
43972
|
2265 |
public final void movzwl(Register dst, AMD64Address src) {
|
|
2266 |
prefix(src, dst);
|
|
2267 |
emitByte(0x0F);
|
|
2268 |
emitByte(0xB7);
|
|
2269 |
emitOperandHelper(dst, src, 0);
|
|
2270 |
}
|
|
2271 |
|
|
2272 |
public final void negl(Register dst) {
|
|
2273 |
NEG.emit(this, DWORD, dst);
|
|
2274 |
}
|
|
2275 |
|
|
2276 |
public final void notl(Register dst) {
|
|
2277 |
NOT.emit(this, DWORD, dst);
|
|
2278 |
}
|
|
2279 |
|
|
2280 |
@Override
|
|
2281 |
public final void ensureUniquePC() {
|
|
2282 |
nop();
|
|
2283 |
}
|
|
2284 |
|
|
2285 |
public final void nop() {
|
|
2286 |
nop(1);
|
|
2287 |
}
|
|
2288 |
|
|
2289 |
public void nop(int count) {
|
|
2290 |
int i = count;
|
|
2291 |
if (UseNormalNop) {
|
|
2292 |
assert i > 0 : " ";
|
|
2293 |
// The fancy nops aren't currently recognized by debuggers making it a
|
|
2294 |
// pain to disassemble code while debugging. If assert are on clearly
|
|
2295 |
// speed is not an issue so simply use the single byte traditional nop
|
|
2296 |
// to do alignment.
|
|
2297 |
|
|
2298 |
for (; i > 0; i--) {
|
|
2299 |
emitByte(0x90);
|
|
2300 |
}
|
|
2301 |
return;
|
|
2302 |
}
|
|
2303 |
|
|
2304 |
if (UseAddressNop) {
|
|
2305 |
//
|
|
2306 |
// Using multi-bytes nops "0x0F 0x1F [Address]" for AMD.
|
|
2307 |
// 1: 0x90
|
|
2308 |
// 2: 0x66 0x90
|
|
2309 |
// 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
|
|
2310 |
// 4: 0x0F 0x1F 0x40 0x00
|
|
2311 |
// 5: 0x0F 0x1F 0x44 0x00 0x00
|
|
2312 |
// 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
|
|
2313 |
// 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
|
|
2314 |
// 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
2315 |
// 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
2316 |
// 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
2317 |
// 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
2318 |
|
|
2319 |
// The rest coding is AMD specific - use consecutive Address nops
|
|
2320 |
|
|
2321 |
// 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
|
|
2322 |
// 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
|
|
2323 |
// 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
|
|
2324 |
// 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
|
|
2325 |
// 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
2326 |
// Size prefixes (0x66) are added for larger sizes
|
|
2327 |
|
|
2328 |
while (i >= 22) {
|
|
2329 |
i -= 11;
|
|
2330 |
emitByte(0x66); // size prefix
|
|
2331 |
emitByte(0x66); // size prefix
|
|
2332 |
emitByte(0x66); // size prefix
|
|
2333 |
addrNop8();
|
|
2334 |
}
|
|
2335 |
// Generate first nop for size between 21-12
|
|
2336 |
switch (i) {
|
|
2337 |
case 21:
|
|
2338 |
i -= 11;
|
|
2339 |
emitByte(0x66); // size prefix
|
|
2340 |
emitByte(0x66); // size prefix
|
|
2341 |
emitByte(0x66); // size prefix
|
|
2342 |
addrNop8();
|
|
2343 |
break;
|
|
2344 |
case 20:
|
|
2345 |
case 19:
|
|
2346 |
i -= 10;
|
|
2347 |
emitByte(0x66); // size prefix
|
|
2348 |
emitByte(0x66); // size prefix
|
|
2349 |
addrNop8();
|
|
2350 |
break;
|
|
2351 |
case 18:
|
|
2352 |
case 17:
|
|
2353 |
i -= 9;
|
|
2354 |
emitByte(0x66); // size prefix
|
|
2355 |
addrNop8();
|
|
2356 |
break;
|
|
2357 |
case 16:
|
|
2358 |
case 15:
|
|
2359 |
i -= 8;
|
|
2360 |
addrNop8();
|
|
2361 |
break;
|
|
2362 |
case 14:
|
|
2363 |
case 13:
|
|
2364 |
i -= 7;
|
|
2365 |
addrNop7();
|
|
2366 |
break;
|
|
2367 |
case 12:
|
|
2368 |
i -= 6;
|
|
2369 |
emitByte(0x66); // size prefix
|
|
2370 |
addrNop5();
|
|
2371 |
break;
|
|
2372 |
default:
|
|
2373 |
assert i < 12;
|
|
2374 |
}
|
|
2375 |
|
|
2376 |
// Generate second nop for size between 11-1
|
|
2377 |
switch (i) {
|
|
2378 |
case 11:
|
|
2379 |
emitByte(0x66); // size prefix
|
|
2380 |
emitByte(0x66); // size prefix
|
|
2381 |
emitByte(0x66); // size prefix
|
|
2382 |
addrNop8();
|
|
2383 |
break;
|
|
2384 |
case 10:
|
|
2385 |
emitByte(0x66); // size prefix
|
|
2386 |
emitByte(0x66); // size prefix
|
|
2387 |
addrNop8();
|
|
2388 |
break;
|
|
2389 |
case 9:
|
|
2390 |
emitByte(0x66); // size prefix
|
|
2391 |
addrNop8();
|
|
2392 |
break;
|
|
2393 |
case 8:
|
|
2394 |
addrNop8();
|
|
2395 |
break;
|
|
2396 |
case 7:
|
|
2397 |
addrNop7();
|
|
2398 |
break;
|
|
2399 |
case 6:
|
|
2400 |
emitByte(0x66); // size prefix
|
|
2401 |
addrNop5();
|
|
2402 |
break;
|
|
2403 |
case 5:
|
|
2404 |
addrNop5();
|
|
2405 |
break;
|
|
2406 |
case 4:
|
|
2407 |
addrNop4();
|
|
2408 |
break;
|
|
2409 |
case 3:
|
|
2410 |
// Don't use "0x0F 0x1F 0x00" - need patching safe padding
|
|
2411 |
emitByte(0x66); // size prefix
|
|
2412 |
emitByte(0x66); // size prefix
|
|
2413 |
emitByte(0x90); // nop
|
|
2414 |
break;
|
|
2415 |
case 2:
|
|
2416 |
emitByte(0x66); // size prefix
|
|
2417 |
emitByte(0x90); // nop
|
|
2418 |
break;
|
|
2419 |
case 1:
|
|
2420 |
emitByte(0x90); // nop
|
|
2421 |
break;
|
|
2422 |
default:
|
|
2423 |
assert i == 0;
|
|
2424 |
}
|
|
2425 |
return;
|
|
2426 |
}
|
|
2427 |
|
|
2428 |
// Using nops with size prefixes "0x66 0x90".
|
|
2429 |
// From AMD Optimization Guide:
|
|
2430 |
// 1: 0x90
|
|
2431 |
// 2: 0x66 0x90
|
|
2432 |
// 3: 0x66 0x66 0x90
|
|
2433 |
// 4: 0x66 0x66 0x66 0x90
|
|
2434 |
// 5: 0x66 0x66 0x90 0x66 0x90
|
|
2435 |
// 6: 0x66 0x66 0x90 0x66 0x66 0x90
|
|
2436 |
// 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
|
|
2437 |
// 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
|
|
2438 |
// 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
|
|
2439 |
// 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
|
|
2440 |
//
|
|
2441 |
while (i > 12) {
|
|
2442 |
i -= 4;
|
|
2443 |
emitByte(0x66); // size prefix
|
|
2444 |
emitByte(0x66);
|
|
2445 |
emitByte(0x66);
|
|
2446 |
emitByte(0x90); // nop
|
|
2447 |
}
|
|
2448 |
// 1 - 12 nops
|
|
2449 |
if (i > 8) {
|
|
2450 |
if (i > 9) {
|
|
2451 |
i -= 1;
|
|
2452 |
emitByte(0x66);
|
|
2453 |
}
|
|
2454 |
i -= 3;
|
|
2455 |
emitByte(0x66);
|
|
2456 |
emitByte(0x66);
|
|
2457 |
emitByte(0x90);
|
|
2458 |
}
|
|
2459 |
// 1 - 8 nops
|
|
2460 |
if (i > 4) {
|
|
2461 |
if (i > 6) {
|
|
2462 |
i -= 1;
|
|
2463 |
emitByte(0x66);
|
|
2464 |
}
|
|
2465 |
i -= 3;
|
|
2466 |
emitByte(0x66);
|
|
2467 |
emitByte(0x66);
|
|
2468 |
emitByte(0x90);
|
|
2469 |
}
|
|
2470 |
switch (i) {
|
|
2471 |
case 4:
|
|
2472 |
emitByte(0x66);
|
|
2473 |
emitByte(0x66);
|
|
2474 |
emitByte(0x66);
|
|
2475 |
emitByte(0x90);
|
|
2476 |
break;
|
|
2477 |
case 3:
|
|
2478 |
emitByte(0x66);
|
|
2479 |
emitByte(0x66);
|
|
2480 |
emitByte(0x90);
|
|
2481 |
break;
|
|
2482 |
case 2:
|
|
2483 |
emitByte(0x66);
|
|
2484 |
emitByte(0x90);
|
|
2485 |
break;
|
|
2486 |
case 1:
|
|
2487 |
emitByte(0x90);
|
|
2488 |
break;
|
|
2489 |
default:
|
|
2490 |
assert i == 0;
|
|
2491 |
}
|
|
2492 |
}
|
|
2493 |
|
|
2494 |
public final void orl(Register dst, Register src) {
|
|
2495 |
OR.rmOp.emit(this, DWORD, dst, src);
|
|
2496 |
}
|
|
2497 |
|
|
2498 |
public final void orl(Register dst, int imm32) {
|
|
2499 |
OR.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
2500 |
}
|
|
2501 |
|
|
2502 |
public final void pop(Register dst) {
|
|
2503 |
int encode = prefixAndEncode(dst.encoding);
|
|
2504 |
emitByte(0x58 | encode);
|
|
2505 |
}
|
|
2506 |
|
|
2507 |
public void popfq() {
|
|
2508 |
emitByte(0x9D);
|
|
2509 |
}
|
|
2510 |
|
|
2511 |
public final void ptest(Register dst, Register src) {
|
|
2512 |
assert supports(CPUFeature.SSE4_1);
|
|
2513 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2514 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2515 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F_38, attributes);
|
|
2516 |
emitByte(0x17);
|
|
2517 |
emitByte(0xC0 | encode);
|
|
2518 |
}
|
|
2519 |
|
|
2520 |
public final void vptest(Register dst, Register src) {
|
|
2521 |
assert supports(CPUFeature.AVX);
|
|
2522 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2523 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_256bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2524 |
int encode = vexPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F_38, attributes);
|
|
2525 |
emitByte(0x17);
|
|
2526 |
emitByte(0xC0 | encode);
|
|
2527 |
}
|
|
2528 |
|
46344
|
2529 |
void pcmpestri(Register dst, AMD64Address src, int imm8) {
|
|
2530 |
assert supports(CPUFeature.SSE4_2);
|
|
2531 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2532 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F_3A, attributes);
|
|
2533 |
emitByte(0x61);
|
|
2534 |
emitOperandHelper(dst, src, 0);
|
|
2535 |
emitByte(imm8);
|
|
2536 |
}
|
|
2537 |
|
|
2538 |
void pcmpestri(Register dst, Register src, int imm8) {
|
|
2539 |
assert supports(CPUFeature.SSE4_2);
|
|
2540 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2541 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F_3A, attributes);
|
|
2542 |
emitByte(0x61);
|
|
2543 |
emitByte(0xC0 | encode);
|
|
2544 |
emitByte(imm8);
|
|
2545 |
}
|
|
2546 |
|
43972
|
2547 |
public final void push(Register src) {
|
|
2548 |
int encode = prefixAndEncode(src.encoding);
|
|
2549 |
emitByte(0x50 | encode);
|
|
2550 |
}
|
|
2551 |
|
|
2552 |
public void pushfq() {
|
|
2553 |
emitByte(0x9c);
|
|
2554 |
}
|
|
2555 |
|
|
2556 |
public final void paddd(Register dst, Register src) {
|
|
2557 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2558 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2559 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2560 |
emitByte(0xFE);
|
|
2561 |
emitByte(0xC0 | encode);
|
|
2562 |
}
|
|
2563 |
|
|
2564 |
public final void paddq(Register dst, Register src) {
|
|
2565 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2566 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2567 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2568 |
emitByte(0xD4);
|
|
2569 |
emitByte(0xC0 | encode);
|
|
2570 |
}
|
|
2571 |
|
|
2572 |
public final void pextrw(Register dst, Register src, int imm8) {
|
|
2573 |
assert dst.getRegisterCategory().equals(AMD64.CPU) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2574 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2575 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2576 |
emitByte(0xC5);
|
|
2577 |
emitByte(0xC0 | encode);
|
|
2578 |
emitByte(imm8);
|
|
2579 |
}
|
|
2580 |
|
|
2581 |
public final void pinsrw(Register dst, Register src, int imm8) {
|
|
2582 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.CPU);
|
|
2583 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2584 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2585 |
emitByte(0xC4);
|
|
2586 |
emitByte(0xC0 | encode);
|
|
2587 |
emitByte(imm8);
|
|
2588 |
}
|
|
2589 |
|
|
2590 |
public final void por(Register dst, Register src) {
|
|
2591 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2592 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2593 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2594 |
emitByte(0xEB);
|
|
2595 |
emitByte(0xC0 | encode);
|
|
2596 |
}
|
|
2597 |
|
|
2598 |
public final void pand(Register dst, Register src) {
|
|
2599 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2600 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2601 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2602 |
emitByte(0xDB);
|
|
2603 |
emitByte(0xC0 | encode);
|
|
2604 |
}
|
|
2605 |
|
|
2606 |
public final void pxor(Register dst, Register src) {
|
|
2607 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2608 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2609 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2610 |
emitByte(0xEF);
|
|
2611 |
emitByte(0xC0 | encode);
|
|
2612 |
}
|
|
2613 |
|
|
2614 |
public final void vpxor(Register dst, Register nds, Register src) {
|
|
2615 |
assert supports(CPUFeature.AVX);
|
|
2616 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2617 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_256bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2618 |
int encode = vexPrefixAndEncode(dst, nds, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2619 |
emitByte(0xEF);
|
|
2620 |
emitByte(0xC0 | encode);
|
|
2621 |
}
|
|
2622 |
|
|
2623 |
public final void pslld(Register dst, int imm8) {
|
|
2624 |
assert isUByte(imm8) : "invalid value";
|
|
2625 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2626 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2627 |
// XMM6 is for /6 encoding: 66 0F 72 /6 ib
|
|
2628 |
int encode = simdPrefixAndEncode(AMD64.xmm6, dst, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2629 |
emitByte(0x72);
|
|
2630 |
emitByte(0xC0 | encode);
|
|
2631 |
emitByte(imm8 & 0xFF);
|
|
2632 |
}
|
|
2633 |
|
|
2634 |
public final void psllq(Register dst, Register shift) {
|
|
2635 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && shift.getRegisterCategory().equals(AMD64.XMM);
|
|
2636 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2637 |
int encode = simdPrefixAndEncode(dst, dst, shift, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2638 |
emitByte(0xF3);
|
|
2639 |
emitByte(0xC0 | encode);
|
|
2640 |
}
|
|
2641 |
|
|
2642 |
public final void psllq(Register dst, int imm8) {
|
|
2643 |
assert isUByte(imm8) : "invalid value";
|
|
2644 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2645 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2646 |
// XMM6 is for /6 encoding: 66 0F 73 /6 ib
|
|
2647 |
int encode = simdPrefixAndEncode(AMD64.xmm6, dst, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2648 |
emitByte(0x73);
|
|
2649 |
emitByte(0xC0 | encode);
|
|
2650 |
emitByte(imm8);
|
|
2651 |
}
|
|
2652 |
|
|
2653 |
public final void psrad(Register dst, int imm8) {
|
|
2654 |
assert isUByte(imm8) : "invalid value";
|
|
2655 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2656 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2657 |
// XMM4 is for /2 encoding: 66 0F 72 /4 ib
|
|
2658 |
int encode = simdPrefixAndEncode(AMD64.xmm4, dst, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2659 |
emitByte(0x72);
|
|
2660 |
emitByte(0xC0 | encode);
|
|
2661 |
emitByte(imm8);
|
|
2662 |
}
|
|
2663 |
|
|
2664 |
public final void psrld(Register dst, int imm8) {
|
|
2665 |
assert isUByte(imm8) : "invalid value";
|
|
2666 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2667 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2668 |
// XMM2 is for /2 encoding: 66 0F 72 /2 ib
|
|
2669 |
int encode = simdPrefixAndEncode(AMD64.xmm2, dst, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2670 |
emitByte(0x72);
|
|
2671 |
emitByte(0xC0 | encode);
|
|
2672 |
emitByte(imm8);
|
|
2673 |
}
|
|
2674 |
|
|
2675 |
public final void psrlq(Register dst, int imm8) {
|
|
2676 |
assert isUByte(imm8) : "invalid value";
|
|
2677 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2678 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2679 |
// XMM2 is for /2 encoding: 66 0F 73 /2 ib
|
|
2680 |
int encode = simdPrefixAndEncode(AMD64.xmm2, dst, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2681 |
emitByte(0x73);
|
|
2682 |
emitByte(0xC0 | encode);
|
|
2683 |
emitByte(imm8);
|
|
2684 |
}
|
|
2685 |
|
46344
|
2686 |
public final void psrldq(Register dst, int imm8) {
|
|
2687 |
assert isUByte(imm8) : "invalid value";
|
|
2688 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2689 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2690 |
int encode = simdPrefixAndEncode(AMD64.xmm3, dst, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2691 |
emitByte(0x73);
|
|
2692 |
emitByte(0xC0 | encode);
|
|
2693 |
emitByte(imm8);
|
|
2694 |
}
|
|
2695 |
|
43972
|
2696 |
public final void pshufd(Register dst, Register src, int imm8) {
|
|
2697 |
assert isUByte(imm8) : "invalid value";
|
|
2698 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2699 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2700 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2701 |
emitByte(0x70);
|
|
2702 |
emitByte(0xC0 | encode);
|
|
2703 |
emitByte(imm8);
|
|
2704 |
}
|
|
2705 |
|
|
2706 |
public final void psubd(Register dst, Register src) {
|
|
2707 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2708 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2709 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2710 |
emitByte(0xFA);
|
|
2711 |
emitByte(0xC0 | encode);
|
|
2712 |
}
|
|
2713 |
|
|
2714 |
public final void rcpps(Register dst, Register src) {
|
|
2715 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2716 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ true, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2717 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_NONE, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2718 |
emitByte(0x53);
|
|
2719 |
emitByte(0xC0 | encode);
|
|
2720 |
}
|
|
2721 |
|
|
2722 |
public final void ret(int imm16) {
|
|
2723 |
if (imm16 == 0) {
|
|
2724 |
emitByte(0xC3);
|
|
2725 |
} else {
|
|
2726 |
emitByte(0xC2);
|
|
2727 |
emitShort(imm16);
|
|
2728 |
}
|
|
2729 |
}
|
|
2730 |
|
|
2731 |
public final void sarl(Register dst, int imm8) {
|
|
2732 |
int encode = prefixAndEncode(dst.encoding);
|
|
2733 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
2734 |
if (imm8 == 1) {
|
|
2735 |
emitByte(0xD1);
|
|
2736 |
emitByte(0xF8 | encode);
|
|
2737 |
} else {
|
|
2738 |
emitByte(0xC1);
|
|
2739 |
emitByte(0xF8 | encode);
|
|
2740 |
emitByte(imm8);
|
|
2741 |
}
|
|
2742 |
}
|
|
2743 |
|
|
2744 |
public final void shll(Register dst, int imm8) {
|
|
2745 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
2746 |
int encode = prefixAndEncode(dst.encoding);
|
|
2747 |
if (imm8 == 1) {
|
|
2748 |
emitByte(0xD1);
|
|
2749 |
emitByte(0xE0 | encode);
|
|
2750 |
} else {
|
|
2751 |
emitByte(0xC1);
|
|
2752 |
emitByte(0xE0 | encode);
|
|
2753 |
emitByte(imm8);
|
|
2754 |
}
|
|
2755 |
}
|
|
2756 |
|
|
2757 |
public final void shll(Register dst) {
|
|
2758 |
int encode = prefixAndEncode(dst.encoding);
|
|
2759 |
emitByte(0xD3);
|
|
2760 |
emitByte(0xE0 | encode);
|
|
2761 |
}
|
|
2762 |
|
|
2763 |
public final void shrl(Register dst, int imm8) {
|
|
2764 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
2765 |
int encode = prefixAndEncode(dst.encoding);
|
|
2766 |
emitByte(0xC1);
|
|
2767 |
emitByte(0xE8 | encode);
|
|
2768 |
emitByte(imm8);
|
|
2769 |
}
|
|
2770 |
|
|
2771 |
public final void shrl(Register dst) {
|
|
2772 |
int encode = prefixAndEncode(dst.encoding);
|
|
2773 |
emitByte(0xD3);
|
|
2774 |
emitByte(0xE8 | encode);
|
|
2775 |
}
|
|
2776 |
|
|
2777 |
public final void subl(AMD64Address dst, int imm32) {
|
|
2778 |
SUB.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
2779 |
}
|
|
2780 |
|
|
2781 |
public final void subl(Register dst, int imm32) {
|
|
2782 |
SUB.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
2783 |
}
|
|
2784 |
|
|
2785 |
public final void subl(Register dst, Register src) {
|
|
2786 |
SUB.rmOp.emit(this, DWORD, dst, src);
|
|
2787 |
}
|
|
2788 |
|
|
2789 |
public final void subpd(Register dst, Register src) {
|
|
2790 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2791 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2792 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2793 |
emitByte(0x5C);
|
|
2794 |
emitByte(0xC0 | encode);
|
|
2795 |
}
|
|
2796 |
|
|
2797 |
public final void subsd(Register dst, Register src) {
|
|
2798 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2799 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2800 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2801 |
emitByte(0x5C);
|
|
2802 |
emitByte(0xC0 | encode);
|
|
2803 |
}
|
|
2804 |
|
|
2805 |
public final void subsd(Register dst, AMD64Address src) {
|
|
2806 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
2807 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2808 |
simdPrefix(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2809 |
emitByte(0x5C);
|
|
2810 |
emitOperandHelper(dst, src, 0);
|
|
2811 |
}
|
|
2812 |
|
|
2813 |
public final void testl(Register dst, int imm32) {
|
|
2814 |
// not using emitArith because test
|
|
2815 |
// doesn't support sign-extension of
|
|
2816 |
// 8bit operands
|
|
2817 |
int encode = dst.encoding;
|
|
2818 |
if (encode == 0) {
|
|
2819 |
emitByte(0xA9);
|
|
2820 |
} else {
|
|
2821 |
encode = prefixAndEncode(encode);
|
|
2822 |
emitByte(0xF7);
|
|
2823 |
emitByte(0xC0 | encode);
|
|
2824 |
}
|
|
2825 |
emitInt(imm32);
|
|
2826 |
}
|
|
2827 |
|
|
2828 |
public final void testl(Register dst, Register src) {
|
|
2829 |
int encode = prefixAndEncode(dst.encoding, src.encoding);
|
|
2830 |
emitByte(0x85);
|
|
2831 |
emitByte(0xC0 | encode);
|
|
2832 |
}
|
|
2833 |
|
|
2834 |
public final void testl(Register dst, AMD64Address src) {
|
|
2835 |
prefix(src, dst);
|
|
2836 |
emitByte(0x85);
|
|
2837 |
emitOperandHelper(dst, src, 0);
|
|
2838 |
}
|
|
2839 |
|
|
2840 |
public final void unpckhpd(Register dst, Register src) {
|
|
2841 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2842 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2843 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2844 |
emitByte(0x15);
|
|
2845 |
emitByte(0xC0 | encode);
|
|
2846 |
}
|
|
2847 |
|
|
2848 |
public final void unpcklpd(Register dst, Register src) {
|
|
2849 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2850 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2851 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2852 |
emitByte(0x14);
|
|
2853 |
emitByte(0xC0 | encode);
|
|
2854 |
}
|
|
2855 |
|
|
2856 |
public final void xorl(Register dst, Register src) {
|
|
2857 |
XOR.rmOp.emit(this, DWORD, dst, src);
|
|
2858 |
}
|
|
2859 |
|
|
2860 |
public final void xorpd(Register dst, Register src) {
|
|
2861 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2862 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2863 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2864 |
emitByte(0x57);
|
|
2865 |
emitByte(0xC0 | encode);
|
|
2866 |
}
|
|
2867 |
|
|
2868 |
public final void xorps(Register dst, Register src) {
|
|
2869 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
2870 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
2871 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_NONE, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
2872 |
emitByte(0x57);
|
|
2873 |
emitByte(0xC0 | encode);
|
|
2874 |
}
|
|
2875 |
|
|
2876 |
protected final void decl(Register dst) {
|
|
2877 |
// Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
|
|
2878 |
int encode = prefixAndEncode(dst.encoding);
|
|
2879 |
emitByte(0xFF);
|
|
2880 |
emitByte(0xC8 | encode);
|
|
2881 |
}
|
|
2882 |
|
|
2883 |
protected final void incl(Register dst) {
|
|
2884 |
// Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
|
|
2885 |
int encode = prefixAndEncode(dst.encoding);
|
|
2886 |
emitByte(0xFF);
|
|
2887 |
emitByte(0xC0 | encode);
|
|
2888 |
}
|
|
2889 |
|
|
2890 |
private int prefixAndEncode(int regEnc) {
|
|
2891 |
return prefixAndEncode(regEnc, false);
|
|
2892 |
}
|
|
2893 |
|
|
2894 |
private int prefixAndEncode(int regEnc, boolean byteinst) {
|
|
2895 |
if (regEnc >= 8) {
|
|
2896 |
emitByte(Prefix.REXB);
|
|
2897 |
return regEnc - 8;
|
|
2898 |
} else if (byteinst && regEnc >= 4) {
|
|
2899 |
emitByte(Prefix.REX);
|
|
2900 |
}
|
|
2901 |
return regEnc;
|
|
2902 |
}
|
|
2903 |
|
|
2904 |
private int prefixqAndEncode(int regEnc) {
|
|
2905 |
if (regEnc < 8) {
|
|
2906 |
emitByte(Prefix.REXW);
|
|
2907 |
return regEnc;
|
|
2908 |
} else {
|
|
2909 |
emitByte(Prefix.REXWB);
|
|
2910 |
return regEnc - 8;
|
|
2911 |
}
|
|
2912 |
}
|
|
2913 |
|
|
2914 |
private int prefixAndEncode(int dstEnc, int srcEnc) {
|
|
2915 |
return prefixAndEncode(dstEnc, false, srcEnc, false);
|
|
2916 |
}
|
|
2917 |
|
|
2918 |
private int prefixAndEncode(int dstEncoding, boolean dstIsByte, int srcEncoding, boolean srcIsByte) {
|
|
2919 |
int srcEnc = srcEncoding;
|
|
2920 |
int dstEnc = dstEncoding;
|
|
2921 |
if (dstEnc < 8) {
|
|
2922 |
if (srcEnc >= 8) {
|
|
2923 |
emitByte(Prefix.REXB);
|
|
2924 |
srcEnc -= 8;
|
|
2925 |
} else if ((srcIsByte && srcEnc >= 4) || (dstIsByte && dstEnc >= 4)) {
|
|
2926 |
emitByte(Prefix.REX);
|
|
2927 |
}
|
|
2928 |
} else {
|
|
2929 |
if (srcEnc < 8) {
|
|
2930 |
emitByte(Prefix.REXR);
|
|
2931 |
} else {
|
|
2932 |
emitByte(Prefix.REXRB);
|
|
2933 |
srcEnc -= 8;
|
|
2934 |
}
|
|
2935 |
dstEnc -= 8;
|
|
2936 |
}
|
|
2937 |
return dstEnc << 3 | srcEnc;
|
|
2938 |
}
|
|
2939 |
|
|
2940 |
/**
|
|
2941 |
* Creates prefix and the encoding of the lower 6 bits of the ModRM-Byte. It emits an operand
|
|
2942 |
* prefix. If the given operands exceed 3 bits, the 4th bit is encoded in the prefix.
|
|
2943 |
*
|
|
2944 |
* @param regEncoding the encoding of the register part of the ModRM-Byte
|
|
2945 |
* @param rmEncoding the encoding of the r/m part of the ModRM-Byte
|
|
2946 |
* @return the lower 6 bits of the ModRM-Byte that should be emitted
|
|
2947 |
*/
|
|
2948 |
private int prefixqAndEncode(int regEncoding, int rmEncoding) {
|
|
2949 |
int rmEnc = rmEncoding;
|
|
2950 |
int regEnc = regEncoding;
|
|
2951 |
if (regEnc < 8) {
|
|
2952 |
if (rmEnc < 8) {
|
|
2953 |
emitByte(Prefix.REXW);
|
|
2954 |
} else {
|
|
2955 |
emitByte(Prefix.REXWB);
|
|
2956 |
rmEnc -= 8;
|
|
2957 |
}
|
|
2958 |
} else {
|
|
2959 |
if (rmEnc < 8) {
|
|
2960 |
emitByte(Prefix.REXWR);
|
|
2961 |
} else {
|
|
2962 |
emitByte(Prefix.REXWRB);
|
|
2963 |
rmEnc -= 8;
|
|
2964 |
}
|
|
2965 |
regEnc -= 8;
|
|
2966 |
}
|
|
2967 |
return regEnc << 3 | rmEnc;
|
|
2968 |
}
|
|
2969 |
|
|
2970 |
private void vexPrefix(int rxb, int ndsEncoding, int pre, int opc, AMD64InstructionAttr attributes) {
|
|
2971 |
int vectorLen = attributes.getVectorLen();
|
|
2972 |
boolean vexW = attributes.isRexVexW();
|
|
2973 |
boolean isXorB = ((rxb & 0x3) > 0);
|
|
2974 |
if (isXorB || vexW || (opc == VexOpcode.VEX_OPCODE_0F_38) || (opc == VexOpcode.VEX_OPCODE_0F_3A)) {
|
|
2975 |
emitByte(Prefix.VEX_3BYTES);
|
|
2976 |
|
|
2977 |
int byte1 = (rxb << 5);
|
|
2978 |
byte1 = ((~byte1) & 0xE0) | opc;
|
|
2979 |
emitByte(byte1);
|
|
2980 |
|
|
2981 |
int byte2 = ((~ndsEncoding) & 0xf) << 3;
|
|
2982 |
byte2 |= (vexW ? VexPrefix.VEX_W : 0) | ((vectorLen > 0) ? 4 : 0) | pre;
|
|
2983 |
emitByte(byte2);
|
|
2984 |
} else {
|
|
2985 |
emitByte(Prefix.VEX_2BYTES);
|
|
2986 |
|
|
2987 |
int byte1 = ((rxb & 0x4) > 0) ? VexPrefix.VEX_R : 0;
|
|
2988 |
byte1 = (~byte1) & 0x80;
|
|
2989 |
byte1 |= ((~ndsEncoding) & 0xf) << 3;
|
|
2990 |
byte1 |= ((vectorLen > 0) ? 4 : 0) | pre;
|
|
2991 |
emitByte(byte1);
|
|
2992 |
}
|
|
2993 |
}
|
|
2994 |
|
|
2995 |
private void vexPrefix(AMD64Address adr, Register nds, Register src, int pre, int opc, AMD64InstructionAttr attributes) {
|
|
2996 |
int rxb = getRXB(src, adr);
|
|
2997 |
int ndsEncoding = nds.isValid() ? nds.encoding : 0;
|
|
2998 |
vexPrefix(rxb, ndsEncoding, pre, opc, attributes);
|
|
2999 |
setCurAttributes(attributes);
|
|
3000 |
}
|
|
3001 |
|
|
3002 |
private int vexPrefixAndEncode(Register dst, Register nds, Register src, int pre, int opc, AMD64InstructionAttr attributes) {
|
|
3003 |
int rxb = getRXB(dst, src);
|
|
3004 |
int ndsEncoding = nds.isValid() ? nds.encoding : 0;
|
|
3005 |
vexPrefix(rxb, ndsEncoding, pre, opc, attributes);
|
|
3006 |
// return modrm byte components for operands
|
|
3007 |
return (((dst.encoding & 7) << 3) | (src.encoding & 7));
|
|
3008 |
}
|
|
3009 |
|
|
3010 |
private void simdPrefix(Register xreg, Register nds, AMD64Address adr, int pre, int opc, AMD64InstructionAttr attributes) {
|
|
3011 |
if (supports(CPUFeature.AVX)) {
|
|
3012 |
vexPrefix(adr, nds, xreg, pre, opc, attributes);
|
|
3013 |
} else {
|
|
3014 |
switch (pre) {
|
|
3015 |
case VexSimdPrefix.VEX_SIMD_66:
|
|
3016 |
emitByte(0x66);
|
|
3017 |
break;
|
|
3018 |
case VexSimdPrefix.VEX_SIMD_F2:
|
|
3019 |
emitByte(0xF2);
|
|
3020 |
break;
|
|
3021 |
case VexSimdPrefix.VEX_SIMD_F3:
|
|
3022 |
emitByte(0xF3);
|
|
3023 |
break;
|
|
3024 |
}
|
|
3025 |
if (attributes.isRexVexW()) {
|
|
3026 |
prefixq(adr, xreg);
|
|
3027 |
} else {
|
|
3028 |
prefix(adr, xreg);
|
|
3029 |
}
|
|
3030 |
switch (opc) {
|
|
3031 |
case VexOpcode.VEX_OPCODE_0F:
|
|
3032 |
emitByte(0x0F);
|
|
3033 |
break;
|
|
3034 |
case VexOpcode.VEX_OPCODE_0F_38:
|
|
3035 |
emitByte(0x0F);
|
|
3036 |
emitByte(0x38);
|
|
3037 |
break;
|
|
3038 |
case VexOpcode.VEX_OPCODE_0F_3A:
|
|
3039 |
emitByte(0x0F);
|
|
3040 |
emitByte(0x3A);
|
|
3041 |
break;
|
|
3042 |
}
|
|
3043 |
}
|
|
3044 |
}
|
|
3045 |
|
|
3046 |
private int simdPrefixAndEncode(Register dst, Register nds, Register src, int pre, int opc, AMD64InstructionAttr attributes) {
|
|
3047 |
if (supports(CPUFeature.AVX)) {
|
|
3048 |
return vexPrefixAndEncode(dst, nds, src, pre, opc, attributes);
|
|
3049 |
} else {
|
|
3050 |
switch (pre) {
|
|
3051 |
case VexSimdPrefix.VEX_SIMD_66:
|
|
3052 |
emitByte(0x66);
|
|
3053 |
break;
|
|
3054 |
case VexSimdPrefix.VEX_SIMD_F2:
|
|
3055 |
emitByte(0xF2);
|
|
3056 |
break;
|
|
3057 |
case VexSimdPrefix.VEX_SIMD_F3:
|
|
3058 |
emitByte(0xF3);
|
|
3059 |
break;
|
|
3060 |
}
|
|
3061 |
int encode;
|
|
3062 |
int dstEncoding = dst.encoding;
|
|
3063 |
int srcEncoding = src.encoding;
|
|
3064 |
if (attributes.isRexVexW()) {
|
|
3065 |
encode = prefixqAndEncode(dstEncoding, srcEncoding);
|
|
3066 |
} else {
|
|
3067 |
encode = prefixAndEncode(dstEncoding, srcEncoding);
|
|
3068 |
}
|
|
3069 |
switch (opc) {
|
|
3070 |
case VexOpcode.VEX_OPCODE_0F:
|
|
3071 |
emitByte(0x0F);
|
|
3072 |
break;
|
|
3073 |
case VexOpcode.VEX_OPCODE_0F_38:
|
|
3074 |
emitByte(0x0F);
|
|
3075 |
emitByte(0x38);
|
|
3076 |
break;
|
|
3077 |
case VexOpcode.VEX_OPCODE_0F_3A:
|
|
3078 |
emitByte(0x0F);
|
|
3079 |
emitByte(0x3A);
|
|
3080 |
break;
|
|
3081 |
}
|
|
3082 |
return encode;
|
|
3083 |
}
|
|
3084 |
}
|
|
3085 |
|
|
3086 |
private static boolean needsRex(Register reg) {
|
|
3087 |
return reg.encoding >= MinEncodingNeedsRex;
|
|
3088 |
}
|
|
3089 |
|
|
3090 |
private void prefix(AMD64Address adr) {
|
|
3091 |
if (needsRex(adr.getBase())) {
|
|
3092 |
if (needsRex(adr.getIndex())) {
|
|
3093 |
emitByte(Prefix.REXXB);
|
|
3094 |
} else {
|
|
3095 |
emitByte(Prefix.REXB);
|
|
3096 |
}
|
|
3097 |
} else {
|
|
3098 |
if (needsRex(adr.getIndex())) {
|
|
3099 |
emitByte(Prefix.REXX);
|
|
3100 |
}
|
|
3101 |
}
|
|
3102 |
}
|
|
3103 |
|
|
3104 |
private void prefixq(AMD64Address adr) {
|
|
3105 |
if (needsRex(adr.getBase())) {
|
|
3106 |
if (needsRex(adr.getIndex())) {
|
|
3107 |
emitByte(Prefix.REXWXB);
|
|
3108 |
} else {
|
|
3109 |
emitByte(Prefix.REXWB);
|
|
3110 |
}
|
|
3111 |
} else {
|
|
3112 |
if (needsRex(adr.getIndex())) {
|
|
3113 |
emitByte(Prefix.REXWX);
|
|
3114 |
} else {
|
|
3115 |
emitByte(Prefix.REXW);
|
|
3116 |
}
|
|
3117 |
}
|
|
3118 |
}
|
|
3119 |
|
|
3120 |
private void prefix(AMD64Address adr, Register reg) {
|
|
3121 |
prefix(adr, reg, false);
|
|
3122 |
}
|
|
3123 |
|
|
3124 |
private void prefix(AMD64Address adr, Register reg, boolean byteinst) {
|
|
3125 |
if (reg.encoding < 8) {
|
|
3126 |
if (needsRex(adr.getBase())) {
|
|
3127 |
if (needsRex(adr.getIndex())) {
|
|
3128 |
emitByte(Prefix.REXXB);
|
|
3129 |
} else {
|
|
3130 |
emitByte(Prefix.REXB);
|
|
3131 |
}
|
|
3132 |
} else {
|
|
3133 |
if (needsRex(adr.getIndex())) {
|
|
3134 |
emitByte(Prefix.REXX);
|
|
3135 |
} else if (byteinst && reg.encoding >= 4) {
|
|
3136 |
emitByte(Prefix.REX);
|
|
3137 |
}
|
|
3138 |
}
|
|
3139 |
} else {
|
|
3140 |
if (needsRex(adr.getBase())) {
|
|
3141 |
if (needsRex(adr.getIndex())) {
|
|
3142 |
emitByte(Prefix.REXRXB);
|
|
3143 |
} else {
|
|
3144 |
emitByte(Prefix.REXRB);
|
|
3145 |
}
|
|
3146 |
} else {
|
|
3147 |
if (needsRex(adr.getIndex())) {
|
|
3148 |
emitByte(Prefix.REXRX);
|
|
3149 |
} else {
|
|
3150 |
emitByte(Prefix.REXR);
|
|
3151 |
}
|
|
3152 |
}
|
|
3153 |
}
|
|
3154 |
}
|
|
3155 |
|
|
3156 |
private void prefixq(AMD64Address adr, Register src) {
|
|
3157 |
if (src.encoding < 8) {
|
|
3158 |
if (needsRex(adr.getBase())) {
|
|
3159 |
if (needsRex(adr.getIndex())) {
|
|
3160 |
emitByte(Prefix.REXWXB);
|
|
3161 |
} else {
|
|
3162 |
emitByte(Prefix.REXWB);
|
|
3163 |
}
|
|
3164 |
} else {
|
|
3165 |
if (needsRex(adr.getIndex())) {
|
|
3166 |
emitByte(Prefix.REXWX);
|
|
3167 |
} else {
|
|
3168 |
emitByte(Prefix.REXW);
|
|
3169 |
}
|
|
3170 |
}
|
|
3171 |
} else {
|
|
3172 |
if (needsRex(adr.getBase())) {
|
|
3173 |
if (needsRex(adr.getIndex())) {
|
|
3174 |
emitByte(Prefix.REXWRXB);
|
|
3175 |
} else {
|
|
3176 |
emitByte(Prefix.REXWRB);
|
|
3177 |
}
|
|
3178 |
} else {
|
|
3179 |
if (needsRex(adr.getIndex())) {
|
|
3180 |
emitByte(Prefix.REXWRX);
|
|
3181 |
} else {
|
|
3182 |
emitByte(Prefix.REXWR);
|
|
3183 |
}
|
|
3184 |
}
|
|
3185 |
}
|
|
3186 |
}
|
|
3187 |
|
|
3188 |
public final void addq(Register dst, int imm32) {
|
|
3189 |
ADD.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
3190 |
}
|
|
3191 |
|
|
3192 |
public final void addq(AMD64Address dst, int imm32) {
|
|
3193 |
ADD.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
3194 |
}
|
|
3195 |
|
|
3196 |
public final void addq(Register dst, Register src) {
|
|
3197 |
ADD.rmOp.emit(this, QWORD, dst, src);
|
|
3198 |
}
|
|
3199 |
|
|
3200 |
public final void addq(AMD64Address dst, Register src) {
|
|
3201 |
ADD.mrOp.emit(this, QWORD, dst, src);
|
|
3202 |
}
|
|
3203 |
|
|
3204 |
public final void andq(Register dst, int imm32) {
|
|
3205 |
AND.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
3206 |
}
|
|
3207 |
|
|
3208 |
public final void bsrq(Register dst, Register src) {
|
|
3209 |
int encode = prefixqAndEncode(dst.encoding(), src.encoding());
|
|
3210 |
emitByte(0x0F);
|
|
3211 |
emitByte(0xBD);
|
|
3212 |
emitByte(0xC0 | encode);
|
|
3213 |
}
|
|
3214 |
|
|
3215 |
public final void bswapq(Register reg) {
|
|
3216 |
int encode = prefixqAndEncode(reg.encoding);
|
|
3217 |
emitByte(0x0F);
|
|
3218 |
emitByte(0xC8 | encode);
|
|
3219 |
}
|
|
3220 |
|
|
3221 |
public final void cdqq() {
|
|
3222 |
emitByte(Prefix.REXW);
|
|
3223 |
emitByte(0x99);
|
|
3224 |
}
|
|
3225 |
|
|
3226 |
public final void cmovq(ConditionFlag cc, Register dst, Register src) {
|
|
3227 |
int encode = prefixqAndEncode(dst.encoding, src.encoding);
|
|
3228 |
emitByte(0x0F);
|
|
3229 |
emitByte(0x40 | cc.getValue());
|
|
3230 |
emitByte(0xC0 | encode);
|
|
3231 |
}
|
|
3232 |
|
47798
|
3233 |
public final void setb(ConditionFlag cc, Register dst) {
|
|
3234 |
int encode = prefixAndEncode(dst.encoding, true);
|
|
3235 |
emitByte(0x0F);
|
|
3236 |
emitByte(0x90 | cc.getValue());
|
|
3237 |
emitByte(0xC0 | encode);
|
|
3238 |
}
|
|
3239 |
|
43972
|
3240 |
public final void cmovq(ConditionFlag cc, Register dst, AMD64Address src) {
|
|
3241 |
prefixq(src, dst);
|
|
3242 |
emitByte(0x0F);
|
|
3243 |
emitByte(0x40 | cc.getValue());
|
|
3244 |
emitOperandHelper(dst, src, 0);
|
|
3245 |
}
|
|
3246 |
|
|
3247 |
public final void cmpq(Register dst, int imm32) {
|
|
3248 |
CMP.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
3249 |
}
|
|
3250 |
|
|
3251 |
public final void cmpq(Register dst, Register src) {
|
|
3252 |
CMP.rmOp.emit(this, QWORD, dst, src);
|
|
3253 |
}
|
|
3254 |
|
|
3255 |
public final void cmpq(Register dst, AMD64Address src) {
|
|
3256 |
CMP.rmOp.emit(this, QWORD, dst, src);
|
|
3257 |
}
|
|
3258 |
|
|
3259 |
public final void cmpxchgq(Register reg, AMD64Address adr) {
|
|
3260 |
prefixq(adr, reg);
|
|
3261 |
emitByte(0x0F);
|
|
3262 |
emitByte(0xB1);
|
|
3263 |
emitOperandHelper(reg, adr, 0);
|
|
3264 |
}
|
|
3265 |
|
|
3266 |
public final void cvtdq2pd(Register dst, Register src) {
|
|
3267 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
3268 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3269 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3270 |
emitByte(0xE6);
|
|
3271 |
emitByte(0xC0 | encode);
|
|
3272 |
}
|
|
3273 |
|
|
3274 |
public final void cvtsi2sdq(Register dst, Register src) {
|
|
3275 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.CPU);
|
|
3276 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3277 |
int encode = simdPrefixAndEncode(dst, dst, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3278 |
emitByte(0x2A);
|
|
3279 |
emitByte(0xC0 | encode);
|
|
3280 |
}
|
|
3281 |
|
|
3282 |
public final void cvttsd2siq(Register dst, Register src) {
|
|
3283 |
assert dst.getRegisterCategory().equals(AMD64.CPU) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
3284 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3285 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3286 |
emitByte(0x2C);
|
|
3287 |
emitByte(0xC0 | encode);
|
|
3288 |
}
|
|
3289 |
|
|
3290 |
public final void cvttpd2dq(Register dst, Register src) {
|
|
3291 |
assert dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.XMM);
|
|
3292 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3293 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3294 |
emitByte(0xE6);
|
|
3295 |
emitByte(0xC0 | encode);
|
|
3296 |
}
|
|
3297 |
|
|
3298 |
protected final void decq(Register dst) {
|
|
3299 |
// Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
|
|
3300 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3301 |
emitByte(0xFF);
|
|
3302 |
emitByte(0xC8 | encode);
|
|
3303 |
}
|
|
3304 |
|
|
3305 |
public final void decq(AMD64Address dst) {
|
|
3306 |
DEC.emit(this, QWORD, dst);
|
|
3307 |
}
|
|
3308 |
|
|
3309 |
public final void imulq(Register dst, Register src) {
|
|
3310 |
int encode = prefixqAndEncode(dst.encoding, src.encoding);
|
|
3311 |
emitByte(0x0F);
|
|
3312 |
emitByte(0xAF);
|
|
3313 |
emitByte(0xC0 | encode);
|
|
3314 |
}
|
|
3315 |
|
|
3316 |
public final void incq(Register dst) {
|
|
3317 |
// Don't use it directly. Use Macroincrementq() instead.
|
|
3318 |
// Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
|
|
3319 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3320 |
emitByte(0xFF);
|
|
3321 |
emitByte(0xC0 | encode);
|
|
3322 |
}
|
|
3323 |
|
|
3324 |
public final void incq(AMD64Address dst) {
|
|
3325 |
INC.emit(this, QWORD, dst);
|
|
3326 |
}
|
|
3327 |
|
|
3328 |
public final void movq(Register dst, long imm64) {
|
|
3329 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3330 |
emitByte(0xB8 | encode);
|
|
3331 |
emitLong(imm64);
|
|
3332 |
}
|
|
3333 |
|
|
3334 |
public final void movslq(Register dst, int imm32) {
|
|
3335 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3336 |
emitByte(0xC7);
|
|
3337 |
emitByte(0xC0 | encode);
|
|
3338 |
emitInt(imm32);
|
|
3339 |
}
|
|
3340 |
|
|
3341 |
public final void movdq(Register dst, AMD64Address src) {
|
|
3342 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
3343 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3344 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3345 |
emitByte(0x6E);
|
|
3346 |
emitOperandHelper(dst, src, 0);
|
|
3347 |
}
|
|
3348 |
|
|
3349 |
public final void movdq(AMD64Address dst, Register src) {
|
|
3350 |
assert src.getRegisterCategory().equals(AMD64.XMM);
|
|
3351 |
// swap src/dst to get correct prefix
|
|
3352 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3353 |
simdPrefix(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3354 |
emitByte(0x7E);
|
|
3355 |
emitOperandHelper(src, dst, 0);
|
|
3356 |
}
|
|
3357 |
|
|
3358 |
public final void movdq(Register dst, Register src) {
|
|
3359 |
if (dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.CPU)) {
|
|
3360 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3361 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3362 |
emitByte(0x6E);
|
|
3363 |
emitByte(0xC0 | encode);
|
|
3364 |
} else if (src.getRegisterCategory().equals(AMD64.XMM) && dst.getRegisterCategory().equals(AMD64.CPU)) {
|
|
3365 |
// swap src/dst to get correct prefix
|
|
3366 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ true, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3367 |
int encode = simdPrefixAndEncode(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3368 |
emitByte(0x7E);
|
|
3369 |
emitByte(0xC0 | encode);
|
|
3370 |
} else {
|
|
3371 |
throw new InternalError("should not reach here");
|
|
3372 |
}
|
|
3373 |
}
|
|
3374 |
|
|
3375 |
public final void movdl(Register dst, Register src) {
|
|
3376 |
if (dst.getRegisterCategory().equals(AMD64.XMM) && src.getRegisterCategory().equals(AMD64.CPU)) {
|
|
3377 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3378 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3379 |
emitByte(0x6E);
|
|
3380 |
emitByte(0xC0 | encode);
|
|
3381 |
} else if (src.getRegisterCategory().equals(AMD64.XMM) && dst.getRegisterCategory().equals(AMD64.CPU)) {
|
|
3382 |
// swap src/dst to get correct prefix
|
|
3383 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3384 |
int encode = simdPrefixAndEncode(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3385 |
emitByte(0x7E);
|
|
3386 |
emitByte(0xC0 | encode);
|
|
3387 |
} else {
|
|
3388 |
throw new InternalError("should not reach here");
|
|
3389 |
}
|
|
3390 |
}
|
|
3391 |
|
46344
|
3392 |
public final void movdl(Register dst, AMD64Address src) {
|
|
3393 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3394 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_66, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3395 |
emitByte(0x6E);
|
|
3396 |
emitOperandHelper(dst, src, 0);
|
|
3397 |
}
|
|
3398 |
|
43972
|
3399 |
public final void movddup(Register dst, Register src) {
|
|
3400 |
assert supports(CPUFeature.SSE3);
|
|
3401 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
3402 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3403 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F2, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3404 |
emitByte(0x12);
|
|
3405 |
emitByte(0xC0 | encode);
|
|
3406 |
}
|
|
3407 |
|
|
3408 |
public final void movdqu(Register dst, AMD64Address src) {
|
|
3409 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
3410 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3411 |
simdPrefix(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3412 |
emitByte(0x6F);
|
|
3413 |
emitOperandHelper(dst, src, 0);
|
|
3414 |
}
|
|
3415 |
|
|
3416 |
public final void movdqu(Register dst, Register src) {
|
|
3417 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
3418 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3419 |
int encode = simdPrefixAndEncode(dst, Register.None, src, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3420 |
emitByte(0x6F);
|
|
3421 |
emitByte(0xC0 | encode);
|
|
3422 |
}
|
|
3423 |
|
|
3424 |
public final void vmovdqu(Register dst, AMD64Address src) {
|
|
3425 |
assert supports(CPUFeature.AVX);
|
|
3426 |
assert dst.getRegisterCategory().equals(AMD64.XMM);
|
|
3427 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_256bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3428 |
vexPrefix(src, Register.None, dst, VexSimdPrefix.VEX_SIMD_F3, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3429 |
emitByte(0x6F);
|
|
3430 |
emitOperandHelper(dst, src, 0);
|
|
3431 |
}
|
|
3432 |
|
|
3433 |
public final void vzeroupper() {
|
|
3434 |
assert supports(CPUFeature.AVX);
|
|
3435 |
AMD64InstructionAttr attributes = new AMD64InstructionAttr(AvxVectorLen.AVX_128bit, /* rexVexW */ false, /* legacyMode */ false, /* noMaskReg */ false, /* usesVl */ false, target);
|
|
3436 |
vexPrefixAndEncode(AMD64.xmm0, AMD64.xmm0, AMD64.xmm0, VexSimdPrefix.VEX_SIMD_NONE, VexOpcode.VEX_OPCODE_0F, attributes);
|
|
3437 |
emitByte(0x77);
|
|
3438 |
}
|
|
3439 |
|
|
3440 |
public final void movslq(AMD64Address dst, int imm32) {
|
|
3441 |
prefixq(dst);
|
|
3442 |
emitByte(0xC7);
|
|
3443 |
emitOperandHelper(0, dst, 4);
|
|
3444 |
emitInt(imm32);
|
|
3445 |
}
|
|
3446 |
|
|
3447 |
public final void movslq(Register dst, AMD64Address src) {
|
|
3448 |
prefixq(src, dst);
|
|
3449 |
emitByte(0x63);
|
|
3450 |
emitOperandHelper(dst, src, 0);
|
|
3451 |
}
|
|
3452 |
|
|
3453 |
public final void movslq(Register dst, Register src) {
|
|
3454 |
int encode = prefixqAndEncode(dst.encoding, src.encoding);
|
|
3455 |
emitByte(0x63);
|
|
3456 |
emitByte(0xC0 | encode);
|
|
3457 |
}
|
|
3458 |
|
|
3459 |
public final void negq(Register dst) {
|
|
3460 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3461 |
emitByte(0xF7);
|
|
3462 |
emitByte(0xD8 | encode);
|
|
3463 |
}
|
|
3464 |
|
|
3465 |
public final void orq(Register dst, Register src) {
|
|
3466 |
OR.rmOp.emit(this, QWORD, dst, src);
|
|
3467 |
}
|
|
3468 |
|
|
3469 |
public final void shlq(Register dst, int imm8) {
|
|
3470 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
3471 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3472 |
if (imm8 == 1) {
|
|
3473 |
emitByte(0xD1);
|
|
3474 |
emitByte(0xE0 | encode);
|
|
3475 |
} else {
|
|
3476 |
emitByte(0xC1);
|
|
3477 |
emitByte(0xE0 | encode);
|
|
3478 |
emitByte(imm8);
|
|
3479 |
}
|
|
3480 |
}
|
|
3481 |
|
|
3482 |
public final void shlq(Register dst) {
|
|
3483 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3484 |
emitByte(0xD3);
|
|
3485 |
emitByte(0xE0 | encode);
|
|
3486 |
}
|
|
3487 |
|
|
3488 |
public final void shrq(Register dst, int imm8) {
|
|
3489 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
3490 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3491 |
if (imm8 == 1) {
|
|
3492 |
emitByte(0xD1);
|
|
3493 |
emitByte(0xE8 | encode);
|
|
3494 |
} else {
|
|
3495 |
emitByte(0xC1);
|
|
3496 |
emitByte(0xE8 | encode);
|
|
3497 |
emitByte(imm8);
|
|
3498 |
}
|
|
3499 |
}
|
|
3500 |
|
|
3501 |
public final void shrq(Register dst) {
|
|
3502 |
int encode = prefixqAndEncode(dst.encoding);
|
|
3503 |
emitByte(0xD3);
|
|
3504 |
emitByte(0xE8 | encode);
|
|
3505 |
}
|
|
3506 |
|
|
3507 |
public final void sbbq(Register dst, Register src) {
|
|
3508 |
SBB.rmOp.emit(this, QWORD, dst, src);
|
|
3509 |
}
|
|
3510 |
|
|
3511 |
public final void subq(Register dst, int imm32) {
|
|
3512 |
SUB.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
3513 |
}
|
|
3514 |
|
|
3515 |
public final void subq(AMD64Address dst, int imm32) {
|
|
3516 |
SUB.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
3517 |
}
|
|
3518 |
|
|
3519 |
public final void subqWide(Register dst, int imm32) {
|
|
3520 |
// don't use the sign-extending version, forcing a 32-bit immediate
|
|
3521 |
SUB.getMIOpcode(QWORD, false).emit(this, QWORD, dst, imm32);
|
|
3522 |
}
|
|
3523 |
|
|
3524 |
public final void subq(Register dst, Register src) {
|
|
3525 |
SUB.rmOp.emit(this, QWORD, dst, src);
|
|
3526 |
}
|
|
3527 |
|
|
3528 |
public final void testq(Register dst, Register src) {
|
|
3529 |
int encode = prefixqAndEncode(dst.encoding, src.encoding);
|
|
3530 |
emitByte(0x85);
|
|
3531 |
emitByte(0xC0 | encode);
|
|
3532 |
}
|
|
3533 |
|
46551
|
3534 |
public final void btrq(Register src, int imm8) {
|
|
3535 |
int encode = prefixqAndEncode(src.encoding);
|
|
3536 |
emitByte(0x0F);
|
|
3537 |
emitByte(0xBA);
|
|
3538 |
emitByte(0xF0 | encode);
|
|
3539 |
emitByte(imm8);
|
|
3540 |
}
|
|
3541 |
|
43972
|
3542 |
public final void xaddl(AMD64Address dst, Register src) {
|
|
3543 |
prefix(dst, src);
|
|
3544 |
emitByte(0x0F);
|
|
3545 |
emitByte(0xC1);
|
|
3546 |
emitOperandHelper(src, dst, 0);
|
|
3547 |
}
|
|
3548 |
|
|
3549 |
public final void xaddq(AMD64Address dst, Register src) {
|
|
3550 |
prefixq(dst, src);
|
|
3551 |
emitByte(0x0F);
|
|
3552 |
emitByte(0xC1);
|
|
3553 |
emitOperandHelper(src, dst, 0);
|
|
3554 |
}
|
|
3555 |
|
|
3556 |
public final void xchgl(Register dst, AMD64Address src) {
|
|
3557 |
prefix(src, dst);
|
|
3558 |
emitByte(0x87);
|
|
3559 |
emitOperandHelper(dst, src, 0);
|
|
3560 |
}
|
|
3561 |
|
|
3562 |
public final void xchgq(Register dst, AMD64Address src) {
|
|
3563 |
prefixq(src, dst);
|
|
3564 |
emitByte(0x87);
|
|
3565 |
emitOperandHelper(dst, src, 0);
|
|
3566 |
}
|
|
3567 |
|
|
3568 |
public final void membar(int barriers) {
|
|
3569 |
if (target.isMP) {
|
|
3570 |
// We only have to handle StoreLoad
|
|
3571 |
if ((barriers & STORE_LOAD) != 0) {
|
|
3572 |
// All usable chips support "locked" instructions which suffice
|
|
3573 |
// as barriers, and are much faster than the alternative of
|
|
3574 |
// using cpuid instruction. We use here a locked add [rsp],0.
|
|
3575 |
// This is conveniently otherwise a no-op except for blowing
|
|
3576 |
// flags.
|
|
3577 |
// Any change to this code may need to revisit other places in
|
|
3578 |
// the code where this idiom is used, in particular the
|
|
3579 |
// orderAccess code.
|
|
3580 |
lock();
|
|
3581 |
addl(new AMD64Address(rsp, 0), 0); // Assert the lock# signal here
|
|
3582 |
}
|
|
3583 |
}
|
|
3584 |
}
|
|
3585 |
|
|
3586 |
@Override
|
|
3587 |
protected final void patchJumpTarget(int branch, int branchTarget) {
|
|
3588 |
int op = getByte(branch);
|
|
3589 |
assert op == 0xE8 // call
|
|
3590 |
||
|
|
3591 |
op == 0x00 // jump table entry
|
|
3592 |
|| op == 0xE9 // jmp
|
|
3593 |
|| op == 0xEB // short jmp
|
|
3594 |
|| (op & 0xF0) == 0x70 // short jcc
|
|
3595 |
|| op == 0x0F && (getByte(branch + 1) & 0xF0) == 0x80 // jcc
|
|
3596 |
: "Invalid opcode at patch point branch=" + branch + ", branchTarget=" + branchTarget + ", op=" + op;
|
|
3597 |
|
|
3598 |
if (op == 0x00) {
|
|
3599 |
int offsetToJumpTableBase = getShort(branch + 1);
|
|
3600 |
int jumpTableBase = branch - offsetToJumpTableBase;
|
|
3601 |
int imm32 = branchTarget - jumpTableBase;
|
|
3602 |
emitInt(imm32, branch);
|
|
3603 |
} else if (op == 0xEB || (op & 0xF0) == 0x70) {
|
|
3604 |
|
|
3605 |
// short offset operators (jmp and jcc)
|
|
3606 |
final int imm8 = branchTarget - (branch + 2);
|
|
3607 |
/*
|
|
3608 |
* Since a wrongly patched short branch can potentially lead to working but really bad
|
|
3609 |
* behaving code we should always fail with an exception instead of having an assert.
|
|
3610 |
*/
|
|
3611 |
if (!NumUtil.isByte(imm8)) {
|
|
3612 |
throw new InternalError("branch displacement out of range: " + imm8);
|
|
3613 |
}
|
|
3614 |
emitByte(imm8, branch + 1);
|
|
3615 |
|
|
3616 |
} else {
|
|
3617 |
|
|
3618 |
int off = 1;
|
|
3619 |
if (op == 0x0F) {
|
|
3620 |
off = 2;
|
|
3621 |
}
|
|
3622 |
|
|
3623 |
int imm32 = branchTarget - (branch + 4 + off);
|
|
3624 |
emitInt(imm32, branch + off);
|
|
3625 |
}
|
|
3626 |
}
|
|
3627 |
|
|
3628 |
public void nullCheck(AMD64Address address) {
|
|
3629 |
testl(AMD64.rax, address);
|
|
3630 |
}
|
|
3631 |
|
|
3632 |
@Override
|
|
3633 |
public void align(int modulus) {
|
|
3634 |
if (position() % modulus != 0) {
|
|
3635 |
nop(modulus - (position() % modulus));
|
|
3636 |
}
|
|
3637 |
}
|
|
3638 |
|
|
3639 |
/**
|
|
3640 |
* Emits a direct call instruction. Note that the actual call target is not specified, because
|
|
3641 |
* all calls need patching anyway. Therefore, 0 is emitted as the call target, and the user is
|
|
3642 |
* responsible to add the call address to the appropriate patching tables.
|
|
3643 |
*/
|
|
3644 |
public final void call() {
|
|
3645 |
if (codePatchingAnnotationConsumer != null) {
|
|
3646 |
int pos = position();
|
|
3647 |
codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(pos, pos + 1, 4, pos + 5));
|
|
3648 |
}
|
|
3649 |
emitByte(0xE8);
|
|
3650 |
emitInt(0);
|
|
3651 |
}
|
|
3652 |
|
|
3653 |
public final void call(Register src) {
|
|
3654 |
int encode = prefixAndEncode(src.encoding);
|
|
3655 |
emitByte(0xFF);
|
|
3656 |
emitByte(0xD0 | encode);
|
|
3657 |
}
|
|
3658 |
|
|
3659 |
public final void int3() {
|
|
3660 |
emitByte(0xCC);
|
|
3661 |
}
|
|
3662 |
|
|
3663 |
public final void pause() {
|
|
3664 |
emitByte(0xF3);
|
|
3665 |
emitByte(0x90);
|
|
3666 |
}
|
|
3667 |
|
|
3668 |
private void emitx87(int b1, int b2, int i) {
|
|
3669 |
assert 0 <= i && i < 8 : "illegal stack offset";
|
|
3670 |
emitByte(b1);
|
|
3671 |
emitByte(b2 + i);
|
|
3672 |
}
|
|
3673 |
|
|
3674 |
public final void fldd(AMD64Address src) {
|
|
3675 |
emitByte(0xDD);
|
|
3676 |
emitOperandHelper(0, src, 0);
|
|
3677 |
}
|
|
3678 |
|
|
3679 |
public final void flds(AMD64Address src) {
|
|
3680 |
emitByte(0xD9);
|
|
3681 |
emitOperandHelper(0, src, 0);
|
|
3682 |
}
|
|
3683 |
|
|
3684 |
public final void fldln2() {
|
|
3685 |
emitByte(0xD9);
|
|
3686 |
emitByte(0xED);
|
|
3687 |
}
|
|
3688 |
|
|
3689 |
public final void fldlg2() {
|
|
3690 |
emitByte(0xD9);
|
|
3691 |
emitByte(0xEC);
|
|
3692 |
}
|
|
3693 |
|
|
3694 |
public final void fyl2x() {
|
|
3695 |
emitByte(0xD9);
|
|
3696 |
emitByte(0xF1);
|
|
3697 |
}
|
|
3698 |
|
|
3699 |
public final void fstps(AMD64Address src) {
|
|
3700 |
emitByte(0xD9);
|
|
3701 |
emitOperandHelper(3, src, 0);
|
|
3702 |
}
|
|
3703 |
|
|
3704 |
public final void fstpd(AMD64Address src) {
|
|
3705 |
emitByte(0xDD);
|
|
3706 |
emitOperandHelper(3, src, 0);
|
|
3707 |
}
|
|
3708 |
|
|
3709 |
private void emitFPUArith(int b1, int b2, int i) {
|
|
3710 |
assert 0 <= i && i < 8 : "illegal FPU register: " + i;
|
|
3711 |
emitByte(b1);
|
|
3712 |
emitByte(b2 + i);
|
|
3713 |
}
|
|
3714 |
|
|
3715 |
public void ffree(int i) {
|
|
3716 |
emitFPUArith(0xDD, 0xC0, i);
|
|
3717 |
}
|
|
3718 |
|
|
3719 |
public void fincstp() {
|
|
3720 |
emitByte(0xD9);
|
|
3721 |
emitByte(0xF7);
|
|
3722 |
}
|
|
3723 |
|
|
3724 |
public void fxch(int i) {
|
|
3725 |
emitFPUArith(0xD9, 0xC8, i);
|
|
3726 |
}
|
|
3727 |
|
|
3728 |
public void fnstswAX() {
|
|
3729 |
emitByte(0xDF);
|
|
3730 |
emitByte(0xE0);
|
|
3731 |
}
|
|
3732 |
|
|
3733 |
public void fwait() {
|
|
3734 |
emitByte(0x9B);
|
|
3735 |
}
|
|
3736 |
|
|
3737 |
public void fprem() {
|
|
3738 |
emitByte(0xD9);
|
|
3739 |
emitByte(0xF8);
|
|
3740 |
}
|
|
3741 |
|
|
3742 |
public final void fsin() {
|
|
3743 |
emitByte(0xD9);
|
|
3744 |
emitByte(0xFE);
|
|
3745 |
}
|
|
3746 |
|
|
3747 |
public final void fcos() {
|
|
3748 |
emitByte(0xD9);
|
|
3749 |
emitByte(0xFF);
|
|
3750 |
}
|
|
3751 |
|
|
3752 |
public final void fptan() {
|
|
3753 |
emitByte(0xD9);
|
|
3754 |
emitByte(0xF2);
|
|
3755 |
}
|
|
3756 |
|
|
3757 |
public final void fstp(int i) {
|
|
3758 |
emitx87(0xDD, 0xD8, i);
|
|
3759 |
}
|
|
3760 |
|
|
3761 |
@Override
|
|
3762 |
public AMD64Address makeAddress(Register base, int displacement) {
|
|
3763 |
return new AMD64Address(base, displacement);
|
|
3764 |
}
|
|
3765 |
|
|
3766 |
@Override
|
|
3767 |
public AMD64Address getPlaceholder(int instructionStartPosition) {
|
|
3768 |
return new AMD64Address(rip, Register.None, Scale.Times1, 0, instructionStartPosition);
|
|
3769 |
}
|
|
3770 |
|
|
3771 |
private void prefetchPrefix(AMD64Address src) {
|
|
3772 |
prefix(src);
|
|
3773 |
emitByte(0x0F);
|
|
3774 |
}
|
|
3775 |
|
|
3776 |
public void prefetchnta(AMD64Address src) {
|
|
3777 |
prefetchPrefix(src);
|
|
3778 |
emitByte(0x18);
|
|
3779 |
emitOperandHelper(0, src, 0);
|
|
3780 |
}
|
|
3781 |
|
|
3782 |
void prefetchr(AMD64Address src) {
|
|
3783 |
assert supports(CPUFeature.AMD_3DNOW_PREFETCH);
|
|
3784 |
prefetchPrefix(src);
|
|
3785 |
emitByte(0x0D);
|
|
3786 |
emitOperandHelper(0, src, 0);
|
|
3787 |
}
|
|
3788 |
|
|
3789 |
public void prefetcht0(AMD64Address src) {
|
|
3790 |
assert supports(CPUFeature.SSE);
|
|
3791 |
prefetchPrefix(src);
|
|
3792 |
emitByte(0x18);
|
|
3793 |
emitOperandHelper(1, src, 0);
|
|
3794 |
}
|
|
3795 |
|
|
3796 |
public void prefetcht1(AMD64Address src) {
|
|
3797 |
assert supports(CPUFeature.SSE);
|
|
3798 |
prefetchPrefix(src);
|
|
3799 |
emitByte(0x18);
|
|
3800 |
emitOperandHelper(2, src, 0);
|
|
3801 |
}
|
|
3802 |
|
|
3803 |
public void prefetcht2(AMD64Address src) {
|
|
3804 |
assert supports(CPUFeature.SSE);
|
|
3805 |
prefix(src);
|
|
3806 |
emitByte(0x0f);
|
|
3807 |
emitByte(0x18);
|
|
3808 |
emitOperandHelper(3, src, 0);
|
|
3809 |
}
|
|
3810 |
|
|
3811 |
public void prefetchw(AMD64Address src) {
|
|
3812 |
assert supports(CPUFeature.AMD_3DNOW_PREFETCH);
|
|
3813 |
prefix(src);
|
|
3814 |
emitByte(0x0f);
|
|
3815 |
emitByte(0x0D);
|
|
3816 |
emitOperandHelper(1, src, 0);
|
|
3817 |
}
|
|
3818 |
|
|
3819 |
public void rdtsc() {
|
|
3820 |
emitByte(0x0F);
|
|
3821 |
emitByte(0x31);
|
|
3822 |
}
|
|
3823 |
|
|
3824 |
/**
|
|
3825 |
* Emits an instruction which is considered to be illegal. This is used if we deliberately want
|
|
3826 |
* to crash the program (debugging etc.).
|
|
3827 |
*/
|
|
3828 |
public void illegal() {
|
|
3829 |
emitByte(0x0f);
|
|
3830 |
emitByte(0x0b);
|
|
3831 |
}
|
|
3832 |
}
|