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/*
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* Copyright (c) 2009, 2018, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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50858
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package org.graalvm.compiler.asm.amd64;
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import static jdk.vm.ci.amd64.AMD64.CPU;
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import static jdk.vm.ci.amd64.AMD64.MASK;
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import static jdk.vm.ci.amd64.AMD64.XMM;
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import static jdk.vm.ci.code.MemoryBarriers.STORE_LOAD;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseAddressNop;
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import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseNormalNop;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.ADD;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.AND;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.CMP;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.OR;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SBB;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SUB;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.XOR;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.DEC;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.INC;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NEG;
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import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NOT;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.B0;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.Z0;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.BYTE;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.DWORD;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.PD;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.PS;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.QWORD;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.SD;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.SS;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.OperandSize.WORD;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.L128;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.M_0F;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.M_0F38;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.M_0F3A;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_66;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_F2;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.P_F3;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.W0;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.W1;
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import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.VEXPrefixConfig.WIG;
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import static org.graalvm.compiler.core.common.NumUtil.isByte;
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import static org.graalvm.compiler.core.common.NumUtil.isInt;
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import static org.graalvm.compiler.core.common.NumUtil.isShiftCount;
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import static org.graalvm.compiler.core.common.NumUtil.isUByte;
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import java.util.EnumSet;
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import org.graalvm.compiler.asm.Label;
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import org.graalvm.compiler.asm.amd64.AMD64Address.Scale;
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import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize;
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import org.graalvm.compiler.core.common.NumUtil;
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import org.graalvm.compiler.core.common.calc.Condition;
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import org.graalvm.compiler.debug.GraalError;
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import jdk.vm.ci.amd64.AMD64;
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import jdk.vm.ci.amd64.AMD64.CPUFeature;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.code.Register;
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import jdk.vm.ci.code.Register.RegisterCategory;
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import jdk.vm.ci.code.TargetDescription;
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/**
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* This class implements an assembler that can encode most X86 instructions.
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*/
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public class AMD64Assembler extends AMD64BaseAssembler {
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/**
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* Constructs an assembler for the AMD64 architecture.
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*/
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public AMD64Assembler(TargetDescription target) {
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super(target);
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}
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/**
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* The x86 condition codes used for conditional jumps/moves.
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*/
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public enum ConditionFlag {
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Zero(0x4, "|zero|"),
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NotZero(0x5, "|nzero|"),
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Equal(0x4, "="),
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NotEqual(0x5, "!="),
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Less(0xc, "<"),
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LessEqual(0xe, "<="),
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Greater(0xf, ">"),
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GreaterEqual(0xd, ">="),
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Below(0x2, "|<|"),
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BelowEqual(0x6, "|<=|"),
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Above(0x7, "|>|"),
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AboveEqual(0x3, "|>=|"),
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Overflow(0x0, "|of|"),
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NoOverflow(0x1, "|nof|"),
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CarrySet(0x2, "|carry|"),
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CarryClear(0x3, "|ncarry|"),
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Negative(0x8, "|neg|"),
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Positive(0x9, "|pos|"),
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Parity(0xa, "|par|"),
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NoParity(0xb, "|npar|");
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private final int value;
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private final String operator;
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ConditionFlag(int value, String operator) {
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this.value = value;
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this.operator = operator;
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}
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public ConditionFlag negate() {
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switch (this) {
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case Zero:
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return NotZero;
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case NotZero:
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return Zero;
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case Equal:
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return NotEqual;
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case NotEqual:
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return Equal;
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case Less:
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return GreaterEqual;
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case LessEqual:
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return Greater;
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case Greater:
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return LessEqual;
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case GreaterEqual:
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return Less;
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case Below:
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return AboveEqual;
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case BelowEqual:
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return Above;
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case Above:
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return BelowEqual;
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case AboveEqual:
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return Below;
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case Overflow:
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return NoOverflow;
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case NoOverflow:
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return Overflow;
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case CarrySet:
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return CarryClear;
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case CarryClear:
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return CarrySet;
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case Negative:
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return Positive;
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case Positive:
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return Negative;
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case Parity:
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return NoParity;
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case NoParity:
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return Parity;
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}
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throw new IllegalArgumentException();
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}
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public int getValue() {
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return value;
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}
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@Override
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public String toString() {
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return operator;
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}
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}
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/**
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* Operand size and register type constraints.
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*/
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private enum OpAssertion {
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ByteAssertion(CPU, CPU, BYTE),
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ByteOrLargerAssertion(CPU, CPU, BYTE, WORD, DWORD, QWORD),
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WordOrLargerAssertion(CPU, CPU, WORD, DWORD, QWORD),
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DwordOrLargerAssertion(CPU, CPU, DWORD, QWORD),
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WordOrDwordAssertion(CPU, CPU, WORD, QWORD),
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QwordAssertion(CPU, CPU, QWORD),
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FloatAssertion(XMM, XMM, SS, SD, PS, PD),
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PackedFloatAssertion(XMM, XMM, PS, PD),
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SingleAssertion(XMM, XMM, SS),
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DoubleAssertion(XMM, XMM, SD),
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PackedDoubleAssertion(XMM, XMM, PD),
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IntToFloatAssertion(XMM, CPU, DWORD, QWORD),
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FloatToIntAssertion(CPU, XMM, DWORD, QWORD);
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private final RegisterCategory resultCategory;
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private final RegisterCategory inputCategory;
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private final OperandSize[] allowedSizes;
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OpAssertion(RegisterCategory resultCategory, RegisterCategory inputCategory, OperandSize... allowedSizes) {
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this.resultCategory = resultCategory;
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this.inputCategory = inputCategory;
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this.allowedSizes = allowedSizes;
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}
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protected boolean checkOperands(AMD64Op op, OperandSize size, Register resultReg, Register inputReg) {
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assert resultReg == null || resultCategory.equals(resultReg.getRegisterCategory()) : "invalid result register " + resultReg + " used in " + op;
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assert inputReg == null || inputCategory.equals(inputReg.getRegisterCategory()) : "invalid input register " + inputReg + " used in " + op;
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for (OperandSize s : allowedSizes) {
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if (size == s) {
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return true;
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}
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}
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assert false : "invalid operand size " + size + " used in " + op;
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return false;
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}
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}
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protected static final int P_0F = 0x0F;
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protected static final int P_0F38 = 0x380F;
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protected static final int P_0F3A = 0x3A0F;
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/**
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* Base class for AMD64 opcodes.
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*/
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public static class AMD64Op {
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private final String opcode;
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protected final int prefix1;
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protected final int prefix2;
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protected final int op;
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private final boolean dstIsByte;
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private final boolean srcIsByte;
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private final OpAssertion assertion;
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private final CPUFeature feature;
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protected AMD64Op(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
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this(opcode, prefix1, prefix2, op, assertion == OpAssertion.ByteAssertion, assertion == OpAssertion.ByteAssertion, assertion, feature);
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}
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protected AMD64Op(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {
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this.opcode = opcode;
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this.prefix1 = prefix1;
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this.prefix2 = prefix2;
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this.op = op;
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this.dstIsByte = dstIsByte;
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this.srcIsByte = srcIsByte;
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this.assertion = assertion;
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this.feature = feature;
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}
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protected final void emitOpcode(AMD64Assembler asm, OperandSize size, int rxb, int dstEnc, int srcEnc) {
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if (prefix1 != 0) {
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asm.emitByte(prefix1);
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}
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if (size.getSizePrefix() != 0) {
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asm.emitByte(size.getSizePrefix());
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}
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int rexPrefix = 0x40 | rxb;
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if (size == QWORD) {
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rexPrefix |= 0x08;
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}
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if (rexPrefix != 0x40 || (dstIsByte && dstEnc >= 4) || (srcIsByte && srcEnc >= 4)) {
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asm.emitByte(rexPrefix);
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}
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if (prefix2 > 0xFF) {
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asm.emitShort(prefix2);
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} else if (prefix2 > 0) {
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asm.emitByte(prefix2);
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}
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asm.emitByte(op);
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}
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protected final boolean verify(AMD64Assembler asm, OperandSize size, Register resultReg, Register inputReg) {
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assert feature == null || asm.supports(feature) : String.format("unsupported feature %s required for %s", feature, opcode);
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assert assertion.checkOperands(this, size, resultReg, inputReg);
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return true;
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}
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public OperandSize[] getAllowedSizes() {
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return assertion.allowedSizes;
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}
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protected final boolean isSSEInstruction() {
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if (feature == null) {
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return false;
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}
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switch (feature) {
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case SSE:
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case SSE2:
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case SSE3:
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case SSSE3:
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case SSE4A:
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case SSE4_1:
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case SSE4_2:
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return true;
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default:
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return false;
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}
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}
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public final OpAssertion getAssertion() {
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return assertion;
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}
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@Override
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public String toString() {
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return opcode;
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|
|
326 |
}
|
|
|
327 |
}
|
|
|
328 |
|
|
|
329 |
/**
|
|
|
330 |
* Base class for AMD64 opcodes with immediate operands.
|
|
|
331 |
*/
|
|
|
332 |
public static class AMD64ImmOp extends AMD64Op {
|
|
|
333 |
|
|
|
334 |
private final boolean immIsByte;
|
|
|
335 |
|
|
|
336 |
protected AMD64ImmOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion) {
|
|
51436
|
337 |
this(opcode, immIsByte, prefix, op, assertion, null);
|
|
|
338 |
}
|
|
|
339 |
|
|
|
340 |
protected AMD64ImmOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
341 |
super(opcode, 0, prefix, op, assertion, feature);
|
|
43972
|
342 |
this.immIsByte = immIsByte;
|
|
|
343 |
}
|
|
|
344 |
|
|
|
345 |
protected final void emitImmediate(AMD64Assembler asm, OperandSize size, int imm) {
|
|
|
346 |
if (immIsByte) {
|
|
|
347 |
assert imm == (byte) imm;
|
|
|
348 |
asm.emitByte(imm);
|
|
|
349 |
} else {
|
|
|
350 |
size.emitImmediate(asm, imm);
|
|
|
351 |
}
|
|
|
352 |
}
|
|
|
353 |
|
|
|
354 |
protected final int immediateSize(OperandSize size) {
|
|
|
355 |
if (immIsByte) {
|
|
|
356 |
return 1;
|
|
|
357 |
} else {
|
|
51436
|
358 |
return size.getBytes();
|
|
43972
|
359 |
}
|
|
|
360 |
}
|
|
|
361 |
}
|
|
|
362 |
|
|
|
363 |
/**
|
|
|
364 |
* Opcode with operand order of either RM or MR for 2 address forms.
|
|
|
365 |
*/
|
|
|
366 |
public abstract static class AMD64RROp extends AMD64Op {
|
|
|
367 |
|
|
|
368 |
protected AMD64RROp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
369 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
|
370 |
}
|
|
|
371 |
|
|
|
372 |
protected AMD64RROp(String opcode, int prefix1, int prefix2, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion, CPUFeature feature) {
|
|
|
373 |
super(opcode, prefix1, prefix2, op, dstIsByte, srcIsByte, assertion, feature);
|
|
|
374 |
}
|
|
|
375 |
|
|
|
376 |
public abstract void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src);
|
|
|
377 |
}
|
|
|
378 |
|
|
|
379 |
/**
|
|
|
380 |
* Opcode with operand order of RM.
|
|
|
381 |
*/
|
|
|
382 |
public static class AMD64RMOp extends AMD64RROp {
|
|
|
383 |
// @formatter:off
|
|
48190
|
384 |
public static final AMD64RMOp IMUL = new AMD64RMOp("IMUL", P_0F, 0xAF, OpAssertion.ByteOrLargerAssertion);
|
|
43972
|
385 |
public static final AMD64RMOp BSF = new AMD64RMOp("BSF", P_0F, 0xBC);
|
|
|
386 |
public static final AMD64RMOp BSR = new AMD64RMOp("BSR", P_0F, 0xBD);
|
|
51436
|
387 |
// POPCNT, TZCNT, and LZCNT support word operation. However, the legacy size prefix should
|
|
|
388 |
// be emitted before the mandatory prefix 0xF3. Since we are not emitting bit count for
|
|
|
389 |
// 16-bit operands, here we simply use DwordOrLargerAssertion.
|
|
|
390 |
public static final AMD64RMOp POPCNT = new AMD64RMOp("POPCNT", 0xF3, P_0F, 0xB8, OpAssertion.DwordOrLargerAssertion, CPUFeature.POPCNT);
|
|
|
391 |
public static final AMD64RMOp TZCNT = new AMD64RMOp("TZCNT", 0xF3, P_0F, 0xBC, OpAssertion.DwordOrLargerAssertion, CPUFeature.BMI1);
|
|
|
392 |
public static final AMD64RMOp LZCNT = new AMD64RMOp("LZCNT", 0xF3, P_0F, 0xBD, OpAssertion.DwordOrLargerAssertion, CPUFeature.LZCNT);
|
|
48190
|
393 |
public static final AMD64RMOp MOVZXB = new AMD64RMOp("MOVZXB", P_0F, 0xB6, false, true, OpAssertion.WordOrLargerAssertion);
|
|
|
394 |
public static final AMD64RMOp MOVZX = new AMD64RMOp("MOVZX", P_0F, 0xB7, OpAssertion.DwordOrLargerAssertion);
|
|
|
395 |
public static final AMD64RMOp MOVSXB = new AMD64RMOp("MOVSXB", P_0F, 0xBE, false, true, OpAssertion.WordOrLargerAssertion);
|
|
|
396 |
public static final AMD64RMOp MOVSX = new AMD64RMOp("MOVSX", P_0F, 0xBF, OpAssertion.DwordOrLargerAssertion);
|
|
|
397 |
public static final AMD64RMOp MOVSXD = new AMD64RMOp("MOVSXD", 0x63, OpAssertion.QwordAssertion);
|
|
43972
|
398 |
public static final AMD64RMOp MOVB = new AMD64RMOp("MOVB", 0x8A, OpAssertion.ByteAssertion);
|
|
|
399 |
public static final AMD64RMOp MOV = new AMD64RMOp("MOV", 0x8B);
|
|
50858
|
400 |
public static final AMD64RMOp CMP = new AMD64RMOp("CMP", 0x3B);
|
|
43972
|
401 |
|
|
|
402 |
// MOVD/MOVQ and MOVSS/MOVSD are the same opcode, just with different operand size prefix
|
|
48190
|
403 |
public static final AMD64RMOp MOVD = new AMD64RMOp("MOVD", 0x66, P_0F, 0x6E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
|
404 |
public static final AMD64RMOp MOVQ = new AMD64RMOp("MOVQ", 0x66, P_0F, 0x6E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
|
405 |
public static final AMD64RMOp MOVSS = new AMD64RMOp("MOVSS", P_0F, 0x10, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
|
|
406 |
public static final AMD64RMOp MOVSD = new AMD64RMOp("MOVSD", P_0F, 0x10, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
|
43972
|
407 |
|
|
|
408 |
// TEST is documented as MR operation, but it's symmetric, and using it as RM operation is more convenient.
|
|
|
409 |
public static final AMD64RMOp TESTB = new AMD64RMOp("TEST", 0x84, OpAssertion.ByteAssertion);
|
|
|
410 |
public static final AMD64RMOp TEST = new AMD64RMOp("TEST", 0x85);
|
|
|
411 |
// @formatter:on
|
|
|
412 |
|
|
|
413 |
protected AMD64RMOp(String opcode, int op) {
|
|
|
414 |
this(opcode, 0, op);
|
|
|
415 |
}
|
|
|
416 |
|
|
|
417 |
protected AMD64RMOp(String opcode, int op, OpAssertion assertion) {
|
|
|
418 |
this(opcode, 0, op, assertion);
|
|
|
419 |
}
|
|
|
420 |
|
|
|
421 |
protected AMD64RMOp(String opcode, int prefix, int op) {
|
|
|
422 |
this(opcode, 0, prefix, op, null);
|
|
|
423 |
}
|
|
|
424 |
|
|
|
425 |
protected AMD64RMOp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
|
426 |
this(opcode, 0, prefix, op, assertion, null);
|
|
|
427 |
}
|
|
|
428 |
|
|
|
429 |
protected AMD64RMOp(String opcode, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
430 |
this(opcode, 0, prefix, op, assertion, feature);
|
|
|
431 |
}
|
|
|
432 |
|
|
|
433 |
protected AMD64RMOp(String opcode, int prefix, int op, boolean dstIsByte, boolean srcIsByte, OpAssertion assertion) {
|
|
|
434 |
super(opcode, 0, prefix, op, dstIsByte, srcIsByte, assertion, null);
|
|
|
435 |
}
|
|
|
436 |
|
|
|
437 |
protected AMD64RMOp(String opcode, int prefix1, int prefix2, int op, CPUFeature feature) {
|
|
48190
|
438 |
this(opcode, prefix1, prefix2, op, OpAssertion.WordOrLargerAssertion, feature);
|
|
43972
|
439 |
}
|
|
|
440 |
|
|
|
441 |
protected AMD64RMOp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
442 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
|
443 |
}
|
|
|
444 |
|
|
|
445 |
@Override
|
|
|
446 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src) {
|
|
|
447 |
assert verify(asm, size, dst, src);
|
|
51436
|
448 |
if (isSSEInstruction()) {
|
|
|
449 |
Register nds = Register.None;
|
|
|
450 |
switch (op) {
|
|
|
451 |
case 0x10:
|
|
|
452 |
case 0x51:
|
|
|
453 |
if ((size == SS) || (size == SD)) {
|
|
|
454 |
nds = dst;
|
|
|
455 |
}
|
|
48861
|
456 |
break;
|
|
51436
|
457 |
case 0x2A:
|
|
|
458 |
case 0x54:
|
|
|
459 |
case 0x55:
|
|
|
460 |
case 0x56:
|
|
|
461 |
case 0x57:
|
|
|
462 |
case 0x58:
|
|
|
463 |
case 0x59:
|
|
|
464 |
case 0x5A:
|
|
|
465 |
case 0x5C:
|
|
|
466 |
case 0x5D:
|
|
|
467 |
case 0x5E:
|
|
|
468 |
case 0x5F:
|
|
|
469 |
nds = dst;
|
|
48861
|
470 |
break;
|
|
|
471 |
default:
|
|
|
472 |
break;
|
|
|
473 |
}
|
|
51436
|
474 |
asm.simdPrefix(dst, nds, src, size, prefix1, prefix2, size == QWORD);
|
|
43972
|
475 |
asm.emitByte(op);
|
|
51436
|
476 |
asm.emitModRM(dst, src);
|
|
43972
|
477 |
} else {
|
|
|
478 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, src.encoding);
|
|
|
479 |
asm.emitModRM(dst, src);
|
|
|
480 |
}
|
|
|
481 |
}
|
|
|
482 |
|
|
|
483 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, AMD64Address src) {
|
|
|
484 |
assert verify(asm, size, dst, null);
|
|
51436
|
485 |
if (isSSEInstruction()) {
|
|
|
486 |
Register nds = Register.None;
|
|
|
487 |
switch (op) {
|
|
|
488 |
case 0x51:
|
|
|
489 |
if ((size == SS) || (size == SD)) {
|
|
|
490 |
nds = dst;
|
|
|
491 |
}
|
|
48861
|
492 |
break;
|
|
51436
|
493 |
case 0x2A:
|
|
|
494 |
case 0x54:
|
|
|
495 |
case 0x55:
|
|
|
496 |
case 0x56:
|
|
|
497 |
case 0x57:
|
|
|
498 |
case 0x58:
|
|
|
499 |
case 0x59:
|
|
|
500 |
case 0x5A:
|
|
|
501 |
case 0x5C:
|
|
|
502 |
case 0x5D:
|
|
|
503 |
case 0x5E:
|
|
|
504 |
case 0x5F:
|
|
|
505 |
nds = dst;
|
|
48861
|
506 |
break;
|
|
|
507 |
default:
|
|
|
508 |
break;
|
|
|
509 |
}
|
|
51436
|
510 |
asm.simdPrefix(dst, nds, src, size, prefix1, prefix2, size == QWORD);
|
|
43972
|
511 |
asm.emitByte(op);
|
|
|
512 |
asm.emitOperandHelper(dst, src, 0);
|
|
|
513 |
} else {
|
|
|
514 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, 0);
|
|
|
515 |
asm.emitOperandHelper(dst, src, 0);
|
|
|
516 |
}
|
|
|
517 |
}
|
|
|
518 |
}
|
|
|
519 |
|
|
|
520 |
/**
|
|
|
521 |
* Opcode with operand order of MR.
|
|
|
522 |
*/
|
|
|
523 |
public static class AMD64MROp extends AMD64RROp {
|
|
|
524 |
// @formatter:off
|
|
|
525 |
public static final AMD64MROp MOVB = new AMD64MROp("MOVB", 0x88, OpAssertion.ByteAssertion);
|
|
|
526 |
public static final AMD64MROp MOV = new AMD64MROp("MOV", 0x89);
|
|
|
527 |
|
|
|
528 |
// MOVD and MOVQ are the same opcode, just with different operand size prefix
|
|
|
529 |
// Note that as MR opcodes, they have reverse operand order, so the IntToFloatingAssertion must be used.
|
|
48190
|
530 |
public static final AMD64MROp MOVD = new AMD64MROp("MOVD", 0x66, P_0F, 0x7E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
|
531 |
public static final AMD64MROp MOVQ = new AMD64MROp("MOVQ", 0x66, P_0F, 0x7E, OpAssertion.IntToFloatAssertion, CPUFeature.SSE2);
|
|
43972
|
532 |
|
|
|
533 |
// MOVSS and MOVSD are the same opcode, just with different operand size prefix
|
|
48190
|
534 |
public static final AMD64MROp MOVSS = new AMD64MROp("MOVSS", P_0F, 0x11, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
|
|
535 |
public static final AMD64MROp MOVSD = new AMD64MROp("MOVSD", P_0F, 0x11, OpAssertion.FloatAssertion, CPUFeature.SSE);
|
|
43972
|
536 |
// @formatter:on
|
|
|
537 |
|
|
|
538 |
protected AMD64MROp(String opcode, int op) {
|
|
|
539 |
this(opcode, 0, op);
|
|
|
540 |
}
|
|
|
541 |
|
|
|
542 |
protected AMD64MROp(String opcode, int op, OpAssertion assertion) {
|
|
|
543 |
this(opcode, 0, op, assertion);
|
|
|
544 |
}
|
|
|
545 |
|
|
|
546 |
protected AMD64MROp(String opcode, int prefix, int op) {
|
|
48190
|
547 |
this(opcode, prefix, op, OpAssertion.WordOrLargerAssertion);
|
|
43972
|
548 |
}
|
|
|
549 |
|
|
|
550 |
protected AMD64MROp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
|
551 |
this(opcode, prefix, op, assertion, null);
|
|
|
552 |
}
|
|
|
553 |
|
|
|
554 |
protected AMD64MROp(String opcode, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
555 |
this(opcode, 0, prefix, op, assertion, feature);
|
|
|
556 |
}
|
|
|
557 |
|
|
|
558 |
protected AMD64MROp(String opcode, int prefix1, int prefix2, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
559 |
super(opcode, prefix1, prefix2, op, assertion, feature);
|
|
|
560 |
}
|
|
|
561 |
|
|
|
562 |
@Override
|
|
|
563 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src) {
|
|
|
564 |
assert verify(asm, size, src, dst);
|
|
51436
|
565 |
if (isSSEInstruction()) {
|
|
|
566 |
Register nds = Register.None;
|
|
|
567 |
switch (op) {
|
|
|
568 |
case 0x11:
|
|
|
569 |
if ((size == SS) || (size == SD)) {
|
|
|
570 |
nds = src;
|
|
|
571 |
}
|
|
48861
|
572 |
break;
|
|
|
573 |
default:
|
|
|
574 |
break;
|
|
|
575 |
}
|
|
51436
|
576 |
asm.simdPrefix(src, nds, dst, size, prefix1, prefix2, size == QWORD);
|
|
43972
|
577 |
asm.emitByte(op);
|
|
51436
|
578 |
asm.emitModRM(src, dst);
|
|
43972
|
579 |
} else {
|
|
|
580 |
emitOpcode(asm, size, getRXB(src, dst), src.encoding, dst.encoding);
|
|
|
581 |
asm.emitModRM(src, dst);
|
|
|
582 |
}
|
|
|
583 |
}
|
|
|
584 |
|
|
|
585 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, Register src) {
|
|
51436
|
586 |
assert verify(asm, size, src, null);
|
|
|
587 |
if (isSSEInstruction()) {
|
|
|
588 |
asm.simdPrefix(src, Register.None, dst, size, prefix1, prefix2, size == QWORD);
|
|
43972
|
589 |
asm.emitByte(op);
|
|
|
590 |
} else {
|
|
|
591 |
emitOpcode(asm, size, getRXB(src, dst), src.encoding, 0);
|
|
|
592 |
}
|
|
51436
|
593 |
asm.emitOperandHelper(src, dst, 0);
|
|
43972
|
594 |
}
|
|
|
595 |
}
|
|
|
596 |
|
|
|
597 |
/**
|
|
|
598 |
* Opcodes with operand order of M.
|
|
|
599 |
*/
|
|
|
600 |
public static class AMD64MOp extends AMD64Op {
|
|
|
601 |
// @formatter:off
|
|
|
602 |
public static final AMD64MOp NOT = new AMD64MOp("NOT", 0xF7, 2);
|
|
|
603 |
public static final AMD64MOp NEG = new AMD64MOp("NEG", 0xF7, 3);
|
|
|
604 |
public static final AMD64MOp MUL = new AMD64MOp("MUL", 0xF7, 4);
|
|
|
605 |
public static final AMD64MOp IMUL = new AMD64MOp("IMUL", 0xF7, 5);
|
|
|
606 |
public static final AMD64MOp DIV = new AMD64MOp("DIV", 0xF7, 6);
|
|
|
607 |
public static final AMD64MOp IDIV = new AMD64MOp("IDIV", 0xF7, 7);
|
|
|
608 |
public static final AMD64MOp INC = new AMD64MOp("INC", 0xFF, 0);
|
|
|
609 |
public static final AMD64MOp DEC = new AMD64MOp("DEC", 0xFF, 1);
|
|
|
610 |
public static final AMD64MOp PUSH = new AMD64MOp("PUSH", 0xFF, 6);
|
|
48190
|
611 |
public static final AMD64MOp POP = new AMD64MOp("POP", 0x8F, 0, OpAssertion.WordOrDwordAssertion);
|
|
43972
|
612 |
// @formatter:on
|
|
|
613 |
|
|
|
614 |
private final int ext;
|
|
|
615 |
|
|
|
616 |
protected AMD64MOp(String opcode, int op, int ext) {
|
|
|
617 |
this(opcode, 0, op, ext);
|
|
|
618 |
}
|
|
|
619 |
|
|
|
620 |
protected AMD64MOp(String opcode, int prefix, int op, int ext) {
|
|
48190
|
621 |
this(opcode, prefix, op, ext, OpAssertion.WordOrLargerAssertion);
|
|
43972
|
622 |
}
|
|
|
623 |
|
|
|
624 |
protected AMD64MOp(String opcode, int op, int ext, OpAssertion assertion) {
|
|
|
625 |
this(opcode, 0, op, ext, assertion);
|
|
|
626 |
}
|
|
|
627 |
|
|
|
628 |
protected AMD64MOp(String opcode, int prefix, int op, int ext, OpAssertion assertion) {
|
|
|
629 |
super(opcode, 0, prefix, op, assertion, null);
|
|
|
630 |
this.ext = ext;
|
|
|
631 |
}
|
|
|
632 |
|
|
|
633 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst) {
|
|
|
634 |
assert verify(asm, size, dst, null);
|
|
|
635 |
emitOpcode(asm, size, getRXB(null, dst), 0, dst.encoding);
|
|
|
636 |
asm.emitModRM(ext, dst);
|
|
|
637 |
}
|
|
|
638 |
|
|
|
639 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst) {
|
|
|
640 |
assert verify(asm, size, null, null);
|
|
|
641 |
emitOpcode(asm, size, getRXB(null, dst), 0, 0);
|
|
|
642 |
asm.emitOperandHelper(ext, dst, 0);
|
|
|
643 |
}
|
|
|
644 |
}
|
|
|
645 |
|
|
|
646 |
/**
|
|
|
647 |
* Opcodes with operand order of MI.
|
|
|
648 |
*/
|
|
|
649 |
public static class AMD64MIOp extends AMD64ImmOp {
|
|
|
650 |
// @formatter:off
|
|
|
651 |
public static final AMD64MIOp MOVB = new AMD64MIOp("MOVB", true, 0xC6, 0, OpAssertion.ByteAssertion);
|
|
|
652 |
public static final AMD64MIOp MOV = new AMD64MIOp("MOV", false, 0xC7, 0);
|
|
|
653 |
public static final AMD64MIOp TEST = new AMD64MIOp("TEST", false, 0xF7, 0);
|
|
|
654 |
// @formatter:on
|
|
|
655 |
|
|
|
656 |
private final int ext;
|
|
|
657 |
|
|
|
658 |
protected AMD64MIOp(String opcode, boolean immIsByte, int op, int ext) {
|
|
48190
|
659 |
this(opcode, immIsByte, op, ext, OpAssertion.WordOrLargerAssertion);
|
|
43972
|
660 |
}
|
|
|
661 |
|
|
|
662 |
protected AMD64MIOp(String opcode, boolean immIsByte, int op, int ext, OpAssertion assertion) {
|
|
|
663 |
this(opcode, immIsByte, 0, op, ext, assertion);
|
|
|
664 |
}
|
|
|
665 |
|
|
|
666 |
protected AMD64MIOp(String opcode, boolean immIsByte, int prefix, int op, int ext, OpAssertion assertion) {
|
|
|
667 |
super(opcode, immIsByte, prefix, op, assertion);
|
|
|
668 |
this.ext = ext;
|
|
|
669 |
}
|
|
|
670 |
|
|
|
671 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, int imm) {
|
|
51436
|
672 |
emit(asm, size, dst, imm, false);
|
|
|
673 |
}
|
|
|
674 |
|
|
|
675 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, int imm, boolean annotateImm) {
|
|
43972
|
676 |
assert verify(asm, size, dst, null);
|
|
51436
|
677 |
int insnPos = asm.position();
|
|
43972
|
678 |
emitOpcode(asm, size, getRXB(null, dst), 0, dst.encoding);
|
|
|
679 |
asm.emitModRM(ext, dst);
|
|
51436
|
680 |
int immPos = asm.position();
|
|
43972
|
681 |
emitImmediate(asm, size, imm);
|
|
51436
|
682 |
int nextInsnPos = asm.position();
|
|
|
683 |
if (annotateImm && asm.codePatchingAnnotationConsumer != null) {
|
|
|
684 |
asm.codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
|
|
|
685 |
}
|
|
43972
|
686 |
}
|
|
|
687 |
|
|
|
688 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, int imm) {
|
|
51436
|
689 |
emit(asm, size, dst, imm, false);
|
|
|
690 |
}
|
|
|
691 |
|
|
|
692 |
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, int imm, boolean annotateImm) {
|
|
43972
|
693 |
assert verify(asm, size, null, null);
|
|
51436
|
694 |
int insnPos = asm.position();
|
|
43972
|
695 |
emitOpcode(asm, size, getRXB(null, dst), 0, 0);
|
|
|
696 |
asm.emitOperandHelper(ext, dst, immediateSize(size));
|
|
51436
|
697 |
int immPos = asm.position();
|
|
43972
|
698 |
emitImmediate(asm, size, imm);
|
|
51436
|
699 |
int nextInsnPos = asm.position();
|
|
|
700 |
if (annotateImm && asm.codePatchingAnnotationConsumer != null) {
|
|
|
701 |
asm.codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
|
|
|
702 |
}
|
|
43972
|
703 |
}
|
|
|
704 |
}
|
|
|
705 |
|
|
|
706 |
/**
|
|
|
707 |
* Opcodes with operand order of RMI.
|
|
|
708 |
*
|
|
|
709 |
* We only have one form of round as the operation is always treated with single variant input,
|
|
|
710 |
* making its extension to 3 address forms redundant.
|
|
|
711 |
*/
|
|
|
712 |
public static class AMD64RMIOp extends AMD64ImmOp {
|
|
|
713 |
// @formatter:off
|
|
|
714 |
public static final AMD64RMIOp IMUL = new AMD64RMIOp("IMUL", false, 0x69);
|
|
|
715 |
public static final AMD64RMIOp IMUL_SX = new AMD64RMIOp("IMUL", true, 0x6B);
|
|
51436
|
716 |
public static final AMD64RMIOp ROUNDSS = new AMD64RMIOp("ROUNDSS", true, P_0F3A, 0x0A, OpAssertion.PackedDoubleAssertion, CPUFeature.SSE4_1);
|
|
|
717 |
public static final AMD64RMIOp ROUNDSD = new AMD64RMIOp("ROUNDSD", true, P_0F3A, 0x0B, OpAssertion.PackedDoubleAssertion, CPUFeature.SSE4_1);
|
|
43972
|
718 |
// @formatter:on
|
|
|
719 |
|
|
|
720 |
protected AMD64RMIOp(String opcode, boolean immIsByte, int op) {
|
|
51436
|
721 |
this(opcode, immIsByte, 0, op, OpAssertion.WordOrLargerAssertion, null);
|
|
43972
|
722 |
}
|
|
|
723 |
|
|
51436
|
724 |
protected AMD64RMIOp(String opcode, boolean immIsByte, int prefix, int op, OpAssertion assertion, CPUFeature feature) {
|
|
|
725 |
super(opcode, immIsByte, prefix, op, assertion, feature);
|
|
43972
|
726 |
}
|
|
|
727 |
|
|
|
728 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, Register src, int imm) {
|
|
|
729 |
assert verify(asm, size, dst, src);
|
|
51436
|
730 |
if (isSSEInstruction()) {
|
|
|
731 |
Register nds = Register.None;
|
|
|
732 |
switch (op) {
|
|
|
733 |
case 0x0A:
|
|
|
734 |
case 0x0B:
|
|
|
735 |
nds = dst;
|
|
48861
|
736 |
break;
|
|
|
737 |
default:
|
|
|
738 |
break;
|
|
|
739 |
}
|
|
51436
|
740 |
asm.simdPrefix(dst, nds, src, size, prefix1, prefix2, false);
|
|
43972
|
741 |
asm.emitByte(op);
|
|
51436
|
742 |
asm.emitModRM(dst, src);
|
|
43972
|
743 |
} else {
|
|
|
744 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, src.encoding);
|
|
|
745 |
asm.emitModRM(dst, src);
|
|
|
746 |
}
|
|
51436
|
747 |
emitImmediate(asm, size, imm);
|
|
43972
|
748 |
}
|
|
|
749 |
|
|
|
750 |
public final void emit(AMD64Assembler asm, OperandSize size, Register dst, AMD64Address src, int imm) {
|
|
|
751 |
assert verify(asm, size, dst, null);
|
|
51436
|
752 |
if (isSSEInstruction()) {
|
|
|
753 |
Register nds = Register.None;
|
|
|
754 |
switch (op) {
|
|
|
755 |
case 0x0A:
|
|
|
756 |
case 0x0B:
|
|
|
757 |
nds = dst;
|
|
48861
|
758 |
break;
|
|
|
759 |
default:
|
|
|
760 |
break;
|
|
|
761 |
}
|
|
51436
|
762 |
asm.simdPrefix(dst, nds, src, size, prefix1, prefix2, false);
|
|
43972
|
763 |
asm.emitByte(op);
|
|
|
764 |
} else {
|
|
|
765 |
emitOpcode(asm, size, getRXB(dst, src), dst.encoding, 0);
|
|
|
766 |
}
|
|
51436
|
767 |
asm.emitOperandHelper(dst, src, immediateSize(size));
|
|
|
768 |
emitImmediate(asm, size, imm);
|
|
43972
|
769 |
}
|
|
|
770 |
}
|
|
|
771 |
|
|
|
772 |
public static class SSEOp extends AMD64RMOp {
|
|
|
773 |
// @formatter:off
|
|
48190
|
774 |
public static final SSEOp CVTSI2SS = new SSEOp("CVTSI2SS", 0xF3, P_0F, 0x2A, OpAssertion.IntToFloatAssertion);
|
|
51436
|
775 |
public static final SSEOp CVTSI2SD = new SSEOp("CVTSI2SD", 0xF2, P_0F, 0x2A, OpAssertion.IntToFloatAssertion);
|
|
48190
|
776 |
public static final SSEOp CVTTSS2SI = new SSEOp("CVTTSS2SI", 0xF3, P_0F, 0x2C, OpAssertion.FloatToIntAssertion);
|
|
|
777 |
public static final SSEOp CVTTSD2SI = new SSEOp("CVTTSD2SI", 0xF2, P_0F, 0x2C, OpAssertion.FloatToIntAssertion);
|
|
|
778 |
public static final SSEOp UCOMIS = new SSEOp("UCOMIS", P_0F, 0x2E, OpAssertion.PackedFloatAssertion);
|
|
43972
|
779 |
public static final SSEOp SQRT = new SSEOp("SQRT", P_0F, 0x51);
|
|
48190
|
780 |
public static final SSEOp AND = new SSEOp("AND", P_0F, 0x54, OpAssertion.PackedFloatAssertion);
|
|
|
781 |
public static final SSEOp ANDN = new SSEOp("ANDN", P_0F, 0x55, OpAssertion.PackedFloatAssertion);
|
|
|
782 |
public static final SSEOp OR = new SSEOp("OR", P_0F, 0x56, OpAssertion.PackedFloatAssertion);
|
|
|
783 |
public static final SSEOp XOR = new SSEOp("XOR", P_0F, 0x57, OpAssertion.PackedFloatAssertion);
|
|
43972
|
784 |
public static final SSEOp ADD = new SSEOp("ADD", P_0F, 0x58);
|
|
|
785 |
public static final SSEOp MUL = new SSEOp("MUL", P_0F, 0x59);
|
|
|
786 |
public static final SSEOp CVTSS2SD = new SSEOp("CVTSS2SD", P_0F, 0x5A, OpAssertion.SingleAssertion);
|
|
|
787 |
public static final SSEOp CVTSD2SS = new SSEOp("CVTSD2SS", P_0F, 0x5A, OpAssertion.DoubleAssertion);
|
|
|
788 |
public static final SSEOp SUB = new SSEOp("SUB", P_0F, 0x5C);
|
|
|
789 |
public static final SSEOp MIN = new SSEOp("MIN", P_0F, 0x5D);
|
|
|
790 |
public static final SSEOp DIV = new SSEOp("DIV", P_0F, 0x5E);
|
|
|
791 |
public static final SSEOp MAX = new SSEOp("MAX", P_0F, 0x5F);
|
|
|
792 |
// @formatter:on
|
|
|
793 |
|
|
|
794 |
protected SSEOp(String opcode, int prefix, int op) {
|
|
48190
|
795 |
this(opcode, prefix, op, OpAssertion.FloatAssertion);
|
|
43972
|
796 |
}
|
|
|
797 |
|
|
|
798 |
protected SSEOp(String opcode, int prefix, int op, OpAssertion assertion) {
|
|
|
799 |
this(opcode, 0, prefix, op, assertion);
|
|
|
800 |
}
|
|
|
801 |
|
|
|
802 |
protected SSEOp(String opcode, int mandatoryPrefix, int prefix, int op, OpAssertion assertion) {
|
|
|
803 |
super(opcode, mandatoryPrefix, prefix, op, assertion, CPUFeature.SSE2);
|
|
|
804 |
}
|
|
|
805 |
}
|
|
|
806 |
|
|
|
807 |
/**
|
|
|
808 |
* Arithmetic operation with operand order of RM, MR or MI.
|
|
|
809 |
*/
|
|
|
810 |
public static final class AMD64BinaryArithmetic {
|
|
|
811 |
// @formatter:off
|
|
|
812 |
public static final AMD64BinaryArithmetic ADD = new AMD64BinaryArithmetic("ADD", 0);
|
|
|
813 |
public static final AMD64BinaryArithmetic OR = new AMD64BinaryArithmetic("OR", 1);
|
|
|
814 |
public static final AMD64BinaryArithmetic ADC = new AMD64BinaryArithmetic("ADC", 2);
|
|
|
815 |
public static final AMD64BinaryArithmetic SBB = new AMD64BinaryArithmetic("SBB", 3);
|
|
|
816 |
public static final AMD64BinaryArithmetic AND = new AMD64BinaryArithmetic("AND", 4);
|
|
|
817 |
public static final AMD64BinaryArithmetic SUB = new AMD64BinaryArithmetic("SUB", 5);
|
|
|
818 |
public static final AMD64BinaryArithmetic XOR = new AMD64BinaryArithmetic("XOR", 6);
|
|
|
819 |
public static final AMD64BinaryArithmetic CMP = new AMD64BinaryArithmetic("CMP", 7);
|
|
|
820 |
// @formatter:on
|
|
|
821 |
|
|
|
822 |
private final AMD64MIOp byteImmOp;
|
|
|
823 |
private final AMD64MROp byteMrOp;
|
|
|
824 |
private final AMD64RMOp byteRmOp;
|
|
|
825 |
|
|
|
826 |
private final AMD64MIOp immOp;
|
|
|
827 |
private final AMD64MIOp immSxOp;
|
|
|
828 |
private final AMD64MROp mrOp;
|
|
|
829 |
private final AMD64RMOp rmOp;
|
|
|
830 |
|
|
|
831 |
private AMD64BinaryArithmetic(String opcode, int code) {
|
|
|
832 |
int baseOp = code << 3;
|
|
|
833 |
|
|
|
834 |
byteImmOp = new AMD64MIOp(opcode, true, 0, 0x80, code, OpAssertion.ByteAssertion);
|
|
|
835 |
byteMrOp = new AMD64MROp(opcode, 0, baseOp, OpAssertion.ByteAssertion);
|
|
|
836 |
byteRmOp = new AMD64RMOp(opcode, 0, baseOp | 0x02, OpAssertion.ByteAssertion);
|
|
|
837 |
|
|
48190
|
838 |
immOp = new AMD64MIOp(opcode, false, 0, 0x81, code, OpAssertion.WordOrLargerAssertion);
|
|
|
839 |
immSxOp = new AMD64MIOp(opcode, true, 0, 0x83, code, OpAssertion.WordOrLargerAssertion);
|
|
|
840 |
mrOp = new AMD64MROp(opcode, 0, baseOp | 0x01, OpAssertion.WordOrLargerAssertion);
|
|
|
841 |
rmOp = new AMD64RMOp(opcode, 0, baseOp | 0x03, OpAssertion.WordOrLargerAssertion);
|
|
43972
|
842 |
}
|
|
|
843 |
|
|
|
844 |
public AMD64MIOp getMIOpcode(OperandSize size, boolean sx) {
|
|
|
845 |
if (size == BYTE) {
|
|
|
846 |
return byteImmOp;
|
|
|
847 |
} else if (sx) {
|
|
|
848 |
return immSxOp;
|
|
|
849 |
} else {
|
|
|
850 |
return immOp;
|
|
|
851 |
}
|
|
|
852 |
}
|
|
|
853 |
|
|
|
854 |
public AMD64MROp getMROpcode(OperandSize size) {
|
|
|
855 |
if (size == BYTE) {
|
|
|
856 |
return byteMrOp;
|
|
|
857 |
} else {
|
|
|
858 |
return mrOp;
|
|
|
859 |
}
|
|
|
860 |
}
|
|
|
861 |
|
|
|
862 |
public AMD64RMOp getRMOpcode(OperandSize size) {
|
|
|
863 |
if (size == BYTE) {
|
|
|
864 |
return byteRmOp;
|
|
|
865 |
} else {
|
|
|
866 |
return rmOp;
|
|
|
867 |
}
|
|
|
868 |
}
|
|
|
869 |
}
|
|
|
870 |
|
|
|
871 |
/**
|
|
|
872 |
* Shift operation with operand order of M1, MC or MI.
|
|
|
873 |
*/
|
|
|
874 |
public static final class AMD64Shift {
|
|
|
875 |
// @formatter:off
|
|
|
876 |
public static final AMD64Shift ROL = new AMD64Shift("ROL", 0);
|
|
|
877 |
public static final AMD64Shift ROR = new AMD64Shift("ROR", 1);
|
|
|
878 |
public static final AMD64Shift RCL = new AMD64Shift("RCL", 2);
|
|
|
879 |
public static final AMD64Shift RCR = new AMD64Shift("RCR", 3);
|
|
|
880 |
public static final AMD64Shift SHL = new AMD64Shift("SHL", 4);
|
|
|
881 |
public static final AMD64Shift SHR = new AMD64Shift("SHR", 5);
|
|
|
882 |
public static final AMD64Shift SAR = new AMD64Shift("SAR", 7);
|
|
|
883 |
// @formatter:on
|
|
|
884 |
|
|
|
885 |
public final AMD64MOp m1Op;
|
|
|
886 |
public final AMD64MOp mcOp;
|
|
|
887 |
public final AMD64MIOp miOp;
|
|
|
888 |
|
|
|
889 |
private AMD64Shift(String opcode, int code) {
|
|
48190
|
890 |
m1Op = new AMD64MOp(opcode, 0, 0xD1, code, OpAssertion.WordOrLargerAssertion);
|
|
|
891 |
mcOp = new AMD64MOp(opcode, 0, 0xD3, code, OpAssertion.WordOrLargerAssertion);
|
|
|
892 |
miOp = new AMD64MIOp(opcode, true, 0, 0xC1, code, OpAssertion.WordOrLargerAssertion);
|
|
43972
|
893 |
}
|
|
|
894 |
}
|
|
|
895 |
|
|
51436
|
896 |
private enum AVXOpAssertion {
|
|
|
897 |
AVX1(CPUFeature.AVX, CPUFeature.AVX),
|
|
|
898 |
AVX1_2(CPUFeature.AVX, CPUFeature.AVX2),
|
|
|
899 |
AVX2(CPUFeature.AVX2, CPUFeature.AVX2),
|
|
|
900 |
AVX1_128ONLY(CPUFeature.AVX, null),
|
|
|
901 |
AVX1_256ONLY(null, CPUFeature.AVX),
|
|
|
902 |
AVX2_256ONLY(null, CPUFeature.AVX2),
|
|
|
903 |
XMM_CPU(CPUFeature.AVX, null, XMM, null, CPU, null),
|
|
|
904 |
XMM_XMM_CPU(CPUFeature.AVX, null, XMM, XMM, CPU, null),
|
|
|
905 |
CPU_XMM(CPUFeature.AVX, null, CPU, null, XMM, null),
|
|
|
906 |
AVX1_2_CPU_XMM(CPUFeature.AVX, CPUFeature.AVX2, CPU, null, XMM, null);
|
|
|
907 |
|
|
|
908 |
private final CPUFeature avx128feature;
|
|
|
909 |
private final CPUFeature avx256feature;
|
|
|
910 |
|
|
|
911 |
private final RegisterCategory rCategory;
|
|
|
912 |
private final RegisterCategory vCategory;
|
|
|
913 |
private final RegisterCategory mCategory;
|
|
|
914 |
private final RegisterCategory imm8Category;
|
|
|
915 |
|
|
|
916 |
AVXOpAssertion(CPUFeature avx128feature, CPUFeature avx256feature) {
|
|
|
917 |
this(avx128feature, avx256feature, XMM, XMM, XMM, XMM);
|
|
|
918 |
}
|
|
|
919 |
|
|
|
920 |
AVXOpAssertion(CPUFeature avx128feature, CPUFeature avx256feature, RegisterCategory rCategory, RegisterCategory vCategory, RegisterCategory mCategory, RegisterCategory imm8Category) {
|
|
|
921 |
this.avx128feature = avx128feature;
|
|
|
922 |
this.avx256feature = avx256feature;
|
|
|
923 |
this.rCategory = rCategory;
|
|
|
924 |
this.vCategory = vCategory;
|
|
|
925 |
this.mCategory = mCategory;
|
|
|
926 |
this.imm8Category = imm8Category;
|
|
|
927 |
}
|
|
|
928 |
|
|
|
929 |
public boolean check(AMD64 arch, AVXSize size, Register r, Register v, Register m) {
|
|
|
930 |
return check(arch, size, r, v, m, null);
|
|
|
931 |
}
|
|
|
932 |
|
|
|
933 |
public boolean check(AMD64 arch, AVXSize size, Register r, Register v, Register m, Register imm8) {
|
|
|
934 |
switch (size) {
|
|
|
935 |
case XMM:
|
|
|
936 |
assert avx128feature != null && arch.getFeatures().contains(avx128feature) : "emitting illegal 128 bit instruction";
|
|
|
937 |
break;
|
|
|
938 |
case YMM:
|
|
|
939 |
assert avx256feature != null && arch.getFeatures().contains(avx256feature) : "emitting illegal 256 bit instruction";
|
|
|
940 |
break;
|
|
|
941 |
}
|
|
|
942 |
if (r != null) {
|
|
|
943 |
assert r.getRegisterCategory().equals(rCategory);
|
|
|
944 |
}
|
|
|
945 |
if (v != null) {
|
|
|
946 |
assert v.getRegisterCategory().equals(vCategory);
|
|
|
947 |
}
|
|
|
948 |
if (m != null) {
|
|
|
949 |
assert m.getRegisterCategory().equals(mCategory);
|
|
|
950 |
}
|
|
|
951 |
if (imm8 != null) {
|
|
|
952 |
assert imm8.getRegisterCategory().equals(imm8Category);
|
|
|
953 |
}
|
|
|
954 |
return true;
|
|
|
955 |
}
|
|
|
956 |
|
|
|
957 |
public boolean supports(EnumSet<CPUFeature> features, AVXSize avxSize) {
|
|
|
958 |
switch (avxSize) {
|
|
|
959 |
case XMM:
|
|
|
960 |
return avx128feature != null && features.contains(avx128feature);
|
|
|
961 |
case YMM:
|
|
|
962 |
return avx256feature != null && features.contains(avx256feature);
|
|
|
963 |
default:
|
|
|
964 |
throw GraalError.shouldNotReachHere();
|
|
|
965 |
}
|
|
|
966 |
}
|
|
|
967 |
}
|
|
|
968 |
|
|
|
969 |
/**
|
|
|
970 |
* Base class for VEX-encoded instructions.
|
|
|
971 |
*/
|
|
|
972 |
public static class VexOp {
|
|
|
973 |
protected final int pp;
|
|
|
974 |
protected final int mmmmm;
|
|
|
975 |
protected final int w;
|
|
|
976 |
protected final int op;
|
|
|
977 |
|
|
|
978 |
private final String opcode;
|
|
|
979 |
protected final AVXOpAssertion assertion;
|
|
|
980 |
|
|
|
981 |
protected VexOp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
982 |
this.pp = pp;
|
|
|
983 |
this.mmmmm = mmmmm;
|
|
|
984 |
this.w = w;
|
|
|
985 |
this.op = op;
|
|
|
986 |
this.opcode = opcode;
|
|
|
987 |
this.assertion = assertion;
|
|
|
988 |
}
|
|
|
989 |
|
|
|
990 |
public boolean isSupported(AMD64Assembler vasm, AMD64Kind kind) {
|
|
|
991 |
return assertion.supports(((AMD64) vasm.target.arch).getFeatures(), AVXKind.getRegisterSize(kind));
|
|
|
992 |
}
|
|
|
993 |
|
|
|
994 |
public final boolean isSupported(AMD64Assembler vasm, AVXSize size) {
|
|
|
995 |
return assertion.supports(((AMD64) vasm.target.arch).getFeatures(), size);
|
|
|
996 |
}
|
|
|
997 |
|
|
|
998 |
@Override
|
|
|
999 |
public String toString() {
|
|
|
1000 |
return opcode;
|
|
|
1001 |
}
|
|
|
1002 |
}
|
|
|
1003 |
|
|
|
1004 |
/**
|
|
|
1005 |
* VEX-encoded instructions with an operand order of RM, but the M operand must be a register.
|
|
|
1006 |
*/
|
|
|
1007 |
public static class VexRROp extends VexOp {
|
|
|
1008 |
// @formatter:off
|
|
|
1009 |
public static final VexRROp VMASKMOVDQU = new VexRROp("VMASKMOVDQU", P_66, M_0F, WIG, 0xF7, AVXOpAssertion.AVX1_128ONLY);
|
|
|
1010 |
// @formatter:on
|
|
|
1011 |
|
|
|
1012 |
protected VexRROp(String opcode, int pp, int mmmmm, int w, int op) {
|
|
|
1013 |
this(opcode, pp, mmmmm, w, op, AVXOpAssertion.AVX1);
|
|
|
1014 |
}
|
|
|
1015 |
|
|
|
1016 |
protected VexRROp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1017 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1018 |
}
|
|
|
1019 |
|
|
|
1020 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src) {
|
|
|
1021 |
assert assertion.check((AMD64) asm.target.arch, size, dst, null, src);
|
|
|
1022 |
assert op != 0x1A || op != 0x5A;
|
|
|
1023 |
asm.vexPrefix(dst, Register.None, src, size, pp, mmmmm, w);
|
|
|
1024 |
asm.emitByte(op);
|
|
|
1025 |
asm.emitModRM(dst, src);
|
|
|
1026 |
}
|
|
|
1027 |
}
|
|
|
1028 |
|
|
|
1029 |
/**
|
|
|
1030 |
* VEX-encoded instructions with an operand order of RM.
|
|
|
1031 |
*/
|
|
|
1032 |
public static class VexRMOp extends VexRROp {
|
|
|
1033 |
// @formatter:off
|
|
|
1034 |
public static final VexRMOp VCVTTSS2SI = new VexRMOp("VCVTTSS2SI", P_F3, M_0F, W0, 0x2C, AVXOpAssertion.CPU_XMM);
|
|
|
1035 |
public static final VexRMOp VCVTTSS2SQ = new VexRMOp("VCVTTSS2SQ", P_F3, M_0F, W1, 0x2C, AVXOpAssertion.CPU_XMM);
|
|
|
1036 |
public static final VexRMOp VCVTTSD2SI = new VexRMOp("VCVTTSD2SI", P_F2, M_0F, W0, 0x2C, AVXOpAssertion.CPU_XMM);
|
|
|
1037 |
public static final VexRMOp VCVTTSD2SQ = new VexRMOp("VCVTTSD2SQ", P_F2, M_0F, W1, 0x2C, AVXOpAssertion.CPU_XMM);
|
|
|
1038 |
public static final VexRMOp VCVTPS2PD = new VexRMOp("VCVTPS2PD", P_, M_0F, WIG, 0x5A);
|
|
|
1039 |
public static final VexRMOp VCVTPD2PS = new VexRMOp("VCVTPD2PS", P_66, M_0F, WIG, 0x5A);
|
|
|
1040 |
public static final VexRMOp VCVTDQ2PS = new VexRMOp("VCVTDQ2PS", P_, M_0F, WIG, 0x5B);
|
|
|
1041 |
public static final VexRMOp VCVTTPS2DQ = new VexRMOp("VCVTTPS2DQ", P_F3, M_0F, WIG, 0x5B);
|
|
|
1042 |
public static final VexRMOp VCVTTPD2DQ = new VexRMOp("VCVTTPD2DQ", P_66, M_0F, WIG, 0xE6);
|
|
|
1043 |
public static final VexRMOp VCVTDQ2PD = new VexRMOp("VCVTDQ2PD", P_F3, M_0F, WIG, 0xE6);
|
|
|
1044 |
public static final VexRMOp VBROADCASTSS = new VexRMOp("VBROADCASTSS", P_66, M_0F38, W0, 0x18);
|
|
|
1045 |
public static final VexRMOp VBROADCASTSD = new VexRMOp("VBROADCASTSD", P_66, M_0F38, W0, 0x19, AVXOpAssertion.AVX1_256ONLY);
|
|
|
1046 |
public static final VexRMOp VBROADCASTF128 = new VexRMOp("VBROADCASTF128", P_66, M_0F38, W0, 0x1A, AVXOpAssertion.AVX1_256ONLY);
|
|
|
1047 |
public static final VexRMOp VPBROADCASTI128 = new VexRMOp("VPBROADCASTI128", P_66, M_0F38, W0, 0x5A, AVXOpAssertion.AVX2_256ONLY);
|
|
|
1048 |
public static final VexRMOp VPBROADCASTB = new VexRMOp("VPBROADCASTB", P_66, M_0F38, W0, 0x78, AVXOpAssertion.AVX2);
|
|
|
1049 |
public static final VexRMOp VPBROADCASTW = new VexRMOp("VPBROADCASTW", P_66, M_0F38, W0, 0x79, AVXOpAssertion.AVX2);
|
|
|
1050 |
public static final VexRMOp VPBROADCASTD = new VexRMOp("VPBROADCASTD", P_66, M_0F38, W0, 0x58, AVXOpAssertion.AVX2);
|
|
|
1051 |
public static final VexRMOp VPBROADCASTQ = new VexRMOp("VPBROADCASTQ", P_66, M_0F38, W0, 0x59, AVXOpAssertion.AVX2);
|
|
|
1052 |
public static final VexRMOp VPMOVMSKB = new VexRMOp("VPMOVMSKB", P_66, M_0F, WIG, 0xD7, AVXOpAssertion.AVX1_2_CPU_XMM);
|
|
|
1053 |
public static final VexRMOp VPMOVSXBW = new VexRMOp("VPMOVSXBW", P_66, M_0F38, WIG, 0x20);
|
|
|
1054 |
public static final VexRMOp VPMOVSXBD = new VexRMOp("VPMOVSXBD", P_66, M_0F38, WIG, 0x21);
|
|
|
1055 |
public static final VexRMOp VPMOVSXBQ = new VexRMOp("VPMOVSXBQ", P_66, M_0F38, WIG, 0x22);
|
|
|
1056 |
public static final VexRMOp VPMOVSXWD = new VexRMOp("VPMOVSXWD", P_66, M_0F38, WIG, 0x23);
|
|
|
1057 |
public static final VexRMOp VPMOVSXWQ = new VexRMOp("VPMOVSXWQ", P_66, M_0F38, WIG, 0x24);
|
|
|
1058 |
public static final VexRMOp VPMOVSXDQ = new VexRMOp("VPMOVSXDQ", P_66, M_0F38, WIG, 0x25);
|
|
|
1059 |
public static final VexRMOp VPMOVZXBW = new VexRMOp("VPMOVZXBW", P_66, M_0F38, WIG, 0x30);
|
|
|
1060 |
public static final VexRMOp VPMOVZXBD = new VexRMOp("VPMOVZXBD", P_66, M_0F38, WIG, 0x31);
|
|
|
1061 |
public static final VexRMOp VPMOVZXBQ = new VexRMOp("VPMOVZXBQ", P_66, M_0F38, WIG, 0x32);
|
|
|
1062 |
public static final VexRMOp VPMOVZXWD = new VexRMOp("VPMOVZXWD", P_66, M_0F38, WIG, 0x33);
|
|
|
1063 |
public static final VexRMOp VPMOVZXWQ = new VexRMOp("VPMOVZXWQ", P_66, M_0F38, WIG, 0x34);
|
|
|
1064 |
public static final VexRMOp VPMOVZXDQ = new VexRMOp("VPMOVZXDQ", P_66, M_0F38, WIG, 0x35);
|
|
|
1065 |
public static final VexRMOp VPTEST = new VexRMOp("VPTEST", P_66, M_0F38, WIG, 0x17);
|
|
|
1066 |
public static final VexRMOp VSQRTPD = new VexRMOp("VSQRTPD", P_66, M_0F, WIG, 0x51);
|
|
|
1067 |
public static final VexRMOp VSQRTPS = new VexRMOp("VSQRTPS", P_, M_0F, WIG, 0x51);
|
|
|
1068 |
public static final VexRMOp VSQRTSD = new VexRMOp("VSQRTSD", P_F2, M_0F, WIG, 0x51);
|
|
|
1069 |
public static final VexRMOp VSQRTSS = new VexRMOp("VSQRTSS", P_F3, M_0F, WIG, 0x51);
|
|
|
1070 |
public static final VexRMOp VUCOMISS = new VexRMOp("VUCOMISS", P_, M_0F, WIG, 0x2E);
|
|
|
1071 |
public static final VexRMOp VUCOMISD = new VexRMOp("VUCOMISD", P_66, M_0F, WIG, 0x2E);
|
|
|
1072 |
// @formatter:on
|
|
|
1073 |
|
|
|
1074 |
protected VexRMOp(String opcode, int pp, int mmmmm, int w, int op) {
|
|
|
1075 |
this(opcode, pp, mmmmm, w, op, AVXOpAssertion.AVX1);
|
|
|
1076 |
}
|
|
|
1077 |
|
|
|
1078 |
protected VexRMOp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1079 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1080 |
}
|
|
|
1081 |
|
|
|
1082 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, AMD64Address src) {
|
|
|
1083 |
assert assertion.check((AMD64) asm.target.arch, size, dst, null, null);
|
|
|
1084 |
asm.vexPrefix(dst, Register.None, src, size, pp, mmmmm, w);
|
|
|
1085 |
asm.emitByte(op);
|
|
|
1086 |
asm.emitOperandHelper(dst, src, 0);
|
|
|
1087 |
}
|
|
|
1088 |
}
|
|
|
1089 |
|
|
|
1090 |
/**
|
|
|
1091 |
* VEX-encoded move instructions.
|
|
|
1092 |
* <p>
|
|
|
1093 |
* These instructions have two opcodes: op is the forward move instruction with an operand order
|
|
|
1094 |
* of RM, and opReverse is the reverse move instruction with an operand order of MR.
|
|
|
1095 |
*/
|
|
|
1096 |
public static final class VexMoveOp extends VexRMOp {
|
|
|
1097 |
// @formatter:off
|
|
|
1098 |
public static final VexMoveOp VMOVDQA = new VexMoveOp("VMOVDQA", P_66, M_0F, WIG, 0x6F, 0x7F);
|
|
|
1099 |
public static final VexMoveOp VMOVDQU = new VexMoveOp("VMOVDQU", P_F3, M_0F, WIG, 0x6F, 0x7F);
|
|
|
1100 |
public static final VexMoveOp VMOVAPS = new VexMoveOp("VMOVAPS", P_, M_0F, WIG, 0x28, 0x29);
|
|
|
1101 |
public static final VexMoveOp VMOVAPD = new VexMoveOp("VMOVAPD", P_66, M_0F, WIG, 0x28, 0x29);
|
|
|
1102 |
public static final VexMoveOp VMOVUPS = new VexMoveOp("VMOVUPS", P_, M_0F, WIG, 0x10, 0x11);
|
|
|
1103 |
public static final VexMoveOp VMOVUPD = new VexMoveOp("VMOVUPD", P_66, M_0F, WIG, 0x10, 0x11);
|
|
|
1104 |
public static final VexMoveOp VMOVSS = new VexMoveOp("VMOVSS", P_F3, M_0F, WIG, 0x10, 0x11);
|
|
|
1105 |
public static final VexMoveOp VMOVSD = new VexMoveOp("VMOVSD", P_F2, M_0F, WIG, 0x10, 0x11);
|
|
|
1106 |
public static final VexMoveOp VMOVD = new VexMoveOp("VMOVD", P_66, M_0F, W0, 0x6E, 0x7E, AVXOpAssertion.XMM_CPU);
|
|
|
1107 |
public static final VexMoveOp VMOVQ = new VexMoveOp("VMOVQ", P_66, M_0F, W1, 0x6E, 0x7E, AVXOpAssertion.XMM_CPU);
|
|
|
1108 |
// @formatter:on
|
|
|
1109 |
|
|
|
1110 |
private final int opReverse;
|
|
|
1111 |
|
|
|
1112 |
private VexMoveOp(String opcode, int pp, int mmmmm, int w, int op, int opReverse) {
|
|
|
1113 |
this(opcode, pp, mmmmm, w, op, opReverse, AVXOpAssertion.AVX1);
|
|
|
1114 |
}
|
|
|
1115 |
|
|
|
1116 |
private VexMoveOp(String opcode, int pp, int mmmmm, int w, int op, int opReverse, AVXOpAssertion assertion) {
|
|
|
1117 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1118 |
this.opReverse = opReverse;
|
|
|
1119 |
}
|
|
|
1120 |
|
|
|
1121 |
public void emit(AMD64Assembler asm, AVXSize size, AMD64Address dst, Register src) {
|
|
|
1122 |
assert assertion.check((AMD64) asm.target.arch, size, src, null, null);
|
|
|
1123 |
asm.vexPrefix(src, Register.None, dst, size, pp, mmmmm, w);
|
|
|
1124 |
asm.emitByte(opReverse);
|
|
|
1125 |
asm.emitOperandHelper(src, dst, 0);
|
|
|
1126 |
}
|
|
|
1127 |
|
|
|
1128 |
public void emitReverse(AMD64Assembler asm, AVXSize size, Register dst, Register src) {
|
|
|
1129 |
assert assertion.check((AMD64) asm.target.arch, size, src, null, dst);
|
|
|
1130 |
asm.vexPrefix(src, Register.None, dst, size, pp, mmmmm, w);
|
|
|
1131 |
asm.emitByte(opReverse);
|
|
|
1132 |
asm.emitModRM(src, dst);
|
|
|
1133 |
}
|
|
|
1134 |
}
|
|
|
1135 |
|
|
|
1136 |
public interface VexRRIOp {
|
|
|
1137 |
void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, int imm8);
|
|
|
1138 |
}
|
|
|
1139 |
|
|
|
1140 |
/**
|
|
|
1141 |
* VEX-encoded instructions with an operand order of RMI.
|
|
|
1142 |
*/
|
|
|
1143 |
public static final class VexRMIOp extends VexOp implements VexRRIOp {
|
|
|
1144 |
// @formatter:off
|
|
|
1145 |
public static final VexRMIOp VPERMQ = new VexRMIOp("VPERMQ", P_66, M_0F3A, W1, 0x00, AVXOpAssertion.AVX2_256ONLY);
|
|
|
1146 |
public static final VexRMIOp VPSHUFLW = new VexRMIOp("VPSHUFLW", P_F2, M_0F, WIG, 0x70, AVXOpAssertion.AVX1_2);
|
|
|
1147 |
public static final VexRMIOp VPSHUFHW = new VexRMIOp("VPSHUFHW", P_F3, M_0F, WIG, 0x70, AVXOpAssertion.AVX1_2);
|
|
|
1148 |
public static final VexRMIOp VPSHUFD = new VexRMIOp("VPSHUFD", P_66, M_0F, WIG, 0x70, AVXOpAssertion.AVX1_2);
|
|
|
1149 |
// @formatter:on
|
|
|
1150 |
|
|
|
1151 |
private VexRMIOp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1152 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1153 |
}
|
|
|
1154 |
|
|
|
1155 |
@Override
|
|
|
1156 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, int imm8) {
|
|
|
1157 |
assert assertion.check((AMD64) asm.target.arch, size, dst, null, src);
|
|
|
1158 |
asm.vexPrefix(dst, Register.None, src, size, pp, mmmmm, w);
|
|
|
1159 |
asm.emitByte(op);
|
|
|
1160 |
asm.emitModRM(dst, src);
|
|
|
1161 |
asm.emitByte(imm8);
|
|
|
1162 |
}
|
|
|
1163 |
|
|
|
1164 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, AMD64Address src, int imm8) {
|
|
|
1165 |
assert assertion.check((AMD64) asm.target.arch, size, dst, null, null);
|
|
|
1166 |
asm.vexPrefix(dst, Register.None, src, size, pp, mmmmm, w);
|
|
|
1167 |
asm.emitByte(op);
|
|
|
1168 |
asm.emitOperandHelper(dst, src, 1);
|
|
|
1169 |
asm.emitByte(imm8);
|
|
|
1170 |
}
|
|
|
1171 |
}
|
|
|
1172 |
|
|
|
1173 |
/**
|
|
|
1174 |
* VEX-encoded instructions with an operand order of MRI.
|
|
|
1175 |
*/
|
|
|
1176 |
public static final class VexMRIOp extends VexOp implements VexRRIOp {
|
|
|
1177 |
// @formatter:off
|
|
|
1178 |
public static final VexMRIOp VEXTRACTF128 = new VexMRIOp("VEXTRACTF128", P_66, M_0F3A, W0, 0x19, AVXOpAssertion.AVX1_256ONLY);
|
|
|
1179 |
public static final VexMRIOp VEXTRACTI128 = new VexMRIOp("VEXTRACTI128", P_66, M_0F3A, W0, 0x39, AVXOpAssertion.AVX2_256ONLY);
|
|
|
1180 |
public static final VexMRIOp VPEXTRB = new VexMRIOp("VPEXTRB", P_66, M_0F3A, W0, 0x14, AVXOpAssertion.XMM_CPU);
|
|
|
1181 |
public static final VexMRIOp VPEXTRW = new VexMRIOp("VPEXTRW", P_66, M_0F3A, W0, 0x15, AVXOpAssertion.XMM_CPU);
|
|
|
1182 |
public static final VexMRIOp VPEXTRD = new VexMRIOp("VPEXTRD", P_66, M_0F3A, W0, 0x16, AVXOpAssertion.XMM_CPU);
|
|
|
1183 |
public static final VexMRIOp VPEXTRQ = new VexMRIOp("VPEXTRQ", P_66, M_0F3A, W1, 0x16, AVXOpAssertion.XMM_CPU);
|
|
|
1184 |
// @formatter:on
|
|
|
1185 |
|
|
|
1186 |
private VexMRIOp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1187 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1188 |
}
|
|
|
1189 |
|
|
|
1190 |
@Override
|
|
|
1191 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, int imm8) {
|
|
|
1192 |
assert assertion.check((AMD64) asm.target.arch, size, src, null, dst);
|
|
|
1193 |
asm.vexPrefix(src, Register.None, dst, size, pp, mmmmm, w);
|
|
|
1194 |
asm.emitByte(op);
|
|
|
1195 |
asm.emitModRM(src, dst);
|
|
|
1196 |
asm.emitByte(imm8);
|
|
|
1197 |
}
|
|
|
1198 |
|
|
|
1199 |
public void emit(AMD64Assembler asm, AVXSize size, AMD64Address dst, Register src, int imm8) {
|
|
|
1200 |
assert assertion.check((AMD64) asm.target.arch, size, src, null, null);
|
|
|
1201 |
asm.vexPrefix(src, Register.None, dst, size, pp, mmmmm, w);
|
|
|
1202 |
asm.emitByte(op);
|
|
|
1203 |
asm.emitOperandHelper(src, dst, 1);
|
|
|
1204 |
asm.emitByte(imm8);
|
|
|
1205 |
}
|
|
|
1206 |
}
|
|
|
1207 |
|
|
|
1208 |
/**
|
|
|
1209 |
* VEX-encoded instructions with an operand order of RVMR.
|
|
|
1210 |
*/
|
|
|
1211 |
public static class VexRVMROp extends VexOp {
|
|
|
1212 |
// @formatter:off
|
|
|
1213 |
public static final VexRVMROp VPBLENDVB = new VexRVMROp("VPBLENDVB", P_66, M_0F3A, W0, 0x4C, AVXOpAssertion.AVX1_2);
|
|
|
1214 |
public static final VexRVMROp VPBLENDVPS = new VexRVMROp("VPBLENDVPS", P_66, M_0F3A, W0, 0x4A, AVXOpAssertion.AVX1);
|
|
|
1215 |
public static final VexRVMROp VPBLENDVPD = new VexRVMROp("VPBLENDVPD", P_66, M_0F3A, W0, 0x4B, AVXOpAssertion.AVX1);
|
|
|
1216 |
// @formatter:on
|
|
|
1217 |
|
|
|
1218 |
protected VexRVMROp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1219 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1220 |
}
|
|
|
1221 |
|
|
|
1222 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register mask, Register src1, Register src2) {
|
|
|
1223 |
assert assertion.check((AMD64) asm.target.arch, size, dst, mask, src1, src2);
|
|
|
1224 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1225 |
asm.emitByte(op);
|
|
|
1226 |
asm.emitModRM(dst, src2);
|
|
|
1227 |
asm.emitByte(mask.encoding() << 4);
|
|
|
1228 |
}
|
|
|
1229 |
|
|
|
1230 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register mask, Register src1, AMD64Address src2) {
|
|
|
1231 |
assert assertion.check((AMD64) asm.target.arch, size, dst, mask, src1, null);
|
|
|
1232 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1233 |
asm.emitByte(op);
|
|
|
1234 |
asm.emitOperandHelper(dst, src2, 0);
|
|
|
1235 |
asm.emitByte(mask.encoding() << 4);
|
|
|
1236 |
}
|
|
|
1237 |
}
|
|
|
1238 |
|
|
|
1239 |
/**
|
|
|
1240 |
* VEX-encoded instructions with an operand order of RVM.
|
|
|
1241 |
*/
|
|
|
1242 |
public static class VexRVMOp extends VexOp {
|
|
|
1243 |
// @formatter:off
|
|
|
1244 |
public static final VexRVMOp VANDPS = new VexRVMOp("VANDPS", P_, M_0F, WIG, 0x54);
|
|
|
1245 |
public static final VexRVMOp VANDPD = new VexRVMOp("VANDPD", P_66, M_0F, WIG, 0x54);
|
|
|
1246 |
public static final VexRVMOp VANDNPS = new VexRVMOp("VANDNPS", P_, M_0F, WIG, 0x55);
|
|
|
1247 |
public static final VexRVMOp VANDNPD = new VexRVMOp("VANDNPD", P_66, M_0F, WIG, 0x55);
|
|
|
1248 |
public static final VexRVMOp VORPS = new VexRVMOp("VORPS", P_, M_0F, WIG, 0x56);
|
|
|
1249 |
public static final VexRVMOp VORPD = new VexRVMOp("VORPD", P_66, M_0F, WIG, 0x56);
|
|
|
1250 |
public static final VexRVMOp VXORPS = new VexRVMOp("VXORPS", P_, M_0F, WIG, 0x57);
|
|
|
1251 |
public static final VexRVMOp VXORPD = new VexRVMOp("VXORPD", P_66, M_0F, WIG, 0x57);
|
|
|
1252 |
public static final VexRVMOp VADDPS = new VexRVMOp("VADDPS", P_, M_0F, WIG, 0x58);
|
|
|
1253 |
public static final VexRVMOp VADDPD = new VexRVMOp("VADDPD", P_66, M_0F, WIG, 0x58);
|
|
|
1254 |
public static final VexRVMOp VADDSS = new VexRVMOp("VADDSS", P_F3, M_0F, WIG, 0x58);
|
|
|
1255 |
public static final VexRVMOp VADDSD = new VexRVMOp("VADDSD", P_F2, M_0F, WIG, 0x58);
|
|
|
1256 |
public static final VexRVMOp VMULPS = new VexRVMOp("VMULPS", P_, M_0F, WIG, 0x59);
|
|
|
1257 |
public static final VexRVMOp VMULPD = new VexRVMOp("VMULPD", P_66, M_0F, WIG, 0x59);
|
|
|
1258 |
public static final VexRVMOp VMULSS = new VexRVMOp("VMULSS", P_F3, M_0F, WIG, 0x59);
|
|
|
1259 |
public static final VexRVMOp VMULSD = new VexRVMOp("VMULSD", P_F2, M_0F, WIG, 0x59);
|
|
|
1260 |
public static final VexRVMOp VSUBPS = new VexRVMOp("VSUBPS", P_, M_0F, WIG, 0x5C);
|
|
|
1261 |
public static final VexRVMOp VSUBPD = new VexRVMOp("VSUBPD", P_66, M_0F, WIG, 0x5C);
|
|
|
1262 |
public static final VexRVMOp VSUBSS = new VexRVMOp("VSUBSS", P_F3, M_0F, WIG, 0x5C);
|
|
|
1263 |
public static final VexRVMOp VSUBSD = new VexRVMOp("VSUBSD", P_F2, M_0F, WIG, 0x5C);
|
|
|
1264 |
public static final VexRVMOp VMINPS = new VexRVMOp("VMINPS", P_, M_0F, WIG, 0x5D);
|
|
|
1265 |
public static final VexRVMOp VMINPD = new VexRVMOp("VMINPD", P_66, M_0F, WIG, 0x5D);
|
|
|
1266 |
public static final VexRVMOp VMINSS = new VexRVMOp("VMINSS", P_F3, M_0F, WIG, 0x5D);
|
|
|
1267 |
public static final VexRVMOp VMINSD = new VexRVMOp("VMINSD", P_F2, M_0F, WIG, 0x5D);
|
|
|
1268 |
public static final VexRVMOp VDIVPS = new VexRVMOp("VDIVPS", P_, M_0F, WIG, 0x5E);
|
|
|
1269 |
public static final VexRVMOp VDIVPD = new VexRVMOp("VDIVPD", P_66, M_0F, WIG, 0x5E);
|
|
|
1270 |
public static final VexRVMOp VDIVSS = new VexRVMOp("VDIVPS", P_F3, M_0F, WIG, 0x5E);
|
|
|
1271 |
public static final VexRVMOp VDIVSD = new VexRVMOp("VDIVPD", P_F2, M_0F, WIG, 0x5E);
|
|
|
1272 |
public static final VexRVMOp VMAXPS = new VexRVMOp("VMAXPS", P_, M_0F, WIG, 0x5F);
|
|
|
1273 |
public static final VexRVMOp VMAXPD = new VexRVMOp("VMAXPD", P_66, M_0F, WIG, 0x5F);
|
|
|
1274 |
public static final VexRVMOp VMAXSS = new VexRVMOp("VMAXSS", P_F3, M_0F, WIG, 0x5F);
|
|
|
1275 |
public static final VexRVMOp VMAXSD = new VexRVMOp("VMAXSD", P_F2, M_0F, WIG, 0x5F);
|
|
|
1276 |
public static final VexRVMOp VADDSUBPS = new VexRVMOp("VADDSUBPS", P_F2, M_0F, WIG, 0xD0);
|
|
|
1277 |
public static final VexRVMOp VADDSUBPD = new VexRVMOp("VADDSUBPD", P_66, M_0F, WIG, 0xD0);
|
|
|
1278 |
public static final VexRVMOp VPAND = new VexRVMOp("VPAND", P_66, M_0F, WIG, 0xDB, AVXOpAssertion.AVX1_2);
|
|
|
1279 |
public static final VexRVMOp VPOR = new VexRVMOp("VPOR", P_66, M_0F, WIG, 0xEB, AVXOpAssertion.AVX1_2);
|
|
|
1280 |
public static final VexRVMOp VPXOR = new VexRVMOp("VPXOR", P_66, M_0F, WIG, 0xEF, AVXOpAssertion.AVX1_2);
|
|
|
1281 |
public static final VexRVMOp VPADDB = new VexRVMOp("VPADDB", P_66, M_0F, WIG, 0xFC, AVXOpAssertion.AVX1_2);
|
|
|
1282 |
public static final VexRVMOp VPADDW = new VexRVMOp("VPADDW", P_66, M_0F, WIG, 0xFD, AVXOpAssertion.AVX1_2);
|
|
|
1283 |
public static final VexRVMOp VPADDD = new VexRVMOp("VPADDD", P_66, M_0F, WIG, 0xFE, AVXOpAssertion.AVX1_2);
|
|
|
1284 |
public static final VexRVMOp VPADDQ = new VexRVMOp("VPADDQ", P_66, M_0F, WIG, 0xD4, AVXOpAssertion.AVX1_2);
|
|
|
1285 |
public static final VexRVMOp VPMULHUW = new VexRVMOp("VPMULHUW", P_66, M_0F, WIG, 0xE4, AVXOpAssertion.AVX1_2);
|
|
|
1286 |
public static final VexRVMOp VPMULHW = new VexRVMOp("VPMULHW", P_66, M_0F, WIG, 0xE5, AVXOpAssertion.AVX1_2);
|
|
|
1287 |
public static final VexRVMOp VPMULLW = new VexRVMOp("VPMULLW", P_66, M_0F, WIG, 0xD5, AVXOpAssertion.AVX1_2);
|
|
|
1288 |
public static final VexRVMOp VPMULLD = new VexRVMOp("VPMULLD", P_66, M_0F38, WIG, 0x40, AVXOpAssertion.AVX1_2);
|
|
|
1289 |
public static final VexRVMOp VPSUBB = new VexRVMOp("VPSUBB", P_66, M_0F, WIG, 0xF8, AVXOpAssertion.AVX1_2);
|
|
|
1290 |
public static final VexRVMOp VPSUBW = new VexRVMOp("VPSUBW", P_66, M_0F, WIG, 0xF9, AVXOpAssertion.AVX1_2);
|
|
|
1291 |
public static final VexRVMOp VPSUBD = new VexRVMOp("VPSUBD", P_66, M_0F, WIG, 0xFA, AVXOpAssertion.AVX1_2);
|
|
|
1292 |
public static final VexRVMOp VPSUBQ = new VexRVMOp("VPSUBQ", P_66, M_0F, WIG, 0xFB, AVXOpAssertion.AVX1_2);
|
|
|
1293 |
public static final VexRVMOp VPSHUFB = new VexRVMOp("VPSHUFB", P_66, M_0F38, WIG, 0x00, AVXOpAssertion.AVX1_2);
|
|
|
1294 |
public static final VexRVMOp VCVTSD2SS = new VexRVMOp("VCVTSD2SS", P_F2, M_0F, WIG, 0x5A);
|
|
|
1295 |
public static final VexRVMOp VCVTSS2SD = new VexRVMOp("VCVTSS2SD", P_F3, M_0F, WIG, 0x5A);
|
|
|
1296 |
public static final VexRVMOp VCVTSI2SD = new VexRVMOp("VCVTSI2SD", P_F2, M_0F, W0, 0x2A, AVXOpAssertion.XMM_XMM_CPU);
|
|
|
1297 |
public static final VexRVMOp VCVTSQ2SD = new VexRVMOp("VCVTSQ2SD", P_F2, M_0F, W1, 0x2A, AVXOpAssertion.XMM_XMM_CPU);
|
|
|
1298 |
public static final VexRVMOp VCVTSI2SS = new VexRVMOp("VCVTSI2SS", P_F3, M_0F, W0, 0x2A, AVXOpAssertion.XMM_XMM_CPU);
|
|
|
1299 |
public static final VexRVMOp VCVTSQ2SS = new VexRVMOp("VCVTSQ2SS", P_F3, M_0F, W1, 0x2A, AVXOpAssertion.XMM_XMM_CPU);
|
|
|
1300 |
public static final VexRVMOp VPCMPEQB = new VexRVMOp("VPCMPEQB", P_66, M_0F, WIG, 0x74, AVXOpAssertion.AVX1_2);
|
|
|
1301 |
public static final VexRVMOp VPCMPEQW = new VexRVMOp("VPCMPEQW", P_66, M_0F, WIG, 0x75, AVXOpAssertion.AVX1_2);
|
|
|
1302 |
public static final VexRVMOp VPCMPEQD = new VexRVMOp("VPCMPEQD", P_66, M_0F, WIG, 0x76, AVXOpAssertion.AVX1_2);
|
|
|
1303 |
public static final VexRVMOp VPCMPEQQ = new VexRVMOp("VPCMPEQQ", P_66, M_0F38, WIG, 0x29, AVXOpAssertion.AVX1_2);
|
|
|
1304 |
public static final VexRVMOp VPCMPGTB = new VexRVMOp("VPCMPGTB", P_66, M_0F, WIG, 0x64, AVXOpAssertion.AVX1_2);
|
|
|
1305 |
public static final VexRVMOp VPCMPGTW = new VexRVMOp("VPCMPGTW", P_66, M_0F, WIG, 0x65, AVXOpAssertion.AVX1_2);
|
|
|
1306 |
public static final VexRVMOp VPCMPGTD = new VexRVMOp("VPCMPGTD", P_66, M_0F, WIG, 0x66, AVXOpAssertion.AVX1_2);
|
|
|
1307 |
public static final VexRVMOp VPCMPGTQ = new VexRVMOp("VPCMPGTQ", P_66, M_0F38, WIG, 0x37, AVXOpAssertion.AVX1_2);
|
|
|
1308 |
// @formatter:on
|
|
|
1309 |
|
|
|
1310 |
private VexRVMOp(String opcode, int pp, int mmmmm, int w, int op) {
|
|
|
1311 |
this(opcode, pp, mmmmm, w, op, AVXOpAssertion.AVX1);
|
|
|
1312 |
}
|
|
|
1313 |
|
|
|
1314 |
protected VexRVMOp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1315 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1316 |
}
|
|
|
1317 |
|
|
|
1318 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src1, Register src2) {
|
|
|
1319 |
assert assertion.check((AMD64) asm.target.arch, size, dst, src1, src2);
|
|
|
1320 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1321 |
asm.emitByte(op);
|
|
|
1322 |
asm.emitModRM(dst, src2);
|
|
|
1323 |
}
|
|
|
1324 |
|
|
|
1325 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src1, AMD64Address src2) {
|
|
|
1326 |
assert assertion.check((AMD64) asm.target.arch, size, dst, src1, null);
|
|
|
1327 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1328 |
asm.emitByte(op);
|
|
|
1329 |
asm.emitOperandHelper(dst, src2, 0);
|
|
|
1330 |
}
|
|
|
1331 |
}
|
|
|
1332 |
|
|
|
1333 |
/**
|
|
|
1334 |
* VEX-encoded shift instructions with an operand order of either RVM or VMI.
|
|
|
1335 |
*/
|
|
|
1336 |
public static final class VexShiftOp extends VexRVMOp implements VexRRIOp {
|
|
|
1337 |
// @formatter:off
|
|
|
1338 |
public static final VexShiftOp VPSRLW = new VexShiftOp("VPSRLW", P_66, M_0F, WIG, 0xD1, 0x71, 2);
|
|
|
1339 |
public static final VexShiftOp VPSRLD = new VexShiftOp("VPSRLD", P_66, M_0F, WIG, 0xD2, 0x72, 2);
|
|
|
1340 |
public static final VexShiftOp VPSRLQ = new VexShiftOp("VPSRLQ", P_66, M_0F, WIG, 0xD3, 0x73, 2);
|
|
|
1341 |
public static final VexShiftOp VPSRAW = new VexShiftOp("VPSRAW", P_66, M_0F, WIG, 0xE1, 0x71, 4);
|
|
|
1342 |
public static final VexShiftOp VPSRAD = new VexShiftOp("VPSRAD", P_66, M_0F, WIG, 0xE2, 0x72, 4);
|
|
|
1343 |
public static final VexShiftOp VPSLLW = new VexShiftOp("VPSLLW", P_66, M_0F, WIG, 0xF1, 0x71, 6);
|
|
|
1344 |
public static final VexShiftOp VPSLLD = new VexShiftOp("VPSLLD", P_66, M_0F, WIG, 0xF2, 0x72, 6);
|
|
|
1345 |
public static final VexShiftOp VPSLLQ = new VexShiftOp("VPSLLQ", P_66, M_0F, WIG, 0xF3, 0x73, 6);
|
|
|
1346 |
// @formatter:on
|
|
|
1347 |
|
|
|
1348 |
private final int immOp;
|
|
|
1349 |
private final int r;
|
|
|
1350 |
|
|
|
1351 |
private VexShiftOp(String opcode, int pp, int mmmmm, int w, int op, int immOp, int r) {
|
|
|
1352 |
super(opcode, pp, mmmmm, w, op, AVXOpAssertion.AVX1_2);
|
|
|
1353 |
this.immOp = immOp;
|
|
|
1354 |
this.r = r;
|
|
|
1355 |
}
|
|
|
1356 |
|
|
|
1357 |
@Override
|
|
|
1358 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, int imm8) {
|
|
|
1359 |
assert assertion.check((AMD64) asm.target.arch, size, null, dst, src);
|
|
|
1360 |
asm.vexPrefix(null, dst, src, size, pp, mmmmm, w);
|
|
|
1361 |
asm.emitByte(immOp);
|
|
|
1362 |
asm.emitModRM(r, src);
|
|
|
1363 |
asm.emitByte(imm8);
|
|
|
1364 |
}
|
|
|
1365 |
}
|
|
|
1366 |
|
|
|
1367 |
public static final class VexMaskMoveOp extends VexOp {
|
|
|
1368 |
// @formatter:off
|
|
|
1369 |
public static final VexMaskMoveOp VMASKMOVPS = new VexMaskMoveOp("VMASKMOVPS", P_66, M_0F38, W0, 0x2C, 0x2E);
|
|
|
1370 |
public static final VexMaskMoveOp VMASKMOVPD = new VexMaskMoveOp("VMASKMOVPD", P_66, M_0F38, W0, 0x2D, 0x2F);
|
|
|
1371 |
public static final VexMaskMoveOp VPMASKMOVD = new VexMaskMoveOp("VPMASKMOVD", P_66, M_0F38, W0, 0x8C, 0x8E, AVXOpAssertion.AVX2);
|
|
|
1372 |
public static final VexMaskMoveOp VPMASKMOVQ = new VexMaskMoveOp("VPMASKMOVQ", P_66, M_0F38, W1, 0x8C, 0x8E, AVXOpAssertion.AVX2);
|
|
|
1373 |
// @formatter:on
|
|
|
1374 |
|
|
|
1375 |
private final int opReverse;
|
|
|
1376 |
|
|
|
1377 |
private VexMaskMoveOp(String opcode, int pp, int mmmmm, int w, int op, int opReverse) {
|
|
|
1378 |
this(opcode, pp, mmmmm, w, op, opReverse, AVXOpAssertion.AVX1);
|
|
|
1379 |
}
|
|
|
1380 |
|
|
|
1381 |
private VexMaskMoveOp(String opcode, int pp, int mmmmm, int w, int op, int opReverse, AVXOpAssertion assertion) {
|
|
|
1382 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1383 |
this.opReverse = opReverse;
|
|
|
1384 |
}
|
|
|
1385 |
|
|
|
1386 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register mask, AMD64Address src) {
|
|
|
1387 |
assert assertion.check((AMD64) asm.target.arch, size, dst, mask, null);
|
|
|
1388 |
asm.vexPrefix(dst, mask, src, size, pp, mmmmm, w);
|
|
|
1389 |
asm.emitByte(op);
|
|
|
1390 |
asm.emitOperandHelper(dst, src, 0);
|
|
|
1391 |
}
|
|
|
1392 |
|
|
|
1393 |
public void emit(AMD64Assembler asm, AVXSize size, AMD64Address dst, Register mask, Register src) {
|
|
|
1394 |
assert assertion.check((AMD64) asm.target.arch, size, src, mask, null);
|
|
|
1395 |
asm.vexPrefix(src, mask, dst, size, pp, mmmmm, w);
|
|
|
1396 |
asm.emitByte(opReverse);
|
|
|
1397 |
asm.emitOperandHelper(src, dst, 0);
|
|
|
1398 |
}
|
|
|
1399 |
}
|
|
|
1400 |
|
|
|
1401 |
/**
|
|
|
1402 |
* VEX-encoded instructions with an operand order of RVMI.
|
|
|
1403 |
*/
|
|
|
1404 |
public static final class VexRVMIOp extends VexOp {
|
|
|
1405 |
// @formatter:off
|
|
|
1406 |
public static final VexRVMIOp VSHUFPS = new VexRVMIOp("VSHUFPS", P_, M_0F, WIG, 0xC6);
|
|
|
1407 |
public static final VexRVMIOp VSHUFPD = new VexRVMIOp("VSHUFPD", P_66, M_0F, WIG, 0xC6);
|
|
|
1408 |
public static final VexRVMIOp VINSERTF128 = new VexRVMIOp("VINSERTF128", P_66, M_0F3A, W0, 0x18, AVXOpAssertion.AVX1_256ONLY);
|
|
|
1409 |
public static final VexRVMIOp VINSERTI128 = new VexRVMIOp("VINSERTI128", P_66, M_0F3A, W0, 0x38, AVXOpAssertion.AVX2_256ONLY);
|
|
|
1410 |
// @formatter:on
|
|
|
1411 |
|
|
|
1412 |
private VexRVMIOp(String opcode, int pp, int mmmmm, int w, int op) {
|
|
|
1413 |
this(opcode, pp, mmmmm, w, op, AVXOpAssertion.AVX1);
|
|
|
1414 |
}
|
|
|
1415 |
|
|
|
1416 |
private VexRVMIOp(String opcode, int pp, int mmmmm, int w, int op, AVXOpAssertion assertion) {
|
|
|
1417 |
super(opcode, pp, mmmmm, w, op, assertion);
|
|
|
1418 |
}
|
|
|
1419 |
|
|
|
1420 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src1, Register src2, int imm8) {
|
|
|
1421 |
assert assertion.check((AMD64) asm.target.arch, size, dst, src1, src2);
|
|
|
1422 |
assert (imm8 & 0xFF) == imm8;
|
|
|
1423 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1424 |
asm.emitByte(op);
|
|
|
1425 |
asm.emitModRM(dst, src2);
|
|
|
1426 |
asm.emitByte(imm8);
|
|
|
1427 |
}
|
|
|
1428 |
|
|
|
1429 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src1, AMD64Address src2, int imm8) {
|
|
|
1430 |
assert assertion.check((AMD64) asm.target.arch, size, dst, src1, null);
|
|
|
1431 |
assert (imm8 & 0xFF) == imm8;
|
|
|
1432 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1433 |
asm.emitByte(op);
|
|
|
1434 |
asm.emitOperandHelper(dst, src2, 1);
|
|
|
1435 |
asm.emitByte(imm8);
|
|
|
1436 |
}
|
|
|
1437 |
}
|
|
|
1438 |
|
|
|
1439 |
/**
|
|
|
1440 |
* VEX-encoded comparison operation with an operand order of RVMI. The immediate operand is a
|
|
|
1441 |
* comparison operator.
|
|
|
1442 |
*/
|
|
|
1443 |
public static final class VexFloatCompareOp extends VexOp {
|
|
|
1444 |
// @formatter:off
|
|
|
1445 |
public static final VexFloatCompareOp VCMPPS = new VexFloatCompareOp("VCMPPS", P_, M_0F, WIG, 0xC2);
|
|
|
1446 |
public static final VexFloatCompareOp VCMPPD = new VexFloatCompareOp("VCMPPD", P_66, M_0F, WIG, 0xC2);
|
|
|
1447 |
public static final VexFloatCompareOp VCMPSS = new VexFloatCompareOp("VCMPSS", P_F2, M_0F, WIG, 0xC2);
|
|
|
1448 |
public static final VexFloatCompareOp VCMPSD = new VexFloatCompareOp("VCMPSD", P_F2, M_0F, WIG, 0xC2);
|
|
|
1449 |
// @formatter:on
|
|
|
1450 |
|
|
|
1451 |
public enum Predicate {
|
|
|
1452 |
EQ_OQ(0x00),
|
|
|
1453 |
LT_OS(0x01),
|
|
|
1454 |
LE_OS(0x02),
|
|
|
1455 |
UNORD_Q(0x03),
|
|
|
1456 |
NEQ_UQ(0x04),
|
|
|
1457 |
NLT_US(0x05),
|
|
|
1458 |
NLE_US(0x06),
|
|
|
1459 |
ORD_Q(0x07),
|
|
|
1460 |
EQ_UQ(0x08),
|
|
|
1461 |
NGE_US(0x09),
|
|
|
1462 |
NGT_US(0x0a),
|
|
|
1463 |
FALSE_OQ(0x0b),
|
|
|
1464 |
NEQ_OQ(0x0c),
|
|
|
1465 |
GE_OS(0x0d),
|
|
|
1466 |
GT_OS(0x0e),
|
|
|
1467 |
TRUE_UQ(0x0f),
|
|
|
1468 |
EQ_OS(0x10),
|
|
|
1469 |
LT_OQ(0x11),
|
|
|
1470 |
LE_OQ(0x12),
|
|
|
1471 |
UNORD_S(0x13),
|
|
|
1472 |
NEQ_US(0x14),
|
|
|
1473 |
NLT_UQ(0x15),
|
|
|
1474 |
NLE_UQ(0x16),
|
|
|
1475 |
ORD_S(0x17),
|
|
|
1476 |
EQ_US(0x18),
|
|
|
1477 |
NGE_UQ(0x19),
|
|
|
1478 |
NGT_UQ(0x1a),
|
|
|
1479 |
FALSE_OS(0x1b),
|
|
|
1480 |
NEQ_OS(0x1c),
|
|
|
1481 |
GE_OQ(0x1d),
|
|
|
1482 |
GT_OQ(0x1e),
|
|
|
1483 |
TRUE_US(0x1f);
|
|
|
1484 |
|
|
|
1485 |
private int imm8;
|
|
|
1486 |
|
|
|
1487 |
Predicate(int imm8) {
|
|
|
1488 |
this.imm8 = imm8;
|
|
|
1489 |
}
|
|
|
1490 |
|
|
|
1491 |
public static Predicate getPredicate(Condition condition, boolean unorderedIsTrue) {
|
|
|
1492 |
if (unorderedIsTrue) {
|
|
|
1493 |
switch (condition) {
|
|
|
1494 |
case EQ:
|
|
|
1495 |
return EQ_UQ;
|
|
|
1496 |
case NE:
|
|
|
1497 |
return NEQ_UQ;
|
|
|
1498 |
case LT:
|
|
|
1499 |
return NGE_UQ;
|
|
|
1500 |
case LE:
|
|
|
1501 |
return NGT_UQ;
|
|
|
1502 |
case GT:
|
|
|
1503 |
return NLE_UQ;
|
|
|
1504 |
case GE:
|
|
|
1505 |
return NLT_UQ;
|
|
|
1506 |
default:
|
|
|
1507 |
throw GraalError.shouldNotReachHere();
|
|
|
1508 |
}
|
|
|
1509 |
} else {
|
|
|
1510 |
switch (condition) {
|
|
|
1511 |
case EQ:
|
|
|
1512 |
return EQ_OQ;
|
|
|
1513 |
case NE:
|
|
|
1514 |
return NEQ_OQ;
|
|
|
1515 |
case LT:
|
|
|
1516 |
return LT_OQ;
|
|
|
1517 |
case LE:
|
|
|
1518 |
return LE_OQ;
|
|
|
1519 |
case GT:
|
|
|
1520 |
return GT_OQ;
|
|
|
1521 |
case GE:
|
|
|
1522 |
return GE_OQ;
|
|
|
1523 |
default:
|
|
|
1524 |
throw GraalError.shouldNotReachHere();
|
|
|
1525 |
}
|
|
|
1526 |
}
|
|
|
1527 |
}
|
|
|
1528 |
}
|
|
|
1529 |
|
|
|
1530 |
private VexFloatCompareOp(String opcode, int pp, int mmmmm, int w, int op) {
|
|
|
1531 |
super(opcode, pp, mmmmm, w, op, AVXOpAssertion.AVX1);
|
|
|
1532 |
}
|
|
|
1533 |
|
|
|
1534 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src1, Register src2, Predicate p) {
|
|
|
1535 |
assert assertion.check((AMD64) asm.target.arch, size, dst, src1, src2);
|
|
|
1536 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1537 |
asm.emitByte(op);
|
|
|
1538 |
asm.emitModRM(dst, src2);
|
|
|
1539 |
asm.emitByte(p.imm8);
|
|
|
1540 |
}
|
|
|
1541 |
|
|
|
1542 |
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src1, AMD64Address src2, Predicate p) {
|
|
|
1543 |
assert assertion.check((AMD64) asm.target.arch, size, dst, src1, null);
|
|
|
1544 |
asm.vexPrefix(dst, src1, src2, size, pp, mmmmm, w);
|
|
|
1545 |
asm.emitByte(op);
|
|
|
1546 |
asm.emitOperandHelper(dst, src2, 1);
|
|
|
1547 |
asm.emitByte(p.imm8);
|
|
|
1548 |
}
|
|
|
1549 |
}
|
|
|
1550 |
|
|
43972
|
1551 |
public final void addl(AMD64Address dst, int imm32) {
|
|
|
1552 |
ADD.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
1553 |
}
|
|
|
1554 |
|
|
|
1555 |
public final void addl(Register dst, int imm32) {
|
|
|
1556 |
ADD.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
1557 |
}
|
|
|
1558 |
|
|
|
1559 |
public final void addl(Register dst, Register src) {
|
|
|
1560 |
ADD.rmOp.emit(this, DWORD, dst, src);
|
|
|
1561 |
}
|
|
|
1562 |
|
|
|
1563 |
public final void addpd(Register dst, Register src) {
|
|
51436
|
1564 |
SSEOp.ADD.emit(this, PD, dst, src);
|
|
43972
|
1565 |
}
|
|
|
1566 |
|
|
|
1567 |
public final void addpd(Register dst, AMD64Address src) {
|
|
51436
|
1568 |
SSEOp.ADD.emit(this, PD, dst, src);
|
|
43972
|
1569 |
}
|
|
|
1570 |
|
|
|
1571 |
public final void addsd(Register dst, Register src) {
|
|
51436
|
1572 |
SSEOp.ADD.emit(this, SD, dst, src);
|
|
43972
|
1573 |
}
|
|
|
1574 |
|
|
|
1575 |
public final void addsd(Register dst, AMD64Address src) {
|
|
51436
|
1576 |
SSEOp.ADD.emit(this, SD, dst, src);
|
|
43972
|
1577 |
}
|
|
|
1578 |
|
|
|
1579 |
private void addrNop4() {
|
|
|
1580 |
// 4 bytes: NOP DWORD PTR [EAX+0]
|
|
|
1581 |
emitByte(0x0F);
|
|
|
1582 |
emitByte(0x1F);
|
|
|
1583 |
emitByte(0x40); // emitRm(cbuf, 0x1, EAXEnc, EAXEnc);
|
|
|
1584 |
emitByte(0); // 8-bits offset (1 byte)
|
|
|
1585 |
}
|
|
|
1586 |
|
|
|
1587 |
private void addrNop5() {
|
|
|
1588 |
// 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
|
|
|
1589 |
emitByte(0x0F);
|
|
|
1590 |
emitByte(0x1F);
|
|
|
1591 |
emitByte(0x44); // emitRm(cbuf, 0x1, EAXEnc, 0x4);
|
|
|
1592 |
emitByte(0x00); // emitRm(cbuf, 0x0, EAXEnc, EAXEnc);
|
|
|
1593 |
emitByte(0); // 8-bits offset (1 byte)
|
|
|
1594 |
}
|
|
|
1595 |
|
|
|
1596 |
private void addrNop7() {
|
|
|
1597 |
// 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
|
|
|
1598 |
emitByte(0x0F);
|
|
|
1599 |
emitByte(0x1F);
|
|
|
1600 |
emitByte(0x80); // emitRm(cbuf, 0x2, EAXEnc, EAXEnc);
|
|
|
1601 |
emitInt(0); // 32-bits offset (4 bytes)
|
|
|
1602 |
}
|
|
|
1603 |
|
|
|
1604 |
private void addrNop8() {
|
|
|
1605 |
// 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
|
|
|
1606 |
emitByte(0x0F);
|
|
|
1607 |
emitByte(0x1F);
|
|
|
1608 |
emitByte(0x84); // emitRm(cbuf, 0x2, EAXEnc, 0x4);
|
|
|
1609 |
emitByte(0x00); // emitRm(cbuf, 0x0, EAXEnc, EAXEnc);
|
|
|
1610 |
emitInt(0); // 32-bits offset (4 bytes)
|
|
|
1611 |
}
|
|
|
1612 |
|
|
|
1613 |
public final void andl(Register dst, int imm32) {
|
|
|
1614 |
AND.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
1615 |
}
|
|
|
1616 |
|
|
|
1617 |
public final void andl(Register dst, Register src) {
|
|
|
1618 |
AND.rmOp.emit(this, DWORD, dst, src);
|
|
|
1619 |
}
|
|
|
1620 |
|
|
|
1621 |
public final void andpd(Register dst, Register src) {
|
|
51436
|
1622 |
SSEOp.AND.emit(this, PD, dst, src);
|
|
43972
|
1623 |
}
|
|
|
1624 |
|
|
|
1625 |
public final void andpd(Register dst, AMD64Address src) {
|
|
51436
|
1626 |
SSEOp.AND.emit(this, PD, dst, src);
|
|
43972
|
1627 |
}
|
|
|
1628 |
|
|
49451
|
1629 |
public final void bsfq(Register dst, Register src) {
|
|
51436
|
1630 |
prefixq(dst, src);
|
|
49451
|
1631 |
emitByte(0x0F);
|
|
|
1632 |
emitByte(0xBC);
|
|
51436
|
1633 |
emitModRM(dst, src);
|
|
49451
|
1634 |
}
|
|
|
1635 |
|
|
43972
|
1636 |
public final void bsrl(Register dst, Register src) {
|
|
51436
|
1637 |
prefix(dst, src);
|
|
43972
|
1638 |
emitByte(0x0F);
|
|
|
1639 |
emitByte(0xBD);
|
|
51436
|
1640 |
emitModRM(dst, src);
|
|
43972
|
1641 |
}
|
|
|
1642 |
|
|
|
1643 |
public final void bswapl(Register reg) {
|
|
51436
|
1644 |
prefix(reg);
|
|
43972
|
1645 |
emitByte(0x0F);
|
|
51436
|
1646 |
emitModRM(1, reg);
|
|
43972
|
1647 |
}
|
|
|
1648 |
|
|
|
1649 |
public final void cdql() {
|
|
|
1650 |
emitByte(0x99);
|
|
|
1651 |
}
|
|
|
1652 |
|
|
|
1653 |
public final void cmovl(ConditionFlag cc, Register dst, Register src) {
|
|
51436
|
1654 |
prefix(dst, src);
|
|
43972
|
1655 |
emitByte(0x0F);
|
|
|
1656 |
emitByte(0x40 | cc.getValue());
|
|
51436
|
1657 |
emitModRM(dst, src);
|
|
43972
|
1658 |
}
|
|
|
1659 |
|
|
|
1660 |
public final void cmovl(ConditionFlag cc, Register dst, AMD64Address src) {
|
|
|
1661 |
prefix(src, dst);
|
|
|
1662 |
emitByte(0x0F);
|
|
|
1663 |
emitByte(0x40 | cc.getValue());
|
|
|
1664 |
emitOperandHelper(dst, src, 0);
|
|
|
1665 |
}
|
|
|
1666 |
|
|
|
1667 |
public final void cmpl(Register dst, int imm32) {
|
|
|
1668 |
CMP.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
1669 |
}
|
|
|
1670 |
|
|
|
1671 |
public final void cmpl(Register dst, Register src) {
|
|
|
1672 |
CMP.rmOp.emit(this, DWORD, dst, src);
|
|
|
1673 |
}
|
|
|
1674 |
|
|
|
1675 |
public final void cmpl(Register dst, AMD64Address src) {
|
|
|
1676 |
CMP.rmOp.emit(this, DWORD, dst, src);
|
|
|
1677 |
}
|
|
|
1678 |
|
|
|
1679 |
public final void cmpl(AMD64Address dst, int imm32) {
|
|
|
1680 |
CMP.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
1681 |
}
|
|
|
1682 |
|
|
50330
|
1683 |
/**
|
|
|
1684 |
* The 8-bit cmpxchg compares the value at adr with the contents of X86.rax, and stores reg into
|
|
|
1685 |
* adr if so; otherwise, the value at adr is loaded into X86.rax,. The ZF is set if the compared
|
|
|
1686 |
* values were equal, and cleared otherwise.
|
|
|
1687 |
*/
|
|
|
1688 |
public final void cmpxchgb(Register reg, AMD64Address adr) { // cmpxchg
|
|
50609
|
1689 |
prefixb(adr, reg);
|
|
50330
|
1690 |
emitByte(0x0F);
|
|
|
1691 |
emitByte(0xB0);
|
|
|
1692 |
emitOperandHelper(reg, adr, 0);
|
|
|
1693 |
}
|
|
|
1694 |
|
|
|
1695 |
/**
|
|
|
1696 |
* The 16-bit cmpxchg compares the value at adr with the contents of X86.rax, and stores reg
|
|
|
1697 |
* into adr if so; otherwise, the value at adr is loaded into X86.rax,. The ZF is set if the
|
|
|
1698 |
* compared values were equal, and cleared otherwise.
|
|
|
1699 |
*/
|
|
|
1700 |
public final void cmpxchgw(Register reg, AMD64Address adr) { // cmpxchg
|
|
|
1701 |
emitByte(0x66); // Switch to 16-bit mode.
|
|
|
1702 |
prefix(adr, reg);
|
|
|
1703 |
emitByte(0x0F);
|
|
|
1704 |
emitByte(0xB1);
|
|
|
1705 |
emitOperandHelper(reg, adr, 0);
|
|
|
1706 |
}
|
|
|
1707 |
|
|
|
1708 |
/**
|
|
|
1709 |
* The 32-bit cmpxchg compares the value at adr with the contents of X86.rax, and stores reg
|
|
|
1710 |
* into adr if so; otherwise, the value at adr is loaded into X86.rax,. The ZF is set if the
|
|
|
1711 |
* compared values were equal, and cleared otherwise.
|
|
|
1712 |
*/
|
|
43972
|
1713 |
public final void cmpxchgl(Register reg, AMD64Address adr) { // cmpxchg
|
|
|
1714 |
prefix(adr, reg);
|
|
|
1715 |
emitByte(0x0F);
|
|
|
1716 |
emitByte(0xB1);
|
|
|
1717 |
emitOperandHelper(reg, adr, 0);
|
|
|
1718 |
}
|
|
|
1719 |
|
|
|
1720 |
public final void cvtsi2sdl(Register dst, Register src) {
|
|
51436
|
1721 |
SSEOp.CVTSI2SD.emit(this, DWORD, dst, src);
|
|
43972
|
1722 |
}
|
|
|
1723 |
|
|
|
1724 |
public final void cvttsd2sil(Register dst, Register src) {
|
|
51436
|
1725 |
SSEOp.CVTTSD2SI.emit(this, DWORD, dst, src);
|
|
43972
|
1726 |
}
|
|
|
1727 |
|
|
51436
|
1728 |
public final void decl(AMD64Address dst) {
|
|
43972
|
1729 |
prefix(dst);
|
|
|
1730 |
emitByte(0xFF);
|
|
|
1731 |
emitOperandHelper(1, dst, 0);
|
|
|
1732 |
}
|
|
|
1733 |
|
|
|
1734 |
public final void divsd(Register dst, Register src) {
|
|
51436
|
1735 |
SSEOp.DIV.emit(this, SD, dst, src);
|
|
49451
|
1736 |
}
|
|
|
1737 |
|
|
43972
|
1738 |
public final void hlt() {
|
|
|
1739 |
emitByte(0xF4);
|
|
|
1740 |
}
|
|
|
1741 |
|
|
|
1742 |
public final void imull(Register dst, Register src, int value) {
|
|
|
1743 |
if (isByte(value)) {
|
|
|
1744 |
AMD64RMIOp.IMUL_SX.emit(this, DWORD, dst, src, value);
|
|
|
1745 |
} else {
|
|
|
1746 |
AMD64RMIOp.IMUL.emit(this, DWORD, dst, src, value);
|
|
|
1747 |
}
|
|
|
1748 |
}
|
|
|
1749 |
|
|
51436
|
1750 |
public final void incl(AMD64Address dst) {
|
|
43972
|
1751 |
prefix(dst);
|
|
|
1752 |
emitByte(0xFF);
|
|
|
1753 |
emitOperandHelper(0, dst, 0);
|
|
|
1754 |
}
|
|
|
1755 |
|
|
|
1756 |
public void jcc(ConditionFlag cc, int jumpTarget, boolean forceDisp32) {
|
|
|
1757 |
int shortSize = 2;
|
|
|
1758 |
int longSize = 6;
|
|
|
1759 |
long disp = jumpTarget - position();
|
|
|
1760 |
if (!forceDisp32 && isByte(disp - shortSize)) {
|
|
|
1761 |
// 0111 tttn #8-bit disp
|
|
|
1762 |
emitByte(0x70 | cc.getValue());
|
|
|
1763 |
emitByte((int) ((disp - shortSize) & 0xFF));
|
|
|
1764 |
} else {
|
|
|
1765 |
// 0000 1111 1000 tttn #32-bit disp
|
|
|
1766 |
assert isInt(disp - longSize) : "must be 32bit offset (call4)";
|
|
|
1767 |
emitByte(0x0F);
|
|
|
1768 |
emitByte(0x80 | cc.getValue());
|
|
|
1769 |
emitInt((int) (disp - longSize));
|
|
|
1770 |
}
|
|
|
1771 |
}
|
|
|
1772 |
|
|
|
1773 |
public final void jcc(ConditionFlag cc, Label l) {
|
|
|
1774 |
assert (0 <= cc.getValue()) && (cc.getValue() < 16) : "illegal cc";
|
|
|
1775 |
if (l.isBound()) {
|
|
|
1776 |
jcc(cc, l.position(), false);
|
|
|
1777 |
} else {
|
|
|
1778 |
// Note: could eliminate cond. jumps to this jump if condition
|
|
|
1779 |
// is the same however, seems to be rather unlikely case.
|
|
|
1780 |
// Note: use jccb() if label to be bound is very close to get
|
|
|
1781 |
// an 8-bit displacement
|
|
|
1782 |
l.addPatchAt(position());
|
|
|
1783 |
emitByte(0x0F);
|
|
|
1784 |
emitByte(0x80 | cc.getValue());
|
|
|
1785 |
emitInt(0);
|
|
|
1786 |
}
|
|
|
1787 |
|
|
|
1788 |
}
|
|
|
1789 |
|
|
|
1790 |
public final void jccb(ConditionFlag cc, Label l) {
|
|
|
1791 |
if (l.isBound()) {
|
|
|
1792 |
int shortSize = 2;
|
|
|
1793 |
int entry = l.position();
|
|
|
1794 |
assert isByte(entry - (position() + shortSize)) : "Dispacement too large for a short jmp";
|
|
|
1795 |
long disp = entry - position();
|
|
|
1796 |
// 0111 tttn #8-bit disp
|
|
|
1797 |
emitByte(0x70 | cc.getValue());
|
|
|
1798 |
emitByte((int) ((disp - shortSize) & 0xFF));
|
|
|
1799 |
} else {
|
|
|
1800 |
l.addPatchAt(position());
|
|
|
1801 |
emitByte(0x70 | cc.getValue());
|
|
|
1802 |
emitByte(0);
|
|
|
1803 |
}
|
|
|
1804 |
}
|
|
|
1805 |
|
|
|
1806 |
public final void jmp(int jumpTarget, boolean forceDisp32) {
|
|
|
1807 |
int shortSize = 2;
|
|
|
1808 |
int longSize = 5;
|
|
|
1809 |
long disp = jumpTarget - position();
|
|
|
1810 |
if (!forceDisp32 && isByte(disp - shortSize)) {
|
|
|
1811 |
emitByte(0xEB);
|
|
|
1812 |
emitByte((int) ((disp - shortSize) & 0xFF));
|
|
|
1813 |
} else {
|
|
|
1814 |
emitByte(0xE9);
|
|
|
1815 |
emitInt((int) (disp - longSize));
|
|
|
1816 |
}
|
|
|
1817 |
}
|
|
|
1818 |
|
|
|
1819 |
@Override
|
|
|
1820 |
public final void jmp(Label l) {
|
|
|
1821 |
if (l.isBound()) {
|
|
|
1822 |
jmp(l.position(), false);
|
|
|
1823 |
} else {
|
|
|
1824 |
// By default, forward jumps are always 32-bit displacements, since
|
|
|
1825 |
// we can't yet know where the label will be bound. If you're sure that
|
|
|
1826 |
// the forward jump will not run beyond 256 bytes, use jmpb to
|
|
|
1827 |
// force an 8-bit displacement.
|
|
|
1828 |
|
|
|
1829 |
l.addPatchAt(position());
|
|
|
1830 |
emitByte(0xE9);
|
|
|
1831 |
emitInt(0);
|
|
|
1832 |
}
|
|
|
1833 |
}
|
|
|
1834 |
|
|
|
1835 |
public final void jmp(Register entry) {
|
|
51436
|
1836 |
prefix(entry);
|
|
43972
|
1837 |
emitByte(0xFF);
|
|
51436
|
1838 |
emitModRM(4, entry);
|
|
43972
|
1839 |
}
|
|
|
1840 |
|
|
|
1841 |
public final void jmp(AMD64Address adr) {
|
|
|
1842 |
prefix(adr);
|
|
|
1843 |
emitByte(0xFF);
|
|
51436
|
1844 |
emitOperandHelper(AMD64.rsp, adr, 0);
|
|
43972
|
1845 |
}
|
|
|
1846 |
|
|
|
1847 |
public final void jmpb(Label l) {
|
|
|
1848 |
if (l.isBound()) {
|
|
|
1849 |
int shortSize = 2;
|
|
|
1850 |
int entry = l.position();
|
|
|
1851 |
assert isByte((entry - position()) + shortSize) : "Dispacement too large for a short jmp";
|
|
|
1852 |
long offs = entry - position();
|
|
|
1853 |
emitByte(0xEB);
|
|
|
1854 |
emitByte((int) ((offs - shortSize) & 0xFF));
|
|
|
1855 |
} else {
|
|
|
1856 |
|
|
|
1857 |
l.addPatchAt(position());
|
|
|
1858 |
emitByte(0xEB);
|
|
|
1859 |
emitByte(0);
|
|
|
1860 |
}
|
|
|
1861 |
}
|
|
|
1862 |
|
|
48190
|
1863 |
public final void lead(Register dst, AMD64Address src) {
|
|
|
1864 |
prefix(src, dst);
|
|
|
1865 |
emitByte(0x8D);
|
|
|
1866 |
emitOperandHelper(dst, src, 0);
|
|
|
1867 |
}
|
|
|
1868 |
|
|
43972
|
1869 |
public final void leaq(Register dst, AMD64Address src) {
|
|
|
1870 |
prefixq(src, dst);
|
|
|
1871 |
emitByte(0x8D);
|
|
|
1872 |
emitOperandHelper(dst, src, 0);
|
|
|
1873 |
}
|
|
|
1874 |
|
|
|
1875 |
public final void leave() {
|
|
|
1876 |
emitByte(0xC9);
|
|
|
1877 |
}
|
|
|
1878 |
|
|
|
1879 |
public final void lock() {
|
|
|
1880 |
emitByte(0xF0);
|
|
|
1881 |
}
|
|
|
1882 |
|
|
|
1883 |
public final void movapd(Register dst, Register src) {
|
|
51436
|
1884 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
1885 |
simdPrefix(dst, Register.None, src, PD, P_0F, false);
|
|
43972
|
1886 |
emitByte(0x28);
|
|
51436
|
1887 |
emitModRM(dst, src);
|
|
43972
|
1888 |
}
|
|
|
1889 |
|
|
|
1890 |
public final void movaps(Register dst, Register src) {
|
|
51436
|
1891 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
1892 |
simdPrefix(dst, Register.None, src, PS, P_0F, false);
|
|
43972
|
1893 |
emitByte(0x28);
|
|
51436
|
1894 |
emitModRM(dst, src);
|
|
43972
|
1895 |
}
|
|
|
1896 |
|
|
|
1897 |
public final void movb(AMD64Address dst, int imm8) {
|
|
|
1898 |
prefix(dst);
|
|
|
1899 |
emitByte(0xC6);
|
|
|
1900 |
emitOperandHelper(0, dst, 1);
|
|
|
1901 |
emitByte(imm8);
|
|
|
1902 |
}
|
|
|
1903 |
|
|
|
1904 |
public final void movb(AMD64Address dst, Register src) {
|
|
51436
|
1905 |
assert src.getRegisterCategory().equals(CPU) : "must have byte register";
|
|
50609
|
1906 |
prefixb(dst, src);
|
|
43972
|
1907 |
emitByte(0x88);
|
|
|
1908 |
emitOperandHelper(src, dst, 0);
|
|
|
1909 |
}
|
|
|
1910 |
|
|
|
1911 |
public final void movl(Register dst, int imm32) {
|
|
51436
|
1912 |
movl(dst, imm32, false);
|
|
|
1913 |
}
|
|
|
1914 |
|
|
|
1915 |
public final void movl(Register dst, int imm32, boolean annotateImm) {
|
|
|
1916 |
int insnPos = position();
|
|
|
1917 |
prefix(dst);
|
|
|
1918 |
emitByte(0xB8 + encode(dst));
|
|
|
1919 |
int immPos = position();
|
|
43972
|
1920 |
emitInt(imm32);
|
|
51436
|
1921 |
int nextInsnPos = position();
|
|
|
1922 |
if (annotateImm && codePatchingAnnotationConsumer != null) {
|
|
|
1923 |
codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
|
|
|
1924 |
}
|
|
43972
|
1925 |
}
|
|
|
1926 |
|
|
|
1927 |
public final void movl(Register dst, Register src) {
|
|
51436
|
1928 |
prefix(dst, src);
|
|
43972
|
1929 |
emitByte(0x8B);
|
|
51436
|
1930 |
emitModRM(dst, src);
|
|
43972
|
1931 |
}
|
|
|
1932 |
|
|
|
1933 |
public final void movl(Register dst, AMD64Address src) {
|
|
|
1934 |
prefix(src, dst);
|
|
|
1935 |
emitByte(0x8B);
|
|
|
1936 |
emitOperandHelper(dst, src, 0);
|
|
|
1937 |
}
|
|
|
1938 |
|
|
49451
|
1939 |
/**
|
|
|
1940 |
* @param wide use 4 byte encoding for displacements that would normally fit in a byte
|
|
|
1941 |
*/
|
|
|
1942 |
public final void movl(Register dst, AMD64Address src, boolean wide) {
|
|
|
1943 |
prefix(src, dst);
|
|
|
1944 |
emitByte(0x8B);
|
|
|
1945 |
emitOperandHelper(dst, src, wide, 0);
|
|
|
1946 |
}
|
|
|
1947 |
|
|
43972
|
1948 |
public final void movl(AMD64Address dst, int imm32) {
|
|
|
1949 |
prefix(dst);
|
|
|
1950 |
emitByte(0xC7);
|
|
|
1951 |
emitOperandHelper(0, dst, 4);
|
|
|
1952 |
emitInt(imm32);
|
|
|
1953 |
}
|
|
|
1954 |
|
|
|
1955 |
public final void movl(AMD64Address dst, Register src) {
|
|
|
1956 |
prefix(dst, src);
|
|
|
1957 |
emitByte(0x89);
|
|
|
1958 |
emitOperandHelper(src, dst, 0);
|
|
|
1959 |
}
|
|
|
1960 |
|
|
|
1961 |
/**
|
|
|
1962 |
* New CPUs require use of movsd and movss to avoid partial register stall when loading from
|
|
|
1963 |
* memory. But for old Opteron use movlpd instead of movsd. The selection is done in
|
|
|
1964 |
* {@link AMD64MacroAssembler#movdbl(Register, AMD64Address)} and
|
|
|
1965 |
* {@link AMD64MacroAssembler#movflt(Register, Register)}.
|
|
|
1966 |
*/
|
|
|
1967 |
public final void movlpd(Register dst, AMD64Address src) {
|
|
51436
|
1968 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
1969 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
1970 |
emitByte(0x12);
|
|
|
1971 |
emitOperandHelper(dst, src, 0);
|
|
|
1972 |
}
|
|
|
1973 |
|
|
|
1974 |
public final void movlhps(Register dst, Register src) {
|
|
51436
|
1975 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
1976 |
simdPrefix(dst, src, src, PS, P_0F, false);
|
|
43972
|
1977 |
emitByte(0x16);
|
|
51436
|
1978 |
emitModRM(dst, src);
|
|
43972
|
1979 |
}
|
|
|
1980 |
|
|
|
1981 |
public final void movq(Register dst, AMD64Address src) {
|
|
|
1982 |
movq(dst, src, false);
|
|
|
1983 |
}
|
|
|
1984 |
|
|
|
1985 |
public final void movq(Register dst, AMD64Address src, boolean wide) {
|
|
51436
|
1986 |
if (dst.getRegisterCategory().equals(XMM)) {
|
|
|
1987 |
simdPrefix(dst, Register.None, src, SS, P_0F, false);
|
|
43972
|
1988 |
emitByte(0x7E);
|
|
|
1989 |
emitOperandHelper(dst, src, wide, 0);
|
|
|
1990 |
} else {
|
|
|
1991 |
// gpr version of movq
|
|
|
1992 |
prefixq(src, dst);
|
|
|
1993 |
emitByte(0x8B);
|
|
|
1994 |
emitOperandHelper(dst, src, wide, 0);
|
|
|
1995 |
}
|
|
|
1996 |
}
|
|
|
1997 |
|
|
|
1998 |
public final void movq(Register dst, Register src) {
|
|
51436
|
1999 |
prefixq(dst, src);
|
|
43972
|
2000 |
emitByte(0x8B);
|
|
51436
|
2001 |
emitModRM(dst, src);
|
|
43972
|
2002 |
}
|
|
|
2003 |
|
|
|
2004 |
public final void movq(AMD64Address dst, Register src) {
|
|
51436
|
2005 |
if (src.getRegisterCategory().equals(XMM)) {
|
|
|
2006 |
simdPrefix(src, Register.None, dst, PD, P_0F, true);
|
|
43972
|
2007 |
emitByte(0xD6);
|
|
|
2008 |
emitOperandHelper(src, dst, 0);
|
|
|
2009 |
} else {
|
|
|
2010 |
// gpr version of movq
|
|
|
2011 |
prefixq(dst, src);
|
|
|
2012 |
emitByte(0x89);
|
|
|
2013 |
emitOperandHelper(src, dst, 0);
|
|
|
2014 |
}
|
|
|
2015 |
}
|
|
|
2016 |
|
|
|
2017 |
public final void movsbl(Register dst, AMD64Address src) {
|
|
|
2018 |
prefix(src, dst);
|
|
|
2019 |
emitByte(0x0F);
|
|
|
2020 |
emitByte(0xBE);
|
|
|
2021 |
emitOperandHelper(dst, src, 0);
|
|
|
2022 |
}
|
|
|
2023 |
|
|
|
2024 |
public final void movsbl(Register dst, Register src) {
|
|
51436
|
2025 |
prefix(dst, false, src, true);
|
|
43972
|
2026 |
emitByte(0x0F);
|
|
|
2027 |
emitByte(0xBE);
|
|
51436
|
2028 |
emitModRM(dst, src);
|
|
43972
|
2029 |
}
|
|
|
2030 |
|
|
|
2031 |
public final void movsbq(Register dst, AMD64Address src) {
|
|
|
2032 |
prefixq(src, dst);
|
|
|
2033 |
emitByte(0x0F);
|
|
|
2034 |
emitByte(0xBE);
|
|
|
2035 |
emitOperandHelper(dst, src, 0);
|
|
|
2036 |
}
|
|
|
2037 |
|
|
|
2038 |
public final void movsbq(Register dst, Register src) {
|
|
51436
|
2039 |
prefixq(dst, src);
|
|
43972
|
2040 |
emitByte(0x0F);
|
|
|
2041 |
emitByte(0xBE);
|
|
51436
|
2042 |
emitModRM(dst, src);
|
|
43972
|
2043 |
}
|
|
|
2044 |
|
|
|
2045 |
public final void movsd(Register dst, Register src) {
|
|
51436
|
2046 |
AMD64RMOp.MOVSD.emit(this, SD, dst, src);
|
|
43972
|
2047 |
}
|
|
|
2048 |
|
|
|
2049 |
public final void movsd(Register dst, AMD64Address src) {
|
|
51436
|
2050 |
AMD64RMOp.MOVSD.emit(this, SD, dst, src);
|
|
43972
|
2051 |
}
|
|
|
2052 |
|
|
|
2053 |
public final void movsd(AMD64Address dst, Register src) {
|
|
51436
|
2054 |
AMD64MROp.MOVSD.emit(this, SD, dst, src);
|
|
43972
|
2055 |
}
|
|
|
2056 |
|
|
|
2057 |
public final void movss(Register dst, Register src) {
|
|
51436
|
2058 |
AMD64RMOp.MOVSS.emit(this, SS, dst, src);
|
|
43972
|
2059 |
}
|
|
|
2060 |
|
|
|
2061 |
public final void movss(Register dst, AMD64Address src) {
|
|
51436
|
2062 |
AMD64RMOp.MOVSS.emit(this, SS, dst, src);
|
|
43972
|
2063 |
}
|
|
|
2064 |
|
|
|
2065 |
public final void movss(AMD64Address dst, Register src) {
|
|
51436
|
2066 |
AMD64MROp.MOVSS.emit(this, SS, dst, src);
|
|
43972
|
2067 |
}
|
|
|
2068 |
|
|
|
2069 |
public final void mulpd(Register dst, Register src) {
|
|
51436
|
2070 |
SSEOp.MUL.emit(this, PD, dst, src);
|
|
43972
|
2071 |
}
|
|
|
2072 |
|
|
|
2073 |
public final void mulpd(Register dst, AMD64Address src) {
|
|
51436
|
2074 |
SSEOp.MUL.emit(this, PD, dst, src);
|
|
43972
|
2075 |
}
|
|
|
2076 |
|
|
|
2077 |
public final void mulsd(Register dst, Register src) {
|
|
51436
|
2078 |
SSEOp.MUL.emit(this, SD, dst, src);
|
|
43972
|
2079 |
}
|
|
|
2080 |
|
|
|
2081 |
public final void mulsd(Register dst, AMD64Address src) {
|
|
51436
|
2082 |
SSEOp.MUL.emit(this, SD, dst, src);
|
|
43972
|
2083 |
}
|
|
|
2084 |
|
|
|
2085 |
public final void mulss(Register dst, Register src) {
|
|
51436
|
2086 |
SSEOp.MUL.emit(this, SS, dst, src);
|
|
43972
|
2087 |
}
|
|
|
2088 |
|
|
|
2089 |
public final void movswl(Register dst, AMD64Address src) {
|
|
|
2090 |
prefix(src, dst);
|
|
|
2091 |
emitByte(0x0F);
|
|
|
2092 |
emitByte(0xBF);
|
|
|
2093 |
emitOperandHelper(dst, src, 0);
|
|
|
2094 |
}
|
|
|
2095 |
|
|
|
2096 |
public final void movw(AMD64Address dst, int imm16) {
|
|
|
2097 |
emitByte(0x66); // switch to 16-bit mode
|
|
|
2098 |
prefix(dst);
|
|
|
2099 |
emitByte(0xC7);
|
|
|
2100 |
emitOperandHelper(0, dst, 2);
|
|
|
2101 |
emitShort(imm16);
|
|
|
2102 |
}
|
|
|
2103 |
|
|
|
2104 |
public final void movw(AMD64Address dst, Register src) {
|
|
|
2105 |
emitByte(0x66);
|
|
|
2106 |
prefix(dst, src);
|
|
|
2107 |
emitByte(0x89);
|
|
|
2108 |
emitOperandHelper(src, dst, 0);
|
|
|
2109 |
}
|
|
|
2110 |
|
|
|
2111 |
public final void movzbl(Register dst, AMD64Address src) {
|
|
|
2112 |
prefix(src, dst);
|
|
|
2113 |
emitByte(0x0F);
|
|
|
2114 |
emitByte(0xB6);
|
|
|
2115 |
emitOperandHelper(dst, src, 0);
|
|
|
2116 |
}
|
|
|
2117 |
|
|
47798
|
2118 |
public final void movzbl(Register dst, Register src) {
|
|
51436
|
2119 |
AMD64RMOp.MOVZXB.emit(this, DWORD, dst, src);
|
|
47798
|
2120 |
}
|
|
|
2121 |
|
|
|
2122 |
public final void movzbq(Register dst, Register src) {
|
|
51436
|
2123 |
AMD64RMOp.MOVZXB.emit(this, QWORD, dst, src);
|
|
47798
|
2124 |
}
|
|
|
2125 |
|
|
43972
|
2126 |
public final void movzwl(Register dst, AMD64Address src) {
|
|
|
2127 |
prefix(src, dst);
|
|
|
2128 |
emitByte(0x0F);
|
|
|
2129 |
emitByte(0xB7);
|
|
|
2130 |
emitOperandHelper(dst, src, 0);
|
|
|
2131 |
}
|
|
|
2132 |
|
|
|
2133 |
public final void negl(Register dst) {
|
|
|
2134 |
NEG.emit(this, DWORD, dst);
|
|
|
2135 |
}
|
|
|
2136 |
|
|
|
2137 |
public final void notl(Register dst) {
|
|
|
2138 |
NOT.emit(this, DWORD, dst);
|
|
|
2139 |
}
|
|
|
2140 |
|
|
49451
|
2141 |
public final void notq(Register dst) {
|
|
|
2142 |
NOT.emit(this, QWORD, dst);
|
|
|
2143 |
}
|
|
|
2144 |
|
|
43972
|
2145 |
@Override
|
|
|
2146 |
public final void ensureUniquePC() {
|
|
|
2147 |
nop();
|
|
|
2148 |
}
|
|
|
2149 |
|
|
|
2150 |
public final void nop() {
|
|
|
2151 |
nop(1);
|
|
|
2152 |
}
|
|
|
2153 |
|
|
|
2154 |
public void nop(int count) {
|
|
|
2155 |
int i = count;
|
|
|
2156 |
if (UseNormalNop) {
|
|
|
2157 |
assert i > 0 : " ";
|
|
|
2158 |
// The fancy nops aren't currently recognized by debuggers making it a
|
|
|
2159 |
// pain to disassemble code while debugging. If assert are on clearly
|
|
|
2160 |
// speed is not an issue so simply use the single byte traditional nop
|
|
|
2161 |
// to do alignment.
|
|
|
2162 |
|
|
|
2163 |
for (; i > 0; i--) {
|
|
|
2164 |
emitByte(0x90);
|
|
|
2165 |
}
|
|
|
2166 |
return;
|
|
|
2167 |
}
|
|
|
2168 |
|
|
|
2169 |
if (UseAddressNop) {
|
|
|
2170 |
//
|
|
|
2171 |
// Using multi-bytes nops "0x0F 0x1F [Address]" for AMD.
|
|
|
2172 |
// 1: 0x90
|
|
|
2173 |
// 2: 0x66 0x90
|
|
|
2174 |
// 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
|
|
|
2175 |
// 4: 0x0F 0x1F 0x40 0x00
|
|
|
2176 |
// 5: 0x0F 0x1F 0x44 0x00 0x00
|
|
|
2177 |
// 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
|
|
|
2178 |
// 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
|
|
|
2179 |
// 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
|
2180 |
// 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
|
2181 |
// 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
|
2182 |
// 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
|
2183 |
|
|
|
2184 |
// The rest coding is AMD specific - use consecutive Address nops
|
|
|
2185 |
|
|
|
2186 |
// 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
|
|
|
2187 |
// 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
|
|
|
2188 |
// 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
|
|
|
2189 |
// 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
|
|
|
2190 |
// 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
|
|
|
2191 |
// Size prefixes (0x66) are added for larger sizes
|
|
|
2192 |
|
|
|
2193 |
while (i >= 22) {
|
|
|
2194 |
i -= 11;
|
|
|
2195 |
emitByte(0x66); // size prefix
|
|
|
2196 |
emitByte(0x66); // size prefix
|
|
|
2197 |
emitByte(0x66); // size prefix
|
|
|
2198 |
addrNop8();
|
|
|
2199 |
}
|
|
|
2200 |
// Generate first nop for size between 21-12
|
|
|
2201 |
switch (i) {
|
|
|
2202 |
case 21:
|
|
|
2203 |
i -= 11;
|
|
|
2204 |
emitByte(0x66); // size prefix
|
|
|
2205 |
emitByte(0x66); // size prefix
|
|
|
2206 |
emitByte(0x66); // size prefix
|
|
|
2207 |
addrNop8();
|
|
|
2208 |
break;
|
|
|
2209 |
case 20:
|
|
|
2210 |
case 19:
|
|
|
2211 |
i -= 10;
|
|
|
2212 |
emitByte(0x66); // size prefix
|
|
|
2213 |
emitByte(0x66); // size prefix
|
|
|
2214 |
addrNop8();
|
|
|
2215 |
break;
|
|
|
2216 |
case 18:
|
|
|
2217 |
case 17:
|
|
|
2218 |
i -= 9;
|
|
|
2219 |
emitByte(0x66); // size prefix
|
|
|
2220 |
addrNop8();
|
|
|
2221 |
break;
|
|
|
2222 |
case 16:
|
|
|
2223 |
case 15:
|
|
|
2224 |
i -= 8;
|
|
|
2225 |
addrNop8();
|
|
|
2226 |
break;
|
|
|
2227 |
case 14:
|
|
|
2228 |
case 13:
|
|
|
2229 |
i -= 7;
|
|
|
2230 |
addrNop7();
|
|
|
2231 |
break;
|
|
|
2232 |
case 12:
|
|
|
2233 |
i -= 6;
|
|
|
2234 |
emitByte(0x66); // size prefix
|
|
|
2235 |
addrNop5();
|
|
|
2236 |
break;
|
|
|
2237 |
default:
|
|
|
2238 |
assert i < 12;
|
|
|
2239 |
}
|
|
|
2240 |
|
|
|
2241 |
// Generate second nop for size between 11-1
|
|
|
2242 |
switch (i) {
|
|
|
2243 |
case 11:
|
|
|
2244 |
emitByte(0x66); // size prefix
|
|
|
2245 |
emitByte(0x66); // size prefix
|
|
|
2246 |
emitByte(0x66); // size prefix
|
|
|
2247 |
addrNop8();
|
|
|
2248 |
break;
|
|
|
2249 |
case 10:
|
|
|
2250 |
emitByte(0x66); // size prefix
|
|
|
2251 |
emitByte(0x66); // size prefix
|
|
|
2252 |
addrNop8();
|
|
|
2253 |
break;
|
|
|
2254 |
case 9:
|
|
|
2255 |
emitByte(0x66); // size prefix
|
|
|
2256 |
addrNop8();
|
|
|
2257 |
break;
|
|
|
2258 |
case 8:
|
|
|
2259 |
addrNop8();
|
|
|
2260 |
break;
|
|
|
2261 |
case 7:
|
|
|
2262 |
addrNop7();
|
|
|
2263 |
break;
|
|
|
2264 |
case 6:
|
|
|
2265 |
emitByte(0x66); // size prefix
|
|
|
2266 |
addrNop5();
|
|
|
2267 |
break;
|
|
|
2268 |
case 5:
|
|
|
2269 |
addrNop5();
|
|
|
2270 |
break;
|
|
|
2271 |
case 4:
|
|
|
2272 |
addrNop4();
|
|
|
2273 |
break;
|
|
|
2274 |
case 3:
|
|
|
2275 |
// Don't use "0x0F 0x1F 0x00" - need patching safe padding
|
|
|
2276 |
emitByte(0x66); // size prefix
|
|
|
2277 |
emitByte(0x66); // size prefix
|
|
|
2278 |
emitByte(0x90); // nop
|
|
|
2279 |
break;
|
|
|
2280 |
case 2:
|
|
|
2281 |
emitByte(0x66); // size prefix
|
|
|
2282 |
emitByte(0x90); // nop
|
|
|
2283 |
break;
|
|
|
2284 |
case 1:
|
|
|
2285 |
emitByte(0x90); // nop
|
|
|
2286 |
break;
|
|
|
2287 |
default:
|
|
|
2288 |
assert i == 0;
|
|
|
2289 |
}
|
|
|
2290 |
return;
|
|
|
2291 |
}
|
|
|
2292 |
|
|
|
2293 |
// Using nops with size prefixes "0x66 0x90".
|
|
|
2294 |
// From AMD Optimization Guide:
|
|
|
2295 |
// 1: 0x90
|
|
|
2296 |
// 2: 0x66 0x90
|
|
|
2297 |
// 3: 0x66 0x66 0x90
|
|
|
2298 |
// 4: 0x66 0x66 0x66 0x90
|
|
|
2299 |
// 5: 0x66 0x66 0x90 0x66 0x90
|
|
|
2300 |
// 6: 0x66 0x66 0x90 0x66 0x66 0x90
|
|
|
2301 |
// 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
|
|
|
2302 |
// 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
|
|
|
2303 |
// 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
|
|
|
2304 |
// 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
|
|
|
2305 |
//
|
|
|
2306 |
while (i > 12) {
|
|
|
2307 |
i -= 4;
|
|
|
2308 |
emitByte(0x66); // size prefix
|
|
|
2309 |
emitByte(0x66);
|
|
|
2310 |
emitByte(0x66);
|
|
|
2311 |
emitByte(0x90); // nop
|
|
|
2312 |
}
|
|
|
2313 |
// 1 - 12 nops
|
|
|
2314 |
if (i > 8) {
|
|
|
2315 |
if (i > 9) {
|
|
|
2316 |
i -= 1;
|
|
|
2317 |
emitByte(0x66);
|
|
|
2318 |
}
|
|
|
2319 |
i -= 3;
|
|
|
2320 |
emitByte(0x66);
|
|
|
2321 |
emitByte(0x66);
|
|
|
2322 |
emitByte(0x90);
|
|
|
2323 |
}
|
|
|
2324 |
// 1 - 8 nops
|
|
|
2325 |
if (i > 4) {
|
|
|
2326 |
if (i > 6) {
|
|
|
2327 |
i -= 1;
|
|
|
2328 |
emitByte(0x66);
|
|
|
2329 |
}
|
|
|
2330 |
i -= 3;
|
|
|
2331 |
emitByte(0x66);
|
|
|
2332 |
emitByte(0x66);
|
|
|
2333 |
emitByte(0x90);
|
|
|
2334 |
}
|
|
|
2335 |
switch (i) {
|
|
|
2336 |
case 4:
|
|
|
2337 |
emitByte(0x66);
|
|
|
2338 |
emitByte(0x66);
|
|
|
2339 |
emitByte(0x66);
|
|
|
2340 |
emitByte(0x90);
|
|
|
2341 |
break;
|
|
|
2342 |
case 3:
|
|
|
2343 |
emitByte(0x66);
|
|
|
2344 |
emitByte(0x66);
|
|
|
2345 |
emitByte(0x90);
|
|
|
2346 |
break;
|
|
|
2347 |
case 2:
|
|
|
2348 |
emitByte(0x66);
|
|
|
2349 |
emitByte(0x90);
|
|
|
2350 |
break;
|
|
|
2351 |
case 1:
|
|
|
2352 |
emitByte(0x90);
|
|
|
2353 |
break;
|
|
|
2354 |
default:
|
|
|
2355 |
assert i == 0;
|
|
|
2356 |
}
|
|
|
2357 |
}
|
|
|
2358 |
|
|
|
2359 |
public final void orl(Register dst, Register src) {
|
|
|
2360 |
OR.rmOp.emit(this, DWORD, dst, src);
|
|
|
2361 |
}
|
|
|
2362 |
|
|
|
2363 |
public final void orl(Register dst, int imm32) {
|
|
|
2364 |
OR.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
2365 |
}
|
|
|
2366 |
|
|
|
2367 |
public final void pop(Register dst) {
|
|
51436
|
2368 |
prefix(dst);
|
|
|
2369 |
emitByte(0x58 + encode(dst));
|
|
43972
|
2370 |
}
|
|
|
2371 |
|
|
|
2372 |
public void popfq() {
|
|
|
2373 |
emitByte(0x9D);
|
|
|
2374 |
}
|
|
|
2375 |
|
|
|
2376 |
public final void ptest(Register dst, Register src) {
|
|
|
2377 |
assert supports(CPUFeature.SSE4_1);
|
|
51436
|
2378 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2379 |
simdPrefix(dst, Register.None, src, PD, P_0F38, false);
|
|
43972
|
2380 |
emitByte(0x17);
|
|
51436
|
2381 |
emitModRM(dst, src);
|
|
43972
|
2382 |
}
|
|
|
2383 |
|
|
51436
|
2384 |
public final void pcmpeqb(Register dst, Register src) {
|
|
|
2385 |
assert supports(CPUFeature.SSE2);
|
|
|
2386 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2387 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
|
2388 |
emitByte(0x74);
|
|
|
2389 |
emitModRM(dst, src);
|
|
|
2390 |
}
|
|
|
2391 |
|
|
|
2392 |
public final void pcmpeqw(Register dst, Register src) {
|
|
|
2393 |
assert supports(CPUFeature.SSE2);
|
|
|
2394 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2395 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
|
2396 |
emitByte(0x75);
|
|
|
2397 |
emitModRM(dst, src);
|
|
43972
|
2398 |
}
|
|
|
2399 |
|
|
49451
|
2400 |
public final void pcmpestri(Register dst, AMD64Address src, int imm8) {
|
|
46344
|
2401 |
assert supports(CPUFeature.SSE4_2);
|
|
51436
|
2402 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
2403 |
simdPrefix(dst, Register.None, src, PD, P_0F3A, false);
|
|
46344
|
2404 |
emitByte(0x61);
|
|
|
2405 |
emitOperandHelper(dst, src, 0);
|
|
|
2406 |
emitByte(imm8);
|
|
|
2407 |
}
|
|
|
2408 |
|
|
49451
|
2409 |
public final void pcmpestri(Register dst, Register src, int imm8) {
|
|
46344
|
2410 |
assert supports(CPUFeature.SSE4_2);
|
|
51436
|
2411 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2412 |
simdPrefix(dst, Register.None, src, PD, P_0F3A, false);
|
|
46344
|
2413 |
emitByte(0x61);
|
|
51436
|
2414 |
emitModRM(dst, src);
|
|
46344
|
2415 |
emitByte(imm8);
|
|
|
2416 |
}
|
|
|
2417 |
|
|
51436
|
2418 |
public final void pmovmskb(Register dst, Register src) {
|
|
|
2419 |
assert supports(CPUFeature.SSE2);
|
|
|
2420 |
assert dst.getRegisterCategory().equals(CPU) && src.getRegisterCategory().equals(XMM);
|
|
|
2421 |
simdPrefix(dst, Register.None, src, PD, P_0F, false);
|
|
|
2422 |
emitByte(0xD7);
|
|
|
2423 |
emitModRM(dst, src);
|
|
|
2424 |
}
|
|
|
2425 |
|
|
49451
|
2426 |
public final void pmovzxbw(Register dst, AMD64Address src) {
|
|
|
2427 |
assert supports(CPUFeature.SSE4_2);
|
|
51436
|
2428 |
assert dst.getRegisterCategory().equals(XMM);
|
|
49451
|
2429 |
// XXX legacy_mode should be: _legacy_mode_bw
|
|
51436
|
2430 |
simdPrefix(dst, Register.None, src, PD, P_0F38, false);
|
|
49451
|
2431 |
emitByte(0x30);
|
|
|
2432 |
emitOperandHelper(dst, src, 0);
|
|
|
2433 |
}
|
|
|
2434 |
|
|
43972
|
2435 |
public final void push(Register src) {
|
|
51436
|
2436 |
prefix(src);
|
|
|
2437 |
emitByte(0x50 + encode(src));
|
|
43972
|
2438 |
}
|
|
|
2439 |
|
|
|
2440 |
public void pushfq() {
|
|
|
2441 |
emitByte(0x9c);
|
|
|
2442 |
}
|
|
|
2443 |
|
|
|
2444 |
public final void paddd(Register dst, Register src) {
|
|
51436
|
2445 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2446 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2447 |
emitByte(0xFE);
|
|
51436
|
2448 |
emitModRM(dst, src);
|
|
43972
|
2449 |
}
|
|
|
2450 |
|
|
|
2451 |
public final void paddq(Register dst, Register src) {
|
|
51436
|
2452 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2453 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2454 |
emitByte(0xD4);
|
|
51436
|
2455 |
emitModRM(dst, src);
|
|
43972
|
2456 |
}
|
|
|
2457 |
|
|
|
2458 |
public final void pextrw(Register dst, Register src, int imm8) {
|
|
51436
|
2459 |
assert dst.getRegisterCategory().equals(CPU) && src.getRegisterCategory().equals(XMM);
|
|
|
2460 |
simdPrefix(dst, Register.None, src, PD, P_0F, false);
|
|
43972
|
2461 |
emitByte(0xC5);
|
|
51436
|
2462 |
emitModRM(dst, src);
|
|
43972
|
2463 |
emitByte(imm8);
|
|
|
2464 |
}
|
|
|
2465 |
|
|
|
2466 |
public final void pinsrw(Register dst, Register src, int imm8) {
|
|
51436
|
2467 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(CPU);
|
|
|
2468 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2469 |
emitByte(0xC4);
|
|
51436
|
2470 |
emitModRM(dst, src);
|
|
43972
|
2471 |
emitByte(imm8);
|
|
|
2472 |
}
|
|
|
2473 |
|
|
|
2474 |
public final void por(Register dst, Register src) {
|
|
51436
|
2475 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2476 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2477 |
emitByte(0xEB);
|
|
51436
|
2478 |
emitModRM(dst, src);
|
|
43972
|
2479 |
}
|
|
|
2480 |
|
|
|
2481 |
public final void pand(Register dst, Register src) {
|
|
51436
|
2482 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2483 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2484 |
emitByte(0xDB);
|
|
51436
|
2485 |
emitModRM(dst, src);
|
|
43972
|
2486 |
}
|
|
|
2487 |
|
|
|
2488 |
public final void pxor(Register dst, Register src) {
|
|
51436
|
2489 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2490 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2491 |
emitByte(0xEF);
|
|
51436
|
2492 |
emitModRM(dst, src);
|
|
49451
|
2493 |
}
|
|
|
2494 |
|
|
43972
|
2495 |
public final void pslld(Register dst, int imm8) {
|
|
|
2496 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2497 |
assert dst.getRegisterCategory().equals(XMM);
|
|
43972
|
2498 |
// XMM6 is for /6 encoding: 66 0F 72 /6 ib
|
|
51436
|
2499 |
simdPrefix(AMD64.xmm6, dst, dst, PD, P_0F, false);
|
|
43972
|
2500 |
emitByte(0x72);
|
|
51436
|
2501 |
emitModRM(6, dst);
|
|
43972
|
2502 |
emitByte(imm8 & 0xFF);
|
|
|
2503 |
}
|
|
|
2504 |
|
|
|
2505 |
public final void psllq(Register dst, Register shift) {
|
|
51436
|
2506 |
assert dst.getRegisterCategory().equals(XMM) && shift.getRegisterCategory().equals(XMM);
|
|
|
2507 |
simdPrefix(dst, dst, shift, PD, P_0F, false);
|
|
43972
|
2508 |
emitByte(0xF3);
|
|
51436
|
2509 |
emitModRM(dst, shift);
|
|
43972
|
2510 |
}
|
|
|
2511 |
|
|
|
2512 |
public final void psllq(Register dst, int imm8) {
|
|
|
2513 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2514 |
assert dst.getRegisterCategory().equals(XMM);
|
|
43972
|
2515 |
// XMM6 is for /6 encoding: 66 0F 73 /6 ib
|
|
51436
|
2516 |
simdPrefix(AMD64.xmm6, dst, dst, PD, P_0F, false);
|
|
43972
|
2517 |
emitByte(0x73);
|
|
51436
|
2518 |
emitModRM(6, dst);
|
|
43972
|
2519 |
emitByte(imm8);
|
|
|
2520 |
}
|
|
|
2521 |
|
|
|
2522 |
public final void psrad(Register dst, int imm8) {
|
|
|
2523 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2524 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
2525 |
// XMM4 is for /4 encoding: 66 0F 72 /4 ib
|
|
|
2526 |
simdPrefix(AMD64.xmm4, dst, dst, PD, P_0F, false);
|
|
43972
|
2527 |
emitByte(0x72);
|
|
51436
|
2528 |
emitModRM(4, dst);
|
|
43972
|
2529 |
emitByte(imm8);
|
|
|
2530 |
}
|
|
|
2531 |
|
|
|
2532 |
public final void psrld(Register dst, int imm8) {
|
|
|
2533 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2534 |
assert dst.getRegisterCategory().equals(XMM);
|
|
43972
|
2535 |
// XMM2 is for /2 encoding: 66 0F 72 /2 ib
|
|
51436
|
2536 |
simdPrefix(AMD64.xmm2, dst, dst, PD, P_0F, false);
|
|
43972
|
2537 |
emitByte(0x72);
|
|
51436
|
2538 |
emitModRM(2, dst);
|
|
43972
|
2539 |
emitByte(imm8);
|
|
|
2540 |
}
|
|
|
2541 |
|
|
|
2542 |
public final void psrlq(Register dst, int imm8) {
|
|
|
2543 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2544 |
assert dst.getRegisterCategory().equals(XMM);
|
|
43972
|
2545 |
// XMM2 is for /2 encoding: 66 0F 73 /2 ib
|
|
51436
|
2546 |
simdPrefix(AMD64.xmm2, dst, dst, PD, P_0F, false);
|
|
43972
|
2547 |
emitByte(0x73);
|
|
51436
|
2548 |
emitModRM(2, dst);
|
|
43972
|
2549 |
emitByte(imm8);
|
|
|
2550 |
}
|
|
|
2551 |
|
|
46344
|
2552 |
public final void psrldq(Register dst, int imm8) {
|
|
|
2553 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2554 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
2555 |
simdPrefix(AMD64.xmm3, dst, dst, PD, P_0F, false);
|
|
46344
|
2556 |
emitByte(0x73);
|
|
51436
|
2557 |
emitModRM(3, dst);
|
|
|
2558 |
emitByte(imm8);
|
|
|
2559 |
}
|
|
|
2560 |
|
|
|
2561 |
public final void pshufb(Register dst, Register src) {
|
|
|
2562 |
assert supports(CPUFeature.SSSE3);
|
|
|
2563 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2564 |
simdPrefix(dst, dst, src, PD, P_0F38, false);
|
|
|
2565 |
emitByte(0x00);
|
|
|
2566 |
emitModRM(dst, src);
|
|
|
2567 |
}
|
|
|
2568 |
|
|
|
2569 |
public final void pshuflw(Register dst, Register src, int imm8) {
|
|
|
2570 |
assert supports(CPUFeature.SSE2);
|
|
|
2571 |
assert isUByte(imm8) : "invalid value";
|
|
|
2572 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2573 |
simdPrefix(dst, Register.None, src, SD, P_0F, false);
|
|
|
2574 |
emitByte(0x70);
|
|
|
2575 |
emitModRM(dst, src);
|
|
46344
|
2576 |
emitByte(imm8);
|
|
|
2577 |
}
|
|
|
2578 |
|
|
43972
|
2579 |
public final void pshufd(Register dst, Register src, int imm8) {
|
|
|
2580 |
assert isUByte(imm8) : "invalid value";
|
|
51436
|
2581 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2582 |
simdPrefix(dst, Register.None, src, PD, P_0F, false);
|
|
43972
|
2583 |
emitByte(0x70);
|
|
51436
|
2584 |
emitModRM(dst, src);
|
|
43972
|
2585 |
emitByte(imm8);
|
|
|
2586 |
}
|
|
|
2587 |
|
|
|
2588 |
public final void psubd(Register dst, Register src) {
|
|
51436
|
2589 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2590 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2591 |
emitByte(0xFA);
|
|
51436
|
2592 |
emitModRM(dst, src);
|
|
43972
|
2593 |
}
|
|
|
2594 |
|
|
|
2595 |
public final void rcpps(Register dst, Register src) {
|
|
51436
|
2596 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2597 |
simdPrefix(dst, Register.None, src, PS, P_0F, false);
|
|
43972
|
2598 |
emitByte(0x53);
|
|
51436
|
2599 |
emitModRM(dst, src);
|
|
43972
|
2600 |
}
|
|
|
2601 |
|
|
|
2602 |
public final void ret(int imm16) {
|
|
|
2603 |
if (imm16 == 0) {
|
|
|
2604 |
emitByte(0xC3);
|
|
|
2605 |
} else {
|
|
|
2606 |
emitByte(0xC2);
|
|
|
2607 |
emitShort(imm16);
|
|
|
2608 |
}
|
|
|
2609 |
}
|
|
|
2610 |
|
|
|
2611 |
public final void sarl(Register dst, int imm8) {
|
|
51436
|
2612 |
prefix(dst);
|
|
43972
|
2613 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
|
2614 |
if (imm8 == 1) {
|
|
|
2615 |
emitByte(0xD1);
|
|
51436
|
2616 |
emitModRM(7, dst);
|
|
43972
|
2617 |
} else {
|
|
|
2618 |
emitByte(0xC1);
|
|
51436
|
2619 |
emitModRM(7, dst);
|
|
43972
|
2620 |
emitByte(imm8);
|
|
|
2621 |
}
|
|
|
2622 |
}
|
|
|
2623 |
|
|
|
2624 |
public final void shll(Register dst, int imm8) {
|
|
|
2625 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
51436
|
2626 |
prefix(dst);
|
|
43972
|
2627 |
if (imm8 == 1) {
|
|
|
2628 |
emitByte(0xD1);
|
|
51436
|
2629 |
emitModRM(4, dst);
|
|
43972
|
2630 |
} else {
|
|
|
2631 |
emitByte(0xC1);
|
|
51436
|
2632 |
emitModRM(4, dst);
|
|
43972
|
2633 |
emitByte(imm8);
|
|
|
2634 |
}
|
|
|
2635 |
}
|
|
|
2636 |
|
|
|
2637 |
public final void shll(Register dst) {
|
|
51436
|
2638 |
// Multiply dst by 2, CL times.
|
|
|
2639 |
prefix(dst);
|
|
43972
|
2640 |
emitByte(0xD3);
|
|
51436
|
2641 |
emitModRM(4, dst);
|
|
43972
|
2642 |
}
|
|
|
2643 |
|
|
|
2644 |
public final void shrl(Register dst, int imm8) {
|
|
|
2645 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
51436
|
2646 |
prefix(dst);
|
|
43972
|
2647 |
emitByte(0xC1);
|
|
51436
|
2648 |
emitModRM(5, dst);
|
|
43972
|
2649 |
emitByte(imm8);
|
|
|
2650 |
}
|
|
|
2651 |
|
|
|
2652 |
public final void shrl(Register dst) {
|
|
51436
|
2653 |
// Unsigned divide dst by 2, CL times.
|
|
|
2654 |
prefix(dst);
|
|
43972
|
2655 |
emitByte(0xD3);
|
|
51436
|
2656 |
emitModRM(5, dst);
|
|
43972
|
2657 |
}
|
|
|
2658 |
|
|
|
2659 |
public final void subl(AMD64Address dst, int imm32) {
|
|
|
2660 |
SUB.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
2661 |
}
|
|
|
2662 |
|
|
|
2663 |
public final void subl(Register dst, int imm32) {
|
|
|
2664 |
SUB.getMIOpcode(DWORD, isByte(imm32)).emit(this, DWORD, dst, imm32);
|
|
|
2665 |
}
|
|
|
2666 |
|
|
|
2667 |
public final void subl(Register dst, Register src) {
|
|
|
2668 |
SUB.rmOp.emit(this, DWORD, dst, src);
|
|
|
2669 |
}
|
|
|
2670 |
|
|
|
2671 |
public final void subpd(Register dst, Register src) {
|
|
51436
|
2672 |
SSEOp.SUB.emit(this, PD, dst, src);
|
|
43972
|
2673 |
}
|
|
|
2674 |
|
|
|
2675 |
public final void subsd(Register dst, Register src) {
|
|
51436
|
2676 |
SSEOp.SUB.emit(this, SD, dst, src);
|
|
43972
|
2677 |
}
|
|
|
2678 |
|
|
|
2679 |
public final void subsd(Register dst, AMD64Address src) {
|
|
51436
|
2680 |
SSEOp.SUB.emit(this, SD, dst, src);
|
|
43972
|
2681 |
}
|
|
|
2682 |
|
|
|
2683 |
public final void testl(Register dst, int imm32) {
|
|
|
2684 |
// not using emitArith because test
|
|
|
2685 |
// doesn't support sign-extension of
|
|
|
2686 |
// 8bit operands
|
|
51436
|
2687 |
if (dst.encoding == 0) {
|
|
43972
|
2688 |
emitByte(0xA9);
|
|
|
2689 |
} else {
|
|
51436
|
2690 |
prefix(dst);
|
|
43972
|
2691 |
emitByte(0xF7);
|
|
51436
|
2692 |
emitModRM(0, dst);
|
|
43972
|
2693 |
}
|
|
|
2694 |
emitInt(imm32);
|
|
|
2695 |
}
|
|
|
2696 |
|
|
|
2697 |
public final void testl(Register dst, Register src) {
|
|
51436
|
2698 |
prefix(dst, src);
|
|
43972
|
2699 |
emitByte(0x85);
|
|
51436
|
2700 |
emitModRM(dst, src);
|
|
43972
|
2701 |
}
|
|
|
2702 |
|
|
|
2703 |
public final void testl(Register dst, AMD64Address src) {
|
|
|
2704 |
prefix(src, dst);
|
|
|
2705 |
emitByte(0x85);
|
|
|
2706 |
emitOperandHelper(dst, src, 0);
|
|
|
2707 |
}
|
|
|
2708 |
|
|
|
2709 |
public final void unpckhpd(Register dst, Register src) {
|
|
51436
|
2710 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2711 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2712 |
emitByte(0x15);
|
|
51436
|
2713 |
emitModRM(dst, src);
|
|
43972
|
2714 |
}
|
|
|
2715 |
|
|
|
2716 |
public final void unpcklpd(Register dst, Register src) {
|
|
51436
|
2717 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2718 |
simdPrefix(dst, dst, src, PD, P_0F, false);
|
|
43972
|
2719 |
emitByte(0x14);
|
|
51436
|
2720 |
emitModRM(dst, src);
|
|
43972
|
2721 |
}
|
|
|
2722 |
|
|
|
2723 |
public final void xorl(Register dst, Register src) {
|
|
|
2724 |
XOR.rmOp.emit(this, DWORD, dst, src);
|
|
|
2725 |
}
|
|
|
2726 |
|
|
|
2727 |
public final void xorpd(Register dst, Register src) {
|
|
51436
|
2728 |
SSEOp.XOR.emit(this, PD, dst, src);
|
|
43972
|
2729 |
}
|
|
|
2730 |
|
|
|
2731 |
public final void xorps(Register dst, Register src) {
|
|
51436
|
2732 |
SSEOp.XOR.emit(this, PS, dst, src);
|
|
43972
|
2733 |
}
|
|
|
2734 |
|
|
|
2735 |
protected final void decl(Register dst) {
|
|
|
2736 |
// Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
|
|
51436
|
2737 |
prefix(dst);
|
|
43972
|
2738 |
emitByte(0xFF);
|
|
51436
|
2739 |
emitModRM(1, dst);
|
|
43972
|
2740 |
}
|
|
|
2741 |
|
|
|
2742 |
protected final void incl(Register dst) {
|
|
|
2743 |
// Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
|
|
51436
|
2744 |
prefix(dst);
|
|
43972
|
2745 |
emitByte(0xFF);
|
|
51436
|
2746 |
emitModRM(0, dst);
|
|
43972
|
2747 |
}
|
|
|
2748 |
|
|
|
2749 |
public final void addq(Register dst, int imm32) {
|
|
|
2750 |
ADD.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
|
2751 |
}
|
|
|
2752 |
|
|
|
2753 |
public final void addq(AMD64Address dst, int imm32) {
|
|
|
2754 |
ADD.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
|
2755 |
}
|
|
|
2756 |
|
|
|
2757 |
public final void addq(Register dst, Register src) {
|
|
|
2758 |
ADD.rmOp.emit(this, QWORD, dst, src);
|
|
|
2759 |
}
|
|
|
2760 |
|
|
|
2761 |
public final void addq(AMD64Address dst, Register src) {
|
|
|
2762 |
ADD.mrOp.emit(this, QWORD, dst, src);
|
|
|
2763 |
}
|
|
|
2764 |
|
|
|
2765 |
public final void andq(Register dst, int imm32) {
|
|
|
2766 |
AND.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
|
2767 |
}
|
|
|
2768 |
|
|
|
2769 |
public final void bsrq(Register dst, Register src) {
|
|
51436
|
2770 |
prefixq(dst, src);
|
|
43972
|
2771 |
emitByte(0x0F);
|
|
|
2772 |
emitByte(0xBD);
|
|
51436
|
2773 |
emitModRM(dst, src);
|
|
43972
|
2774 |
}
|
|
|
2775 |
|
|
|
2776 |
public final void bswapq(Register reg) {
|
|
51436
|
2777 |
prefixq(reg);
|
|
43972
|
2778 |
emitByte(0x0F);
|
|
51436
|
2779 |
emitByte(0xC8 + encode(reg));
|
|
43972
|
2780 |
}
|
|
|
2781 |
|
|
|
2782 |
public final void cdqq() {
|
|
51436
|
2783 |
rexw();
|
|
43972
|
2784 |
emitByte(0x99);
|
|
|
2785 |
}
|
|
|
2786 |
|
|
|
2787 |
public final void cmovq(ConditionFlag cc, Register dst, Register src) {
|
|
51436
|
2788 |
prefixq(dst, src);
|
|
43972
|
2789 |
emitByte(0x0F);
|
|
|
2790 |
emitByte(0x40 | cc.getValue());
|
|
51436
|
2791 |
emitModRM(dst, src);
|
|
43972
|
2792 |
}
|
|
|
2793 |
|
|
47798
|
2794 |
public final void setb(ConditionFlag cc, Register dst) {
|
|
51436
|
2795 |
prefix(dst, true);
|
|
47798
|
2796 |
emitByte(0x0F);
|
|
|
2797 |
emitByte(0x90 | cc.getValue());
|
|
51436
|
2798 |
emitModRM(0, dst);
|
|
47798
|
2799 |
}
|
|
|
2800 |
|
|
43972
|
2801 |
public final void cmovq(ConditionFlag cc, Register dst, AMD64Address src) {
|
|
|
2802 |
prefixq(src, dst);
|
|
|
2803 |
emitByte(0x0F);
|
|
|
2804 |
emitByte(0x40 | cc.getValue());
|
|
|
2805 |
emitOperandHelper(dst, src, 0);
|
|
|
2806 |
}
|
|
|
2807 |
|
|
|
2808 |
public final void cmpq(Register dst, int imm32) {
|
|
|
2809 |
CMP.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
|
2810 |
}
|
|
|
2811 |
|
|
|
2812 |
public final void cmpq(Register dst, Register src) {
|
|
|
2813 |
CMP.rmOp.emit(this, QWORD, dst, src);
|
|
|
2814 |
}
|
|
|
2815 |
|
|
|
2816 |
public final void cmpq(Register dst, AMD64Address src) {
|
|
|
2817 |
CMP.rmOp.emit(this, QWORD, dst, src);
|
|
|
2818 |
}
|
|
|
2819 |
|
|
|
2820 |
public final void cmpxchgq(Register reg, AMD64Address adr) {
|
|
|
2821 |
prefixq(adr, reg);
|
|
|
2822 |
emitByte(0x0F);
|
|
|
2823 |
emitByte(0xB1);
|
|
|
2824 |
emitOperandHelper(reg, adr, 0);
|
|
|
2825 |
}
|
|
|
2826 |
|
|
|
2827 |
public final void cvtdq2pd(Register dst, Register src) {
|
|
51436
|
2828 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2829 |
simdPrefix(dst, Register.None, src, SS, P_0F, false);
|
|
43972
|
2830 |
emitByte(0xE6);
|
|
51436
|
2831 |
emitModRM(dst, src);
|
|
43972
|
2832 |
}
|
|
|
2833 |
|
|
|
2834 |
public final void cvtsi2sdq(Register dst, Register src) {
|
|
51436
|
2835 |
SSEOp.CVTSI2SD.emit(this, QWORD, dst, src);
|
|
43972
|
2836 |
}
|
|
|
2837 |
|
|
|
2838 |
public final void cvttsd2siq(Register dst, Register src) {
|
|
51436
|
2839 |
SSEOp.CVTTSD2SI.emit(this, QWORD, dst, src);
|
|
43972
|
2840 |
}
|
|
|
2841 |
|
|
|
2842 |
public final void cvttpd2dq(Register dst, Register src) {
|
|
51436
|
2843 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2844 |
simdPrefix(dst, Register.None, src, PD, P_0F, false);
|
|
43972
|
2845 |
emitByte(0xE6);
|
|
51436
|
2846 |
emitModRM(dst, src);
|
|
43972
|
2847 |
}
|
|
|
2848 |
|
|
51436
|
2849 |
public final void decq(Register dst) {
|
|
43972
|
2850 |
// Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
|
|
51436
|
2851 |
prefixq(dst);
|
|
43972
|
2852 |
emitByte(0xFF);
|
|
51436
|
2853 |
emitModRM(1, dst);
|
|
43972
|
2854 |
}
|
|
|
2855 |
|
|
|
2856 |
public final void decq(AMD64Address dst) {
|
|
|
2857 |
DEC.emit(this, QWORD, dst);
|
|
|
2858 |
}
|
|
|
2859 |
|
|
|
2860 |
public final void imulq(Register dst, Register src) {
|
|
51436
|
2861 |
prefixq(dst, src);
|
|
43972
|
2862 |
emitByte(0x0F);
|
|
|
2863 |
emitByte(0xAF);
|
|
51436
|
2864 |
emitModRM(dst, src);
|
|
43972
|
2865 |
}
|
|
|
2866 |
|
|
|
2867 |
public final void incq(Register dst) {
|
|
|
2868 |
// Don't use it directly. Use Macroincrementq() instead.
|
|
|
2869 |
// Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
|
|
51436
|
2870 |
prefixq(dst);
|
|
43972
|
2871 |
emitByte(0xFF);
|
|
51436
|
2872 |
emitModRM(0, dst);
|
|
43972
|
2873 |
}
|
|
|
2874 |
|
|
|
2875 |
public final void incq(AMD64Address dst) {
|
|
|
2876 |
INC.emit(this, QWORD, dst);
|
|
|
2877 |
}
|
|
|
2878 |
|
|
|
2879 |
public final void movq(Register dst, long imm64) {
|
|
51436
|
2880 |
movq(dst, imm64, false);
|
|
|
2881 |
}
|
|
|
2882 |
|
|
|
2883 |
public final void movq(Register dst, long imm64, boolean annotateImm) {
|
|
|
2884 |
int insnPos = position();
|
|
|
2885 |
prefixq(dst);
|
|
|
2886 |
emitByte(0xB8 + encode(dst));
|
|
|
2887 |
int immPos = position();
|
|
43972
|
2888 |
emitLong(imm64);
|
|
51436
|
2889 |
int nextInsnPos = position();
|
|
|
2890 |
if (annotateImm && codePatchingAnnotationConsumer != null) {
|
|
|
2891 |
codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
|
|
|
2892 |
}
|
|
43972
|
2893 |
}
|
|
|
2894 |
|
|
|
2895 |
public final void movslq(Register dst, int imm32) {
|
|
51436
|
2896 |
prefixq(dst);
|
|
43972
|
2897 |
emitByte(0xC7);
|
|
51436
|
2898 |
emitModRM(0, dst);
|
|
43972
|
2899 |
emitInt(imm32);
|
|
|
2900 |
}
|
|
|
2901 |
|
|
|
2902 |
public final void movdq(Register dst, AMD64Address src) {
|
|
51436
|
2903 |
AMD64RMOp.MOVQ.emit(this, QWORD, dst, src);
|
|
43972
|
2904 |
}
|
|
|
2905 |
|
|
|
2906 |
public final void movdq(AMD64Address dst, Register src) {
|
|
51436
|
2907 |
AMD64MROp.MOVQ.emit(this, QWORD, dst, src);
|
|
43972
|
2908 |
}
|
|
|
2909 |
|
|
|
2910 |
public final void movdq(Register dst, Register src) {
|
|
51436
|
2911 |
if (dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(CPU)) {
|
|
|
2912 |
AMD64RMOp.MOVQ.emit(this, QWORD, dst, src);
|
|
|
2913 |
} else if (src.getRegisterCategory().equals(XMM) && dst.getRegisterCategory().equals(CPU)) {
|
|
|
2914 |
AMD64MROp.MOVQ.emit(this, QWORD, dst, src);
|
|
43972
|
2915 |
} else {
|
|
|
2916 |
throw new InternalError("should not reach here");
|
|
|
2917 |
}
|
|
|
2918 |
}
|
|
|
2919 |
|
|
|
2920 |
public final void movdl(Register dst, Register src) {
|
|
51436
|
2921 |
if (dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(CPU)) {
|
|
|
2922 |
AMD64RMOp.MOVD.emit(this, DWORD, dst, src);
|
|
|
2923 |
} else if (src.getRegisterCategory().equals(XMM) && dst.getRegisterCategory().equals(CPU)) {
|
|
|
2924 |
AMD64MROp.MOVD.emit(this, DWORD, dst, src);
|
|
43972
|
2925 |
} else {
|
|
|
2926 |
throw new InternalError("should not reach here");
|
|
|
2927 |
}
|
|
|
2928 |
}
|
|
|
2929 |
|
|
46344
|
2930 |
public final void movdl(Register dst, AMD64Address src) {
|
|
51436
|
2931 |
AMD64RMOp.MOVD.emit(this, DWORD, dst, src);
|
|
46344
|
2932 |
}
|
|
|
2933 |
|
|
43972
|
2934 |
public final void movddup(Register dst, Register src) {
|
|
|
2935 |
assert supports(CPUFeature.SSE3);
|
|
51436
|
2936 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2937 |
simdPrefix(dst, Register.None, src, SD, P_0F, false);
|
|
43972
|
2938 |
emitByte(0x12);
|
|
51436
|
2939 |
emitModRM(dst, src);
|
|
43972
|
2940 |
}
|
|
|
2941 |
|
|
|
2942 |
public final void movdqu(Register dst, AMD64Address src) {
|
|
51436
|
2943 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
2944 |
simdPrefix(dst, Register.None, src, SS, P_0F, false);
|
|
43972
|
2945 |
emitByte(0x6F);
|
|
|
2946 |
emitOperandHelper(dst, src, 0);
|
|
|
2947 |
}
|
|
|
2948 |
|
|
|
2949 |
public final void movdqu(Register dst, Register src) {
|
|
51436
|
2950 |
assert dst.getRegisterCategory().equals(XMM) && src.getRegisterCategory().equals(XMM);
|
|
|
2951 |
simdPrefix(dst, Register.None, src, SS, P_0F, false);
|
|
43972
|
2952 |
emitByte(0x6F);
|
|
51436
|
2953 |
emitModRM(dst, src);
|
|
43972
|
2954 |
}
|
|
|
2955 |
|
|
|
2956 |
public final void movslq(AMD64Address dst, int imm32) {
|
|
|
2957 |
prefixq(dst);
|
|
|
2958 |
emitByte(0xC7);
|
|
|
2959 |
emitOperandHelper(0, dst, 4);
|
|
|
2960 |
emitInt(imm32);
|
|
|
2961 |
}
|
|
|
2962 |
|
|
|
2963 |
public final void movslq(Register dst, AMD64Address src) {
|
|
|
2964 |
prefixq(src, dst);
|
|
|
2965 |
emitByte(0x63);
|
|
|
2966 |
emitOperandHelper(dst, src, 0);
|
|
|
2967 |
}
|
|
|
2968 |
|
|
|
2969 |
public final void movslq(Register dst, Register src) {
|
|
51436
|
2970 |
prefixq(dst, src);
|
|
43972
|
2971 |
emitByte(0x63);
|
|
51436
|
2972 |
emitModRM(dst, src);
|
|
43972
|
2973 |
}
|
|
|
2974 |
|
|
|
2975 |
public final void negq(Register dst) {
|
|
51436
|
2976 |
prefixq(dst);
|
|
43972
|
2977 |
emitByte(0xF7);
|
|
51436
|
2978 |
emitModRM(3, dst);
|
|
43972
|
2979 |
}
|
|
|
2980 |
|
|
|
2981 |
public final void orq(Register dst, Register src) {
|
|
|
2982 |
OR.rmOp.emit(this, QWORD, dst, src);
|
|
|
2983 |
}
|
|
|
2984 |
|
|
|
2985 |
public final void shlq(Register dst, int imm8) {
|
|
|
2986 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
51436
|
2987 |
prefixq(dst);
|
|
43972
|
2988 |
if (imm8 == 1) {
|
|
|
2989 |
emitByte(0xD1);
|
|
51436
|
2990 |
emitModRM(4, dst);
|
|
43972
|
2991 |
} else {
|
|
|
2992 |
emitByte(0xC1);
|
|
51436
|
2993 |
emitModRM(4, dst);
|
|
43972
|
2994 |
emitByte(imm8);
|
|
|
2995 |
}
|
|
|
2996 |
}
|
|
|
2997 |
|
|
|
2998 |
public final void shlq(Register dst) {
|
|
51436
|
2999 |
// Multiply dst by 2, CL times.
|
|
|
3000 |
prefixq(dst);
|
|
43972
|
3001 |
emitByte(0xD3);
|
|
51436
|
3002 |
emitModRM(4, dst);
|
|
43972
|
3003 |
}
|
|
|
3004 |
|
|
|
3005 |
public final void shrq(Register dst, int imm8) {
|
|
|
3006 |
assert isShiftCount(imm8 >> 1) : "illegal shift count";
|
|
51436
|
3007 |
prefixq(dst);
|
|
43972
|
3008 |
if (imm8 == 1) {
|
|
|
3009 |
emitByte(0xD1);
|
|
51436
|
3010 |
emitModRM(5, dst);
|
|
43972
|
3011 |
} else {
|
|
|
3012 |
emitByte(0xC1);
|
|
51436
|
3013 |
emitModRM(5, dst);
|
|
43972
|
3014 |
emitByte(imm8);
|
|
|
3015 |
}
|
|
|
3016 |
}
|
|
|
3017 |
|
|
|
3018 |
public final void shrq(Register dst) {
|
|
51436
|
3019 |
prefixq(dst);
|
|
43972
|
3020 |
emitByte(0xD3);
|
|
51436
|
3021 |
// Unsigned divide dst by 2, CL times.
|
|
|
3022 |
emitModRM(5, dst);
|
|
43972
|
3023 |
}
|
|
|
3024 |
|
|
|
3025 |
public final void sbbq(Register dst, Register src) {
|
|
|
3026 |
SBB.rmOp.emit(this, QWORD, dst, src);
|
|
|
3027 |
}
|
|
|
3028 |
|
|
|
3029 |
public final void subq(Register dst, int imm32) {
|
|
|
3030 |
SUB.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
|
3031 |
}
|
|
|
3032 |
|
|
|
3033 |
public final void subq(AMD64Address dst, int imm32) {
|
|
|
3034 |
SUB.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
|
|
|
3035 |
}
|
|
|
3036 |
|
|
|
3037 |
public final void subqWide(Register dst, int imm32) {
|
|
|
3038 |
// don't use the sign-extending version, forcing a 32-bit immediate
|
|
|
3039 |
SUB.getMIOpcode(QWORD, false).emit(this, QWORD, dst, imm32);
|
|
|
3040 |
}
|
|
|
3041 |
|
|
|
3042 |
public final void subq(Register dst, Register src) {
|
|
|
3043 |
SUB.rmOp.emit(this, QWORD, dst, src);
|
|
|
3044 |
}
|
|
|
3045 |
|
|
|
3046 |
public final void testq(Register dst, Register src) {
|
|
51436
|
3047 |
prefixq(dst, src);
|
|
43972
|
3048 |
emitByte(0x85);
|
|
51436
|
3049 |
emitModRM(dst, src);
|
|
43972
|
3050 |
}
|
|
|
3051 |
|
|
46551
|
3052 |
public final void btrq(Register src, int imm8) {
|
|
51436
|
3053 |
prefixq(src);
|
|
46551
|
3054 |
emitByte(0x0F);
|
|
|
3055 |
emitByte(0xBA);
|
|
51436
|
3056 |
emitModRM(6, src);
|
|
46551
|
3057 |
emitByte(imm8);
|
|
|
3058 |
}
|
|
|
3059 |
|
|
50330
|
3060 |
public final void xaddb(AMD64Address dst, Register src) {
|
|
50609
|
3061 |
prefixb(dst, src);
|
|
50330
|
3062 |
emitByte(0x0F);
|
|
|
3063 |
emitByte(0xC0);
|
|
|
3064 |
emitOperandHelper(src, dst, 0);
|
|
|
3065 |
}
|
|
|
3066 |
|
|
|
3067 |
public final void xaddw(AMD64Address dst, Register src) {
|
|
|
3068 |
emitByte(0x66); // Switch to 16-bit mode.
|
|
|
3069 |
prefix(dst, src);
|
|
|
3070 |
emitByte(0x0F);
|
|
|
3071 |
emitByte(0xC1);
|
|
|
3072 |
emitOperandHelper(src, dst, 0);
|
|
|
3073 |
}
|
|
|
3074 |
|
|
43972
|
3075 |
public final void xaddl(AMD64Address dst, Register src) {
|
|
|
3076 |
prefix(dst, src);
|
|
|
3077 |
emitByte(0x0F);
|
|
|
3078 |
emitByte(0xC1);
|
|
|
3079 |
emitOperandHelper(src, dst, 0);
|
|
|
3080 |
}
|
|
|
3081 |
|
|
|
3082 |
public final void xaddq(AMD64Address dst, Register src) {
|
|
|
3083 |
prefixq(dst, src);
|
|
|
3084 |
emitByte(0x0F);
|
|
|
3085 |
emitByte(0xC1);
|
|
|
3086 |
emitOperandHelper(src, dst, 0);
|
|
|
3087 |
}
|
|
|
3088 |
|
|
50330
|
3089 |
public final void xchgb(Register dst, AMD64Address src) {
|
|
50609
|
3090 |
prefixb(src, dst);
|
|
50330
|
3091 |
emitByte(0x86);
|
|
|
3092 |
emitOperandHelper(dst, src, 0);
|
|
|
3093 |
}
|
|
|
3094 |
|
|
|
3095 |
public final void xchgw(Register dst, AMD64Address src) {
|
|
|
3096 |
emitByte(0x66);
|
|
|
3097 |
prefix(src, dst);
|
|
|
3098 |
emitByte(0x87);
|
|
|
3099 |
emitOperandHelper(dst, src, 0);
|
|
|
3100 |
}
|
|
|
3101 |
|
|
43972
|
3102 |
public final void xchgl(Register dst, AMD64Address src) {
|
|
|
3103 |
prefix(src, dst);
|
|
|
3104 |
emitByte(0x87);
|
|
|
3105 |
emitOperandHelper(dst, src, 0);
|
|
|
3106 |
}
|
|
|
3107 |
|
|
|
3108 |
public final void xchgq(Register dst, AMD64Address src) {
|
|
|
3109 |
prefixq(src, dst);
|
|
|
3110 |
emitByte(0x87);
|
|
|
3111 |
emitOperandHelper(dst, src, 0);
|
|
|
3112 |
}
|
|
|
3113 |
|
|
|
3114 |
public final void membar(int barriers) {
|
|
|
3115 |
if (target.isMP) {
|
|
|
3116 |
// We only have to handle StoreLoad
|
|
|
3117 |
if ((barriers & STORE_LOAD) != 0) {
|
|
|
3118 |
// All usable chips support "locked" instructions which suffice
|
|
|
3119 |
// as barriers, and are much faster than the alternative of
|
|
|
3120 |
// using cpuid instruction. We use here a locked add [rsp],0.
|
|
|
3121 |
// This is conveniently otherwise a no-op except for blowing
|
|
|
3122 |
// flags.
|
|
|
3123 |
// Any change to this code may need to revisit other places in
|
|
|
3124 |
// the code where this idiom is used, in particular the
|
|
|
3125 |
// orderAccess code.
|
|
|
3126 |
lock();
|
|
51436
|
3127 |
addl(new AMD64Address(AMD64.rsp, 0), 0); // Assert the lock# signal here
|
|
43972
|
3128 |
}
|
|
|
3129 |
}
|
|
|
3130 |
}
|
|
|
3131 |
|
|
|
3132 |
@Override
|
|
|
3133 |
protected final void patchJumpTarget(int branch, int branchTarget) {
|
|
|
3134 |
int op = getByte(branch);
|
|
|
3135 |
assert op == 0xE8 // call
|
|
|
3136 |
||
|
|
|
3137 |
op == 0x00 // jump table entry
|
|
|
3138 |
|| op == 0xE9 // jmp
|
|
|
3139 |
|| op == 0xEB // short jmp
|
|
|
3140 |
|| (op & 0xF0) == 0x70 // short jcc
|
|
|
3141 |
|| op == 0x0F && (getByte(branch + 1) & 0xF0) == 0x80 // jcc
|
|
|
3142 |
: "Invalid opcode at patch point branch=" + branch + ", branchTarget=" + branchTarget + ", op=" + op;
|
|
|
3143 |
|
|
|
3144 |
if (op == 0x00) {
|
|
|
3145 |
int offsetToJumpTableBase = getShort(branch + 1);
|
|
|
3146 |
int jumpTableBase = branch - offsetToJumpTableBase;
|
|
|
3147 |
int imm32 = branchTarget - jumpTableBase;
|
|
|
3148 |
emitInt(imm32, branch);
|
|
|
3149 |
} else if (op == 0xEB || (op & 0xF0) == 0x70) {
|
|
|
3150 |
|
|
|
3151 |
// short offset operators (jmp and jcc)
|
|
|
3152 |
final int imm8 = branchTarget - (branch + 2);
|
|
|
3153 |
/*
|
|
|
3154 |
* Since a wrongly patched short branch can potentially lead to working but really bad
|
|
|
3155 |
* behaving code we should always fail with an exception instead of having an assert.
|
|
|
3156 |
*/
|
|
|
3157 |
if (!NumUtil.isByte(imm8)) {
|
|
|
3158 |
throw new InternalError("branch displacement out of range: " + imm8);
|
|
|
3159 |
}
|
|
|
3160 |
emitByte(imm8, branch + 1);
|
|
|
3161 |
|
|
|
3162 |
} else {
|
|
|
3163 |
|
|
|
3164 |
int off = 1;
|
|
|
3165 |
if (op == 0x0F) {
|
|
|
3166 |
off = 2;
|
|
|
3167 |
}
|
|
|
3168 |
|
|
|
3169 |
int imm32 = branchTarget - (branch + 4 + off);
|
|
|
3170 |
emitInt(imm32, branch + off);
|
|
|
3171 |
}
|
|
|
3172 |
}
|
|
|
3173 |
|
|
|
3174 |
public void nullCheck(AMD64Address address) {
|
|
|
3175 |
testl(AMD64.rax, address);
|
|
|
3176 |
}
|
|
|
3177 |
|
|
|
3178 |
@Override
|
|
|
3179 |
public void align(int modulus) {
|
|
|
3180 |
if (position() % modulus != 0) {
|
|
|
3181 |
nop(modulus - (position() % modulus));
|
|
|
3182 |
}
|
|
|
3183 |
}
|
|
|
3184 |
|
|
|
3185 |
/**
|
|
|
3186 |
* Emits a direct call instruction. Note that the actual call target is not specified, because
|
|
|
3187 |
* all calls need patching anyway. Therefore, 0 is emitted as the call target, and the user is
|
|
|
3188 |
* responsible to add the call address to the appropriate patching tables.
|
|
|
3189 |
*/
|
|
|
3190 |
public final void call() {
|
|
51436
|
3191 |
annotatePatchingImmediate(1, 4);
|
|
43972
|
3192 |
emitByte(0xE8);
|
|
|
3193 |
emitInt(0);
|
|
|
3194 |
}
|
|
|
3195 |
|
|
|
3196 |
public final void call(Register src) {
|
|
51436
|
3197 |
prefix(src);
|
|
43972
|
3198 |
emitByte(0xFF);
|
|
51436
|
3199 |
emitModRM(2, src);
|
|
43972
|
3200 |
}
|
|
|
3201 |
|
|
|
3202 |
public final void int3() {
|
|
|
3203 |
emitByte(0xCC);
|
|
|
3204 |
}
|
|
|
3205 |
|
|
|
3206 |
public final void pause() {
|
|
|
3207 |
emitByte(0xF3);
|
|
|
3208 |
emitByte(0x90);
|
|
|
3209 |
}
|
|
|
3210 |
|
|
|
3211 |
private void emitx87(int b1, int b2, int i) {
|
|
|
3212 |
assert 0 <= i && i < 8 : "illegal stack offset";
|
|
|
3213 |
emitByte(b1);
|
|
|
3214 |
emitByte(b2 + i);
|
|
|
3215 |
}
|
|
|
3216 |
|
|
|
3217 |
public final void fldd(AMD64Address src) {
|
|
|
3218 |
emitByte(0xDD);
|
|
|
3219 |
emitOperandHelper(0, src, 0);
|
|
|
3220 |
}
|
|
|
3221 |
|
|
|
3222 |
public final void flds(AMD64Address src) {
|
|
|
3223 |
emitByte(0xD9);
|
|
|
3224 |
emitOperandHelper(0, src, 0);
|
|
|
3225 |
}
|
|
|
3226 |
|
|
|
3227 |
public final void fldln2() {
|
|
|
3228 |
emitByte(0xD9);
|
|
|
3229 |
emitByte(0xED);
|
|
|
3230 |
}
|
|
|
3231 |
|
|
|
3232 |
public final void fldlg2() {
|
|
|
3233 |
emitByte(0xD9);
|
|
|
3234 |
emitByte(0xEC);
|
|
|
3235 |
}
|
|
|
3236 |
|
|
|
3237 |
public final void fyl2x() {
|
|
|
3238 |
emitByte(0xD9);
|
|
|
3239 |
emitByte(0xF1);
|
|
|
3240 |
}
|
|
|
3241 |
|
|
|
3242 |
public final void fstps(AMD64Address src) {
|
|
|
3243 |
emitByte(0xD9);
|
|
|
3244 |
emitOperandHelper(3, src, 0);
|
|
|
3245 |
}
|
|
|
3246 |
|
|
|
3247 |
public final void fstpd(AMD64Address src) {
|
|
|
3248 |
emitByte(0xDD);
|
|
|
3249 |
emitOperandHelper(3, src, 0);
|
|
|
3250 |
}
|
|
|
3251 |
|
|
|
3252 |
private void emitFPUArith(int b1, int b2, int i) {
|
|
|
3253 |
assert 0 <= i && i < 8 : "illegal FPU register: " + i;
|
|
|
3254 |
emitByte(b1);
|
|
|
3255 |
emitByte(b2 + i);
|
|
|
3256 |
}
|
|
|
3257 |
|
|
|
3258 |
public void ffree(int i) {
|
|
|
3259 |
emitFPUArith(0xDD, 0xC0, i);
|
|
|
3260 |
}
|
|
|
3261 |
|
|
|
3262 |
public void fincstp() {
|
|
|
3263 |
emitByte(0xD9);
|
|
|
3264 |
emitByte(0xF7);
|
|
|
3265 |
}
|
|
|
3266 |
|
|
|
3267 |
public void fxch(int i) {
|
|
|
3268 |
emitFPUArith(0xD9, 0xC8, i);
|
|
|
3269 |
}
|
|
|
3270 |
|
|
|
3271 |
public void fnstswAX() {
|
|
|
3272 |
emitByte(0xDF);
|
|
|
3273 |
emitByte(0xE0);
|
|
|
3274 |
}
|
|
|
3275 |
|
|
|
3276 |
public void fwait() {
|
|
|
3277 |
emitByte(0x9B);
|
|
|
3278 |
}
|
|
|
3279 |
|
|
|
3280 |
public void fprem() {
|
|
|
3281 |
emitByte(0xD9);
|
|
|
3282 |
emitByte(0xF8);
|
|
|
3283 |
}
|
|
|
3284 |
|
|
|
3285 |
public final void fsin() {
|
|
|
3286 |
emitByte(0xD9);
|
|
|
3287 |
emitByte(0xFE);
|
|
|
3288 |
}
|
|
|
3289 |
|
|
|
3290 |
public final void fcos() {
|
|
|
3291 |
emitByte(0xD9);
|
|
|
3292 |
emitByte(0xFF);
|
|
|
3293 |
}
|
|
|
3294 |
|
|
|
3295 |
public final void fptan() {
|
|
|
3296 |
emitByte(0xD9);
|
|
|
3297 |
emitByte(0xF2);
|
|
|
3298 |
}
|
|
|
3299 |
|
|
|
3300 |
public final void fstp(int i) {
|
|
|
3301 |
emitx87(0xDD, 0xD8, i);
|
|
|
3302 |
}
|
|
|
3303 |
|
|
|
3304 |
@Override
|
|
|
3305 |
public AMD64Address makeAddress(Register base, int displacement) {
|
|
|
3306 |
return new AMD64Address(base, displacement);
|
|
|
3307 |
}
|
|
|
3308 |
|
|
|
3309 |
@Override
|
|
|
3310 |
public AMD64Address getPlaceholder(int instructionStartPosition) {
|
|
51436
|
3311 |
return new AMD64Address(AMD64.rip, Register.None, Scale.Times1, 0, instructionStartPosition);
|
|
43972
|
3312 |
}
|
|
|
3313 |
|
|
|
3314 |
private void prefetchPrefix(AMD64Address src) {
|
|
|
3315 |
prefix(src);
|
|
|
3316 |
emitByte(0x0F);
|
|
|
3317 |
}
|
|
|
3318 |
|
|
|
3319 |
public void prefetchnta(AMD64Address src) {
|
|
|
3320 |
prefetchPrefix(src);
|
|
|
3321 |
emitByte(0x18);
|
|
|
3322 |
emitOperandHelper(0, src, 0);
|
|
|
3323 |
}
|
|
|
3324 |
|
|
|
3325 |
void prefetchr(AMD64Address src) {
|
|
|
3326 |
assert supports(CPUFeature.AMD_3DNOW_PREFETCH);
|
|
|
3327 |
prefetchPrefix(src);
|
|
|
3328 |
emitByte(0x0D);
|
|
|
3329 |
emitOperandHelper(0, src, 0);
|
|
|
3330 |
}
|
|
|
3331 |
|
|
|
3332 |
public void prefetcht0(AMD64Address src) {
|
|
|
3333 |
assert supports(CPUFeature.SSE);
|
|
|
3334 |
prefetchPrefix(src);
|
|
|
3335 |
emitByte(0x18);
|
|
|
3336 |
emitOperandHelper(1, src, 0);
|
|
|
3337 |
}
|
|
|
3338 |
|
|
|
3339 |
public void prefetcht1(AMD64Address src) {
|
|
|
3340 |
assert supports(CPUFeature.SSE);
|
|
|
3341 |
prefetchPrefix(src);
|
|
|
3342 |
emitByte(0x18);
|
|
|
3343 |
emitOperandHelper(2, src, 0);
|
|
|
3344 |
}
|
|
|
3345 |
|
|
|
3346 |
public void prefetcht2(AMD64Address src) {
|
|
|
3347 |
assert supports(CPUFeature.SSE);
|
|
|
3348 |
prefix(src);
|
|
|
3349 |
emitByte(0x0f);
|
|
|
3350 |
emitByte(0x18);
|
|
|
3351 |
emitOperandHelper(3, src, 0);
|
|
|
3352 |
}
|
|
|
3353 |
|
|
|
3354 |
public void prefetchw(AMD64Address src) {
|
|
|
3355 |
assert supports(CPUFeature.AMD_3DNOW_PREFETCH);
|
|
|
3356 |
prefix(src);
|
|
|
3357 |
emitByte(0x0f);
|
|
|
3358 |
emitByte(0x0D);
|
|
|
3359 |
emitOperandHelper(1, src, 0);
|
|
|
3360 |
}
|
|
|
3361 |
|
|
|
3362 |
public void rdtsc() {
|
|
|
3363 |
emitByte(0x0F);
|
|
|
3364 |
emitByte(0x31);
|
|
|
3365 |
}
|
|
|
3366 |
|
|
|
3367 |
/**
|
|
|
3368 |
* Emits an instruction which is considered to be illegal. This is used if we deliberately want
|
|
|
3369 |
* to crash the program (debugging etc.).
|
|
|
3370 |
*/
|
|
|
3371 |
public void illegal() {
|
|
|
3372 |
emitByte(0x0f);
|
|
|
3373 |
emitByte(0x0b);
|
|
|
3374 |
}
|
|
49451
|
3375 |
|
|
|
3376 |
public void lfence() {
|
|
|
3377 |
emitByte(0x0f);
|
|
|
3378 |
emitByte(0xae);
|
|
|
3379 |
emitByte(0xe8);
|
|
51436
|
3380 |
}
|
|
|
3381 |
|
|
|
3382 |
public final void vptest(Register dst, Register src) {
|
|
|
3383 |
VexRMOp.VPTEST.emit(this, AVXSize.YMM, dst, src);
|
|
|
3384 |
}
|
|
|
3385 |
|
|
|
3386 |
public final void vpxor(Register dst, Register nds, Register src) {
|
|
|
3387 |
VexRVMOp.VPXOR.emit(this, AVXSize.YMM, dst, nds, src);
|
|
|
3388 |
}
|
|
|
3389 |
|
|
|
3390 |
public final void vpxor(Register dst, Register nds, AMD64Address src) {
|
|
|
3391 |
VexRVMOp.VPXOR.emit(this, AVXSize.YMM, dst, nds, src);
|
|
|
3392 |
}
|
|
|
3393 |
|
|
|
3394 |
public final void vmovdqu(Register dst, AMD64Address src) {
|
|
|
3395 |
VexMoveOp.VMOVDQU.emit(this, AVXSize.YMM, dst, src);
|
|
|
3396 |
}
|
|
|
3397 |
|
|
|
3398 |
public final void vpmovzxbw(Register dst, AMD64Address src) {
|
|
|
3399 |
VexRMOp.VPMOVZXBW.emit(this, AVXSize.YMM, dst, src);
|
|
|
3400 |
}
|
|
|
3401 |
|
|
|
3402 |
public final void vzeroupper() {
|
|
|
3403 |
emitVEX(L128, P_, M_0F, W0, 0, 0);
|
|
|
3404 |
emitByte(0x77);
|
|
|
3405 |
}
|
|
|
3406 |
|
|
|
3407 |
// This instruction produces ZF or CF flags
|
|
|
3408 |
public final void kortestq(Register src1, Register src2) {
|
|
|
3409 |
assert supports(CPUFeature.AVX512BW);
|
|
|
3410 |
assert src1.getRegisterCategory().equals(MASK) && src2.getRegisterCategory().equals(MASK);
|
|
|
3411 |
vexPrefix(src1, Register.None, src2, AVXSize.XMM, P_, M_0F, W1);
|
|
|
3412 |
emitByte(0x98);
|
|
|
3413 |
emitModRM(src1, src2);
|
|
|
3414 |
}
|
|
|
3415 |
|
|
|
3416 |
public final void kmovq(Register dst, Register src) {
|
|
|
3417 |
assert supports(CPUFeature.AVX512BW);
|
|
|
3418 |
assert dst.getRegisterCategory().equals(MASK) || dst.getRegisterCategory().equals(CPU);
|
|
|
3419 |
assert src.getRegisterCategory().equals(MASK) || src.getRegisterCategory().equals(CPU);
|
|
|
3420 |
assert !(dst.getRegisterCategory().equals(CPU) && src.getRegisterCategory().equals(CPU));
|
|
|
3421 |
|
|
|
3422 |
if (dst.getRegisterCategory().equals(MASK)) {
|
|
|
3423 |
if (src.getRegisterCategory().equals(MASK)) {
|
|
|
3424 |
// kmovq(KRegister dst, KRegister src)
|
|
|
3425 |
vexPrefix(dst, Register.None, src, AVXSize.XMM, P_, M_0F, W1);
|
|
|
3426 |
emitByte(0x90);
|
|
|
3427 |
emitModRM(dst, src);
|
|
|
3428 |
} else {
|
|
|
3429 |
// kmovq(KRegister dst, Register src)
|
|
|
3430 |
vexPrefix(dst, Register.None, src, AVXSize.XMM, P_F2, M_0F, W1);
|
|
|
3431 |
emitByte(0x92);
|
|
|
3432 |
emitModRM(dst, src);
|
|
|
3433 |
}
|
|
|
3434 |
} else {
|
|
|
3435 |
if (src.getRegisterCategory().equals(MASK)) {
|
|
|
3436 |
// kmovq(Register dst, KRegister src)
|
|
|
3437 |
vexPrefix(dst, Register.None, src, AVXSize.XMM, P_F2, M_0F, W1);
|
|
|
3438 |
emitByte(0x93);
|
|
|
3439 |
emitModRM(dst, src);
|
|
|
3440 |
} else {
|
|
|
3441 |
throw GraalError.shouldNotReachHere();
|
|
|
3442 |
}
|
|
|
3443 |
}
|
|
|
3444 |
}
|
|
|
3445 |
|
|
|
3446 |
public final void evmovdqu64(Register dst, AMD64Address src) {
|
|
|
3447 |
assert supports(CPUFeature.AVX512F);
|
|
|
3448 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
3449 |
evexPrefix(dst, Register.None, Register.None, src, AVXSize.ZMM, P_F3, M_0F, W1, Z0, B0);
|
|
|
3450 |
emitByte(0x6F);
|
|
|
3451 |
emitEVEXOperandHelper(dst, src, 0, EVEXTuple.FVM.getDisp8ScalingFactor(AVXSize.ZMM));
|
|
|
3452 |
}
|
|
|
3453 |
|
|
|
3454 |
public final void evpmovzxbw(Register dst, AMD64Address src) {
|
|
|
3455 |
assert supports(CPUFeature.AVX512BW);
|
|
|
3456 |
assert dst.getRegisterCategory().equals(XMM);
|
|
|
3457 |
evexPrefix(dst, Register.None, Register.None, src, AVXSize.ZMM, P_66, M_0F38, WIG, Z0, B0);
|
|
|
3458 |
emitByte(0x30);
|
|
|
3459 |
emitEVEXOperandHelper(dst, src, 0, EVEXTuple.HVM.getDisp8ScalingFactor(AVXSize.ZMM));
|
|
|
3460 |
}
|
|
|
3461 |
|
|
|
3462 |
public final void evpcmpeqb(Register kdst, Register nds, AMD64Address src) {
|
|
|
3463 |
assert supports(CPUFeature.AVX512BW);
|
|
|
3464 |
assert kdst.getRegisterCategory().equals(MASK) && nds.getRegisterCategory().equals(XMM);
|
|
|
3465 |
evexPrefix(kdst, Register.None, nds, src, AVXSize.ZMM, P_66, M_0F, WIG, Z0, B0);
|
|
|
3466 |
emitByte(0x74);
|
|
|
3467 |
emitEVEXOperandHelper(kdst, src, 0, EVEXTuple.FVM.getDisp8ScalingFactor(AVXSize.ZMM));
|
|
49451
|
3468 |
}
|
|
43972
|
3469 |
}
|