/*

 * Copyright (c) 2009, 2016, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 */

package org.graalvm.compiler.asm.amd64;

import static org.graalvm.compiler.core.common.NumUtil.isByte;

import static org.graalvm.compiler.core.common.NumUtil.isInt;

import static org.graalvm.compiler.core.common.NumUtil.isShiftCount;

import static org.graalvm.compiler.core.common.NumUtil.isUByte;

import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseAddressNop;

import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseNormalNop;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.ADD;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.AND;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.CMP;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.OR;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SBB;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.SUB;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.XOR;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.DEC;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.INC;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NEG;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NOT;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.BYTE;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.DWORD;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.PD;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.PS;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.QWORD;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.SD;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.SS;

import static org.graalvm.compiler.asm.amd64.AMD64Assembler.OperandSize.WORD;

import static jdk.vm.ci.amd64.AMD64.CPU;

import static jdk.vm.ci.amd64.AMD64.XMM;

import static jdk.vm.ci.amd64.AMD64.r12;

import static jdk.vm.ci.amd64.AMD64.r13;

import static jdk.vm.ci.amd64.AMD64.rbp;

import static jdk.vm.ci.amd64.AMD64.rip;

import static jdk.vm.ci.amd64.AMD64.rsp;

import static jdk.vm.ci.code.MemoryBarriers.STORE_LOAD;

import org.graalvm.compiler.asm.Assembler;

import org.graalvm.compiler.asm.Label;

import org.graalvm.compiler.core.common.NumUtil;

import org.graalvm.compiler.asm.amd64.AMD64Address.Scale;

import jdk.vm.ci.amd64.AMD64;

import jdk.vm.ci.amd64.AMD64.CPUFeature;

import jdk.vm.ci.code.Register;

import jdk.vm.ci.code.Register.RegisterCategory;

import jdk.vm.ci.code.TargetDescription;

/**

 * This class implements an assembler that can encode most X86 instructions.

 */

public class AMD64Assembler extends Assembler {

    private static final int MinEncodingNeedsRex = 8;

    /**

     * The x86 condition codes used for conditional jumps/moves.

     */

    public enum ConditionFlag {

        Zero(0x4, "|zero|"),

        NotZero(0x5, "|nzero|"),

        Equal(0x4, "="),

        NotEqual(0x5, "!="),

        Less(0xc, "<"),

        LessEqual(0xe, "<="),

        Greater(0xf, ">"),

        GreaterEqual(0xd, ">="),

        Below(0x2, "|<|"),

        BelowEqual(0x6, "|<=|"),

        Above(0x7, "|>|"),

        AboveEqual(0x3, "|>=|"),

        Overflow(0x0, "|of|"),

        NoOverflow(0x1, "|nof|"),

        CarrySet(0x2, "|carry|"),

        CarryClear(0x3, "|ncarry|"),

        Negative(0x8, "|neg|"),

        Positive(0x9, "|pos|"),

        Parity(0xa, "|par|"),

        NoParity(0xb, "|npar|");

        private final int value;

        private final String operator;

        ConditionFlag(int value, String operator) {

            this.value = value;

            this.operator = operator;

        }

        public ConditionFlag negate() {

            switch (this) {

                case Zero:

                    return NotZero;

                case NotZero:

                    return Zero;

                case Equal:

                    return NotEqual;

                case NotEqual:

                    return Equal;

                case Less:

                    return GreaterEqual;

                case LessEqual:

                    return Greater;

                case Greater:

                    return LessEqual;

                case GreaterEqual:

                    return Less;

                case Below:

                    return AboveEqual;

                case BelowEqual:

                    return Above;

                case Above:

                    return BelowEqual;

                case AboveEqual:

                    return Below;

                case Overflow:

                    return NoOverflow;

                case NoOverflow:

                    return Overflow;

                case CarrySet:

                    return CarryClear;

                case CarryClear:

                    return CarrySet;

                case Negative:

                    return Positive;

                case Positive:

                    return Negative;

                case Parity:

                    return NoParity;

                case NoParity:

                    return Parity;

            }

            throw new IllegalArgumentException();

        }

        public int getValue() {

            return value;

        }

        @Override

        public String toString() {

            return operator;

        }

    }

    /**

     * Constants for X86 prefix bytes.

     */

    private static class Prefix {

        private static final int REX = 0x40;

        private static final int REXB = 0x41;

        private static final int REXX = 0x42;

        private static final int REXXB = 0x43;

        private static final int REXR = 0x44;

        private static final int REXRB = 0x45;

        private static final int REXRX = 0x46;

        private static final int REXRXB = 0x47;

        private static final int REXW = 0x48;

        private static final int REXWB = 0x49;

        private static final int REXWX = 0x4A;

        private static final int REXWXB = 0x4B;

        private static final int REXWR = 0x4C;

        private static final int REXWRB = 0x4D;

        private static final int REXWRX = 0x4E;

        private static final int REXWRXB = 0x4F;

        private static final int VEX_3BYTES = 0xC4;

        private static final int VEX_2BYTES = 0xC5;

    }

    private static class VexPrefix {

        private static final int VEX_R = 0x80;

        private static final int VEX_W = 0x80;

    }

    private static class AvxVectorLen {

        private static final int AVX_128bit = 0x0;

        private static final int AVX_256bit = 0x1;

    }

    private static class VexSimdPrefix {

        private static final int VEX_SIMD_NONE = 0x0;

        private static final int VEX_SIMD_66 = 0x1;

        private static final int VEX_SIMD_F3 = 0x2;

        private static final int VEX_SIMD_F2 = 0x3;

    }

    private static class VexOpcode {

        private static final int VEX_OPCODE_NONE = 0x0;

        private static final int VEX_OPCODE_0F = 0x1;

        private static final int VEX_OPCODE_0F_38 = 0x2;

        private static final int VEX_OPCODE_0F_3A = 0x3;

    }

    private AMD64InstructionAttr curAttributes;

    AMD64InstructionAttr getCurAttributes() {

        return curAttributes;

    }

    void setCurAttributes(AMD64InstructionAttr attributes) {

        curAttributes = attributes;

    }

    /**

     * The x86 operand sizes.

     */

    public enum OperandSize {

        BYTE(1) {

            @Override

            protected void emitImmediate(AMD64Assembler asm, int imm) {

                assert imm == (byte) imm;

                asm.emitByte(imm);

            }

            @Override

            protected int immediateSize() {

                return 1;

            }

        },

        WORD(2, 0x66) {

            @Override

            protected void emitImmediate(AMD64Assembler asm, int imm) {

                assert imm == (short) imm;

                asm.emitShort(imm);

            }

            @Override

            protected int immediateSize() {

                return 2;

            }

        },

        DWORD(4) {

            @Override

            protected void emitImmediate(AMD64Assembler asm, int imm) {

                asm.emitInt(imm);

            }

            @Override

            protected int immediateSize() {

                return 4;

            }

        },

        QWORD(8) {

            @Override

            protected void emitImmediate(AMD64Assembler asm, int imm) {

                asm.emitInt(imm);

            }

            @Override

            protected int immediateSize() {

                return 4;

            }

        },

        SS(4, 0xF3, true),

        SD(8, 0xF2, true),

        PS(16, true),

        PD(16, 0x66, true);

        private final int sizePrefix;

        private final int bytes;

        private final boolean xmm;

        OperandSize(int bytes) {

            this(bytes, 0);

        }

        OperandSize(int bytes, int sizePrefix) {

            this(bytes, sizePrefix, false);

        }

        OperandSize(int bytes, boolean xmm) {

            this(bytes, 0, xmm);

        }

        OperandSize(int bytes, int sizePrefix, boolean xmm) {

            this.sizePrefix = sizePrefix;

            this.bytes = bytes;

            this.xmm = xmm;

        }

        public int getBytes() {

            return bytes;

        }

        public boolean isXmmType() {

            return xmm;

        }

        /**

         * Emit an immediate of this size. Note that immediate {@link #QWORD} operands are encoded

         * as sign-extended 32-bit values.

         *

         * @param asm

         * @param imm

         */

        protected void emitImmediate(AMD64Assembler asm, int imm) {

            throw new UnsupportedOperationException();

        }

        protected int immediateSize() {

            throw new UnsupportedOperationException();

        }

    }

    /**

     * Operand size and register type constraints.

     */

    private enum OpAssertion {

        ByteAssertion(CPU, CPU, BYTE),

        IntegerAssertion(CPU, CPU, WORD, DWORD, QWORD),

        No16BitAssertion(CPU, CPU, DWORD, QWORD),

        No32BitAssertion(CPU, CPU, WORD, QWORD),

        QwordOnlyAssertion(CPU, CPU, QWORD),

        FloatingAssertion(XMM, XMM, SS, SD, PS, PD),

        PackedFloatingAssertion(XMM, XMM, PS, PD),

        SingleAssertion(XMM, XMM, SS),

        DoubleAssertion(XMM, XMM, SD),

        PackedDoubleAssertion(XMM, XMM, PD),

        IntToFloatingAssertion(XMM, CPU, DWORD, QWORD),

        FloatingToIntAssertion(CPU, XMM, DWORD, QWORD);

        private final RegisterCategory resultCategory;

        private final RegisterCategory inputCategory;

        private final OperandSize[] allowedSizes;

        OpAssertion(RegisterCategory resultCategory, RegisterCategory inputCategory, OperandSize... allowedSizes) {

            this.resultCategory = resultCategory;

            this.inputCategory = inputCategory;

            this.allowedSizes = allowedSizes;

        }

        protected boolean checkOperands(AMD64Op op, OperandSize size, Register resultReg, Register inputReg) {

            assert resultReg == null || resultCategory.equals(resultReg.getRegisterCategory()) : "invalid result register " + resultReg + " used in " + op;

            assert inputReg == null || inputCategory.equals(inputReg.getRegisterCategory()) : "invalid input register " + inputReg + " used in " + op;

            for (OperandSize s : allowedSizes) {

                if (size == s) {

                    return true;

                }

            }

            assert false : "invalid operand size " + size + " used in " + op;

            return false;

        }

    }

    public abstract static class OperandDataAnnotation extends CodeAnnotation {

        /**

         * The position (bytes from the beginning of the method) of the operand.

         */

        public final int operandPosition;

        /**

         * The size of the operand, in bytes.

         */

        public final int operandSize;

        /**

         * The position (bytes from the beginning of the method) of the next instruction. On AMD64,

         * RIP-relative operands are relative to this position.

         */

        public final int nextInstructionPosition;

        OperandDataAnnotation(int instructionPosition, int operandPosition, int operandSize, int nextInstructionPosition) {

            super(instructionPosition);

            this.operandPosition = operandPosition;

            this.operandSize = operandSize;

            this.nextInstructionPosition = nextInstructionPosition;

        }

        @Override

        public String toString() {

            return getClass().getSimpleName() + " instruction [" + instructionPosition + ", " + nextInstructionPosition + "[ operand at " + operandPosition + " size " + operandSize;

        }

    }

    /**

     * Annotation that stores additional information about the displacement of a

     * {@link Assembler#getPlaceholder placeholder address} that needs patching.

     */

    public static class AddressDisplacementAnnotation extends OperandDataAnnotation {

        AddressDisplacementAnnotation(int instructionPosition, int operandPosition, int operndSize, int nextInstructionPosition) {

            super(instructionPosition, operandPosition, operndSize, nextInstructionPosition);

        }

    }

    /**

     * Annotation that stores additional information about the immediate operand, e.g., of a call

     * instruction, that needs patching.

     */

    public static class ImmediateOperandAnnotation extends OperandDataAnnotation {

        ImmediateOperandAnnotation(int instructionPosition, int operandPosition, int operndSize, int nextInstructionPosition) {

            super(instructionPosition, operandPosition, operndSize, nextInstructionPosition);

        }

    }

    /**

     * Constructs an assembler for the AMD64 architecture.

     */

    public AMD64Assembler(TargetDescription target) {

        super(target);

    }

    public boolean supports(CPUFeature feature) {

        return ((AMD64) target.arch).getFeatures().contains(feature);

    }

    private static int encode(Register r) {

        assert r.encoding < 16 && r.encoding >= 0 : "encoding out of range: " + r.encoding;

        return r.encoding & 0x7;

    }

    /**

     * Get RXB bits for register-register instruction. In that encoding, ModRM.rm contains a

     * register index. The R bit extends the ModRM.reg field and the B bit extends the ModRM.rm

     * field. The X bit must be 0.

     */

    protected static int getRXB(Register reg, Register rm) {

        int rxb = (reg == null ? 0 : reg.encoding & 0x08) >> 1;

        rxb |= (rm == null ? 0 : rm.encoding & 0x08) >> 3;

        return rxb;

    }

    /**

     * Get RXB bits for register-memory instruction. The R bit extends the ModRM.reg field. There

     * are two cases for the memory operand:<br>

     * ModRM.rm contains the base register: In that case, B extends the ModRM.rm field and X = 0.

     * <br>

     * There is an SIB byte: In that case, X extends SIB.index and B extends SIB.base.

     */

    protected static int getRXB(Register reg, AMD64Address rm) {

        int rxb = (reg == null ? 0 : reg.encoding & 0x08) >> 1;

        if (!rm.getIndex().equals(Register.None)) {

            rxb |= (rm.getIndex().encoding & 0x08) >> 2;

        }

        if (!rm.getBase().equals(Register.None)) {

            rxb |= (rm.getBase().encoding & 0x08) >> 3;

        }

        return rxb;

    }

    /**

     * Emit the ModR/M byte for one register operand and an opcode extension in the R field.

     * <p>

     * Format: [ 11 reg r/m ]

     */

    protected void emitModRM(int reg, Register rm) {

        assert (reg & 0x07) == reg;

        emitByte(0xC0 | (reg << 3) | (rm.encoding & 0x07));

    }

    /**

     * Emit the ModR/M byte for two register operands.

     * <p>

     * Format: [ 11 reg r/m ]

     */

    protected void emitModRM(Register reg, Register rm) {

        emitModRM(reg.encoding & 0x07, rm);

    }

    protected void emitOperandHelper(Register reg, AMD64Address addr, int additionalInstructionSize) {

        assert !reg.equals(Register.None);

        emitOperandHelper(encode(reg), addr, false, additionalInstructionSize);

    }

    /**

     * Emits the ModR/M byte and optionally the SIB byte for one register and one memory operand.

     *

     * @param force4Byte use 4 byte encoding for displacements that would normally fit in a byte

     */

    protected void emitOperandHelper(Register reg, AMD64Address addr, boolean force4Byte, int additionalInstructionSize) {

        assert !reg.equals(Register.None);

        emitOperandHelper(encode(reg), addr, force4Byte, additionalInstructionSize);

    }

    protected void emitOperandHelper(int reg, AMD64Address addr, int additionalInstructionSize) {

        emitOperandHelper(reg, addr, false, additionalInstructionSize);

    }

    /**

     * Emits the ModR/M byte and optionally the SIB byte for one memory operand and an opcode

     * extension in the R field.

     *

     * @param force4Byte use 4 byte encoding for displacements that would normally fit in a byte

     * @param additionalInstructionSize the number of bytes that will be emitted after the operand,

     *            so that the start position of the next instruction can be computed even though

     *            this instruction has not been completely emitted yet.

     */

    protected void emitOperandHelper(int reg, AMD64Address addr, boolean force4Byte, int additionalInstructionSize) {

        assert (reg & 0x07) == reg;

        int regenc = reg << 3;

        Register base = addr.getBase();

        Register index = addr.getIndex();

        AMD64Address.Scale scale = addr.getScale();

        int disp = addr.getDisplacement();

        if (base.equals(AMD64.rip)) { // also matches addresses returned by getPlaceholder()

            // [00 000 101] disp32

            assert index.equals(Register.None) : "cannot use RIP relative addressing with index register";