/*

 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/macroAssembler.hpp"

#include "asm/macroAssembler.inline.hpp"

#include "memory/resourceArea.hpp"

#include "runtime/java.hpp"

#include "runtime/os.hpp"

#include "runtime/stubCodeGenerator.hpp"

#include "vm_version_x86.hpp"

int VM_Version::_cpu;

int VM_Version::_model;

int VM_Version::_stepping;

uint64_t VM_Version::_cpuFeatures;

const char*           VM_Version::_features_str = "";

VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };

// Address of instruction which causes SEGV

address VM_Version::_cpuinfo_segv_addr = 0;

// Address of instruction after the one which causes SEGV

address VM_Version::_cpuinfo_cont_addr = 0;

static BufferBlob* stub_blob;

static const int stub_size = 1000;

extern "C" {

  typedef void (*get_cpu_info_stub_t)(void*);

}

static get_cpu_info_stub_t get_cpu_info_stub = NULL;

class VM_Version_StubGenerator: public StubCodeGenerator {

 public:

  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}

  address generate_get_cpu_info() {

    // Flags to test CPU type.

    const uint32_t HS_EFL_AC = 0x40000;

    const uint32_t HS_EFL_ID = 0x200000;

    // Values for when we don't have a CPUID instruction.

    const int      CPU_FAMILY_SHIFT = 8;

    const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);

    const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);

    Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;

    Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;

    Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;

    StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");

#   define __ _masm->

    address start = __ pc();

    //

    // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);

    //

    // LP64: rcx and rdx are first and second argument registers on windows

    __ push(rbp);

#ifdef _LP64

    __ mov(rbp, c_rarg0); // cpuid_info address

#else

    __ movptr(rbp, Address(rsp, 8)); // cpuid_info address

#endif

    __ push(rbx);

    __ push(rsi);

    __ pushf();          // preserve rbx, and flags

    __ pop(rax);

    __ push(rax);

    __ mov(rcx, rax);

    //

    // if we are unable to change the AC flag, we have a 386

    //

    __ xorl(rax, HS_EFL_AC);

    __ push(rax);

    __ popf();

    __ pushf();

    __ pop(rax);

    __ cmpptr(rax, rcx);

    __ jccb(Assembler::notEqual, detect_486);

    __ movl(rax, CPU_FAMILY_386);

    __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);

    __ jmp(done);

    //

    // If we are unable to change the ID flag, we have a 486 which does

    // not support the "cpuid" instruction.

    //

    __ bind(detect_486);

    __ mov(rax, rcx);

    __ xorl(rax, HS_EFL_ID);

    __ push(rax);

    __ popf();

    __ pushf();

    __ pop(rax);

    __ cmpptr(rcx, rax);

    __ jccb(Assembler::notEqual, detect_586);

    __ bind(cpu486);

    __ movl(rax, CPU_FAMILY_486);

    __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);

    __ jmp(done);

    //

    // At this point, we have a chip which supports the "cpuid" instruction

    //

    __ bind(detect_586);

    __ xorl(rax, rax);

    __ cpuid();

    __ orl(rax, rax);

    __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input

                                        // value of at least 1, we give up and

                                        // assume a 486

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?

    __ jccb(Assembler::belowEqual, std_cpuid4);

    //

    // cpuid(0xB) Processor Topology

    //

    __ movl(rax, 0xb);

    __ xorl(rcx, rcx);   // Threads level

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    __ movl(rax, 0xb);

    __ movl(rcx, 1);     // Cores level

    __ cpuid();

    __ push(rax);

    __ andl(rax, 0x1f);  // Determine if valid topology level

    __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level

    __ andl(rax, 0xffff);

    __ pop(rax);

    __ jccb(Assembler::equal, std_cpuid4);

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    __ movl(rax, 0xb);

    __ movl(rcx, 2);     // Packages level

    __ cpuid();

    __ push(rax);

    __ andl(rax, 0x1f);  // Determine if valid topology level

    __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level

    __ andl(rax, 0xffff);

    __ pop(rax);

    __ jccb(Assembler::equal, std_cpuid4);

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // cpuid(0x4) Deterministic cache params

    //

    __ bind(std_cpuid4);

    __ movl(rax, 4);

    __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?

    __ jccb(Assembler::greater, std_cpuid1);

    __ xorl(rcx, rcx);   // L1 cache

    __ cpuid();

    __ push(rax);

    __ andl(rax, 0x1f);  // Determine if valid cache parameters used

    __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache

    __ pop(rax);

    __ jccb(Assembler::equal, std_cpuid1);

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // Standard cpuid(0x1)

    //

    __ bind(std_cpuid1);

    __ movl(rax, 1);

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // Check if OS has enabled XGETBV instruction to access XCR0

    // (OSXSAVE feature flag) and CPU supports AVX

    //

    __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx

    __ cmpl(rcx, 0x18000000);

    __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported

    //

    // XCR0, XFEATURE_ENABLED_MASK register

    //

    __ xorl(rcx, rcx);   // zero for XCR0 register

    __ xgetbv();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rdx);

    //

    // cpuid(0x7) Structured Extended Features

    //

    __ bind(sef_cpuid);

    __ movl(rax, 7);

    __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?

    __ jccb(Assembler::greater, ext_cpuid);

    __ xorl(rcx, rcx);

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    //

    // Extended cpuid(0x80000000)

    //

    __ bind(ext_cpuid);

    __ movl(rax, 0x80000000);

    __ cpuid();

    __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?

    __ jcc(Assembler::belowEqual, done);

    __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?

    __ jccb(Assembler::belowEqual, ext_cpuid1);

    __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?

    __ jccb(Assembler::belowEqual, ext_cpuid5);

    __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?

    __ jccb(Assembler::belowEqual, ext_cpuid7);

    //

    // Extended cpuid(0x80000008)

    //

    __ movl(rax, 0x80000008);

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // Extended cpuid(0x80000007)

    //

    __ bind(ext_cpuid7);

    __ movl(rax, 0x80000007);

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // Extended cpuid(0x80000005)

    //

    __ bind(ext_cpuid5);

    __ movl(rax, 0x80000005);

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // Extended cpuid(0x80000001)

    //

    __ bind(ext_cpuid1);

    __ movl(rax, 0x80000001);

    __ cpuid();

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));

    __ movl(Address(rsi, 0), rax);

    __ movl(Address(rsi, 4), rbx);

    __ movl(Address(rsi, 8), rcx);

    __ movl(Address(rsi,12), rdx);

    //

    // Check if OS has enabled XGETBV instruction to access XCR0

    // (OSXSAVE feature flag) and CPU supports AVX

    //

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));

    __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx

    __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx

    __ cmpl(rcx, 0x18000000);

    __ jccb(Assembler::notEqual, done); // jump if AVX is not supported

    __ movl(rax, 0x6);

    __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm

    __ cmpl(rax, 0x6);

    __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported

    // we need to bridge farther than imm8, so we use this island as a thunk

    __ bind(done);

    __ jmp(wrapup);

    __ bind(start_simd_check);

    //

    // Some OSs have a bug when upper 128/256bits of YMM/ZMM

    // registers are not restored after a signal processing.

    // Generate SEGV here (reference through NULL)

    // and check upper YMM/ZMM bits after it.

    //

    intx saved_useavx = UseAVX;

    intx saved_usesse = UseSSE;

    // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));

    __ movl(rax, 0x10000);

    __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm

    __ cmpl(rax, 0x10000);

    __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported

    // check _cpuid_info.xem_xcr0_eax.bits.opmask

    // check _cpuid_info.xem_xcr0_eax.bits.zmm512

    // check _cpuid_info.xem_xcr0_eax.bits.zmm32

    __ movl(rax, 0xE0);

    __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm

    __ cmpl(rax, 0xE0);

    __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported

    // EVEX setup: run in lowest evex mode

    VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts

    UseAVX = 3;

    UseSSE = 2;

    // load value into all 64 bytes of zmm7 register

    __ movl(rcx, VM_Version::ymm_test_value());

    __ movdl(xmm0, rcx);

    __ movl(rcx, 0xffff);

    __ kmovwl(k1, rcx);

    __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);

    __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);

#ifdef _LP64

    __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);

    __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);

#endif

    VM_Version::clean_cpuFeatures();

    __ jmp(save_restore_except);

    __ bind(legacy_setup);

    // AVX setup

    VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts

    UseAVX = 1;

    UseSSE = 2;

    // load value into all 32 bytes of ymm7 register

    __ movl(rcx, VM_Version::ymm_test_value());

    __ movdl(xmm0, rcx);

    __ pshufd(xmm0, xmm0, 0x00);

    __ vinsertf128h(xmm0, xmm0, xmm0);

    __ vmovdqu(xmm7, xmm0);

#ifdef _LP64

    __ vmovdqu(xmm8, xmm0);

    __ vmovdqu(xmm15, xmm0);

#endif

    VM_Version::clean_cpuFeatures();

    __ bind(save_restore_except);

    __ xorl(rsi, rsi);

    VM_Version::set_cpuinfo_segv_addr(__ pc());

    // Generate SEGV

    __ movl(rax, Address(rsi, 0));

    VM_Version::set_cpuinfo_cont_addr(__ pc());

    // Returns here after signal. Save xmm0 to check it later.

    // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));

    __ movl(rax, 0x10000);

    __ andl(rax, Address(rsi, 4));

    __ cmpl(rax, 0x10000);

    __ jccb(Assembler::notEqual, legacy_save_restore);

    // check _cpuid_info.xem_xcr0_eax.bits.opmask

    // check _cpuid_info.xem_xcr0_eax.bits.zmm512

    // check _cpuid_info.xem_xcr0_eax.bits.zmm32

    __ movl(rax, 0xE0);

    __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm

    __ cmpl(rax, 0xE0);

    __ jccb(Assembler::notEqual, legacy_save_restore);

    // EVEX check: run in lowest evex mode

    VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts

    UseAVX = 3;

    UseSSE = 2;

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));

    __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);

    __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);

#ifdef _LP64

    __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);

    __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);

#endif

    VM_Version::clean_cpuFeatures();

    UseAVX = saved_useavx;

    UseSSE = saved_usesse;

    __ jmp(wrapup);

    __ bind(legacy_save_restore);

    // AVX check

    VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts

    UseAVX = 1;

    UseSSE = 2;

    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));

    __ vmovdqu(Address(rsi, 0), xmm0);

    __ vmovdqu(Address(rsi, 32), xmm7);

#ifdef _LP64

    __ vmovdqu(Address(rsi, 64), xmm8);

    __ vmovdqu(Address(rsi, 96), xmm15);

#endif

    VM_Version::clean_cpuFeatures();

    UseAVX = saved_useavx;

    UseSSE = saved_usesse;

    __ bind(wrapup);

    __ popf();

    __ pop(rsi);

    __ pop(rbx);

    __ pop(rbp);

    __ ret(0);

#   undef __

    return start;

  };

};

void VM_Version::get_processor_features() {

  _cpu = 4; // 486 by default

  _model = 0;

  _stepping = 0;

  _cpuFeatures = 0;

  _logical_processors_per_package = 1;

  // i486 internal cache is both I&D and has a 16-byte line size

  _L1_data_cache_line_size = 16;

  // Get raw processor info

  get_cpu_info_stub(&_cpuid_info);

  assert_is_initialized();

  _cpu = extended_cpu_family();

  _model = extended_cpu_model();

  _stepping = cpu_stepping();

  if (cpu_family() > 4) { // it supports CPUID

    _cpuFeatures = feature_flags();

    // Logical processors are only available on P4s and above,

    // and only if hyperthreading is available.

    _logical_processors_per_package = logical_processor_count();

    _L1_data_cache_line_size = L1_line_size();

  }

  _supports_cx8 = supports_cmpxchg8();

  // xchg and xadd instructions

  _supports_atomic_getset4 = true;

  _supports_atomic_getadd4 = true;

  LP64_ONLY(_supports_atomic_getset8 = true);

  LP64_ONLY(_supports_atomic_getadd8 = true);

#ifdef _LP64

  // OS should support SSE for x64 and hardware should support at least SSE2.

  if (!VM_Version::supports_sse2()) {

    vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");

  }