author | kvn |
Tue, 06 Nov 2012 09:22:55 -0800 | |
changeset 14394 | c76096a5d82b |
parent 14132 | 3c1437abcefd |
child 14626 | 0cf4eccf130f |
permissions | -rw-r--r-- |
2111 | 1 |
/* |
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* Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include "precompiled.hpp" |
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#include "assembler_x86.inline.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "runtime/java.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
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#include "vm_version_x86.hpp" |
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#ifdef TARGET_OS_FAMILY_linux |
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# include "os_linux.inline.hpp" |
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#endif |
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#ifdef TARGET_OS_FAMILY_solaris |
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# include "os_solaris.inline.hpp" |
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#endif |
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#ifdef TARGET_OS_FAMILY_windows |
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# include "os_windows.inline.hpp" |
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#endif |
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#ifdef TARGET_OS_FAMILY_bsd |
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# include "os_bsd.inline.hpp" |
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#endif |
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||
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int VM_Version::_cpu; |
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int VM_Version::_model; |
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int VM_Version::_stepping; |
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int VM_Version::_cpuFeatures; |
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const char* VM_Version::_features_str = ""; |
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VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
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static BufferBlob* stub_blob; |
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static const int stub_size = 550; |
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extern "C" { |
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typedef void (*getPsrInfo_stub_t)(void*); |
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} |
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static getPsrInfo_stub_t getPsrInfo_stub = NULL; |
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class VM_Version_StubGenerator: public StubCodeGenerator { |
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public: |
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VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
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||
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address generate_getPsrInfo() { |
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// Flags to test CPU type. |
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const uint32_t HS_EFL_AC = 0x40000; |
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const uint32_t HS_EFL_ID = 0x200000; |
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// Values for when we don't have a CPUID instruction. |
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const int CPU_FAMILY_SHIFT = 8; |
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const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
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const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
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Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
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Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
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StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); |
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# define __ _masm-> |
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address start = __ pc(); |
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// |
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// void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
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// |
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// LP64: rcx and rdx are first and second argument registers on windows |
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__ push(rbp); |
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#ifdef _LP64 |
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__ mov(rbp, c_rarg0); // cpuid_info address |
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#else |
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__ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
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#endif |
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__ push(rbx); |
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__ push(rsi); |
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__ pushf(); // preserve rbx, and flags |
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__ pop(rax); |
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__ push(rax); |
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__ mov(rcx, rax); |
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// |
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// if we are unable to change the AC flag, we have a 386 |
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// |
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__ xorl(rax, HS_EFL_AC); |
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__ push(rax); |
105 |
__ popf(); |
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__ pushf(); |
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__ pop(rax); |
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__ cmpptr(rax, rcx); |
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__ jccb(Assembler::notEqual, detect_486); |
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110 |
||
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__ movl(rax, CPU_FAMILY_386); |
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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__ jmp(done); |
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115 |
// |
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// If we are unable to change the ID flag, we have a 486 which does |
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// not support the "cpuid" instruction. |
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// |
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__ bind(detect_486); |
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__ mov(rax, rcx); |
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__ xorl(rax, HS_EFL_ID); |
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__ push(rax); |
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__ popf(); |
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__ pushf(); |
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__ pop(rax); |
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__ cmpptr(rcx, rax); |
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__ jccb(Assembler::notEqual, detect_586); |
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128 |
||
129 |
__ bind(cpu486); |
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__ movl(rax, CPU_FAMILY_486); |
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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__ jmp(done); |
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// |
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// At this point, we have a chip which supports the "cpuid" instruction |
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// |
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__ bind(detect_586); |
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__ xorl(rax, rax); |
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__ cpuid(); |
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__ orl(rax, rax); |
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__ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
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// value of at least 1, we give up and |
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// assume a 486 |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
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__ jccb(Assembler::belowEqual, std_cpuid4); |
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// |
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// cpuid(0xB) Processor Topology |
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155 |
// |
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__ movl(rax, 0xb); |
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__ xorl(rcx, rcx); // Threads level |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ movl(rax, 0xb); |
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__ movl(rcx, 1); // Cores level |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid topology level |
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__ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
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__ andl(rax, 0xffff); |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid4); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ movl(rax, 0xb); |
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__ movl(rcx, 2); // Packages level |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid topology level |
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__ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
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__ andl(rax, 0xffff); |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid4); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// cpuid(0x4) Deterministic cache params |
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200 |
// |
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__ bind(std_cpuid4); |
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__ movl(rax, 4); |
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__ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
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__ jccb(Assembler::greater, std_cpuid1); |
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__ xorl(rcx, rcx); // L1 cache |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid cache parameters used |
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__ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid1); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// Standard cpuid(0x1) |
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// |
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__ bind(std_cpuid1); |
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__ movl(rax, 1); |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// Check if OS has enabled XGETBV instruction to access XCR0 |
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// (OSXSAVE feature flag) and CPU supports AVX |
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// |
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__ andl(rcx, 0x18000000); |
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__ cmpl(rcx, 0x18000000); |
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__ jccb(Assembler::notEqual, sef_cpuid); |
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239 |
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// |
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// XCR0, XFEATURE_ENABLED_MASK register |
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// |
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__ xorl(rcx, rcx); // zero for XCR0 register |
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__ xgetbv(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rdx); |
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248 |
||
249 |
// |
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// cpuid(0x7) Structured Extended Features |
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251 |
// |
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252 |
__ bind(sef_cpuid); |
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__ movl(rax, 7); |
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__ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? |
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__ jccb(Assembler::greater, ext_cpuid); |
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256 |
||
257 |
__ xorl(rcx, rcx); |
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__ cpuid(); |
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259 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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261 |
__ movl(Address(rsi, 4), rbx); |
|
262 |
||
263 |
// |
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264 |
// Extended cpuid(0x80000000) |
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265 |
// |
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266 |
__ bind(ext_cpuid); |
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2111 | 267 |
__ movl(rax, 0x80000000); |
268 |
__ cpuid(); |
|
269 |
__ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
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270 |
__ jcc(Assembler::belowEqual, done); |
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271 |
__ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
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272 |
__ jccb(Assembler::belowEqual, ext_cpuid1); |
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__ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid5); |
2111 | 275 |
__ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid7); |
2111 | 277 |
// |
278 |
// Extended cpuid(0x80000008) |
|
279 |
// |
|
280 |
__ movl(rax, 0x80000008); |
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281 |
__ cpuid(); |
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282 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
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283 |
__ movl(Address(rsi, 0), rax); |
|
284 |
__ movl(Address(rsi, 4), rbx); |
|
285 |
__ movl(Address(rsi, 8), rcx); |
|
286 |
__ movl(Address(rsi,12), rdx); |
|
287 |
||
288 |
// |
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// Extended cpuid(0x80000007) |
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// |
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291 |
__ bind(ext_cpuid7); |
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__ movl(rax, 0x80000007); |
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293 |
__ cpuid(); |
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294 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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300 |
// |
2111 | 301 |
// Extended cpuid(0x80000005) |
302 |
// |
|
303 |
__ bind(ext_cpuid5); |
|
304 |
__ movl(rax, 0x80000005); |
|
305 |
__ cpuid(); |
|
306 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
|
307 |
__ movl(Address(rsi, 0), rax); |
|
308 |
__ movl(Address(rsi, 4), rbx); |
|
309 |
__ movl(Address(rsi, 8), rcx); |
|
310 |
__ movl(Address(rsi,12), rdx); |
|
311 |
||
312 |
// |
|
313 |
// Extended cpuid(0x80000001) |
|
314 |
// |
|
315 |
__ bind(ext_cpuid1); |
|
316 |
__ movl(rax, 0x80000001); |
|
317 |
__ cpuid(); |
|
318 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
|
319 |
__ movl(Address(rsi, 0), rax); |
|
320 |
__ movl(Address(rsi, 4), rbx); |
|
321 |
__ movl(Address(rsi, 8), rcx); |
|
322 |
__ movl(Address(rsi,12), rdx); |
|
323 |
||
324 |
// |
|
325 |
// return |
|
326 |
// |
|
327 |
__ bind(done); |
|
328 |
__ popf(); |
|
329 |
__ pop(rsi); |
|
330 |
__ pop(rbx); |
|
331 |
__ pop(rbp); |
|
332 |
__ ret(0); |
|
333 |
||
334 |
# undef __ |
|
335 |
||
336 |
return start; |
|
337 |
}; |
|
338 |
}; |
|
339 |
||
340 |
||
341 |
void VM_Version::get_processor_features() { |
|
342 |
||
343 |
_cpu = 4; // 486 by default |
|
344 |
_model = 0; |
|
345 |
_stepping = 0; |
|
346 |
_cpuFeatures = 0; |
|
347 |
_logical_processors_per_package = 1; |
|
348 |
||
349 |
if (!Use486InstrsOnly) { |
|
350 |
// Get raw processor info |
|
351 |
getPsrInfo_stub(&_cpuid_info); |
|
352 |
assert_is_initialized(); |
|
353 |
_cpu = extended_cpu_family(); |
|
354 |
_model = extended_cpu_model(); |
|
355 |
_stepping = cpu_stepping(); |
|
356 |
||
357 |
if (cpu_family() > 4) { // it supports CPUID |
|
358 |
_cpuFeatures = feature_flags(); |
|
359 |
// Logical processors are only available on P4s and above, |
|
360 |
// and only if hyperthreading is available. |
|
361 |
_logical_processors_per_package = logical_processor_count(); |
|
362 |
} |
|
363 |
} |
|
364 |
||
365 |
_supports_cx8 = supports_cmpxchg8(); |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
366 |
// xchg and xadd instructions |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
367 |
_supports_atomic_getset4 = true; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
368 |
_supports_atomic_getadd4 = true; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
369 |
LP64_ONLY(_supports_atomic_getset8 = true); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
370 |
LP64_ONLY(_supports_atomic_getadd8 = true); |
2111 | 371 |
|
372 |
#ifdef _LP64 |
|
373 |
// OS should support SSE for x64 and hardware should support at least SSE2. |
|
374 |
if (!VM_Version::supports_sse2()) { |
|
375 |
vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
|
376 |
} |
|
4430 | 377 |
// in 64 bit the use of SSE2 is the minimum |
378 |
if (UseSSE < 2) UseSSE = 2; |
|
2111 | 379 |
#endif |
380 |
||
10010
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
381 |
#ifdef AMD64 |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
382 |
// flush_icache_stub have to be generated first. |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
383 |
// That is why Icache line size is hard coded in ICache class, |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
384 |
// see icache_x86.hpp. It is also the reason why we can't use |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
385 |
// clflush instruction in 32-bit VM since it could be running |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
386 |
// on CPU which does not support it. |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
387 |
// |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
388 |
// The only thing we can do is to verify that flushed |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
389 |
// ICache::line_size has correct value. |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
390 |
guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
391 |
// clflush_size is size in quadwords (8 bytes). |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
392 |
guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
393 |
#endif |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
394 |
|
2111 | 395 |
// If the OS doesn't support SSE, we can't use this feature even if the HW does |
396 |
if (!os::supports_sse()) |
|
397 |
_cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
|
398 |
||
399 |
if (UseSSE < 4) { |
|
400 |
_cpuFeatures &= ~CPU_SSE4_1; |
|
401 |
_cpuFeatures &= ~CPU_SSE4_2; |
|
402 |
} |
|
403 |
||
404 |
if (UseSSE < 3) { |
|
405 |
_cpuFeatures &= ~CPU_SSE3; |
|
406 |
_cpuFeatures &= ~CPU_SSSE3; |
|
407 |
_cpuFeatures &= ~CPU_SSE4A; |
|
408 |
} |
|
409 |
||
410 |
if (UseSSE < 2) |
|
411 |
_cpuFeatures &= ~CPU_SSE2; |
|
412 |
||
413 |
if (UseSSE < 1) |
|
414 |
_cpuFeatures &= ~CPU_SSE; |
|
415 |
||
11427 | 416 |
if (UseAVX < 2) |
417 |
_cpuFeatures &= ~CPU_AVX2; |
|
418 |
||
419 |
if (UseAVX < 1) |
|
420 |
_cpuFeatures &= ~CPU_AVX; |
|
421 |
||
14132 | 422 |
if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) |
423 |
_cpuFeatures &= ~CPU_AES; |
|
424 |
||
2111 | 425 |
if (logical_processors_per_package() == 1) { |
426 |
// HT processor could be installed on a system which doesn't support HT. |
|
427 |
_cpuFeatures &= ~CPU_HT; |
|
428 |
} |
|
429 |
||
430 |
char buf[256]; |
|
14132 | 431 |
jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
2111 | 432 |
cores_per_cpu(), threads_per_core(), |
433 |
cpu_family(), _model, _stepping, |
|
434 |
(supports_cmov() ? ", cmov" : ""), |
|
435 |
(supports_cmpxchg8() ? ", cx8" : ""), |
|
436 |
(supports_fxsr() ? ", fxsr" : ""), |
|
437 |
(supports_mmx() ? ", mmx" : ""), |
|
438 |
(supports_sse() ? ", sse" : ""), |
|
439 |
(supports_sse2() ? ", sse2" : ""), |
|
440 |
(supports_sse3() ? ", sse3" : ""), |
|
441 |
(supports_ssse3()? ", ssse3": ""), |
|
442 |
(supports_sse4_1() ? ", sse4.1" : ""), |
|
443 |
(supports_sse4_2() ? ", sse4.2" : ""), |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
444 |
(supports_popcnt() ? ", popcnt" : ""), |
11427 | 445 |
(supports_avx() ? ", avx" : ""), |
446 |
(supports_avx2() ? ", avx2" : ""), |
|
14132 | 447 |
(supports_aes() ? ", aes" : ""), |
2111 | 448 |
(supports_mmx_ext() ? ", mmxext" : ""), |
9135 | 449 |
(supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
450 |
(supports_lzcnt() ? ", lzcnt": ""), |
2111 | 451 |
(supports_sse4a() ? ", sse4a": ""), |
11417
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
452 |
(supports_ht() ? ", ht": ""), |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
453 |
(supports_tsc() ? ", tsc": ""), |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
454 |
(supports_tscinv_bit() ? ", tscinvbit": ""), |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
455 |
(supports_tscinv() ? ", tscinv": "")); |
2111 | 456 |
_features_str = strdup(buf); |
457 |
||
458 |
// UseSSE is set to the smaller of what hardware supports and what |
|
459 |
// the command line requires. I.e., you cannot set UseSSE to 2 on |
|
460 |
// older Pentiums which do not support it. |
|
11427 | 461 |
if (UseSSE > 4) UseSSE=4; |
462 |
if (UseSSE < 0) UseSSE=0; |
|
463 |
if (!supports_sse4_1()) // Drop to 3 if no SSE4 support |
|
2111 | 464 |
UseSSE = MIN2((intx)3,UseSSE); |
11427 | 465 |
if (!supports_sse3()) // Drop to 2 if no SSE3 support |
2111 | 466 |
UseSSE = MIN2((intx)2,UseSSE); |
11427 | 467 |
if (!supports_sse2()) // Drop to 1 if no SSE2 support |
2111 | 468 |
UseSSE = MIN2((intx)1,UseSSE); |
11427 | 469 |
if (!supports_sse ()) // Drop to 0 if no SSE support |
2111 | 470 |
UseSSE = 0; |
471 |
||
11427 | 472 |
if (UseAVX > 2) UseAVX=2; |
473 |
if (UseAVX < 0) UseAVX=0; |
|
474 |
if (!supports_avx2()) // Drop to 1 if no AVX2 support |
|
475 |
UseAVX = MIN2((intx)1,UseAVX); |
|
476 |
if (!supports_avx ()) // Drop to 0 if no AVX support |
|
477 |
UseAVX = 0; |
|
478 |
||
14132 | 479 |
// Use AES instructions if available. |
480 |
if (supports_aes()) { |
|
481 |
if (FLAG_IS_DEFAULT(UseAES)) { |
|
482 |
UseAES = true; |
|
483 |
} |
|
484 |
} else if (UseAES) { |
|
485 |
if (!FLAG_IS_DEFAULT(UseAES)) |
|
486 |
warning("AES instructions not available on this CPU"); |
|
487 |
FLAG_SET_DEFAULT(UseAES, false); |
|
488 |
} |
|
489 |
||
490 |
// The AES intrinsic stubs require AES instruction support (of course) |
|
14394 | 491 |
// but also require AVX and sse3 modes for instructions it use. |
492 |
if (UseAES && (UseAVX > 0) && (UseSSE > 2)) { |
|
14132 | 493 |
if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
494 |
UseAESIntrinsics = true; |
|
495 |
} |
|
496 |
} else if (UseAESIntrinsics) { |
|
497 |
if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) |
|
498 |
warning("AES intrinsics not available on this CPU"); |
|
499 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
|
500 |
} |
|
501 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
502 |
#ifdef COMPILER2 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
503 |
if (UseFPUForSpilling) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
504 |
if (UseSSE < 2) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
505 |
// Only supported with SSE2+ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
506 |
FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
507 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
508 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
509 |
if (MaxVectorSize > 0) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
510 |
if (!is_power_of_2(MaxVectorSize)) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
511 |
warning("MaxVectorSize must be a power of 2"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
512 |
FLAG_SET_DEFAULT(MaxVectorSize, 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
513 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
514 |
if (MaxVectorSize > 32) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
515 |
FLAG_SET_DEFAULT(MaxVectorSize, 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
516 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
517 |
if (MaxVectorSize > 16 && UseAVX == 0) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
518 |
// Only supported with AVX+ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
519 |
FLAG_SET_DEFAULT(MaxVectorSize, 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
520 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
521 |
if (UseSSE < 2) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
522 |
// Only supported with SSE2+ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
523 |
FLAG_SET_DEFAULT(MaxVectorSize, 0); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
524 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
525 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
526 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
527 |
|
2111 | 528 |
// On new cpus instructions which update whole XMM register should be used |
529 |
// to prevent partial register stall due to dependencies on high half. |
|
530 |
// |
|
531 |
// UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
|
532 |
// UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
|
533 |
// UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
|
534 |
// UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
|
535 |
||
536 |
if( is_amd() ) { // AMD cpus specific settings |
|
537 |
if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
|
538 |
// Use it on new AMD cpus starting from Opteron. |
|
539 |
UseAddressNop = true; |
|
540 |
} |
|
541 |
if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
|
542 |
// Use it on new AMD cpus starting from Opteron. |
|
543 |
UseNewLongLShift = true; |
|
544 |
} |
|
545 |
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
546 |
if( supports_sse4a() ) { |
|
547 |
UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
|
548 |
} else { |
|
549 |
UseXmmLoadAndClearUpper = false; |
|
550 |
} |
|
551 |
} |
|
552 |
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
553 |
if( supports_sse4a() ) { |
|
554 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
|
555 |
} else { |
|
556 |
UseXmmRegToRegMoveAll = false; |
|
557 |
} |
|
558 |
} |
|
559 |
if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
|
560 |
if( supports_sse4a() ) { |
|
561 |
UseXmmI2F = true; |
|
562 |
} else { |
|
563 |
UseXmmI2F = false; |
|
564 |
} |
|
565 |
} |
|
566 |
if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
|
567 |
if( supports_sse4a() ) { |
|
568 |
UseXmmI2D = true; |
|
569 |
} else { |
|
570 |
UseXmmI2D = false; |
|
571 |
} |
|
572 |
} |
|
8873 | 573 |
if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
574 |
if( supports_sse4_2() && UseSSE >= 4 ) { |
|
575 |
UseSSE42Intrinsics = true; |
|
576 |
} |
|
577 |
} |
|
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
578 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
579 |
// Use count leading zeros count instruction if available. |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
580 |
if (supports_lzcnt()) { |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
581 |
if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
582 |
UseCountLeadingZerosInstruction = true; |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
583 |
} |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
584 |
} |
8677 | 585 |
|
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
586 |
// some defaults for AMD family 15h |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
587 |
if ( cpu_family() == 0x15 ) { |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
588 |
// On family 15h processors default is no sw prefetch |
8677 | 589 |
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
590 |
AllocatePrefetchStyle = 0; |
|
591 |
} |
|
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
592 |
// Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
593 |
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
594 |
AllocatePrefetchInstr = 3; |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
595 |
} |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
596 |
// On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
13885 | 597 |
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
598 |
UseXMMForArrayCopy = true; |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
599 |
} |
13885 | 600 |
if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
601 |
UseUnalignedLoadStores = true; |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
602 |
} |
8677 | 603 |
} |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
604 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
605 |
#ifdef COMPILER2 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
606 |
if (MaxVectorSize > 16) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
607 |
// Limit vectors size to 16 bytes on current AMD cpus. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
608 |
FLAG_SET_DEFAULT(MaxVectorSize, 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
609 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
610 |
#endif // COMPILER2 |
2111 | 611 |
} |
612 |
||
613 |
if( is_intel() ) { // Intel cpus specific settings |
|
614 |
if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
|
615 |
UseStoreImmI16 = false; // don't use it on Intel cpus |
|
616 |
} |
|
617 |
if( cpu_family() == 6 || cpu_family() == 15 ) { |
|
618 |
if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
|
619 |
// Use it on all Intel cpus starting from PentiumPro |
|
620 |
UseAddressNop = true; |
|
621 |
} |
|
622 |
} |
|
623 |
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
624 |
UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
|
625 |
} |
|
626 |
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
627 |
if( supports_sse3() ) { |
|
628 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
|
629 |
} else { |
|
630 |
UseXmmRegToRegMoveAll = false; |
|
631 |
} |
|
632 |
} |
|
633 |
if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
|
634 |
#ifdef COMPILER2 |
|
635 |
if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
|
636 |
// For new Intel cpus do the next optimization: |
|
637 |
// don't align the beginning of a loop if there are enough instructions |
|
638 |
// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
|
639 |
// in current fetch line (OptoLoopAlignment) or the padding |
|
640 |
// is big (> MaxLoopPad). |
|
641 |
// Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
|
642 |
// generated NOP instructions. 11 is the largest size of one |
|
643 |
// address NOP instruction '0F 1F' (see Assembler::nop(i)). |
|
644 |
MaxLoopPad = 11; |
|
645 |
} |
|
646 |
#endif // COMPILER2 |
|
13885 | 647 |
if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
2111 | 648 |
UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
649 |
} |
|
13885 | 650 |
if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
651 |
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
|
2111 | 652 |
UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
653 |
} |
|
654 |
} |
|
13885 | 655 |
if (supports_sse4_2() && UseSSE >= 4) { |
656 |
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
|
2348 | 657 |
UseSSE42Intrinsics = true; |
658 |
} |
|
659 |
} |
|
2111 | 660 |
} |
661 |
} |
|
662 |
||
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
663 |
// Use population count instruction if available. |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
664 |
if (supports_popcnt()) { |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
665 |
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
666 |
UsePopCountInstruction = true; |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
667 |
} |
11427 | 668 |
} else if (UsePopCountInstruction) { |
669 |
warning("POPCNT instruction is not available on this CPU"); |
|
670 |
FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
671 |
} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
672 |
|
13885 | 673 |
#ifdef COMPILER2 |
674 |
if (FLAG_IS_DEFAULT(AlignVector)) { |
|
675 |
// Modern processors allow misaligned memory operations for vectors. |
|
676 |
AlignVector = !UseUnalignedLoadStores; |
|
677 |
} |
|
678 |
#endif // COMPILER2 |
|
679 |
||
2111 | 680 |
assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
681 |
assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
|
682 |
||
683 |
// set valid Prefetch instruction |
|
684 |
if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
|
685 |
if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
|
9135 | 686 |
if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
687 |
if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; |
|
2111 | 688 |
|
689 |
if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
|
690 |
if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
|
9135 | 691 |
if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
692 |
if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; |
|
2111 | 693 |
|
694 |
// Allocation prefetch settings |
|
10267 | 695 |
intx cache_line_size = prefetch_data_size(); |
2111 | 696 |
if( cache_line_size > AllocatePrefetchStepSize ) |
697 |
AllocatePrefetchStepSize = cache_line_size; |
|
10267 | 698 |
|
2111 | 699 |
assert(AllocatePrefetchLines > 0, "invalid value"); |
10267 | 700 |
if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
701 |
AllocatePrefetchLines = 3; |
|
702 |
assert(AllocateInstancePrefetchLines > 0, "invalid value"); |
|
703 |
if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM |
|
704 |
AllocateInstancePrefetchLines = 1; |
|
2111 | 705 |
|
706 |
AllocatePrefetchDistance = allocate_prefetch_distance(); |
|
707 |
AllocatePrefetchStyle = allocate_prefetch_style(); |
|
708 |
||
5902 | 709 |
if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
710 |
if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core |
|
2111 | 711 |
#ifdef _LP64 |
5902 | 712 |
AllocatePrefetchDistance = 384; |
2111 | 713 |
#else |
5902 | 714 |
AllocatePrefetchDistance = 320; |
2111 | 715 |
#endif |
5902 | 716 |
} |
717 |
if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus |
|
718 |
AllocatePrefetchDistance = 192; |
|
719 |
AllocatePrefetchLines = 4; |
|
6272
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
720 |
#ifdef COMPILER2 |
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
721 |
if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
722 |
FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
723 |
} |
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
724 |
#endif |
5902 | 725 |
} |
2111 | 726 |
} |
727 |
assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
|
728 |
||
729 |
#ifdef _LP64 |
|
730 |
// Prefetch settings |
|
731 |
PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
|
732 |
PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
|
733 |
PrefetchFieldsAhead = prefetch_fields_ahead(); |
|
734 |
#endif |
|
735 |
||
736 |
#ifndef PRODUCT |
|
737 |
if (PrintMiscellaneous && Verbose) { |
|
738 |
tty->print_cr("Logical CPUs per core: %u", |
|
739 |
logical_processors_per_package()); |
|
11427 | 740 |
tty->print("UseSSE=%d",UseSSE); |
741 |
if (UseAVX > 0) { |
|
742 |
tty->print(" UseAVX=%d",UseAVX); |
|
743 |
} |
|
14132 | 744 |
if (UseAES) { |
745 |
tty->print(" UseAES=1"); |
|
746 |
} |
|
11427 | 747 |
tty->cr(); |
10267 | 748 |
tty->print("Allocation"); |
9135 | 749 |
if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
10267 | 750 |
tty->print_cr(": no prefetching"); |
2111 | 751 |
} else { |
10267 | 752 |
tty->print(" prefetching: "); |
9135 | 753 |
if (UseSSE == 0 && supports_3dnow_prefetch()) { |
2111 | 754 |
tty->print("PREFETCHW"); |
755 |
} else if (UseSSE >= 1) { |
|
756 |
if (AllocatePrefetchInstr == 0) { |
|
757 |
tty->print("PREFETCHNTA"); |
|
758 |
} else if (AllocatePrefetchInstr == 1) { |
|
759 |
tty->print("PREFETCHT0"); |
|
760 |
} else if (AllocatePrefetchInstr == 2) { |
|
761 |
tty->print("PREFETCHT2"); |
|
762 |
} else if (AllocatePrefetchInstr == 3) { |
|
763 |
tty->print("PREFETCHW"); |
|
764 |
} |
|
765 |
} |
|
766 |
if (AllocatePrefetchLines > 1) { |
|
10267 | 767 |
tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
2111 | 768 |
} else { |
10267 | 769 |
tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
2111 | 770 |
} |
771 |
} |
|
772 |
||
773 |
if (PrefetchCopyIntervalInBytes > 0) { |
|
774 |
tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); |
|
775 |
} |
|
776 |
if (PrefetchScanIntervalInBytes > 0) { |
|
777 |
tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); |
|
778 |
} |
|
779 |
if (PrefetchFieldsAhead > 0) { |
|
780 |
tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); |
|
781 |
} |
|
782 |
} |
|
783 |
#endif // !PRODUCT |
|
784 |
} |
|
785 |
||
786 |
void VM_Version::initialize() { |
|
787 |
ResourceMark rm; |
|
788 |
// Making this stub must be FIRST use of assembler |
|
789 |
||
790 |
stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); |
|
791 |
if (stub_blob == NULL) { |
|
792 |
vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); |
|
793 |
} |
|
6418 | 794 |
CodeBuffer c(stub_blob); |
2111 | 795 |
VM_Version_StubGenerator g(&c); |
796 |
getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, |
|
797 |
g.generate_getPsrInfo()); |
|
798 |
||
799 |
get_processor_features(); |
|
800 |
} |