hotspot/src/cpu/x86/vm/vm_version_x86.cpp
author kvn
Thu, 03 Sep 2015 15:03:12 -0700
changeset 32581 632402f18fe6
parent 31588 2a864a4a414c
child 32727 320855c2baef
permissions -rw-r--r--
8132081: C2 support for Adler32 on SPARC Summary: Add C2 instrinsic support for Adler32 checksum on SPARC. Reviewed-by: kvn Contributed-by: ahmed.khawaja@oracle.com
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/*
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 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "memory/resourceArea.hpp"
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#include "runtime/java.hpp"
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#include "runtime/os.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "vm_version_x86.hpp"
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int VM_Version::_cpu;
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int VM_Version::_model;
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int VM_Version::_stepping;
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uint64_t VM_Version::_cpuFeatures;
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const char*           VM_Version::_features_str = "";
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VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
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// Address of instruction which causes SEGV
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address VM_Version::_cpuinfo_segv_addr = 0;
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// Address of instruction after the one which causes SEGV
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address VM_Version::_cpuinfo_cont_addr = 0;
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static BufferBlob* stub_blob;
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static const int stub_size = 1000;
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extern "C" {
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  typedef void (*get_cpu_info_stub_t)(void*);
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}
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static get_cpu_info_stub_t get_cpu_info_stub = NULL;
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class VM_Version_StubGenerator: public StubCodeGenerator {
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 public:
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  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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  address generate_get_cpu_info() {
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    // Flags to test CPU type.
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    const uint32_t HS_EFL_AC = 0x40000;
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    const uint32_t HS_EFL_ID = 0x200000;
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    // Values for when we don't have a CPUID instruction.
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    const int      CPU_FAMILY_SHIFT = 8;
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    const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
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    const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
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    Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
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    Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
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    Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
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    StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
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#   define __ _masm->
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    address start = __ pc();
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    //
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    // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
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    //
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    // LP64: rcx and rdx are first and second argument registers on windows
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    __ push(rbp);
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#ifdef _LP64
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    __ mov(rbp, c_rarg0); // cpuid_info address
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#else
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    __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
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#endif
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    __ push(rbx);
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    __ push(rsi);
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    __ pushf();          // preserve rbx, and flags
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    __ pop(rax);
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    __ push(rax);
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    __ mov(rcx, rax);
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    //
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    // if we are unable to change the AC flag, we have a 386
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    //
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    __ xorl(rax, HS_EFL_AC);
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    __ push(rax);
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    __ popf();
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    __ pushf();
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    __ pop(rax);
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    __ cmpptr(rax, rcx);
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    __ jccb(Assembler::notEqual, detect_486);
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    __ movl(rax, CPU_FAMILY_386);
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    __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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    __ jmp(done);
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    //
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    // If we are unable to change the ID flag, we have a 486 which does
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    // not support the "cpuid" instruction.
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    //
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    __ bind(detect_486);
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    __ mov(rax, rcx);
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    __ xorl(rax, HS_EFL_ID);
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    __ push(rax);
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    __ popf();
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    __ pushf();
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    __ pop(rax);
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    __ cmpptr(rcx, rax);
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    __ jccb(Assembler::notEqual, detect_586);
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    __ bind(cpu486);
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    __ movl(rax, CPU_FAMILY_486);
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    __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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    __ jmp(done);
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    //
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    // At this point, we have a chip which supports the "cpuid" instruction
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    //
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    __ bind(detect_586);
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    __ xorl(rax, rax);
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    __ cpuid();
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    __ orl(rax, rax);
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    __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
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                                        // value of at least 1, we give up and
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                                        // assume a 486
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
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    __ jccb(Assembler::belowEqual, std_cpuid4);
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    //
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    // cpuid(0xB) Processor Topology
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    //
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    __ movl(rax, 0xb);
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    __ xorl(rcx, rcx);   // Threads level
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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   161
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    __ movl(rax, 0xb);
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    __ movl(rcx, 1);     // Cores level
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    __ cpuid();
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    __ push(rax);
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    __ andl(rax, 0x1f);  // Determine if valid topology level
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    __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
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    __ andl(rax, 0xffff);
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid4);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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   177
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    __ movl(rax, 0xb);
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    __ movl(rcx, 2);     // Packages level
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    __ cpuid();
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    __ push(rax);
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    __ andl(rax, 0x1f);  // Determine if valid topology level
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    __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
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    __ andl(rax, 0xffff);
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid4);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // cpuid(0x4) Deterministic cache params
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    //
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    __ bind(std_cpuid4);
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    __ movl(rax, 4);
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    __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
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    __ jccb(Assembler::greater, std_cpuid1);
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    __ xorl(rcx, rcx);   // L1 cache
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    __ cpuid();
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    __ push(rax);
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    __ andl(rax, 0x1f);  // Determine if valid cache parameters used
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    __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
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    __ pop(rax);
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    __ jccb(Assembler::equal, std_cpuid1);
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Standard cpuid(0x1)
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    //
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    __ bind(std_cpuid1);
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    __ movl(rax, 1);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    __ movl(Address(rsi, 8), rcx);
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    __ movl(Address(rsi,12), rdx);
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    //
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    // Check if OS has enabled XGETBV instruction to access XCR0
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    // (OSXSAVE feature flag) and CPU supports AVX
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    //
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    __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
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    __ cmpl(rcx, 0x18000000);
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    __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
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    //
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    // XCR0, XFEATURE_ENABLED_MASK register
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    //
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    __ xorl(rcx, rcx);   // zero for XCR0 register
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    __ xgetbv();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rdx);
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    //
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    // cpuid(0x7) Structured Extended Features
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    //
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    __ bind(sef_cpuid);
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    __ movl(rax, 7);
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    __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
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    __ jccb(Assembler::greater, ext_cpuid);
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    __ xorl(rcx, rcx);
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    __ cpuid();
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    __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
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    __ movl(Address(rsi, 0), rax);
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    __ movl(Address(rsi, 4), rbx);
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    //
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    // Extended cpuid(0x80000000)
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    //
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    __ bind(ext_cpuid);
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    __ movl(rax, 0x80000000);
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    __ cpuid();
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    __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
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    __ jcc(Assembler::belowEqual, done);
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    __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid1);
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    __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid5);
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    __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
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    __ jccb(Assembler::belowEqual, ext_cpuid7);
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    //
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    // Extended cpuid(0x80000008)
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    //
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    __ movl(rax, 0x80000008);
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   277
    __ cpuid();
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   278
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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diff changeset
   279
    __ movl(Address(rsi, 0), rax);
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parents:
diff changeset
   280
    __ movl(Address(rsi, 4), rbx);
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parents:
diff changeset
   281
    __ movl(Address(rsi, 8), rcx);
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parents:
diff changeset
   282
    __ movl(Address(rsi,12), rdx);
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parents:
diff changeset
   283
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parents:
diff changeset
   284
    //
11417
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phh
parents: 10565
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   285
    // Extended cpuid(0x80000007)
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phh
parents: 10565
diff changeset
   286
    //
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   287
    __ bind(ext_cpuid7);
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phh
parents: 10565
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   288
    __ movl(rax, 0x80000007);
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parents: 10565
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   289
    __ cpuid();
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parents: 10565
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   290
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   291
    __ movl(Address(rsi, 0), rax);
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phh
parents: 10565
diff changeset
   292
    __ movl(Address(rsi, 4), rbx);
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phh
parents: 10565
diff changeset
   293
    __ movl(Address(rsi, 8), rcx);
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   294
    __ movl(Address(rsi,12), rdx);
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phh
parents: 10565
diff changeset
   295
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   296
    //
2111
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parents:
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   297
    // Extended cpuid(0x80000005)
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parents:
diff changeset
   298
    //
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parents:
diff changeset
   299
    __ bind(ext_cpuid5);
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parents:
diff changeset
   300
    __ movl(rax, 0x80000005);
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parents:
diff changeset
   301
    __ cpuid();
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diff changeset
   302
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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parents:
diff changeset
   303
    __ movl(Address(rsi, 0), rax);
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twisti
parents:
diff changeset
   304
    __ movl(Address(rsi, 4), rbx);
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twisti
parents:
diff changeset
   305
    __ movl(Address(rsi, 8), rcx);
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twisti
parents:
diff changeset
   306
    __ movl(Address(rsi,12), rdx);
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parents:
diff changeset
   307
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parents:
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   308
    //
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twisti
parents:
diff changeset
   309
    // Extended cpuid(0x80000001)
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parents:
diff changeset
   310
    //
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parents:
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   311
    __ bind(ext_cpuid1);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
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parents:
diff changeset
   312
    __ movl(rax, 0x80000001);
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parents:
diff changeset
   313
    __ cpuid();
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parents:
diff changeset
   314
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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parents:
diff changeset
   315
    __ movl(Address(rsi, 0), rax);
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twisti
parents:
diff changeset
   316
    __ movl(Address(rsi, 4), rbx);
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parents:
diff changeset
   317
    __ movl(Address(rsi, 8), rcx);
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parents:
diff changeset
   318
    __ movl(Address(rsi,12), rdx);
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parents:
diff changeset
   319
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parents:
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   320
    //
30624
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kvn
parents: 30227
diff changeset
   321
    // Check if OS has enabled XGETBV instruction to access XCR0
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diff changeset
   322
    // (OSXSAVE feature flag) and CPU supports AVX
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diff changeset
   323
    //
2e1803c8a26d 8076276: Add support for AVX512
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diff changeset
   324
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   325
    __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
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kvn
parents: 30227
diff changeset
   326
    __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
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kvn
parents: 30227
diff changeset
   327
    __ cmpl(rcx, 0x18000000);
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kvn
parents: 30227
diff changeset
   328
    __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
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kvn
parents: 30227
diff changeset
   329
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kvn
parents: 30227
diff changeset
   330
    __ movl(rax, 0x6);
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kvn
parents: 30227
diff changeset
   331
    __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   332
    __ cmpl(rax, 0x6);
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kvn
parents: 30227
diff changeset
   333
    __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   334
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kvn
parents: 30227
diff changeset
   335
    // we need to bridge farther than imm8, so we use this island as a thunk
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kvn
parents: 30227
diff changeset
   336
    __ bind(done);
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kvn
parents: 30227
diff changeset
   337
    __ jmp(wrapup);
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kvn
parents: 30227
diff changeset
   338
2e1803c8a26d 8076276: Add support for AVX512
kvn
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diff changeset
   339
    __ bind(start_simd_check);
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kvn
parents: 30227
diff changeset
   340
    //
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kvn
parents: 30227
diff changeset
   341
    // Some OSs have a bug when upper 128/256bits of YMM/ZMM
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kvn
parents: 30227
diff changeset
   342
    // registers are not restored after a signal processing.
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kvn
parents: 30227
diff changeset
   343
    // Generate SEGV here (reference through NULL)
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diff changeset
   344
    // and check upper YMM/ZMM bits after it.
2111
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   345
    //
30624
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   346
    intx saved_useavx = UseAVX;
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diff changeset
   347
    intx saved_usesse = UseSSE;
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kvn
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diff changeset
   348
    // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   349
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
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kvn
parents: 30227
diff changeset
   350
    __ movl(rax, 0x10000);
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kvn
parents: 30227
diff changeset
   351
    __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   352
    __ cmpl(rax, 0x10000);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   353
    __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   354
    // check _cpuid_info.xem_xcr0_eax.bits.opmask
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kvn
parents: 30227
diff changeset
   355
    // check _cpuid_info.xem_xcr0_eax.bits.zmm512
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   356
    // check _cpuid_info.xem_xcr0_eax.bits.zmm32
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   357
    __ movl(rax, 0xE0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   358
    __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   359
    __ cmpl(rax, 0xE0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   360
    __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   361
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   362
    // EVEX setup: run in lowest evex mode
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   363
    VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   364
    UseAVX = 3;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   365
    UseSSE = 2;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   366
    // load value into all 64 bytes of zmm7 register
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   367
    __ movl(rcx, VM_Version::ymm_test_value());
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   368
    __ movdl(xmm0, rcx);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   369
    __ movl(rcx, 0xffff);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   370
#ifdef _LP64
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kvn
parents: 30227
diff changeset
   371
    __ kmovql(k1, rcx);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   372
#else
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   373
    __ kmovdl(k1, rcx);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   374
#endif
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   375
    __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   376
    __ evmovdqu(xmm7, xmm0, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   377
#ifdef _LP64
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   378
    __ evmovdqu(xmm8, xmm0, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   379
    __ evmovdqu(xmm31, xmm0, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   380
#endif
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   381
    VM_Version::clean_cpuFeatures();
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   382
    __ jmp(save_restore_except);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   383
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   384
    __ bind(legacy_setup);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   385
    // AVX setup
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   386
    VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   387
    UseAVX = 1;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   388
    UseSSE = 2;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   389
    // load value into all 32 bytes of ymm7 register
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   390
    __ movl(rcx, VM_Version::ymm_test_value());
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   391
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   392
    __ movdl(xmm0, rcx);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   393
    __ pshufd(xmm0, xmm0, 0x00);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   394
    __ vinsertf128h(xmm0, xmm0, xmm0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   395
    __ vmovdqu(xmm7, xmm0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   396
#ifdef _LP64
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   397
    __ vmovdqu(xmm8, xmm0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   398
    __ vmovdqu(xmm15, xmm0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   399
#endif
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   400
    VM_Version::clean_cpuFeatures();
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   401
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   402
    __ bind(save_restore_except);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   403
    __ xorl(rsi, rsi);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   404
    VM_Version::set_cpuinfo_segv_addr(__ pc());
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   405
    // Generate SEGV
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   406
    __ movl(rax, Address(rsi, 0));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   407
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   408
    VM_Version::set_cpuinfo_cont_addr(__ pc());
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   409
    // Returns here after signal. Save xmm0 to check it later.
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   410
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   411
    // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   412
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   413
    __ movl(rax, 0x10000);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   414
    __ andl(rax, Address(rsi, 4));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   415
    __ cmpl(rax, 0x10000);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   416
    __ jccb(Assembler::notEqual, legacy_save_restore);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   417
    // check _cpuid_info.xem_xcr0_eax.bits.opmask
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   418
    // check _cpuid_info.xem_xcr0_eax.bits.zmm512
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   419
    // check _cpuid_info.xem_xcr0_eax.bits.zmm32
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   420
    __ movl(rax, 0xE0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   421
    __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   422
    __ cmpl(rax, 0xE0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   423
    __ jccb(Assembler::notEqual, legacy_save_restore);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   424
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   425
    // EVEX check: run in lowest evex mode
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   426
    VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   427
    UseAVX = 3;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   428
    UseSSE = 2;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   429
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   430
    __ evmovdqu(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   431
    __ evmovdqu(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   432
#ifdef _LP64
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   433
    __ evmovdqu(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   434
    __ evmovdqu(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   435
#endif
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   436
    VM_Version::clean_cpuFeatures();
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   437
    UseAVX = saved_useavx;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   438
    UseSSE = saved_usesse;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   439
    __ jmp(wrapup);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   440
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   441
    __ bind(legacy_save_restore);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   442
    // AVX check
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   443
    VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   444
    UseAVX = 1;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   445
    UseSSE = 2;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   446
    __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   447
    __ vmovdqu(Address(rsi, 0), xmm0);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   448
    __ vmovdqu(Address(rsi, 32), xmm7);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   449
#ifdef _LP64
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   450
    __ vmovdqu(Address(rsi, 64), xmm8);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   451
    __ vmovdqu(Address(rsi, 96), xmm15);
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   452
#endif
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   453
    VM_Version::clean_cpuFeatures();
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   454
    UseAVX = saved_useavx;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   455
    UseSSE = saved_usesse;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   456
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   457
    __ bind(wrapup);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   458
    __ popf();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   459
    __ pop(rsi);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   460
    __ pop(rbx);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   461
    __ pop(rbp);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   462
    __ ret(0);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   463
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   464
#   undef __
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   465
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   466
    return start;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   467
  };
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   468
};
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   469
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   470
void VM_Version::get_processor_features() {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   471
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   472
  _cpu = 4; // 486 by default
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   473
  _model = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   474
  _stepping = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   475
  _cpuFeatures = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   476
  _logical_processors_per_package = 1;
25633
4cd9c4622c8c 8049717: expose L1_data_cache_line_size for diagnostic/sanity checks
dcubed
parents: 25468
diff changeset
   477
  // i486 internal cache is both I&D and has a 16-byte line size
4cd9c4622c8c 8049717: expose L1_data_cache_line_size for diagnostic/sanity checks
dcubed
parents: 25468
diff changeset
   478
  _L1_data_cache_line_size = 16;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   479
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   480
  if (!Use486InstrsOnly) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   481
    // Get raw processor info
23527
397b6816032d 8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents: 23491
diff changeset
   482
30143
7e99f2b4bae5 8074860: Structured Exception Catcher missing around CreateJavaVM on Windows
stuefe
parents: 28954
diff changeset
   483
    get_cpu_info_stub(&_cpuid_info);
23527
397b6816032d 8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents: 23491
diff changeset
   484
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   485
    assert_is_initialized();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   486
    _cpu = extended_cpu_family();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   487
    _model = extended_cpu_model();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   488
    _stepping = cpu_stepping();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   489
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   490
    if (cpu_family() > 4) { // it supports CPUID
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   491
      _cpuFeatures = feature_flags();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   492
      // Logical processors are only available on P4s and above,
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   493
      // and only if hyperthreading is available.
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   494
      _logical_processors_per_package = logical_processor_count();
25633
4cd9c4622c8c 8049717: expose L1_data_cache_line_size for diagnostic/sanity checks
dcubed
parents: 25468
diff changeset
   495
      _L1_data_cache_line_size = L1_line_size();
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   496
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   497
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   498
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   499
  _supports_cx8 = supports_cmpxchg8();
13886
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13885
diff changeset
   500
  // xchg and xadd instructions
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13885
diff changeset
   501
  _supports_atomic_getset4 = true;
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13885
diff changeset
   502
  _supports_atomic_getadd4 = true;
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13885
diff changeset
   503
  LP64_ONLY(_supports_atomic_getset8 = true);
8d82c4dfa722 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 13885
diff changeset
   504
  LP64_ONLY(_supports_atomic_getadd8 = true);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   505
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   506
#ifdef _LP64
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   507
  // OS should support SSE for x64 and hardware should support at least SSE2.
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   508
  if (!VM_Version::supports_sse2()) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   509
    vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   510
  }
4430
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 2862
diff changeset
   511
  // in 64 bit the use of SSE2 is the minimum
95b539dfa1e8 6769124: various 64-bit fixes for c1
roland
parents: 2862
diff changeset
   512
  if (UseSSE < 2) UseSSE = 2;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   513
#endif
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   514
10010
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   515
#ifdef AMD64
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   516
  // flush_icache_stub have to be generated first.
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   517
  // That is why Icache line size is hard coded in ICache class,
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   518
  // see icache_x86.hpp. It is also the reason why we can't use
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   519
  // clflush instruction in 32-bit VM since it could be running
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   520
  // on CPU which does not support it.
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   521
  //
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   522
  // The only thing we can do is to verify that flushed
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   523
  // ICache::line_size has correct value.
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   524
  guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   525
  // clflush_size is size in quadwords (8 bytes).
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   526
  guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   527
#endif
72de7c910672 6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents: 9325
diff changeset
   528
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   529
  // If the OS doesn't support SSE, we can't use this feature even if the HW does
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   530
  if (!os::supports_sse())
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   531
    _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   532
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   533
  if (UseSSE < 4) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   534
    _cpuFeatures &= ~CPU_SSE4_1;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   535
    _cpuFeatures &= ~CPU_SSE4_2;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   536
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   537
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   538
  if (UseSSE < 3) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   539
    _cpuFeatures &= ~CPU_SSE3;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   540
    _cpuFeatures &= ~CPU_SSSE3;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   541
    _cpuFeatures &= ~CPU_SSE4A;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   542
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   543
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   544
  if (UseSSE < 2)
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   545
    _cpuFeatures &= ~CPU_SSE2;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   546
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   547
  if (UseSSE < 1)
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   548
    _cpuFeatures &= ~CPU_SSE;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   549
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   550
  // first try initial setting and detect what we can support
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   551
  if (UseAVX > 0) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   552
    if (UseAVX > 2 && supports_evex()) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   553
      UseAVX = 3;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   554
    } else if (UseAVX > 1 && supports_avx2()) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   555
      UseAVX = 2;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   556
    } else if (UseAVX > 0 && supports_avx()) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   557
      UseAVX = 1;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   558
    } else {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   559
      UseAVX = 0;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   560
    }
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   561
  } else if (UseAVX < 0) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   562
    UseAVX = 0;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   563
  }
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   564
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   565
  if (UseAVX < 3) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   566
    _cpuFeatures &= ~CPU_AVX512F;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   567
    _cpuFeatures &= ~CPU_AVX512DQ;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   568
    _cpuFeatures &= ~CPU_AVX512CD;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   569
    _cpuFeatures &= ~CPU_AVX512BW;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   570
    _cpuFeatures &= ~CPU_AVX512VL;
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   571
  }
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   572
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   573
  if (UseAVX < 2)
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   574
    _cpuFeatures &= ~CPU_AVX2;
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   575
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   576
  if (UseAVX < 1)
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   577
    _cpuFeatures &= ~CPU_AVX;
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   578
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   579
  if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   580
    _cpuFeatures &= ~CPU_AES;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   581
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   582
  if (logical_processors_per_package() == 1) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   583
    // HT processor could be installed on a system which doesn't support HT.
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   584
    _cpuFeatures &= ~CPU_HT;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   585
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   586
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   587
  char buf[256];
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   588
  jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   589
               cores_per_cpu(), threads_per_core(),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   590
               cpu_family(), _model, _stepping,
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   591
               (supports_cmov() ? ", cmov" : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   592
               (supports_cmpxchg8() ? ", cx8" : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   593
               (supports_fxsr() ? ", fxsr" : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   594
               (supports_mmx()  ? ", mmx"  : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   595
               (supports_sse()  ? ", sse"  : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   596
               (supports_sse2() ? ", sse2" : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   597
               (supports_sse3() ? ", sse3" : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   598
               (supports_ssse3()? ", ssse3": ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   599
               (supports_sse4_1() ? ", sse4.1" : ""),
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   600
               (supports_sse4_2() ? ", sse4.2" : ""),
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
   601
               (supports_popcnt() ? ", popcnt" : ""),
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   602
               (supports_avx()    ? ", avx" : ""),
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   603
               (supports_avx2()   ? ", avx2" : ""),
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   604
               (supports_aes()    ? ", aes" : ""),
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   605
               (supports_clmul()  ? ", clmul" : ""),
15114
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
   606
               (supports_erms()   ? ", erms" : ""),
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   607
               (supports_rtm()    ? ", rtm" : ""),
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   608
               (supports_mmx_ext() ? ", mmxext" : ""),
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
   609
               (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   610
               (supports_lzcnt()   ? ", lzcnt": ""),
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   611
               (supports_sse4a()   ? ", sse4a": ""),
11417
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   612
               (supports_ht() ? ", ht": ""),
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   613
               (supports_tsc() ? ", tsc": ""),
4ecc3253bec4 7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents: 10565
diff changeset
   614
               (supports_tscinv_bit() ? ", tscinvbit": ""),
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
   615
               (supports_tscinv() ? ", tscinv": ""),
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
   616
               (supports_bmi1() ? ", bmi1" : ""),
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   617
               (supports_bmi2() ? ", bmi2" : ""),
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   618
               (supports_adx() ? ", adx" : ""),
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   619
               (supports_evex() ? ", evex" : ""));
25949
34557722059b 6424123: JVM crashes on failed 'strdup' call
zgu
parents: 25932
diff changeset
   620
  _features_str = os::strdup(buf);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   621
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   622
  // UseSSE is set to the smaller of what hardware supports and what
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   623
  // the command line requires.  I.e., you cannot set UseSSE to 2 on
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   624
  // older Pentiums which do not support it.
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   625
  if (UseSSE > 4) UseSSE=4;
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   626
  if (UseSSE < 0) UseSSE=0;
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   627
  if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   628
    UseSSE = MIN2((intx)3,UseSSE);
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   629
  if (!supports_sse3()) // Drop to 2 if no SSE3 support
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   630
    UseSSE = MIN2((intx)2,UseSSE);
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   631
  if (!supports_sse2()) // Drop to 1 if no SSE2 support
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   632
    UseSSE = MIN2((intx)1,UseSSE);
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
   633
  if (!supports_sse ()) // Drop to 0 if no SSE  support
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   634
    UseSSE = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   635
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   636
  // Use AES instructions if available.
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   637
  if (supports_aes()) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   638
    if (FLAG_IS_DEFAULT(UseAES)) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   639
      UseAES = true;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   640
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   641
  } else if (UseAES) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   642
    if (!FLAG_IS_DEFAULT(UseAES))
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   643
      warning("AES instructions are not available on this CPU");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   644
    FLAG_SET_DEFAULT(UseAES, false);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   645
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   646
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   647
  // Use CLMUL instructions if available.
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   648
  if (supports_clmul()) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   649
    if (FLAG_IS_DEFAULT(UseCLMUL)) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   650
      UseCLMUL = true;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   651
    }
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   652
  } else if (UseCLMUL) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   653
    if (!FLAG_IS_DEFAULT(UseCLMUL))
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   654
      warning("CLMUL instructions not available on this CPU (AVX may also be required)");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   655
    FLAG_SET_DEFAULT(UseCLMUL, false);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   656
  }
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   657
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
   658
  if (UseCLMUL && (UseSSE > 2)) {
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   659
    if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   660
      UseCRC32Intrinsics = true;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   661
    }
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   662
  } else if (UseCRC32Intrinsics) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   663
    if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   664
      warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   665
    FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   666
  }
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 15243
diff changeset
   667
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   668
  // The AES intrinsic stubs require AES instruction support (of course)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14626
diff changeset
   669
  // but also require sse3 mode for instructions it use.
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14626
diff changeset
   670
  if (UseAES && (UseSSE > 2)) {
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   671
    if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   672
      UseAESIntrinsics = true;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   673
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   674
  } else if (UseAESIntrinsics) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   675
    if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   676
      warning("AES intrinsics are not available on this CPU");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   677
    FLAG_SET_DEFAULT(UseAESIntrinsics, false);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   678
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
   679
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   680
  // GHASH/GCM intrinsics
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   681
  if (UseCLMUL && (UseSSE > 2)) {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   682
    if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   683
      UseGHASHIntrinsics = true;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   684
    }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   685
  } else if (UseGHASHIntrinsics) {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   686
    if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   687
      warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   688
    FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   689
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
   690
24953
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   691
  if (UseSHA) {
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   692
    warning("SHA instructions are not available on this CPU");
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   693
    FLAG_SET_DEFAULT(UseSHA, false);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   694
  }
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   695
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   696
  if (UseSHA1Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   697
    warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
24953
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   698
    FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   699
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   700
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   701
  if (UseSHA256Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   702
    warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
24953
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   703
    FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
31588
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   704
  }
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   705
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   706
  if (UseSHA512Intrinsics) {
2a864a4a414c 8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents: 31584
diff changeset
   707
    warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
24953
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   708
    FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   709
  }
9680119572be 8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents: 24424
diff changeset
   710
31515
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   711
  if (UseCRC32CIntrinsics) {
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   712
    if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   713
      warning("CRC32C intrinsics are not available on this CPU");
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   714
    FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   715
  }
6aed85dadbe6 8073583: C2 support for CRC32C on SPARC
kvn
parents: 31404
diff changeset
   716
32581
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31588
diff changeset
   717
  if (UseAdler32Intrinsics) {
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31588
diff changeset
   718
    warning("Adler32Intrinsics not available on this CPU.");
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31588
diff changeset
   719
    FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31588
diff changeset
   720
  }
632402f18fe6 8132081: C2 support for Adler32 on SPARC
kvn
parents: 31588
diff changeset
   721
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   722
  // Adjust RTM (Restricted Transactional Memory) flags
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   723
  if (!supports_rtm() && UseRTMLocking) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   724
    // Can't continue because UseRTMLocking affects UseBiasedLocking flag
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   725
    // setting during arguments processing. See use_biased_locking().
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   726
    // VM_Version_init() is executed after UseBiasedLocking is used
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   727
    // in Thread::allocate().
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   728
    vm_exit_during_initialization("RTM instructions are not available on this CPU");
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   729
  }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   730
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   731
#if INCLUDE_RTM_OPT
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   732
  if (UseRTMLocking) {
26306
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   733
    if (is_intel_family_core()) {
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   734
      if ((_model == CPU_MODEL_HASWELL_E3) ||
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   735
          (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   736
          (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   737
        // currently a collision between SKL and HSW_E3
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   738
        if (!UnlockExperimentalVMOptions && UseAVX < 3) {
26306
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   739
          vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   740
        } else {
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   741
          warning("UseRTMLocking is only available as experimental option on this platform.");
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   742
        }
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   743
      }
2b4cf8eb3de7 8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents: 25949
diff changeset
   744
    }
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   745
    if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   746
      // RTM locking should be used only for applications with
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   747
      // high lock contention. For now we do not use it by default.
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   748
      vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   749
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   750
    if (!is_power_of_2(RTMTotalCountIncrRate)) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   751
      warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   752
      FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   753
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   754
    if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   755
      warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   756
      FLAG_SET_DEFAULT(RTMAbortRatio, 50);
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   757
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   758
  } else { // !UseRTMLocking
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   759
    if (UseRTMForStackLocks) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   760
      if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   761
        warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   762
      }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   763
      FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   764
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   765
    if (UseRTMDeopt) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   766
      FLAG_SET_DEFAULT(UseRTMDeopt, false);
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   767
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   768
    if (PrintPreciseRTMLockingStatistics) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   769
      FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   770
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   771
  }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   772
#else
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   773
  if (UseRTMLocking) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   774
    // Only C2 does RTM locking optimization.
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   775
    // Can't continue because UseRTMLocking affects UseBiasedLocking flag
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   776
    // setting during arguments processing. See use_biased_locking().
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   777
    vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   778
  }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   779
#endif
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
   780
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   781
#ifdef COMPILER2
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   782
  if (UseFPUForSpilling) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   783
    if (UseSSE < 2) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   784
      // Only supported with SSE2+
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   785
      FLAG_SET_DEFAULT(UseFPUForSpilling, false);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   786
    }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   787
  }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   788
  if (MaxVectorSize > 0) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   789
    if (!is_power_of_2(MaxVectorSize)) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   790
      warning("MaxVectorSize must be a power of 2");
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   791
      FLAG_SET_DEFAULT(MaxVectorSize, 64);
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   792
    }
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   793
    if (MaxVectorSize > 64) {
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30227
diff changeset
   794
      FLAG_SET_DEFAULT(MaxVectorSize, 64);
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   795
    }
23487
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   796
    if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   797
      // 32 bytes vectors (in YMM) are only supported with AVX+
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   798
      FLAG_SET_DEFAULT(MaxVectorSize, 16);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   799
    }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   800
    if (UseSSE < 2) {
23487
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   801
      // Vectors (in XMM) are only supported with SSE2+
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   802
      FLAG_SET_DEFAULT(MaxVectorSize, 0);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   803
    }
23487
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   804
#ifdef ASSERT
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   805
    if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   806
      tty->print_cr("State of YMM registers after signal handle:");
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   807
      int nreg = 2 LP64_ONLY(+2);
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   808
      const char* ymm_name[4] = {"0", "7", "8", "15"};
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   809
      for (int i = 0; i < nreg; i++) {
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   810
        tty->print("YMM%s:", ymm_name[i]);
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   811
        for (int j = 7; j >=0; j--) {
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   812
          tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   813
        }
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   814
        tty->cr();
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   815
      }
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   816
    }
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
   817
#endif
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   818
  }
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   819
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   820
#ifdef _LP64
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   821
  if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   822
    UseMultiplyToLenIntrinsic = true;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   823
  }
31129
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   824
  if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   825
    UseSquareToLenIntrinsic = true;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   826
  }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   827
  if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   828
    UseMulAddIntrinsic = true;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   829
  }
31583
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   830
  if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   831
    UseMontgomeryMultiplyIntrinsic = true;
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   832
  }
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   833
  if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   834
    UseMontgomerySquareIntrinsic = true;
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   835
  }
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   836
#else
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   837
  if (UseMultiplyToLenIntrinsic) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   838
    if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   839
      warning("multiplyToLen intrinsic is not available in 32-bit VM");
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   840
    }
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   841
    FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   842
  }
31583
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   843
  if (UseMontgomeryMultiplyIntrinsic) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   844
    if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   845
      warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   846
    }
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   847
    FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   848
  }
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   849
  if (UseMontgomerySquareIntrinsic) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   850
    if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   851
      warning("montgomerySquare intrinsic is not available in 32-bit VM");
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   852
    }
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   853
    FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
   854
  }
31129
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   855
  if (UseSquareToLenIntrinsic) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   856
    if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   857
      warning("squareToLen intrinsic is not available in 32-bit VM");
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   858
    }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   859
    FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   860
  }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   861
  if (UseMulAddIntrinsic) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   862
    if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   863
      warning("mulAdd intrinsic is not available in 32-bit VM");
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   864
    }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   865
    FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
   866
  }
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   867
#endif
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
   868
#endif // COMPILER2
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   869
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   870
  // On new cpus instructions which update whole XMM register should be used
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   871
  // to prevent partial register stall due to dependencies on high half.
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   872
  //
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   873
  // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   874
  // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   875
  // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   876
  // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   877
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   878
  if( is_amd() ) { // AMD cpus specific settings
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   879
    if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   880
      // Use it on new AMD cpus starting from Opteron.
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   881
      UseAddressNop = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   882
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   883
    if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   884
      // Use it on new AMD cpus starting from Opteron.
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   885
      UseNewLongLShift = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   886
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   887
    if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   888
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   889
        UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   890
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   891
        UseXmmLoadAndClearUpper = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   892
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   893
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   894
    if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   895
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   896
        UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   897
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   898
        UseXmmRegToRegMoveAll = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   899
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   900
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   901
    if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   902
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   903
        UseXmmI2F = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   904
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   905
        UseXmmI2F = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   906
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   907
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   908
    if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   909
      if( supports_sse4a() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   910
        UseXmmI2D = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   911
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   912
        UseXmmI2D = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   913
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   914
    }
8873
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   915
    if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   916
      if( supports_sse4_2() && UseSSE >= 4 ) {
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   917
        UseSSE42Intrinsics = true;
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   918
      }
d3031147b912 7032133: Enable sse4.2 for new AMD processors
kvn
parents: 8677
diff changeset
   919
    }
2862
fad636edf18f 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 2348
diff changeset
   920
9325
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   921
    // some defaults for AMD family 15h
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   922
    if ( cpu_family() == 0x15 ) {
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   923
      // On family 15h processors default is no sw prefetch
8677
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   924
      if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   925
        AllocatePrefetchStyle = 0;
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   926
      }
9325
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   927
      // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   928
      if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   929
        AllocatePrefetchInstr = 3;
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   930
      }
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   931
      // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
13885
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   932
      if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
9325
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   933
        UseXMMForArrayCopy = true;
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   934
      }
13885
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   935
      if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
9325
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   936
        UseUnalignedLoadStores = true;
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   937
      }
8677
45d01baba334 7028394: Newer AMD Processor Prefetch Defaults
kvn
parents: 7397
diff changeset
   938
    }
9325
2b95b2b2b60f 7037812: few more defaults changes for new AMD processors
kvn
parents: 9135
diff changeset
   939
13104
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   940
#ifdef COMPILER2
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   941
    if (MaxVectorSize > 16) {
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   942
      // Limit vectors size to 16 bytes on current AMD cpus.
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   943
      FLAG_SET_DEFAULT(MaxVectorSize, 16);
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   944
    }
657b387034fb 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 11881
diff changeset
   945
#endif // COMPILER2
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   946
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   947
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   948
  if( is_intel() ) { // Intel cpus specific settings
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   949
    if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   950
      UseStoreImmI16 = false; // don't use it on Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   951
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   952
    if( cpu_family() == 6 || cpu_family() == 15 ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   953
      if( FLAG_IS_DEFAULT(UseAddressNop) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   954
        // Use it on all Intel cpus starting from PentiumPro
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   955
        UseAddressNop = true;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   956
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   957
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   958
    if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   959
      UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   960
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   961
    if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   962
      if( supports_sse3() ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   963
        UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   964
      } else {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   965
        UseXmmRegToRegMoveAll = false;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   966
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   967
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   968
    if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   969
#ifdef COMPILER2
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   970
      if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   971
        // For new Intel cpus do the next optimization:
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   972
        // don't align the beginning of a loop if there are enough instructions
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   973
        // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   974
        // in current fetch line (OptoLoopAlignment) or the padding
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   975
        // is big (> MaxLoopPad).
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   976
        // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   977
        // generated NOP instructions. 11 is the largest size of one
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   978
        // address NOP instruction '0F 1F' (see Assembler::nop(i)).
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   979
        MaxLoopPad = 11;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   980
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   981
#endif // COMPILER2
13885
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   982
      if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   983
        UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   984
      }
13885
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   985
      if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   986
        if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   987
          UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   988
        }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   989
      }
13885
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   990
      if (supports_sse4_2() && UseSSE >= 4) {
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
   991
        if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
2348
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   992
          UseSSE42Intrinsics = true;
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   993
        }
4e71ed4c2709 6761600: Use sse 4.2 in intrinsics
cfang
parents: 2255
diff changeset
   994
      }
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
   995
    }
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
   996
    if ((cpu_family() == 0x06) &&
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
   997
        ((extended_cpu_model() == 0x36) || // Centerton
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
   998
         (extended_cpu_model() == 0x37) || // Silvermont
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
   999
         (extended_cpu_model() == 0x4D))) {
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1000
#ifdef COMPILER2
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1001
      if (FLAG_IS_DEFAULT(OptoScheduling)) {
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1002
        OptoScheduling = true;
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1003
      }
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1004
#endif
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1005
      if (supports_sse4_2()) { // Silvermont
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1006
        if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1007
          UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1008
        }
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1009
      }
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1010
    }
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1011
    if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1012
      AllocatePrefetchInstr = 3;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1013
    }
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1014
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1015
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1016
  // Use count leading zeros count instruction if available.
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1017
  if (supports_lzcnt()) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1018
    if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1019
      UseCountLeadingZerosInstruction = true;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1020
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1021
   } else if (UseCountLeadingZerosInstruction) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1022
    warning("lzcnt instruction is not available on this CPU");
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1023
    FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1024
  }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1025
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1026
  // Use count trailing zeros instruction if available
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1027
  if (supports_bmi1()) {
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1028
    // tzcnt does not require VEX prefix
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1029
    if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
27414
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1030
      if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1031
        // Don't use tzcnt if BMI1 is switched off on command line.
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1032
        UseCountTrailingZerosInstruction = false;
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1033
      } else {
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1034
        UseCountTrailingZerosInstruction = true;
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1035
      }
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1036
    }
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1037
  } else if (UseCountTrailingZerosInstruction) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1038
    warning("tzcnt instruction is not available on this CPU");
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1039
    FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1040
  }
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1041
27414
39d976b80fb4 8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents: 26434
diff changeset
  1042
  // BMI instructions (except tzcnt) use an encoding with VEX prefix.
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1043
  // VEX prefix is generated only when AVX > 0.
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1044
  if (supports_bmi1() && supports_avx()) {
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1045
    if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1046
      UseBMI1Instructions = true;
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1047
    }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1048
  } else if (UseBMI1Instructions) {
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1049
    warning("BMI1 instructions are not available on this CPU (AVX is also required)");
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1050
    FLAG_SET_DEFAULT(UseBMI1Instructions, false);
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1051
  }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1052
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1053
  if (supports_bmi2() && supports_avx()) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1054
    if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1055
      UseBMI2Instructions = true;
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1056
    }
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1057
  } else if (UseBMI2Instructions) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1058
    warning("BMI2 instructions are not available on this CPU (AVX is also required)");
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 26306
diff changeset
  1059
    FLAG_SET_DEFAULT(UseBMI2Instructions, false);
23220
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1060
  }
fc827339dc37 8031321: Support Intel bit manipulation instructions
iveresov
parents: 18507
diff changeset
  1061
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1062
  // Use population count instruction if available.
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1063
  if (supports_popcnt()) {
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1064
    if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1065
      UsePopCountInstruction = true;
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1066
    }
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
  1067
  } else if (UsePopCountInstruction) {
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
  1068
    warning("POPCNT instruction is not available on this CPU");
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
  1069
    FLAG_SET_DEFAULT(UsePopCountInstruction, false);
2255
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1070
  }
54abdf3e1055 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 2111
diff changeset
  1071
15114
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1072
  // Use fast-string operations if available.
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1073
  if (supports_erms()) {
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1074
    if (FLAG_IS_DEFAULT(UseFastStosb)) {
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1075
      UseFastStosb = true;
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1076
    }
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1077
  } else if (UseFastStosb) {
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1078
    warning("fast-string operations are not available on this CPU");
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1079
    FLAG_SET_DEFAULT(UseFastStosb, false);
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1080
  }
4074553c678b 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 14834
diff changeset
  1081
13885
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1082
#ifdef COMPILER2
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1083
  if (FLAG_IS_DEFAULT(AlignVector)) {
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1084
    // Modern processors allow misaligned memory operations for vectors.
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1085
    AlignVector = !UseUnalignedLoadStores;
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1086
  }
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1087
#endif // COMPILER2
6b056026ecad 7199010: incorrect vector alignment
kvn
parents: 13294
diff changeset
  1088
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1089
  assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1090
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1091
  // set valid Prefetch instruction
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1092
  if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1093
  if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
  1094
  if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
  1095
  if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1096
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1097
  // Allocation prefetch settings
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1098
  intx cache_line_size = prefetch_data_size();
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1099
  if( cache_line_size > AllocatePrefetchStepSize )
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1100
    AllocatePrefetchStepSize = cache_line_size;
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1101
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1102
  assert(AllocatePrefetchLines > 0, "invalid value");
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1103
  if( AllocatePrefetchLines < 1 )     // set valid value in product VM
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1104
    AllocatePrefetchLines = 3;
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1105
  assert(AllocateInstancePrefetchLines > 0, "invalid value");
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1106
  if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1107
    AllocateInstancePrefetchLines = 1;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1108
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1109
  AllocatePrefetchDistance = allocate_prefetch_distance();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1110
  AllocatePrefetchStyle    = allocate_prefetch_style();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1111
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1112
  if (is_intel() && cpu_family() == 6 && supports_sse3()) {
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1113
    if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1114
#ifdef _LP64
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
  1115
      AllocatePrefetchDistance = 384;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1116
#else
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
  1117
      AllocatePrefetchDistance = 320;
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1118
#endif
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
  1119
    }
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1120
    if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
5902
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
  1121
      AllocatePrefetchDistance = 192;
ba0c3b725081 6964774: Adjust optimization flags setting
kvn
parents: 5547
diff changeset
  1122
      AllocatePrefetchLines = 4;
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1123
    }
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
  1124
#ifdef COMPILER2
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1125
    if (supports_sse4_2()) {
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1126
      if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
  1127
        FLAG_SET_DEFAULT(UseFPUForSpilling, true);
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
  1128
      }
25932
15d133edd8f6 8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents: 25633
diff changeset
  1129
    }
6272
94a20ad0e9de 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 5902
diff changeset
  1130
#endif
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1131
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1132
  assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1133
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1134
#ifdef _LP64
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1135
  // Prefetch settings
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1136
  PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1137
  PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1138
  PrefetchFieldsAhead         = prefetch_fields_ahead();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1139
#endif
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1140
15193
8e6b5694267f 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 14834
diff changeset
  1141
  if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
8e6b5694267f 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 14834
diff changeset
  1142
     (cache_line_size > ContendedPaddingWidth))
8e6b5694267f 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 14834
diff changeset
  1143
     ContendedPaddingWidth = cache_line_size;
8e6b5694267f 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 14834
diff changeset
  1144
30209
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 28954
diff changeset
  1145
  // This machine allows unaligned memory accesses
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 28954
diff changeset
  1146
  if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 28954
diff changeset
  1147
    FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 28954
diff changeset
  1148
  }
8ea30dc99369 8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents: 28954
diff changeset
  1149
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1150
#ifndef PRODUCT
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1151
  if (PrintMiscellaneous && Verbose) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1152
    tty->print_cr("Logical CPUs per core: %u",
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1153
                  logical_processors_per_package());
25633
4cd9c4622c8c 8049717: expose L1_data_cache_line_size for diagnostic/sanity checks
dcubed
parents: 25468
diff changeset
  1154
    tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1155
    tty->print("UseSSE=%d", (int) UseSSE);
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
  1156
    if (UseAVX > 0) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1157
      tty->print("  UseAVX=%d", (int) UseAVX);
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
  1158
    }
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
  1159
    if (UseAES) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
  1160
      tty->print("  UseAES=1");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13886
diff changeset
  1161
    }
23487
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
  1162
#ifdef COMPILER2
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
  1163
    if (MaxVectorSize > 0) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1164
      tty->print("  MaxVectorSize=%d", (int) MaxVectorSize);
23487
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
  1165
    }
0f7e268cd9e3 8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents: 23220
diff changeset
  1166
#endif
11427
bf248009cbbe 7116452: Add support for AVX instructions
kvn
parents: 10565
diff changeset
  1167
    tty->cr();
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1168
    tty->print("Allocation");
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
  1169
    if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1170
      tty->print_cr(": no prefetching");
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1171
    } else {
10267
8bdeec886dc4 7079329: Adjust allocation prefetching for T4
kvn
parents: 10010
diff changeset
  1172
      tty->print(" prefetching: ");
9135
f76543993e9d 7035713: 3DNow Prefetch Instruction Support
kvn
parents: 8921
diff changeset
  1173
      if (UseSSE == 0 && supports_3dnow_prefetch()) {
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1174
        tty->print("PREFETCHW");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1175
      } else if (UseSSE >= 1) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1176
        if (AllocatePrefetchInstr == 0) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1177
          tty->print("PREFETCHNTA");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1178
        } else if (AllocatePrefetchInstr == 1) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1179
          tty->print("PREFETCHT0");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1180
        } else if (AllocatePrefetchInstr == 2) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1181
          tty->print("PREFETCHT2");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1182
        } else if (AllocatePrefetchInstr == 3) {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1183
          tty->print("PREFETCHW");
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1184
        }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1185
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1186
      if (AllocatePrefetchLines > 1) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1187
        tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1188
      } else {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1189
        tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1190
      }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1191
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1192
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1193
    if (PrefetchCopyIntervalInBytes > 0) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1194
      tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1195
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1196
    if (PrefetchScanIntervalInBytes > 0) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1197
      tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1198
    }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1199
    if (PrefetchFieldsAhead > 0) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1200
      tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1201
    }
15193
8e6b5694267f 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 14834
diff changeset
  1202
    if (ContendedPaddingWidth > 0) {
24424
2658d7834c6e 8037816: Fix for 8036122 breaks build with Xcode5/clang
drchase
parents: 24325
diff changeset
  1203
      tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
15193
8e6b5694267f 8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents: 14834
diff changeset
  1204
    }
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1205
  }
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1206
#endif // !PRODUCT
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1207
}
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1208
23491
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1209
bool VM_Version::use_biased_locking() {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1210
#if INCLUDE_RTM_OPT
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1211
  // RTM locking is most useful when there is high lock contention and
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1212
  // low data contention.  With high lock contention the lock is usually
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1213
  // inflated and biased locking is not suitable for that case.
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1214
  // RTM locking code requires that biased locking is off.
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1215
  // Note: we can't switch off UseBiasedLocking in get_processor_features()
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1216
  // because it is used by Thread::allocate() which is called before
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1217
  // VM_Version::initialize().
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1218
  if (UseRTMLocking && UseBiasedLocking) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1219
    if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1220
      FLAG_SET_DEFAULT(UseBiasedLocking, false);
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1221
    } else {
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1222
      warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1223
      UseBiasedLocking = false;
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1224
    }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1225
  }
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1226
#endif
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1227
  return UseBiasedLocking;
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1228
}
f690330b10b9 8031320: Use Intel RTM instructions for locks
kvn
parents: 23487
diff changeset
  1229
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1230
void VM_Version::initialize() {
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1231
  ResourceMark rm;
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1232
  // Making this stub must be FIRST use of assembler
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1233
23527
397b6816032d 8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents: 23491
diff changeset
  1234
  stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1235
  if (stub_blob == NULL) {
23527
397b6816032d 8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents: 23491
diff changeset
  1236
    vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1237
  }
6418
6671edbd230e 6978355: renaming for 6961697
twisti
parents: 6272
diff changeset
  1238
  CodeBuffer c(stub_blob);
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1239
  VM_Version_StubGenerator g(&c);
23527
397b6816032d 8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents: 23491
diff changeset
  1240
  get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
397b6816032d 8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents: 23491
diff changeset
  1241
                                     g.generate_get_cpu_info());
2111
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1242
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1243
  get_processor_features();
dab8a43dd738 6808589: Merge vm_version_x86_{32,64}.{cpp,hpp}
twisti
parents:
diff changeset
  1244
}