author | twisti |
Fri, 13 Mar 2009 11:35:17 -0700 | |
changeset 2255 | 54abdf3e1055 |
parent 2111 | dab8a43dd738 |
child 2348 | 4e71ed4c2709 |
permissions | -rw-r--r-- |
2111 | 1 |
/* |
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* Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
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* CA 95054 USA or visit www.sun.com if you need additional information or |
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* have any questions. |
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* |
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*/ |
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# include "incls/_precompiled.incl" |
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# include "incls/_vm_version_x86.cpp.incl" |
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int VM_Version::_cpu; |
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int VM_Version::_model; |
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int VM_Version::_stepping; |
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int VM_Version::_cpuFeatures; |
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const char* VM_Version::_features_str = ""; |
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VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
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static BufferBlob* stub_blob; |
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static const int stub_size = 300; |
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extern "C" { |
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typedef void (*getPsrInfo_stub_t)(void*); |
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} |
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static getPsrInfo_stub_t getPsrInfo_stub = NULL; |
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class VM_Version_StubGenerator: public StubCodeGenerator { |
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public: |
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VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
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address generate_getPsrInfo() { |
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// Flags to test CPU type. |
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const uint32_t EFL_AC = 0x40000; |
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const uint32_t EFL_ID = 0x200000; |
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// Values for when we don't have a CPUID instruction. |
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const int CPU_FAMILY_SHIFT = 8; |
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const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
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const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
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Label detect_486, cpu486, detect_586, std_cpuid1; |
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Label ext_cpuid1, ext_cpuid5, done; |
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StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); |
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# define __ _masm-> |
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address start = __ pc(); |
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// |
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// void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); |
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// |
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// LP64: rcx and rdx are first and second argument registers on windows |
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__ push(rbp); |
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#ifdef _LP64 |
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__ mov(rbp, c_rarg0); // cpuid_info address |
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#else |
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__ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
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#endif |
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__ push(rbx); |
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__ push(rsi); |
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__ pushf(); // preserve rbx, and flags |
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__ pop(rax); |
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__ push(rax); |
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__ mov(rcx, rax); |
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// |
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// if we are unable to change the AC flag, we have a 386 |
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// |
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__ xorl(rax, EFL_AC); |
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__ push(rax); |
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__ popf(); |
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__ pushf(); |
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__ pop(rax); |
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__ cmpptr(rax, rcx); |
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__ jccb(Assembler::notEqual, detect_486); |
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__ movl(rax, CPU_FAMILY_386); |
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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__ jmp(done); |
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// |
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// If we are unable to change the ID flag, we have a 486 which does |
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// not support the "cpuid" instruction. |
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// |
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__ bind(detect_486); |
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__ mov(rax, rcx); |
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__ xorl(rax, EFL_ID); |
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__ push(rax); |
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__ popf(); |
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__ pushf(); |
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__ pop(rax); |
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__ cmpptr(rcx, rax); |
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__ jccb(Assembler::notEqual, detect_586); |
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__ bind(cpu486); |
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__ movl(rax, CPU_FAMILY_486); |
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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__ jmp(done); |
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// |
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// At this point, we have a chip which supports the "cpuid" instruction |
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// |
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__ bind(detect_586); |
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__ xorl(rax, rax); |
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__ cpuid(); |
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__ orl(rax, rax); |
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__ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
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// value of at least 1, we give up and |
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// assume a 486 |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ cmpl(rax, 3); // Is cpuid(0x4) supported? |
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__ jccb(Assembler::belowEqual, std_cpuid1); |
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// |
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// cpuid(0x4) Deterministic cache params |
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// |
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__ movl(rax, 4); |
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__ xorl(rcx, rcx); // L1 cache |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid cache parameters used |
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__ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid1); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// Standard cpuid(0x1) |
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// |
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__ bind(std_cpuid1); |
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__ movl(rax, 1); |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ movl(rax, 0x80000000); |
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__ cpuid(); |
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__ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
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__ jcc(Assembler::belowEqual, done); |
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__ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid1); |
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__ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid5); |
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// |
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// Extended cpuid(0x80000008) |
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// |
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__ movl(rax, 0x80000008); |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// Extended cpuid(0x80000005) |
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// |
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__ bind(ext_cpuid5); |
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__ movl(rax, 0x80000005); |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// Extended cpuid(0x80000001) |
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// |
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__ bind(ext_cpuid1); |
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__ movl(rax, 0x80000001); |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// return |
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// |
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__ bind(done); |
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__ popf(); |
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__ pop(rsi); |
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__ pop(rbx); |
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__ pop(rbp); |
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__ ret(0); |
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# undef __ |
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return start; |
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}; |
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}; |
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void VM_Version::get_processor_features() { |
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_cpu = 4; // 486 by default |
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_model = 0; |
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_stepping = 0; |
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_cpuFeatures = 0; |
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_logical_processors_per_package = 1; |
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if (!Use486InstrsOnly) { |
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// Get raw processor info |
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getPsrInfo_stub(&_cpuid_info); |
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assert_is_initialized(); |
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_cpu = extended_cpu_family(); |
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_model = extended_cpu_model(); |
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_stepping = cpu_stepping(); |
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if (cpu_family() > 4) { // it supports CPUID |
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_cpuFeatures = feature_flags(); |
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// Logical processors are only available on P4s and above, |
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// and only if hyperthreading is available. |
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_logical_processors_per_package = logical_processor_count(); |
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} |
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} |
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_supports_cx8 = supports_cmpxchg8(); |
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#ifdef _LP64 |
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// OS should support SSE for x64 and hardware should support at least SSE2. |
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if (!VM_Version::supports_sse2()) { |
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vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
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} |
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#endif |
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// If the OS doesn't support SSE, we can't use this feature even if the HW does |
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if (!os::supports_sse()) |
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_cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
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if (UseSSE < 4) { |
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_cpuFeatures &= ~CPU_SSE4_1; |
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_cpuFeatures &= ~CPU_SSE4_2; |
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} |
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if (UseSSE < 3) { |
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_cpuFeatures &= ~CPU_SSE3; |
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_cpuFeatures &= ~CPU_SSSE3; |
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_cpuFeatures &= ~CPU_SSE4A; |
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} |
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if (UseSSE < 2) |
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_cpuFeatures &= ~CPU_SSE2; |
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if (UseSSE < 1) |
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_cpuFeatures &= ~CPU_SSE; |
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if (logical_processors_per_package() == 1) { |
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// HT processor could be installed on a system which doesn't support HT. |
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_cpuFeatures &= ~CPU_HT; |
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} |
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char buf[256]; |
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2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
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jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
2111 | 288 |
cores_per_cpu(), threads_per_core(), |
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cpu_family(), _model, _stepping, |
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(supports_cmov() ? ", cmov" : ""), |
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(supports_cmpxchg8() ? ", cx8" : ""), |
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(supports_fxsr() ? ", fxsr" : ""), |
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(supports_mmx() ? ", mmx" : ""), |
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(supports_sse() ? ", sse" : ""), |
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(supports_sse2() ? ", sse2" : ""), |
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(supports_sse3() ? ", sse3" : ""), |
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(supports_ssse3()? ", ssse3": ""), |
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(supports_sse4_1() ? ", sse4.1" : ""), |
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(supports_sse4_2() ? ", sse4.2" : ""), |
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2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
300 |
(supports_popcnt() ? ", popcnt" : ""), |
2111 | 301 |
(supports_mmx_ext() ? ", mmxext" : ""), |
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(supports_3dnow() ? ", 3dnow" : ""), |
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(supports_3dnow2() ? ", 3dnowext" : ""), |
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(supports_sse4a() ? ", sse4a": ""), |
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(supports_ht() ? ", ht": "")); |
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_features_str = strdup(buf); |
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307 |
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// UseSSE is set to the smaller of what hardware supports and what |
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// the command line requires. I.e., you cannot set UseSSE to 2 on |
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// older Pentiums which do not support it. |
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if( UseSSE > 4 ) UseSSE=4; |
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if( UseSSE < 0 ) UseSSE=0; |
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if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support |
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UseSSE = MIN2((intx)3,UseSSE); |
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if( !supports_sse3() ) // Drop to 2 if no SSE3 support |
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UseSSE = MIN2((intx)2,UseSSE); |
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if( !supports_sse2() ) // Drop to 1 if no SSE2 support |
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UseSSE = MIN2((intx)1,UseSSE); |
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if( !supports_sse () ) // Drop to 0 if no SSE support |
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UseSSE = 0; |
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322 |
// On new cpus instructions which update whole XMM register should be used |
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// to prevent partial register stall due to dependencies on high half. |
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// |
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// UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
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// UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
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// UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
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// UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
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330 |
if( is_amd() ) { // AMD cpus specific settings |
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331 |
if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
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// Use it on new AMD cpus starting from Opteron. |
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UseAddressNop = true; |
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} |
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335 |
if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
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336 |
// Use it on new AMD cpus starting from Opteron. |
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UseNewLongLShift = true; |
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338 |
} |
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339 |
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
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340 |
if( supports_sse4a() ) { |
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341 |
UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
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342 |
} else { |
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343 |
UseXmmLoadAndClearUpper = false; |
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344 |
} |
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345 |
} |
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346 |
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
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347 |
if( supports_sse4a() ) { |
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348 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
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349 |
} else { |
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350 |
UseXmmRegToRegMoveAll = false; |
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351 |
} |
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352 |
} |
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353 |
if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
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354 |
if( supports_sse4a() ) { |
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355 |
UseXmmI2F = true; |
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356 |
} else { |
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357 |
UseXmmI2F = false; |
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358 |
} |
|
359 |
} |
|
360 |
if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
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361 |
if( supports_sse4a() ) { |
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362 |
UseXmmI2D = true; |
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363 |
} else { |
|
364 |
UseXmmI2D = false; |
|
365 |
} |
|
366 |
} |
|
367 |
} |
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368 |
||
369 |
if( is_intel() ) { // Intel cpus specific settings |
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370 |
if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
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371 |
UseStoreImmI16 = false; // don't use it on Intel cpus |
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372 |
} |
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373 |
if( cpu_family() == 6 || cpu_family() == 15 ) { |
|
374 |
if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
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375 |
// Use it on all Intel cpus starting from PentiumPro |
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376 |
UseAddressNop = true; |
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377 |
} |
|
378 |
} |
|
379 |
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
380 |
UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
|
381 |
} |
|
382 |
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
383 |
if( supports_sse3() ) { |
|
384 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
|
385 |
} else { |
|
386 |
UseXmmRegToRegMoveAll = false; |
|
387 |
} |
|
388 |
} |
|
389 |
if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
|
390 |
#ifdef COMPILER2 |
|
391 |
if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
|
392 |
// For new Intel cpus do the next optimization: |
|
393 |
// don't align the beginning of a loop if there are enough instructions |
|
394 |
// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
|
395 |
// in current fetch line (OptoLoopAlignment) or the padding |
|
396 |
// is big (> MaxLoopPad). |
|
397 |
// Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
|
398 |
// generated NOP instructions. 11 is the largest size of one |
|
399 |
// address NOP instruction '0F 1F' (see Assembler::nop(i)). |
|
400 |
MaxLoopPad = 11; |
|
401 |
} |
|
402 |
#endif // COMPILER2 |
|
403 |
if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { |
|
404 |
UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
|
405 |
} |
|
406 |
if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus |
|
407 |
if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { |
|
408 |
UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
|
409 |
} |
|
410 |
} |
|
411 |
} |
|
412 |
} |
|
413 |
||
2255
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changeset
|
414 |
// Use population count instruction if available. |
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diff
changeset
|
415 |
if (supports_popcnt()) { |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
changeset
|
416 |
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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parents:
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diff
changeset
|
417 |
UsePopCountInstruction = true; |
54abdf3e1055
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twisti
parents:
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diff
changeset
|
418 |
} |
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parents:
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diff
changeset
|
419 |
} |
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changeset
|
420 |
|
2111 | 421 |
assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
422 |
assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); |
|
423 |
||
424 |
// set valid Prefetch instruction |
|
425 |
if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; |
|
426 |
if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; |
|
427 |
if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0; |
|
428 |
if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3; |
|
429 |
||
430 |
if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; |
|
431 |
if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; |
|
432 |
if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0; |
|
433 |
if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3; |
|
434 |
||
435 |
// Allocation prefetch settings |
|
436 |
intx cache_line_size = L1_data_cache_line_size(); |
|
437 |
if( cache_line_size > AllocatePrefetchStepSize ) |
|
438 |
AllocatePrefetchStepSize = cache_line_size; |
|
439 |
if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) |
|
440 |
AllocatePrefetchLines = 3; // Optimistic value |
|
441 |
assert(AllocatePrefetchLines > 0, "invalid value"); |
|
442 |
if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
|
443 |
AllocatePrefetchLines = 1; // Conservative value |
|
444 |
||
445 |
AllocatePrefetchDistance = allocate_prefetch_distance(); |
|
446 |
AllocatePrefetchStyle = allocate_prefetch_style(); |
|
447 |
||
448 |
if( AllocatePrefetchStyle == 2 && is_intel() && |
|
449 |
cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core |
|
450 |
#ifdef _LP64 |
|
451 |
AllocatePrefetchDistance = 384; |
|
452 |
#else |
|
453 |
AllocatePrefetchDistance = 320; |
|
454 |
#endif |
|
455 |
} |
|
456 |
assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); |
|
457 |
||
458 |
#ifdef _LP64 |
|
459 |
// Prefetch settings |
|
460 |
PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); |
|
461 |
PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); |
|
462 |
PrefetchFieldsAhead = prefetch_fields_ahead(); |
|
463 |
#endif |
|
464 |
||
465 |
#ifndef PRODUCT |
|
466 |
if (PrintMiscellaneous && Verbose) { |
|
467 |
tty->print_cr("Logical CPUs per core: %u", |
|
468 |
logical_processors_per_package()); |
|
469 |
tty->print_cr("UseSSE=%d",UseSSE); |
|
470 |
tty->print("Allocation: "); |
|
471 |
if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) { |
|
472 |
tty->print_cr("no prefetching"); |
|
473 |
} else { |
|
474 |
if (UseSSE == 0 && supports_3dnow()) { |
|
475 |
tty->print("PREFETCHW"); |
|
476 |
} else if (UseSSE >= 1) { |
|
477 |
if (AllocatePrefetchInstr == 0) { |
|
478 |
tty->print("PREFETCHNTA"); |
|
479 |
} else if (AllocatePrefetchInstr == 1) { |
|
480 |
tty->print("PREFETCHT0"); |
|
481 |
} else if (AllocatePrefetchInstr == 2) { |
|
482 |
tty->print("PREFETCHT2"); |
|
483 |
} else if (AllocatePrefetchInstr == 3) { |
|
484 |
tty->print("PREFETCHW"); |
|
485 |
} |
|
486 |
} |
|
487 |
if (AllocatePrefetchLines > 1) { |
|
488 |
tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
|
489 |
} else { |
|
490 |
tty->print_cr(" %d, one line", AllocatePrefetchDistance); |
|
491 |
} |
|
492 |
} |
|
493 |
||
494 |
if (PrefetchCopyIntervalInBytes > 0) { |
|
495 |
tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); |
|
496 |
} |
|
497 |
if (PrefetchScanIntervalInBytes > 0) { |
|
498 |
tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); |
|
499 |
} |
|
500 |
if (PrefetchFieldsAhead > 0) { |
|
501 |
tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); |
|
502 |
} |
|
503 |
} |
|
504 |
#endif // !PRODUCT |
|
505 |
} |
|
506 |
||
507 |
void VM_Version::initialize() { |
|
508 |
ResourceMark rm; |
|
509 |
// Making this stub must be FIRST use of assembler |
|
510 |
||
511 |
stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); |
|
512 |
if (stub_blob == NULL) { |
|
513 |
vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); |
|
514 |
} |
|
515 |
CodeBuffer c(stub_blob->instructions_begin(), |
|
516 |
stub_blob->instructions_size()); |
|
517 |
VM_Version_StubGenerator g(&c); |
|
518 |
getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, |
|
519 |
g.generate_getPsrInfo()); |
|
520 |
||
521 |
get_processor_features(); |
|
522 |
} |