author | eosterlund |
Wed, 09 Oct 2019 12:30:06 +0000 | |
changeset 58516 | d376d86b0a01 |
parent 57804 | 9b7b9f16dfd9 |
child 58679 | 9c3209ff7550 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
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* Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP |
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#define CPU_AARCH64_ASSEMBLER_AARCH64_HPP |
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#include "asm/register.hpp" |
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// definitions of various symbolic names for machine registers |
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// First intercalls between C and Java which use 8 general registers |
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// and 8 floating registers |
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||
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// we also have to copy between x86 and ARM registers but that's a |
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// secondary complication -- not all code employing C call convention |
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// executes as x86 code though -- we generate some of it |
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class Argument { |
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public: |
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enum { |
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n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... ) |
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n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ... |
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n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ... |
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}; |
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}; |
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REGISTER_DECLARATION(Register, c_rarg0, r0); |
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REGISTER_DECLARATION(Register, c_rarg1, r1); |
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REGISTER_DECLARATION(Register, c_rarg2, r2); |
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REGISTER_DECLARATION(Register, c_rarg3, r3); |
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REGISTER_DECLARATION(Register, c_rarg4, r4); |
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REGISTER_DECLARATION(Register, c_rarg5, r5); |
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REGISTER_DECLARATION(Register, c_rarg6, r6); |
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REGISTER_DECLARATION(Register, c_rarg7, r7); |
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REGISTER_DECLARATION(FloatRegister, c_farg0, v0); |
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REGISTER_DECLARATION(FloatRegister, c_farg1, v1); |
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REGISTER_DECLARATION(FloatRegister, c_farg2, v2); |
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REGISTER_DECLARATION(FloatRegister, c_farg3, v3); |
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REGISTER_DECLARATION(FloatRegister, c_farg4, v4); |
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REGISTER_DECLARATION(FloatRegister, c_farg5, v5); |
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REGISTER_DECLARATION(FloatRegister, c_farg6, v6); |
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REGISTER_DECLARATION(FloatRegister, c_farg7, v7); |
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// Symbolically name the register arguments used by the Java calling convention. |
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// We have control over the convention for java so we can do what we please. |
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// What pleases us is to offset the java calling convention so that when |
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// we call a suitable jni method the arguments are lined up and we don't |
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// have to do much shuffling. A suitable jni method is non-static and a |
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// small number of arguments |
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// |
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// |--------------------------------------------------------------------| |
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// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 | |
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// |--------------------------------------------------------------------| |
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// | r0 r1 r2 r3 r4 r5 r6 r7 | |
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// |--------------------------------------------------------------------| |
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// | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 | |
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// |--------------------------------------------------------------------| |
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REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
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REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
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REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
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REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
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REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
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REGISTER_DECLARATION(Register, j_rarg5, c_rarg6); |
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REGISTER_DECLARATION(Register, j_rarg6, c_rarg7); |
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REGISTER_DECLARATION(Register, j_rarg7, c_rarg0); |
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// Java floating args are passed as per C |
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REGISTER_DECLARATION(FloatRegister, j_farg0, v0); |
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REGISTER_DECLARATION(FloatRegister, j_farg1, v1); |
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REGISTER_DECLARATION(FloatRegister, j_farg2, v2); |
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REGISTER_DECLARATION(FloatRegister, j_farg3, v3); |
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REGISTER_DECLARATION(FloatRegister, j_farg4, v4); |
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REGISTER_DECLARATION(FloatRegister, j_farg5, v5); |
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REGISTER_DECLARATION(FloatRegister, j_farg6, v6); |
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REGISTER_DECLARATION(FloatRegister, j_farg7, v7); |
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// registers used to hold VM data either temporarily within a method |
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// or across method calls |
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// volatile (caller-save) registers |
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// r8 is used for indirect result location return |
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// we use it and r9 as scratch registers |
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REGISTER_DECLARATION(Register, rscratch1, r8); |
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REGISTER_DECLARATION(Register, rscratch2, r9); |
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// current method -- must be in a call-clobbered register |
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REGISTER_DECLARATION(Register, rmethod, r12); |
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// non-volatile (callee-save) registers are r16-29 |
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// of which the following are dedicated global state |
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// link register |
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REGISTER_DECLARATION(Register, lr, r30); |
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// frame pointer |
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REGISTER_DECLARATION(Register, rfp, r29); |
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// current thread |
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REGISTER_DECLARATION(Register, rthread, r28); |
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// base of heap |
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REGISTER_DECLARATION(Register, rheapbase, r27); |
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// constant pool cache |
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REGISTER_DECLARATION(Register, rcpool, r26); |
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// monitors allocated on stack |
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REGISTER_DECLARATION(Register, rmonitors, r25); |
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// locals on stack |
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REGISTER_DECLARATION(Register, rlocals, r24); |
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// bytecode pointer |
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REGISTER_DECLARATION(Register, rbcp, r22); |
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// Dispatch table base |
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REGISTER_DECLARATION(Register, rdispatch, r21); |
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// Java stack pointer |
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REGISTER_DECLARATION(Register, esp, r20); |
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#define assert_cond(ARG1) assert(ARG1, #ARG1) |
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namespace asm_util { |
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uint32_t encode_logical_immediate(bool is32, uint64_t imm); |
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}; |
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using namespace asm_util; |
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class Assembler; |
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class Instruction_aarch64 { |
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unsigned insn; |
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#ifdef ASSERT |
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unsigned bits; |
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#endif |
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Assembler *assem; |
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public: |
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Instruction_aarch64(class Assembler *as) { |
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#ifdef ASSERT |
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bits = 0; |
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#endif |
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insn = 0; |
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assem = as; |
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} |
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inline ~Instruction_aarch64(); |
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unsigned &get_insn() { return insn; } |
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#ifdef ASSERT |
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unsigned &get_bits() { return bits; } |
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#endif |
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static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) { |
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union { |
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unsigned u; |
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int n; |
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}; |
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u = val << (31 - hi); |
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n = n >> (31 - hi + lo); |
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return n; |
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} |
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static inline uint32_t extract(uint32_t val, int msb, int lsb) { |
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int nbits = msb - lsb + 1; |
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assert_cond(msb >= lsb); |
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uint32_t mask = (1U << nbits) - 1; |
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uint32_t result = val >> lsb; |
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result &= mask; |
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return result; |
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} |
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static inline int32_t sextract(uint32_t val, int msb, int lsb) { |
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uint32_t uval = extract(val, msb, lsb); |
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return extend(uval, msb - lsb); |
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} |
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static void patch(address a, int msb, int lsb, unsigned long val) { |
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int nbits = msb - lsb + 1; |
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guarantee(val < (1U << nbits), "Field too big for insn"); |
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assert_cond(msb >= lsb); |
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unsigned mask = (1U << nbits) - 1; |
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val <<= lsb; |
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mask <<= lsb; |
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unsigned target = *(unsigned *)a; |
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target &= ~mask; |
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target |= val; |
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*(unsigned *)a = target; |
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} |
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static void spatch(address a, int msb, int lsb, long val) { |
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int nbits = msb - lsb + 1; |
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long chk = val >> (nbits - 1); |
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guarantee (chk == -1 || chk == 0, "Field too big for insn"); |
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unsigned uval = val; |
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unsigned mask = (1U << nbits) - 1; |
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uval &= mask; |
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uval <<= lsb; |
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mask <<= lsb; |
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unsigned target = *(unsigned *)a; |
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target &= ~mask; |
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target |= uval; |
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*(unsigned *)a = target; |
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} |
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void f(unsigned val, int msb, int lsb) { |
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int nbits = msb - lsb + 1; |
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guarantee(val < (1U << nbits), "Field too big for insn"); |
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assert_cond(msb >= lsb); |
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unsigned mask = (1U << nbits) - 1; |
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val <<= lsb; |
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mask <<= lsb; |
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insn |= val; |
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assert_cond((bits & mask) == 0); |
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#ifdef ASSERT |
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bits |= mask; |
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#endif |
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} |
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void f(unsigned val, int bit) { |
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f(val, bit, bit); |
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} |
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void sf(long val, int msb, int lsb) { |
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int nbits = msb - lsb + 1; |
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long chk = val >> (nbits - 1); |
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guarantee (chk == -1 || chk == 0, "Field too big for insn"); |
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unsigned uval = val; |
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unsigned mask = (1U << nbits) - 1; |
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uval &= mask; |
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f(uval, lsb + nbits - 1, lsb); |
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} |
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void rf(Register r, int lsb) { |
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f(r->encoding_nocheck(), lsb + 4, lsb); |
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} |
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// reg|ZR |
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void zrf(Register r, int lsb) { |
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f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb); |
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} |
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// reg|SP |
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void srf(Register r, int lsb) { |
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f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb); |
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} |
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void rf(FloatRegister r, int lsb) { |
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f(r->encoding_nocheck(), lsb + 4, lsb); |
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} |
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unsigned get(int msb = 31, int lsb = 0) { |
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int nbits = msb - lsb + 1; |
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unsigned mask = ((1U << nbits) - 1) << lsb; |
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assert_cond((bits & mask) == mask); |
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return (insn & mask) >> lsb; |
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} |
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void fixed(unsigned value, unsigned mask) { |
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assert_cond ((mask & bits) == 0); |
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#ifdef ASSERT |
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bits |= mask; |
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#endif |
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insn |= value; |
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} |
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}; |
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#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) |
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class PrePost { |
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int _offset; |
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Register _r; |
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public: |
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PrePost(Register reg, int o) : _offset(o), _r(reg) { } |
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int offset() { return _offset; } |
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Register reg() { return _r; } |
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}; |
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class Pre : public PrePost { |
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public: |
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Pre(Register reg, int o) : PrePost(reg, o) { } |
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}; |
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class Post : public PrePost { |
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Register _idx; |
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bool _is_postreg; |
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public: |
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Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; } |
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Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; } |
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Register idx_reg() { return _idx; } |
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bool is_postreg() {return _is_postreg; } |
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}; |
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namespace ext |
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{ |
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enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx }; |
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}; |
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// Addressing modes |
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class Address { |
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public: |
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enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel, |
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base_plus_offset_reg, literal }; |
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// Shift and extend for base reg + reg offset addressing |
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330 |
class extend { |
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331 |
int _option, _shift; |
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ext::operation _op; |
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public: |
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extend() { } |
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extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { } |
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int option() const{ return _option; } |
337 |
int shift() const { return _shift; } |
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338 |
ext::operation op() const { return _op; } |
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339 |
}; |
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340 |
class uxtw : public extend { |
|
341 |
public: |
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342 |
uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { } |
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343 |
}; |
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class lsl : public extend { |
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345 |
public: |
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lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { } |
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347 |
}; |
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class sxtw : public extend { |
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349 |
public: |
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350 |
sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { } |
|
351 |
}; |
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class sxtx : public extend { |
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353 |
public: |
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354 |
sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { } |
|
355 |
}; |
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357 |
private: |
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358 |
Register _base; |
|
359 |
Register _index; |
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360 |
long _offset; |
|
361 |
enum mode _mode; |
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362 |
extend _ext; |
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363 |
||
364 |
RelocationHolder _rspec; |
|
365 |
||
366 |
// Typically we use AddressLiterals we want to use their rval |
|
367 |
// However in some situations we want the lval (effect address) of |
|
368 |
// the item. We provide a special factory for making those lvals. |
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369 |
bool _is_lval; |
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370 |
||
371 |
// If the target is far we'll need to load the ea of this to a |
|
372 |
// register to reach it. Otherwise if near we can do PC-relative |
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373 |
// addressing. |
|
374 |
address _target; |
|
375 |
||
376 |
public: |
|
377 |
Address() |
|
378 |
: _mode(no_mode) { } |
|
379 |
Address(Register r) |
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380 |
: _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { } |
29183 | 381 |
Address(Register r, int o) |
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382 |
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { } |
29183 | 383 |
Address(Register r, long o) |
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|
384 |
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { } |
29183 | 385 |
Address(Register r, unsigned long o) |
51383
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
386 |
: _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { } |
29183 | 387 |
#ifdef ASSERT |
388 |
Address(Register r, ByteSize disp) |
|
51383
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
389 |
: _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { } |
29183 | 390 |
#endif |
391 |
Address(Register r, Register r1, extend ext = lsl()) |
|
51383
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
392 |
: _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg), |
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
393 |
_ext(ext), _target(0) { } |
29183 | 394 |
Address(Pre p) |
51383
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
395 |
: _base(p.reg()), _offset(p.offset()), _mode(pre) { } |
29183 | 396 |
Address(Post p) |
51383
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
397 |
: _base(p.reg()), _index(p.idx_reg()), _offset(p.offset()), |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
398 |
_mode(p.is_postreg() ? post_reg : post), _target(0) { } |
29183 | 399 |
Address(address target, RelocationHolder const& rspec) |
400 |
: _mode(literal), |
|
401 |
_rspec(rspec), |
|
402 |
_is_lval(false), |
|
403 |
_target(target) { } |
|
404 |
Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type); |
|
405 |
Address(Register base, RegisterOrConstant index, extend ext = lsl()) |
|
406 |
: _base (base), |
|
51383
2f58537e1bc0
8209193: Fix aarch64-linux compilation after -Wreorder changes
tschatzl
parents:
50754
diff
changeset
|
407 |
_offset(0), _ext(ext), _target(0) { |
29183 | 408 |
if (index.is_register()) { |
409 |
_mode = base_plus_offset_reg; |
|
410 |
_index = index.as_register(); |
|
411 |
} else { |
|
412 |
guarantee(ext.option() == ext::uxtx, "should be"); |
|
413 |
assert(index.is_constant(), "should be"); |
|
414 |
_mode = base_plus_offset; |
|
415 |
_offset = index.as_constant() << ext.shift(); |
|
416 |
} |
|
417 |
} |
|
418 |
||
419 |
Register base() const { |
|
420 |
guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg |
|
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
421 |
| _mode == post | _mode == post_reg), |
29183 | 422 |
"wrong mode"); |
423 |
return _base; |
|
424 |
} |
|
425 |
long offset() const { |
|
426 |
return _offset; |
|
427 |
} |
|
428 |
Register index() const { |
|
429 |
return _index; |
|
430 |
} |
|
431 |
mode getMode() const { |
|
432 |
return _mode; |
|
433 |
} |
|
434 |
bool uses(Register reg) const { return _base == reg || _index == reg; } |
|
435 |
address target() const { return _target; } |
|
436 |
const RelocationHolder& rspec() const { return _rspec; } |
|
437 |
||
438 |
void encode(Instruction_aarch64 *i) const { |
|
439 |
i->f(0b111, 29, 27); |
|
440 |
i->srf(_base, 5); |
|
441 |
||
442 |
switch(_mode) { |
|
443 |
case base_plus_offset: |
|
444 |
{ |
|
445 |
unsigned size = i->get(31, 30); |
|
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
446 |
if (i->get(26, 26) && i->get(23, 23)) { |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
447 |
// SIMD Q Type - Size = 128 bits |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
448 |
assert(size == 0, "bad size"); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
449 |
size = 0b100; |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
450 |
} |
29183 | 451 |
unsigned mask = (1 << size) - 1; |
452 |
if (_offset < 0 || _offset & mask) |
|
453 |
{ |
|
454 |
i->f(0b00, 25, 24); |
|
455 |
i->f(0, 21), i->f(0b00, 11, 10); |
|
456 |
i->sf(_offset, 20, 12); |
|
457 |
} else { |
|
458 |
i->f(0b01, 25, 24); |
|
459 |
i->f(_offset >> size, 21, 10); |
|
460 |
} |
|
461 |
} |
|
462 |
break; |
|
463 |
||
464 |
case base_plus_offset_reg: |
|
465 |
{ |
|
466 |
i->f(0b00, 25, 24); |
|
467 |
i->f(1, 21); |
|
468 |
i->rf(_index, 16); |
|
469 |
i->f(_ext.option(), 15, 13); |
|
470 |
unsigned size = i->get(31, 30); |
|
31227
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
471 |
if (i->get(26, 26) && i->get(23, 23)) { |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
472 |
// SIMD Q Type - Size = 128 bits |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
473 |
assert(size == 0, "bad size"); |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
474 |
size = 0b100; |
964d24a82077
8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents:
30890
diff
changeset
|
475 |
} |
29183 | 476 |
if (size == 0) // It's a byte |
477 |
i->f(_ext.shift() >= 0, 12); |
|
478 |
else { |
|
479 |
if (_ext.shift() > 0) |
|
480 |
assert(_ext.shift() == (int)size, "bad shift"); |
|
481 |
i->f(_ext.shift() > 0, 12); |
|
482 |
} |
|
483 |
i->f(0b10, 11, 10); |
|
484 |
} |
|
485 |
break; |
|
486 |
||
487 |
case pre: |
|
488 |
i->f(0b00, 25, 24); |
|
489 |
i->f(0, 21), i->f(0b11, 11, 10); |
|
490 |
i->sf(_offset, 20, 12); |
|
491 |
break; |
|
492 |
||
493 |
case post: |
|
494 |
i->f(0b00, 25, 24); |
|
495 |
i->f(0, 21), i->f(0b01, 11, 10); |
|
496 |
i->sf(_offset, 20, 12); |
|
497 |
break; |
|
498 |
||
499 |
default: |
|
500 |
ShouldNotReachHere(); |
|
501 |
} |
|
502 |
} |
|
503 |
||
504 |
void encode_pair(Instruction_aarch64 *i) const { |
|
505 |
switch(_mode) { |
|
506 |
case base_plus_offset: |
|
507 |
i->f(0b010, 25, 23); |
|
508 |
break; |
|
509 |
case pre: |
|
510 |
i->f(0b011, 25, 23); |
|
511 |
break; |
|
512 |
case post: |
|
513 |
i->f(0b001, 25, 23); |
|
514 |
break; |
|
515 |
default: |
|
516 |
ShouldNotReachHere(); |
|
517 |
} |
|
518 |
||
519 |
unsigned size; // Operand shift in 32-bit words |
|
520 |
||
521 |
if (i->get(26, 26)) { // float |
|
522 |
switch(i->get(31, 30)) { |
|
523 |
case 0b10: |
|
524 |
size = 2; break; |
|
525 |
case 0b01: |
|
526 |
size = 1; break; |
|
527 |
case 0b00: |
|
528 |
size = 0; break; |
|
529 |
default: |
|
530 |
ShouldNotReachHere(); |
|
35127 | 531 |
size = 0; // unreachable |
29183 | 532 |
} |
533 |
} else { |
|
534 |
size = i->get(31, 31); |
|
535 |
} |
|
536 |
||
537 |
size = 4 << size; |
|
538 |
guarantee(_offset % size == 0, "bad offset"); |
|
539 |
i->sf(_offset / size, 21, 15); |
|
540 |
i->srf(_base, 5); |
|
541 |
} |
|
542 |
||
543 |
void encode_nontemporal_pair(Instruction_aarch64 *i) const { |
|
544 |
// Only base + offset is allowed |
|
545 |
i->f(0b000, 25, 23); |
|
546 |
unsigned size = i->get(31, 31); |
|
547 |
size = 4 << size; |
|
548 |
guarantee(_offset % size == 0, "bad offset"); |
|
549 |
i->sf(_offset / size, 21, 15); |
|
550 |
i->srf(_base, 5); |
|
551 |
guarantee(_mode == Address::base_plus_offset, |
|
552 |
"Bad addressing mode for non-temporal op"); |
|
553 |
} |
|
554 |
||
555 |
void lea(MacroAssembler *, Register) const; |
|
556 |
||
557 |
static bool offset_ok_for_immed(long offset, int shift = 0) { |
|
558 |
unsigned mask = (1 << shift) - 1; |
|
559 |
if (offset < 0 || offset & mask) { |
|
560 |
return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset |
|
561 |
} else { |
|
562 |
return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset |
|
563 |
} |
|
564 |
} |
|
565 |
}; |
|
566 |
||
567 |
// Convience classes |
|
568 |
class RuntimeAddress: public Address { |
|
569 |
||
570 |
public: |
|
571 |
||
572 |
RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {} |
|
573 |
||
574 |
}; |
|
575 |
||
576 |
class OopAddress: public Address { |
|
577 |
||
578 |
public: |
|
579 |
||
580 |
OopAddress(address target) : Address(target, relocInfo::oop_type){} |
|
581 |
||
582 |
}; |
|
583 |
||
584 |
class ExternalAddress: public Address { |
|
585 |
private: |
|
586 |
static relocInfo::relocType reloc_for_target(address target) { |
|
587 |
// Sometimes ExternalAddress is used for values which aren't |
|
588 |
// exactly addresses, like the card table base. |
|
589 |
// external_word_type can't be used for values in the first page |
|
590 |
// so just skip the reloc in that case. |
|
591 |
return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
|
592 |
} |
|
593 |
||
594 |
public: |
|
595 |
||
596 |
ExternalAddress(address target) : Address(target, reloc_for_target(target)) {} |
|
597 |
||
598 |
}; |
|
599 |
||
600 |
class InternalAddress: public Address { |
|
601 |
||
602 |
public: |
|
603 |
||
604 |
InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} |
|
605 |
}; |
|
606 |
||
607 |
const int FPUStateSizeInWords = 32 * 2; |
|
608 |
typedef enum { |
|
609 |
PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, |
|
610 |
PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, |
|
611 |
PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM |
|
612 |
} prfop; |
|
613 |
||
614 |
class Assembler : public AbstractAssembler { |
|
615 |
||
616 |
#ifndef PRODUCT |
|
617 |
static const unsigned long asm_bp; |
|
618 |
||
619 |
void emit_long(jint x) { |
|
620 |
if ((unsigned long)pc() == asm_bp) |
|
621 |
asm volatile ("nop"); |
|
622 |
AbstractAssembler::emit_int32(x); |
|
623 |
} |
|
624 |
#else |
|
625 |
void emit_long(jint x) { |
|
626 |
AbstractAssembler::emit_int32(x); |
|
627 |
} |
|
628 |
#endif |
|
629 |
||
630 |
public: |
|
631 |
||
632 |
enum { instruction_size = 4 }; |
|
633 |
||
54960
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
634 |
//---< calculate length of instruction >--- |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
635 |
// We just use the values set above. |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
636 |
// instruction must start at passed address |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
637 |
static unsigned int instr_len(unsigned char *instr) { return instruction_size; } |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
638 |
|
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
639 |
//---< longest instructions >--- |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
640 |
static unsigned int instr_maxlen() { return instruction_size; } |
e46fe26d7f77
8213084: Rework and enhance Print[Opto]Assembly output
lucy
parents:
54453
diff
changeset
|
641 |
|
29183 | 642 |
Address adjust(Register base, int offset, bool preIncrement) { |
643 |
if (preIncrement) |
|
644 |
return Address(Pre(base, offset)); |
|
645 |
else |
|
646 |
return Address(Post(base, offset)); |
|
647 |
} |
|
648 |
||
649 |
Address pre(Register base, int offset) { |
|
650 |
return adjust(base, offset, true); |
|
651 |
} |
|
652 |
||
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
653 |
Address post(Register base, int offset) { |
29183 | 654 |
return adjust(base, offset, false); |
655 |
} |
|
656 |
||
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
657 |
Address post(Register base, Register idx) { |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
658 |
return Address(Post(base, idx)); |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
659 |
} |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
660 |
|
29183 | 661 |
Instruction_aarch64* current; |
662 |
||
663 |
void set_current(Instruction_aarch64* i) { current = i; } |
|
664 |
||
665 |
void f(unsigned val, int msb, int lsb) { |
|
666 |
current->f(val, msb, lsb); |
|
667 |
} |
|
668 |
void f(unsigned val, int msb) { |
|
669 |
current->f(val, msb, msb); |
|
670 |
} |
|
671 |
void sf(long val, int msb, int lsb) { |
|
672 |
current->sf(val, msb, lsb); |
|
673 |
} |
|
674 |
void rf(Register reg, int lsb) { |
|
675 |
current->rf(reg, lsb); |
|
676 |
} |
|
677 |
void srf(Register reg, int lsb) { |
|
678 |
current->srf(reg, lsb); |
|
679 |
} |
|
680 |
void zrf(Register reg, int lsb) { |
|
681 |
current->zrf(reg, lsb); |
|
682 |
} |
|
683 |
void rf(FloatRegister reg, int lsb) { |
|
684 |
current->rf(reg, lsb); |
|
685 |
} |
|
686 |
void fixed(unsigned value, unsigned mask) { |
|
687 |
current->fixed(value, mask); |
|
688 |
} |
|
689 |
||
690 |
void emit() { |
|
691 |
emit_long(current->get_insn()); |
|
692 |
assert_cond(current->get_bits() == 0xffffffff); |
|
693 |
current = NULL; |
|
694 |
} |
|
695 |
||
696 |
typedef void (Assembler::* uncond_branch_insn)(address dest); |
|
697 |
typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest); |
|
698 |
typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest); |
|
699 |
typedef void (Assembler::* prefetch_insn)(address target, prfop); |
|
700 |
||
701 |
void wrap_label(Label &L, uncond_branch_insn insn); |
|
702 |
void wrap_label(Register r, Label &L, compare_and_branch_insn insn); |
|
703 |
void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn); |
|
704 |
void wrap_label(Label &L, prfop, prefetch_insn insn); |
|
705 |
||
706 |
// PC-rel. addressing |
|
707 |
||
708 |
void adr(Register Rd, address dest); |
|
709 |
void _adrp(Register Rd, address dest); |
|
710 |
||
711 |
void adr(Register Rd, const Address &dest); |
|
712 |
void _adrp(Register Rd, const Address &dest); |
|
713 |
||
714 |
void adr(Register Rd, Label &L) { |
|
715 |
wrap_label(Rd, L, &Assembler::Assembler::adr); |
|
716 |
} |
|
717 |
void _adrp(Register Rd, Label &L) { |
|
718 |
wrap_label(Rd, L, &Assembler::_adrp); |
|
719 |
} |
|
720 |
||
721 |
void adrp(Register Rd, const Address &dest, unsigned long &offset); |
|
722 |
||
723 |
#undef INSN |
|
724 |
||
725 |
void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, |
|
726 |
int negated_op); |
|
727 |
||
728 |
// Add/subtract (immediate) |
|
729 |
#define INSN(NAME, decode, negated) \ |
|
730 |
void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ |
|
731 |
starti; \ |
|
732 |
f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \ |
|
733 |
zrf(Rd, 0), srf(Rn, 5); \ |
|
734 |
} \ |
|
735 |
\ |
|
736 |
void NAME(Register Rd, Register Rn, unsigned imm) { \ |
|
737 |
starti; \ |
|
738 |
add_sub_immediate(Rd, Rn, imm, decode, negated); \ |
|
739 |
} |
|
740 |
||
741 |
INSN(addsw, 0b001, 0b011); |
|
742 |
INSN(subsw, 0b011, 0b001); |
|
743 |
INSN(adds, 0b101, 0b111); |
|
744 |
INSN(subs, 0b111, 0b101); |
|
745 |
||
746 |
#undef INSN |
|
747 |
||
748 |
#define INSN(NAME, decode, negated) \ |
|
749 |
void NAME(Register Rd, Register Rn, unsigned imm) { \ |
|
750 |
starti; \ |
|
751 |
add_sub_immediate(Rd, Rn, imm, decode, negated); \ |
|
752 |
} |
|
753 |
||
754 |
INSN(addw, 0b000, 0b010); |
|
755 |
INSN(subw, 0b010, 0b000); |
|
756 |
INSN(add, 0b100, 0b110); |
|
757 |
INSN(sub, 0b110, 0b100); |
|
758 |
||
759 |
#undef INSN |
|
760 |
||
761 |
// Logical (immediate) |
|
762 |
#define INSN(NAME, decode, is32) \ |
|
763 |
void NAME(Register Rd, Register Rn, uint64_t imm) { \ |
|
764 |
starti; \ |
|
765 |
uint32_t val = encode_logical_immediate(is32, imm); \ |
|
766 |
f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ |
|
767 |
srf(Rd, 0), zrf(Rn, 5); \ |
|
768 |
} |
|
769 |
||
770 |
INSN(andw, 0b000, true); |
|
771 |
INSN(orrw, 0b001, true); |
|
772 |
INSN(eorw, 0b010, true); |
|
773 |
INSN(andr, 0b100, false); |
|
774 |
INSN(orr, 0b101, false); |
|
775 |
INSN(eor, 0b110, false); |
|
776 |
||
777 |
#undef INSN |
|
778 |
||
779 |
#define INSN(NAME, decode, is32) \ |
|
780 |
void NAME(Register Rd, Register Rn, uint64_t imm) { \ |
|
781 |
starti; \ |
|
782 |
uint32_t val = encode_logical_immediate(is32, imm); \ |
|
783 |
f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ |
|
784 |
zrf(Rd, 0), zrf(Rn, 5); \ |
|
785 |
} |
|
786 |
||
787 |
INSN(ands, 0b111, false); |
|
788 |
INSN(andsw, 0b011, true); |
|
789 |
||
790 |
#undef INSN |
|
791 |
||
792 |
// Move wide (immediate) |
|
793 |
#define INSN(NAME, opcode) \ |
|
794 |
void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ |
|
795 |
assert_cond((shift/16)*16 == shift); \ |
|
796 |
starti; \ |
|
797 |
f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ |
|
798 |
f(imm, 20, 5); \ |
|
799 |
rf(Rd, 0); \ |
|
800 |
} |
|
801 |
||
802 |
INSN(movnw, 0b000); |
|
803 |
INSN(movzw, 0b010); |
|
804 |
INSN(movkw, 0b011); |
|
805 |
INSN(movn, 0b100); |
|
806 |
INSN(movz, 0b110); |
|
807 |
INSN(movk, 0b111); |
|
808 |
||
809 |
#undef INSN |
|
810 |
||
811 |
// Bitfield |
|
55314
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parents:
55054
diff
changeset
|
812 |
#define INSN(NAME, opcode, size) \ |
29183 | 813 |
void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ |
814 |
starti; \ |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
815 |
guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\ |
29183 | 816 |
f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ |
49723
06ef6db47ec7
8201185: AARCH64: bfm instruction encoding hits assert on zero register
dpochepk
parents:
49364
diff
changeset
|
817 |
zrf(Rn, 5), rf(Rd, 0); \ |
29183 | 818 |
} |
819 |
||
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
820 |
INSN(sbfmw, 0b0001001100, 0); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
821 |
INSN(bfmw, 0b0011001100, 0); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
822 |
INSN(ubfmw, 0b0101001100, 0); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
823 |
INSN(sbfm, 0b1001001101, 1); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
824 |
INSN(bfm, 0b1011001101, 1); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
825 |
INSN(ubfm, 0b1101001101, 1); |
29183 | 826 |
|
827 |
#undef INSN |
|
828 |
||
829 |
// Extract |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
830 |
#define INSN(NAME, opcode, size) \ |
29183 | 831 |
void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ |
832 |
starti; \ |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
833 |
guarantee(size == 1 || imms < 32, "incorrect imms"); \ |
29183 | 834 |
f(opcode, 31, 21), f(imms, 15, 10); \ |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
835 |
zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ |
29183 | 836 |
} |
837 |
||
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
838 |
INSN(extrw, 0b00010011100, 0); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
839 |
INSN(extr, 0b10010011110, 1); |
29183 | 840 |
|
841 |
#undef INSN |
|
842 |
||
843 |
// The maximum range of a branch is fixed for the AArch64 |
|
844 |
// architecture. In debug mode we shrink it in order to test |
|
845 |
// trampolines, but not so small that branches in the interpreter |
|
846 |
// are out of range. |
|
48487 | 847 |
static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); |
29183 | 848 |
|
849 |
static bool reachable_from_branch_at(address branch, address target) { |
|
850 |
return uabs(target - branch) < branch_range; |
|
851 |
} |
|
852 |
||
853 |
// Unconditional branch (immediate) |
|
854 |
#define INSN(NAME, opcode) \ |
|
855 |
void NAME(address dest) { \ |
|
856 |
starti; \ |
|
857 |
long offset = (dest - pc()) >> 2; \ |
|
858 |
DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \ |
|
859 |
f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \ |
|
860 |
} \ |
|
861 |
void NAME(Label &L) { \ |
|
862 |
wrap_label(L, &Assembler::NAME); \ |
|
863 |
} \ |
|
864 |
void NAME(const Address &dest); |
|
865 |
||
866 |
INSN(b, 0); |
|
867 |
INSN(bl, 1); |
|
868 |
||
869 |
#undef INSN |
|
870 |
||
871 |
// Compare & branch (immediate) |
|
872 |
#define INSN(NAME, opcode) \ |
|
873 |
void NAME(Register Rt, address dest) { \ |
|
874 |
long offset = (dest - pc()) >> 2; \ |
|
875 |
starti; \ |
|
876 |
f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ |
|
877 |
} \ |
|
878 |
void NAME(Register Rt, Label &L) { \ |
|
879 |
wrap_label(Rt, L, &Assembler::NAME); \ |
|
880 |
} |
|
881 |
||
882 |
INSN(cbzw, 0b00110100); |
|
883 |
INSN(cbnzw, 0b00110101); |
|
884 |
INSN(cbz, 0b10110100); |
|
885 |
INSN(cbnz, 0b10110101); |
|
886 |
||
887 |
#undef INSN |
|
888 |
||
889 |
// Test & branch (immediate) |
|
890 |
#define INSN(NAME, opcode) \ |
|
891 |
void NAME(Register Rt, int bitpos, address dest) { \ |
|
892 |
long offset = (dest - pc()) >> 2; \ |
|
893 |
int b5 = bitpos >> 5; \ |
|
894 |
bitpos &= 0x1f; \ |
|
895 |
starti; \ |
|
896 |
f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ |
|
897 |
rf(Rt, 0); \ |
|
898 |
} \ |
|
899 |
void NAME(Register Rt, int bitpos, Label &L) { \ |
|
900 |
wrap_label(Rt, bitpos, L, &Assembler::NAME); \ |
|
901 |
} |
|
902 |
||
903 |
INSN(tbz, 0b0110110); |
|
904 |
INSN(tbnz, 0b0110111); |
|
905 |
||
906 |
#undef INSN |
|
907 |
||
908 |
// Conditional branch (immediate) |
|
909 |
enum Condition |
|
910 |
{EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV}; |
|
911 |
||
912 |
void br(Condition cond, address dest) { |
|
913 |
long offset = (dest - pc()) >> 2; |
|
914 |
starti; |
|
915 |
f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); |
|
916 |
} |
|
917 |
||
918 |
#define INSN(NAME, cond) \ |
|
919 |
void NAME(address dest) { \ |
|
920 |
br(cond, dest); \ |
|
921 |
} |
|
922 |
||
923 |
INSN(beq, EQ); |
|
924 |
INSN(bne, NE); |
|
925 |
INSN(bhs, HS); |
|
926 |
INSN(bcs, CS); |
|
927 |
INSN(blo, LO); |
|
928 |
INSN(bcc, CC); |
|
929 |
INSN(bmi, MI); |
|
930 |
INSN(bpl, PL); |
|
931 |
INSN(bvs, VS); |
|
932 |
INSN(bvc, VC); |
|
933 |
INSN(bhi, HI); |
|
934 |
INSN(bls, LS); |
|
935 |
INSN(bge, GE); |
|
936 |
INSN(blt, LT); |
|
937 |
INSN(bgt, GT); |
|
938 |
INSN(ble, LE); |
|
939 |
INSN(bal, AL); |
|
940 |
INSN(bnv, NV); |
|
941 |
||
942 |
void br(Condition cc, Label &L); |
|
943 |
||
944 |
#undef INSN |
|
945 |
||
946 |
// Exception generation |
|
947 |
void generate_exception(int opc, int op2, int LL, unsigned imm) { |
|
948 |
starti; |
|
949 |
f(0b11010100, 31, 24); |
|
950 |
f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0); |
|
951 |
} |
|
952 |
||
953 |
#define INSN(NAME, opc, op2, LL) \ |
|
954 |
void NAME(unsigned imm) { \ |
|
955 |
generate_exception(opc, op2, LL, imm); \ |
|
956 |
} |
|
957 |
||
958 |
INSN(svc, 0b000, 0, 0b01); |
|
959 |
INSN(hvc, 0b000, 0, 0b10); |
|
960 |
INSN(smc, 0b000, 0, 0b11); |
|
961 |
INSN(brk, 0b001, 0, 0b00); |
|
962 |
INSN(hlt, 0b010, 0, 0b00); |
|
963 |
INSN(dpcs1, 0b101, 0, 0b01); |
|
964 |
INSN(dpcs2, 0b101, 0, 0b10); |
|
965 |
INSN(dpcs3, 0b101, 0, 0b11); |
|
966 |
||
967 |
#undef INSN |
|
968 |
||
969 |
// System |
|
970 |
void system(int op0, int op1, int CRn, int CRm, int op2, |
|
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
35127
diff
changeset
|
971 |
Register rt = dummy_reg) |
29183 | 972 |
{ |
973 |
starti; |
|
974 |
f(0b11010101000, 31, 21); |
|
975 |
f(op0, 20, 19); |
|
976 |
f(op1, 18, 16); |
|
977 |
f(CRn, 15, 12); |
|
978 |
f(CRm, 11, 8); |
|
979 |
f(op2, 7, 5); |
|
980 |
rf(rt, 0); |
|
981 |
} |
|
982 |
||
983 |
void hint(int imm) { |
|
48141 | 984 |
system(0b00, 0b011, 0b0010, 0b0000, imm); |
29183 | 985 |
} |
986 |
||
987 |
void nop() { |
|
988 |
hint(0); |
|
989 |
} |
|
48141 | 990 |
|
991 |
void yield() { |
|
992 |
hint(1); |
|
993 |
} |
|
994 |
||
995 |
void wfe() { |
|
996 |
hint(2); |
|
997 |
} |
|
998 |
||
999 |
void wfi() { |
|
1000 |
hint(3); |
|
1001 |
} |
|
1002 |
||
1003 |
void sev() { |
|
1004 |
hint(4); |
|
1005 |
} |
|
1006 |
||
1007 |
void sevl() { |
|
1008 |
hint(5); |
|
1009 |
} |
|
1010 |
||
29183 | 1011 |
// we only provide mrs and msr for the special purpose system |
1012 |
// registers where op1 (instr[20:19]) == 11 and, (currently) only |
|
1013 |
// use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1 |
|
1014 |
||
1015 |
void msr(int op1, int CRn, int CRm, int op2, Register rt) { |
|
1016 |
starti; |
|
1017 |
f(0b1101010100011, 31, 19); |
|
1018 |
f(op1, 18, 16); |
|
1019 |
f(CRn, 15, 12); |
|
1020 |
f(CRm, 11, 8); |
|
1021 |
f(op2, 7, 5); |
|
1022 |
// writing zr is ok |
|
1023 |
zrf(rt, 0); |
|
1024 |
} |
|
1025 |
||
1026 |
void mrs(int op1, int CRn, int CRm, int op2, Register rt) { |
|
1027 |
starti; |
|
1028 |
f(0b1101010100111, 31, 19); |
|
1029 |
f(op1, 18, 16); |
|
1030 |
f(CRn, 15, 12); |
|
1031 |
f(CRm, 11, 8); |
|
1032 |
f(op2, 7, 5); |
|
1033 |
// reading to zr is a mistake |
|
1034 |
rf(rt, 0); |
|
1035 |
} |
|
1036 |
||
1037 |
enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH, |
|
1038 |
ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; |
|
1039 |
||
1040 |
void dsb(barrier imm) { |
|
1041 |
system(0b00, 0b011, 0b00011, imm, 0b100); |
|
1042 |
} |
|
1043 |
||
1044 |
void dmb(barrier imm) { |
|
1045 |
system(0b00, 0b011, 0b00011, imm, 0b101); |
|
1046 |
} |
|
1047 |
||
1048 |
void isb() { |
|
1049 |
system(0b00, 0b011, 0b00011, SY, 0b110); |
|
1050 |
} |
|
1051 |
||
38143 | 1052 |
void sys(int op1, int CRn, int CRm, int op2, |
1053 |
Register rt = (Register)0b11111) { |
|
1054 |
system(0b01, op1, CRn, CRm, op2, rt); |
|
29183 | 1055 |
} |
1056 |
||
38143 | 1057 |
// Only implement operations accessible from EL0 or higher, i.e., |
1058 |
// op1 CRn CRm op2 |
|
1059 |
// IC IVAU 3 7 5 1 |
|
1060 |
// DC CVAC 3 7 10 1 |
|
57804 | 1061 |
// DC CVAP 3 7 12 1 |
38143 | 1062 |
// DC CVAU 3 7 11 1 |
1063 |
// DC CIVAC 3 7 14 1 |
|
1064 |
// DC ZVA 3 7 4 1 |
|
1065 |
// So only deal with the CRm field. |
|
1066 |
enum icache_maintenance {IVAU = 0b0101}; |
|
57804 | 1067 |
enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100}; |
38143 | 1068 |
|
1069 |
void dc(dcache_maintenance cm, Register Rt) { |
|
1070 |
sys(0b011, 0b0111, cm, 0b001, Rt); |
|
1071 |
} |
|
1072 |
||
1073 |
void ic(icache_maintenance cm, Register Rt) { |
|
1074 |
sys(0b011, 0b0111, cm, 0b001, Rt); |
|
29183 | 1075 |
} |
1076 |
||
1077 |
// A more convenient access to dmb for our purposes |
|
1078 |
enum Membar_mask_bits { |
|
1079 |
// We can use ISH for a barrier because the ARM ARM says "This |
|
1080 |
// architecture assumes that all Processing Elements that use the |
|
1081 |
// same operating system or hypervisor are in the same Inner |
|
1082 |
// Shareable shareability domain." |
|
1083 |
StoreStore = ISHST, |
|
1084 |
LoadStore = ISHLD, |
|
1085 |
LoadLoad = ISHLD, |
|
1086 |
StoreLoad = ISH, |
|
1087 |
AnyAny = ISH |
|
1088 |
}; |
|
1089 |
||
1090 |
void membar(Membar_mask_bits order_constraint) { |
|
1091 |
dmb(Assembler::barrier(order_constraint)); |
|
1092 |
} |
|
1093 |
||
1094 |
// Unconditional branch (register) |
|
1095 |
void branch_reg(Register R, int opc) { |
|
1096 |
starti; |
|
1097 |
f(0b1101011, 31, 25); |
|
1098 |
f(opc, 24, 21); |
|
1099 |
f(0b11111000000, 20, 10); |
|
1100 |
rf(R, 5); |
|
1101 |
f(0b00000, 4, 0); |
|
1102 |
} |
|
1103 |
||
1104 |
#define INSN(NAME, opc) \ |
|
1105 |
void NAME(Register R) { \ |
|
1106 |
branch_reg(R, opc); \ |
|
1107 |
} |
|
1108 |
||
1109 |
INSN(br, 0b0000); |
|
1110 |
INSN(blr, 0b0001); |
|
1111 |
INSN(ret, 0b0010); |
|
1112 |
||
1113 |
void ret(void *p); // This forces a compile-time error for ret(0) |
|
1114 |
||
1115 |
#undef INSN |
|
1116 |
||
1117 |
#define INSN(NAME, opc) \ |
|
1118 |
void NAME() { \ |
|
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
35127
diff
changeset
|
1119 |
branch_reg(dummy_reg, opc); \ |
29183 | 1120 |
} |
1121 |
||
1122 |
INSN(eret, 0b0100); |
|
1123 |
INSN(drps, 0b0101); |
|
1124 |
||
1125 |
#undef INSN |
|
1126 |
||
1127 |
// Load/store exclusive |
|
1128 |
enum operand_size { byte, halfword, word, xword }; |
|
1129 |
||
1130 |
void load_store_exclusive(Register Rs, Register Rt1, Register Rt2, |
|
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
35127
diff
changeset
|
1131 |
Register Rn, enum operand_size sz, int op, bool ordered) { |
29183 | 1132 |
starti; |
1133 |
f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
1134 |
rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0); |
36562
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
35127
diff
changeset
|
1135 |
} |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
enevill
parents:
35127
diff
changeset
|
1136 |
|
4d1e93624d6a
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changeset
|
1137 |
void load_exclusive(Register dst, Register addr, |
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|
1138 |
enum operand_size sz, bool ordered) { |
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|
1139 |
load_store_exclusive(dummy_reg, dst, dummy_reg, addr, |
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|
1140 |
sz, 0b010, ordered); |
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8150394: aarch64: add support for 8.1 LSE CAS instructions
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changeset
|
1141 |
} |
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changeset
|
1142 |
|
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changeset
|
1143 |
void store_exclusive(Register status, Register new_val, Register addr, |
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changeset
|
1144 |
enum operand_size sz, bool ordered) { |
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changeset
|
1145 |
load_store_exclusive(status, new_val, dummy_reg, addr, |
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|
1146 |
sz, 0b000, ordered); |
29183 | 1147 |
} |
1148 |
||
1149 |
#define INSN4(NAME, sz, op, o0) /* Four registers */ \ |
|
1150 |
void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ |
|
32395
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changeset
|
1151 |
guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \ |
29183 | 1152 |
load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ |
1153 |
} |
|
1154 |
||
1155 |
#define INSN3(NAME, sz, op, o0) /* Three registers */ \ |
|
1156 |
void NAME(Register Rs, Register Rt, Register Rn) { \ |
|
32395
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changeset
|
1157 |
guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ |
36562
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changeset
|
1158 |
load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \ |
29183 | 1159 |
} |
1160 |
||
1161 |
#define INSN2(NAME, sz, op, o0) /* Two registers */ \ |
|
1162 |
void NAME(Register Rt, Register Rn) { \ |
|
36562
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|
1163 |
load_store_exclusive(dummy_reg, Rt, dummy_reg, \ |
29183 | 1164 |
Rn, sz, op, o0); \ |
1165 |
} |
|
1166 |
||
1167 |
#define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \ |
|
1168 |
void NAME(Register Rt1, Register Rt2, Register Rn) { \ |
|
32395
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changeset
|
1169 |
guarantee(Rt1 != Rt2, "unpredictable instruction"); \ |
36562
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changeset
|
1170 |
load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \ |
29183 | 1171 |
} |
1172 |
||
1173 |
// bytes |
|
1174 |
INSN3(stxrb, byte, 0b000, 0); |
|
1175 |
INSN3(stlxrb, byte, 0b000, 1); |
|
1176 |
INSN2(ldxrb, byte, 0b010, 0); |
|
1177 |
INSN2(ldaxrb, byte, 0b010, 1); |
|
1178 |
INSN2(stlrb, byte, 0b100, 1); |
|
1179 |
INSN2(ldarb, byte, 0b110, 1); |
|
1180 |
||
1181 |
// halfwords |
|
1182 |
INSN3(stxrh, halfword, 0b000, 0); |
|
1183 |
INSN3(stlxrh, halfword, 0b000, 1); |
|
1184 |
INSN2(ldxrh, halfword, 0b010, 0); |
|
1185 |
INSN2(ldaxrh, halfword, 0b010, 1); |
|
1186 |
INSN2(stlrh, halfword, 0b100, 1); |
|
1187 |
INSN2(ldarh, halfword, 0b110, 1); |
|
1188 |
||
1189 |
// words |
|
1190 |
INSN3(stxrw, word, 0b000, 0); |
|
1191 |
INSN3(stlxrw, word, 0b000, 1); |
|
1192 |
INSN4(stxpw, word, 0b001, 0); |
|
1193 |
INSN4(stlxpw, word, 0b001, 1); |
|
1194 |
INSN2(ldxrw, word, 0b010, 0); |
|
1195 |
INSN2(ldaxrw, word, 0b010, 1); |
|
1196 |
INSN_FOO(ldxpw, word, 0b011, 0); |
|
1197 |
INSN_FOO(ldaxpw, word, 0b011, 1); |
|
1198 |
INSN2(stlrw, word, 0b100, 1); |
|
1199 |
INSN2(ldarw, word, 0b110, 1); |
|
1200 |
||
1201 |
// xwords |
|
1202 |
INSN3(stxr, xword, 0b000, 0); |
|
1203 |
INSN3(stlxr, xword, 0b000, 1); |
|
1204 |
INSN4(stxp, xword, 0b001, 0); |
|
1205 |
INSN4(stlxp, xword, 0b001, 1); |
|
1206 |
INSN2(ldxr, xword, 0b010, 0); |
|
1207 |
INSN2(ldaxr, xword, 0b010, 1); |
|
1208 |
INSN_FOO(ldxp, xword, 0b011, 0); |
|
1209 |
INSN_FOO(ldaxp, xword, 0b011, 1); |
|
1210 |
INSN2(stlr, xword, 0b100, 1); |
|
1211 |
INSN2(ldar, xword, 0b110, 1); |
|
1212 |
||
1213 |
#undef INSN2 |
|
1214 |
#undef INSN3 |
|
1215 |
#undef INSN4 |
|
1216 |
#undef INSN_FOO |
|
1217 |
||
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changeset
|
1218 |
// 8.1 Compare and swap extensions |
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changeset
|
1219 |
void lse_cas(Register Rs, Register Rt, Register Rn, |
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changeset
|
1220 |
enum operand_size sz, bool a, bool r, bool not_pair) { |
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changeset
|
1221 |
starti; |
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changeset
|
1222 |
if (! not_pair) { // Pair |
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changeset
|
1223 |
assert(sz == word || sz == xword, "invalid size"); |
4d1e93624d6a
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changeset
|
1224 |
/* The size bit is in bit 30, not 31 */ |
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changeset
|
1225 |
sz = (operand_size)(sz == word ? 0b00:0b01); |
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changeset
|
1226 |
} |
54453
7b5e2bc79e68
8221995: AARCH64: problems with CAS instructions encoding
dpochepk
parents:
54066
diff
changeset
|
1227 |
f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21); |
7b5e2bc79e68
8221995: AARCH64: problems with CAS instructions encoding
dpochepk
parents:
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diff
changeset
|
1228 |
zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0); |
36562
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changeset
|
1229 |
} |
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changeset
|
1230 |
|
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changeset
|
1231 |
// CAS |
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changeset
|
1232 |
#define INSN(NAME, a, r) \ |
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changeset
|
1233 |
void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \ |
4d1e93624d6a
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changeset
|
1234 |
assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ |
4d1e93624d6a
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changeset
|
1235 |
lse_cas(Rs, Rt, Rn, sz, a, r, true); \ |
4d1e93624d6a
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changeset
|
1236 |
} |
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changeset
|
1237 |
INSN(cas, false, false) |
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changeset
|
1238 |
INSN(casa, true, false) |
4d1e93624d6a
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changeset
|
1239 |
INSN(casl, false, true) |
4d1e93624d6a
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changeset
|
1240 |
INSN(casal, true, true) |
4d1e93624d6a
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changeset
|
1241 |
#undef INSN |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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changeset
|
1242 |
|
4d1e93624d6a
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changeset
|
1243 |
// CASP |
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changeset
|
1244 |
#define INSN(NAME, a, r) \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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changeset
|
1245 |
void NAME(operand_size sz, Register Rs, Register Rs1, \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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changeset
|
1246 |
Register Rt, Register Rt1, Register Rn) { \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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changeset
|
1247 |
assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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diff
changeset
|
1248 |
Rs->successor() == Rs1 && Rt->successor() == Rt1 && \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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diff
changeset
|
1249 |
Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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changeset
|
1250 |
lse_cas(Rs, Rt, Rn, sz, a, r, false); \ |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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diff
changeset
|
1251 |
} |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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diff
changeset
|
1252 |
INSN(casp, false, false) |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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diff
changeset
|
1253 |
INSN(caspa, true, false) |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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parents:
35127
diff
changeset
|
1254 |
INSN(caspl, false, true) |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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parents:
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diff
changeset
|
1255 |
INSN(caspal, true, true) |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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parents:
35127
diff
changeset
|
1256 |
#undef INSN |
4d1e93624d6a
8150394: aarch64: add support for 8.1 LSE CAS instructions
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parents:
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diff
changeset
|
1257 |
|
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1258 |
// 8.1 Atomic operations |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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changeset
|
1259 |
void lse_atomic(Register Rs, Register Rt, Register Rn, |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1260 |
enum operand_size sz, int op1, int op2, bool a, bool r) { |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1261 |
starti; |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1262 |
f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21); |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
1263 |
zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0); |
37269
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1264 |
} |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1265 |
|
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
36562
diff
changeset
|
1266 |
#define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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diff
changeset
|
1267 |
void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1268 |
lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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diff
changeset
|
1269 |
} \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1270 |
void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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diff
changeset
|
1271 |
lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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diff
changeset
|
1272 |
} \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
36562
diff
changeset
|
1273 |
void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1274 |
lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1275 |
} \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1276 |
void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1277 |
lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \ |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1278 |
} |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
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parents:
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diff
changeset
|
1279 |
INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1280 |
INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1281 |
INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1282 |
INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1283 |
INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1284 |
INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1285 |
INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1286 |
INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
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diff
changeset
|
1287 |
INSN(swp, swpa, swpl, swpal, 1, 0b000); |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1288 |
#undef INSN |
5c2c4e5bb067
8151775: aarch64: add support for 8.1 LSE atomic operations
enevill
parents:
36562
diff
changeset
|
1289 |
|
29183 | 1290 |
// Load register (literal) |
1291 |
#define INSN(NAME, opc, V) \ |
|
1292 |
void NAME(Register Rt, address dest) { \ |
|
1293 |
long offset = (dest - pc()) >> 2; \ |
|
1294 |
starti; \ |
|
1295 |
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ |
|
1296 |
sf(offset, 23, 5); \ |
|
1297 |
rf(Rt, 0); \ |
|
1298 |
} \ |
|
1299 |
void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ |
|
1300 |
InstructionMark im(this); \ |
|
1301 |
guarantee(rtype == relocInfo::internal_word_type, \ |
|
1302 |
"only internal_word_type relocs make sense here"); \ |
|
1303 |
code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \ |
|
1304 |
NAME(Rt, dest); \ |
|
1305 |
} \ |
|
1306 |
void NAME(Register Rt, Label &L) { \ |
|
1307 |
wrap_label(Rt, L, &Assembler::NAME); \ |
|
1308 |
} |
|
1309 |
||
1310 |
INSN(ldrw, 0b00, 0); |
|
1311 |
INSN(ldr, 0b01, 0); |
|
1312 |
INSN(ldrsw, 0b10, 0); |
|
1313 |
||
1314 |
#undef INSN |
|
1315 |
||
1316 |
#define INSN(NAME, opc, V) \ |
|
1317 |
void NAME(FloatRegister Rt, address dest) { \ |
|
1318 |
long offset = (dest - pc()) >> 2; \ |
|
1319 |
starti; \ |
|
1320 |
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ |
|
1321 |
sf(offset, 23, 5); \ |
|
1322 |
rf((Register)Rt, 0); \ |
|
1323 |
} |
|
1324 |
||
1325 |
INSN(ldrs, 0b00, 1); |
|
1326 |
INSN(ldrd, 0b01, 1); |
|
32574 | 1327 |
INSN(ldrq, 0b10, 1); |
29183 | 1328 |
|
1329 |
#undef INSN |
|
1330 |
||
1331 |
#define INSN(NAME, opc, V) \ |
|
1332 |
void NAME(address dest, prfop op = PLDL1KEEP) { \ |
|
1333 |
long offset = (dest - pc()) >> 2; \ |
|
1334 |
starti; \ |
|
1335 |
f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ |
|
1336 |
sf(offset, 23, 5); \ |
|
1337 |
f(op, 4, 0); \ |
|
1338 |
} \ |
|
1339 |
void NAME(Label &L, prfop op = PLDL1KEEP) { \ |
|
1340 |
wrap_label(L, op, &Assembler::NAME); \ |
|
1341 |
} |
|
1342 |
||
1343 |
INSN(prfm, 0b11, 0); |
|
1344 |
||
1345 |
#undef INSN |
|
1346 |
||
1347 |
// Load/store |
|
1348 |
void ld_st1(int opc, int p1, int V, int L, |
|
1349 |
Register Rt1, Register Rt2, Address adr, bool no_allocate) { |
|
1350 |
starti; |
|
1351 |
f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22); |
|
1352 |
zrf(Rt2, 10), zrf(Rt1, 0); |
|
1353 |
if (no_allocate) { |
|
1354 |
adr.encode_nontemporal_pair(current); |
|
1355 |
} else { |
|
1356 |
adr.encode_pair(current); |
|
1357 |
} |
|
1358 |
} |
|
1359 |
||
1360 |
// Load/store register pair (offset) |
|
1361 |
#define INSN(NAME, size, p1, V, L, no_allocate) \ |
|
1362 |
void NAME(Register Rt1, Register Rt2, Address adr) { \ |
|
1363 |
ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ |
|
1364 |
} |
|
1365 |
||
1366 |
INSN(stpw, 0b00, 0b101, 0, 0, false); |
|
1367 |
INSN(ldpw, 0b00, 0b101, 0, 1, false); |
|
1368 |
INSN(ldpsw, 0b01, 0b101, 0, 1, false); |
|
1369 |
INSN(stp, 0b10, 0b101, 0, 0, false); |
|
1370 |
INSN(ldp, 0b10, 0b101, 0, 1, false); |
|
1371 |
||
1372 |
// Load/store no-allocate pair (offset) |
|
1373 |
INSN(stnpw, 0b00, 0b101, 0, 0, true); |
|
1374 |
INSN(ldnpw, 0b00, 0b101, 0, 1, true); |
|
1375 |
INSN(stnp, 0b10, 0b101, 0, 0, true); |
|
1376 |
INSN(ldnp, 0b10, 0b101, 0, 1, true); |
|
1377 |
||
1378 |
#undef INSN |
|
1379 |
||
1380 |
#define INSN(NAME, size, p1, V, L, no_allocate) \ |
|
1381 |
void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ |
|
1382 |
ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \ |
|
1383 |
} |
|
1384 |
||
1385 |
INSN(stps, 0b00, 0b101, 1, 0, false); |
|
1386 |
INSN(ldps, 0b00, 0b101, 1, 1, false); |
|
1387 |
INSN(stpd, 0b01, 0b101, 1, 0, false); |
|
1388 |
INSN(ldpd, 0b01, 0b101, 1, 1, false); |
|
1389 |
INSN(stpq, 0b10, 0b101, 1, 0, false); |
|
1390 |
INSN(ldpq, 0b10, 0b101, 1, 1, false); |
|
1391 |
||
1392 |
#undef INSN |
|
1393 |
||
1394 |
// Load/store register (all modes) |
|
1395 |
void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) { |
|
1396 |
starti; |
|
1397 |
||
1398 |
f(V, 26); // general reg? |
|
1399 |
zrf(Rt, 0); |
|
1400 |
||
1401 |
// Encoding for literal loads is done here (rather than pushed |
|
1402 |
// down into Address::encode) because the encoding of this |
|
1403 |
// instruction is too different from all of the other forms to |
|
1404 |
// make it worth sharing. |
|
1405 |
if (adr.getMode() == Address::literal) { |
|
1406 |
assert(size == 0b10 || size == 0b11, "bad operand size in ldr"); |
|
1407 |
assert(op == 0b01, "literal form can only be used with loads"); |
|
1408 |
f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24); |
|
1409 |
long offset = (adr.target() - pc()) >> 2; |
|
1410 |
sf(offset, 23, 5); |
|
1411 |
code_section()->relocate(pc(), adr.rspec()); |
|
1412 |
return; |
|
1413 |
} |
|
1414 |
||
1415 |
f(size, 31, 30); |
|
1416 |
f(op, 23, 22); // str |
|
1417 |
adr.encode(current); |
|
1418 |
} |
|
1419 |
||
1420 |
#define INSN(NAME, size, op) \ |
|
1421 |
void NAME(Register Rt, const Address &adr) { \ |
|
1422 |
ld_st2(Rt, adr, size, op); \ |
|
1423 |
} \ |
|
1424 |
||
1425 |
INSN(str, 0b11, 0b00); |
|
1426 |
INSN(strw, 0b10, 0b00); |
|
1427 |
INSN(strb, 0b00, 0b00); |
|
1428 |
INSN(strh, 0b01, 0b00); |
|
1429 |
||
1430 |
INSN(ldr, 0b11, 0b01); |
|
1431 |
INSN(ldrw, 0b10, 0b01); |
|
1432 |
INSN(ldrb, 0b00, 0b01); |
|
1433 |
INSN(ldrh, 0b01, 0b01); |
|
1434 |
||
1435 |
INSN(ldrsb, 0b00, 0b10); |
|
1436 |
INSN(ldrsbw, 0b00, 0b11); |
|
1437 |
INSN(ldrsh, 0b01, 0b10); |
|
1438 |
INSN(ldrshw, 0b01, 0b11); |
|
1439 |
INSN(ldrsw, 0b10, 0b10); |
|
1440 |
||
1441 |
#undef INSN |
|
1442 |
||
1443 |
#define INSN(NAME, size, op) \ |
|
1444 |
void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ |
|
1445 |
ld_st2((Register)pfop, adr, size, op); \ |
|
1446 |
} |
|
1447 |
||
1448 |
INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with |
|
1449 |
// writeback modes, but the assembler |
|
1450 |
// doesn't enfore that. |
|
1451 |
||
1452 |
#undef INSN |
|
1453 |
||
1454 |
#define INSN(NAME, size, op) \ |
|
1455 |
void NAME(FloatRegister Rt, const Address &adr) { \ |
|
1456 |
ld_st2((Register)Rt, adr, size, op, 1); \ |
|
1457 |
} |
|
1458 |
||
1459 |
INSN(strd, 0b11, 0b00); |
|
1460 |
INSN(strs, 0b10, 0b00); |
|
1461 |
INSN(ldrd, 0b11, 0b01); |
|
1462 |
INSN(ldrs, 0b10, 0b01); |
|
1463 |
INSN(strq, 0b00, 0b10); |
|
1464 |
INSN(ldrq, 0x00, 0b11); |
|
1465 |
||
1466 |
#undef INSN |
|
1467 |
||
1468 |
enum shift_kind { LSL, LSR, ASR, ROR }; |
|
1469 |
||
1470 |
void op_shifted_reg(unsigned decode, |
|
1471 |
enum shift_kind kind, unsigned shift, |
|
1472 |
unsigned size, unsigned op) { |
|
1473 |
f(size, 31); |
|
1474 |
f(op, 30, 29); |
|
1475 |
f(decode, 28, 24); |
|
1476 |
f(shift, 15, 10); |
|
1477 |
f(kind, 23, 22); |
|
1478 |
} |
|
1479 |
||
1480 |
// Logical (shifted register) |
|
1481 |
#define INSN(NAME, size, op, N) \ |
|
1482 |
void NAME(Register Rd, Register Rn, Register Rm, \ |
|
1483 |
enum shift_kind kind = LSL, unsigned shift = 0) { \ |
|
1484 |
starti; \ |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
1485 |
guarantee(size == 1 || shift < 32, "incorrect shift"); \ |
29183 | 1486 |
f(N, 21); \ |
1487 |
zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ |
|
1488 |
op_shifted_reg(0b01010, kind, shift, size, op); \ |
|
1489 |
} |
|
1490 |
||
1491 |
INSN(andr, 1, 0b00, 0); |
|
1492 |
INSN(orr, 1, 0b01, 0); |
|
1493 |
INSN(eor, 1, 0b10, 0); |
|
1494 |
INSN(ands, 1, 0b11, 0); |
|
1495 |
INSN(andw, 0, 0b00, 0); |
|
1496 |
INSN(orrw, 0, 0b01, 0); |
|
1497 |
INSN(eorw, 0, 0b10, 0); |
|
1498 |
INSN(andsw, 0, 0b11, 0); |
|
1499 |
||
55054
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1500 |
#undef INSN |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1501 |
|
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1502 |
#define INSN(NAME, size, op, N) \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1503 |
void NAME(Register Rd, Register Rn, Register Rm, \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1504 |
enum shift_kind kind = LSL, unsigned shift = 0) { \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1505 |
starti; \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1506 |
f(N, 21); \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1507 |
zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1508 |
op_shifted_reg(0b01010, kind, shift, size, op); \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1509 |
} \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1510 |
\ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1511 |
/* These instructions have no immediate form. Provide an overload so \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1512 |
that if anyone does try to use an immediate operand -- this has \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1513 |
happened! -- we'll get a compile-time error. */ \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1514 |
void NAME(Register Rd, Register Rn, unsigned imm, \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1515 |
enum shift_kind kind = LSL, unsigned shift = 0) { \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1516 |
assert(false, " can't be used with immediate operand"); \ |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1517 |
} |
78e49883146f
8224671: AArch64: mauve System.arraycopy test failure
aph
parents:
54960
diff
changeset
|
1518 |
|
29183 | 1519 |
INSN(bic, 1, 0b00, 1); |
1520 |
INSN(orn, 1, 0b01, 1); |
|
1521 |
INSN(eon, 1, 0b10, 1); |
|
1522 |
INSN(bics, 1, 0b11, 1); |
|
1523 |
INSN(bicw, 0, 0b00, 1); |
|
1524 |
INSN(ornw, 0, 0b01, 1); |
|
1525 |
INSN(eonw, 0, 0b10, 1); |
|
1526 |
INSN(bicsw, 0, 0b11, 1); |
|
1527 |
||
1528 |
#undef INSN |
|
1529 |
||
47773
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1530 |
// Aliases for short forms of orn |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1531 |
void mvn(Register Rd, Register Rm, |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1532 |
enum shift_kind kind = LSL, unsigned shift = 0) { |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1533 |
orn(Rd, zr, Rm, kind, shift); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1534 |
} |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1535 |
|
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1536 |
void mvnw(Register Rd, Register Rm, |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1537 |
enum shift_kind kind = LSL, unsigned shift = 0) { |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1538 |
ornw(Rd, zr, Rm, kind, shift); |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1539 |
} |
6e3ab27f9144
8189176: AARCH64: Improve _updateBytesCRC32 intrinsic
dchuyko
parents:
47216
diff
changeset
|
1540 |
|
29183 | 1541 |
// Add/subtract (shifted register) |
1542 |
#define INSN(NAME, size, op) \ |
|
1543 |
void NAME(Register Rd, Register Rn, Register Rm, \ |
|
1544 |
enum shift_kind kind, unsigned shift = 0) { \ |
|
1545 |
starti; \ |
|
1546 |
f(0, 21); \ |
|
1547 |
assert_cond(kind != ROR); \ |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
1548 |
guarantee(size == 1 || shift < 32, "incorrect shift");\ |
29183 | 1549 |
zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ |
1550 |
op_shifted_reg(0b01011, kind, shift, size, op); \ |
|
1551 |
} |
|
1552 |
||
1553 |
INSN(add, 1, 0b000); |
|
1554 |
INSN(sub, 1, 0b10); |
|
1555 |
INSN(addw, 0, 0b000); |
|
1556 |
INSN(subw, 0, 0b10); |
|
1557 |
||
1558 |
INSN(adds, 1, 0b001); |
|
1559 |
INSN(subs, 1, 0b11); |
|
1560 |
INSN(addsw, 0, 0b001); |
|
1561 |
INSN(subsw, 0, 0b11); |
|
1562 |
||
1563 |
#undef INSN |
|
1564 |
||
1565 |
// Add/subtract (extended register) |
|
1566 |
#define INSN(NAME, op) \ |
|
1567 |
void NAME(Register Rd, Register Rn, Register Rm, \ |
|
1568 |
ext::operation option, int amount = 0) { \ |
|
1569 |
starti; \ |
|
1570 |
zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ |
|
1571 |
add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ |
|
1572 |
} |
|
1573 |
||
1574 |
void add_sub_extended_reg(unsigned op, unsigned decode, |
|
1575 |
Register Rd, Register Rn, Register Rm, |
|
1576 |
unsigned opt, ext::operation option, unsigned imm) { |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
1577 |
guarantee(imm <= 4, "shift amount must be <= 4"); |
29183 | 1578 |
f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21); |
1579 |
f(option, 15, 13), f(imm, 12, 10); |
|
1580 |
} |
|
1581 |
||
1582 |
INSN(addw, 0b000); |
|
1583 |
INSN(subw, 0b010); |
|
1584 |
INSN(add, 0b100); |
|
1585 |
INSN(sub, 0b110); |
|
1586 |
||
1587 |
#undef INSN |
|
1588 |
||
1589 |
#define INSN(NAME, op) \ |
|
1590 |
void NAME(Register Rd, Register Rn, Register Rm, \ |
|
1591 |
ext::operation option, int amount = 0) { \ |
|
1592 |
starti; \ |
|
1593 |
zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ |
|
1594 |
add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ |
|
1595 |
} |
|
1596 |
||
1597 |
INSN(addsw, 0b001); |
|
1598 |
INSN(subsw, 0b011); |
|
1599 |
INSN(adds, 0b101); |
|
1600 |
INSN(subs, 0b111); |
|
1601 |
||
1602 |
#undef INSN |
|
1603 |
||
1604 |
// Aliases for short forms of add and sub |
|
1605 |
#define INSN(NAME) \ |
|
1606 |
void NAME(Register Rd, Register Rn, Register Rm) { \ |
|
1607 |
if (Rd == sp || Rn == sp) \ |
|
1608 |
NAME(Rd, Rn, Rm, ext::uxtx); \ |
|
1609 |
else \ |
|
1610 |
NAME(Rd, Rn, Rm, LSL); \ |
|
1611 |
} |
|
1612 |
||
1613 |
INSN(addw); |
|
1614 |
INSN(subw); |
|
1615 |
INSN(add); |
|
1616 |
INSN(sub); |
|
1617 |
||
1618 |
INSN(addsw); |
|
1619 |
INSN(subsw); |
|
1620 |
INSN(adds); |
|
1621 |
INSN(subs); |
|
1622 |
||
1623 |
#undef INSN |
|
1624 |
||
1625 |
// Add/subtract (with carry) |
|
1626 |
void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) { |
|
1627 |
starti; |
|
1628 |
f(op, 31, 29); |
|
1629 |
f(0b11010000, 28, 21); |
|
1630 |
f(0b000000, 15, 10); |
|
30225
e9722ea461d4
8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents:
29183
diff
changeset
|
1631 |
zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); |
29183 | 1632 |
} |
1633 |
||
1634 |
#define INSN(NAME, op) \ |
|
1635 |
void NAME(Register Rd, Register Rn, Register Rm) { \ |
|
1636 |
add_sub_carry(op, Rd, Rn, Rm); \ |
|
1637 |
} |
|
1638 |
||
1639 |
INSN(adcw, 0b000); |
|
1640 |
INSN(adcsw, 0b001); |
|
1641 |
INSN(sbcw, 0b010); |
|
1642 |
INSN(sbcsw, 0b011); |
|
1643 |
INSN(adc, 0b100); |
|
1644 |
INSN(adcs, 0b101); |
|
1645 |
INSN(sbc,0b110); |
|
1646 |
INSN(sbcs, 0b111); |
|
1647 |
||
1648 |
#undef INSN |
|
1649 |
||
1650 |
// Conditional compare (both kinds) |
|
50717
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1651 |
void conditional_compare(unsigned op, int o1, int o2, int o3, |
29183 | 1652 |
Register Rn, unsigned imm5, unsigned nzcv, |
1653 |
unsigned cond) { |
|
50717
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1654 |
starti; |
29183 | 1655 |
f(op, 31, 29); |
1656 |
f(0b11010010, 28, 21); |
|
1657 |
f(cond, 15, 12); |
|
50717
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1658 |
f(o1, 11); |
29183 | 1659 |
f(o2, 10); |
1660 |
f(o3, 4); |
|
1661 |
f(nzcv, 3, 0); |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
1662 |
f(imm5, 20, 16), zrf(Rn, 5); |
29183 | 1663 |
} |
1664 |
||
1665 |
#define INSN(NAME, op) \ |
|
1666 |
void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ |
|
50717
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1667 |
int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm); \ |
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1668 |
conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond); \ |
29183 | 1669 |
} \ |
1670 |
\ |
|
50717
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1671 |
void NAME(Register Rn, int imm5, int imm, Condition cond) { \ |
365e137617ff
8205474: AARCH64: wrong zr encoding for ccmp instruction
dpochepk
parents:
50644
diff
changeset
|
1672 |
conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond); \ |
29183 | 1673 |
} |
1674 |
||
1675 |
INSN(ccmnw, 0b001); |
|
1676 |
INSN(ccmpw, 0b011); |
|
1677 |
INSN(ccmn, 0b101); |
|
1678 |
INSN(ccmp, 0b111); |
|
1679 |
||
1680 |
#undef INSN |
|
1681 |
||
1682 |
// Conditional select |
|
1683 |
void conditional_select(unsigned op, unsigned op2, |
|
1684 |
Register Rd, Register Rn, Register Rm, |
|
1685 |
unsigned cond) { |
|
1686 |
starti; |
|
1687 |
f(op, 31, 29); |
|
1688 |
f(0b11010100, 28, 21); |
|
1689 |
f(cond, 15, 12); |
|
1690 |
f(op2, 11, 10); |
|
1691 |
zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0); |
|
1692 |
} |
|
1693 |
||
1694 |
#define INSN(NAME, op, op2) \ |
|
1695 |
void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \ |
|
1696 |
conditional_select(op, op2, Rd, Rn, Rm, cond); \ |
|
1697 |
} |
|
1698 |
||
1699 |
INSN(cselw, 0b000, 0b00); |
|
1700 |
INSN(csincw, 0b000, 0b01); |
|
1701 |
INSN(csinvw, 0b010, 0b00); |
|
1702 |
INSN(csnegw, 0b010, 0b01); |
|
1703 |
INSN(csel, 0b100, 0b00); |
|
1704 |
INSN(csinc, 0b100, 0b01); |
|
1705 |
INSN(csinv, 0b110, 0b00); |
|
1706 |
INSN(csneg, 0b110, 0b01); |
|
1707 |
||
1708 |
#undef INSN |
|
1709 |
||
1710 |
// Data processing |
|
1711 |
void data_processing(unsigned op29, unsigned opcode, |
|
1712 |
Register Rd, Register Rn) { |
|
1713 |
f(op29, 31, 29), f(0b11010110, 28, 21); |
|
1714 |
f(opcode, 15, 10); |
|
1715 |
rf(Rn, 5), rf(Rd, 0); |
|
1716 |
} |
|
1717 |
||
1718 |
// (1 source) |
|
1719 |
#define INSN(NAME, op29, opcode2, opcode) \ |
|
1720 |
void NAME(Register Rd, Register Rn) { \ |
|
1721 |
starti; \ |
|
1722 |
f(opcode2, 20, 16); \ |
|
1723 |
data_processing(op29, opcode, Rd, Rn); \ |
|
1724 |
} |
|
1725 |
||
1726 |
INSN(rbitw, 0b010, 0b00000, 0b00000); |
|
1727 |
INSN(rev16w, 0b010, 0b00000, 0b00001); |
|
1728 |
INSN(revw, 0b010, 0b00000, 0b00010); |
|
1729 |
INSN(clzw, 0b010, 0b00000, 0b00100); |
|
1730 |
INSN(clsw, 0b010, 0b00000, 0b00101); |
|
1731 |
||
1732 |
INSN(rbit, 0b110, 0b00000, 0b00000); |
|
1733 |
INSN(rev16, 0b110, 0b00000, 0b00001); |
|
1734 |
INSN(rev32, 0b110, 0b00000, 0b00010); |
|
1735 |
INSN(rev, 0b110, 0b00000, 0b00011); |
|
1736 |
INSN(clz, 0b110, 0b00000, 0b00100); |
|
1737 |
INSN(cls, 0b110, 0b00000, 0b00101); |
|
1738 |
||
1739 |
#undef INSN |
|
1740 |
||
1741 |
// (2 sources) |
|
1742 |
#define INSN(NAME, op29, opcode) \ |
|
1743 |
void NAME(Register Rd, Register Rn, Register Rm) { \ |
|
1744 |
starti; \ |
|
1745 |
rf(Rm, 16); \ |
|
1746 |
data_processing(op29, opcode, Rd, Rn); \ |
|
1747 |
} |
|
1748 |
||
1749 |
INSN(udivw, 0b000, 0b000010); |
|
1750 |
INSN(sdivw, 0b000, 0b000011); |
|
1751 |
INSN(lslvw, 0b000, 0b001000); |
|
1752 |
INSN(lsrvw, 0b000, 0b001001); |
|
1753 |
INSN(asrvw, 0b000, 0b001010); |
|
1754 |
INSN(rorvw, 0b000, 0b001011); |
|
1755 |
||
1756 |
INSN(udiv, 0b100, 0b000010); |
|
1757 |
INSN(sdiv, 0b100, 0b000011); |
|
1758 |
INSN(lslv, 0b100, 0b001000); |
|
1759 |
INSN(lsrv, 0b100, 0b001001); |
|
1760 |
INSN(asrv, 0b100, 0b001010); |
|
1761 |
INSN(rorv, 0b100, 0b001011); |
|
1762 |
||
1763 |
#undef INSN |
|
1764 |
||
1765 |
// (3 sources) |
|
1766 |
void data_processing(unsigned op54, unsigned op31, unsigned o0, |
|
1767 |
Register Rd, Register Rn, Register Rm, |
|
1768 |
Register Ra) { |
|
1769 |
starti; |
|
1770 |
f(op54, 31, 29), f(0b11011, 28, 24); |
|
1771 |
f(op31, 23, 21), f(o0, 15); |
|
1772 |
zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0); |
|
1773 |
} |
|
1774 |
||
1775 |
#define INSN(NAME, op54, op31, o0) \ |
|
1776 |
void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ |
|
1777 |
data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ |
|
1778 |
} |
|
1779 |
||
1780 |
INSN(maddw, 0b000, 0b000, 0); |
|
1781 |
INSN(msubw, 0b000, 0b000, 1); |
|
1782 |
INSN(madd, 0b100, 0b000, 0); |
|
1783 |
INSN(msub, 0b100, 0b000, 1); |
|
1784 |
INSN(smaddl, 0b100, 0b001, 0); |
|
1785 |
INSN(smsubl, 0b100, 0b001, 1); |
|
1786 |
INSN(umaddl, 0b100, 0b101, 0); |
|
1787 |
INSN(umsubl, 0b100, 0b101, 1); |
|
1788 |
||
1789 |
#undef INSN |
|
1790 |
||
1791 |
#define INSN(NAME, op54, op31, o0) \ |
|
1792 |
void NAME(Register Rd, Register Rn, Register Rm) { \ |
|
1793 |
data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ |
|
1794 |
} |
|
1795 |
||
1796 |
INSN(smulh, 0b100, 0b010, 0); |
|
1797 |
INSN(umulh, 0b100, 0b110, 0); |
|
1798 |
||
1799 |
#undef INSN |
|
1800 |
||
1801 |
// Floating-point data-processing (1 source) |
|
1802 |
void data_processing(unsigned op31, unsigned type, unsigned opcode, |
|
1803 |
FloatRegister Vd, FloatRegister Vn) { |
|
1804 |
starti; |
|
1805 |
f(op31, 31, 29); |
|
1806 |
f(0b11110, 28, 24); |
|
1807 |
f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10); |
|
1808 |
rf(Vn, 5), rf(Vd, 0); |
|
1809 |
} |
|
1810 |
||
1811 |
#define INSN(NAME, op31, type, opcode) \ |
|
1812 |
void NAME(FloatRegister Vd, FloatRegister Vn) { \ |
|
1813 |
data_processing(op31, type, opcode, Vd, Vn); \ |
|
1814 |
} |
|
1815 |
||
1816 |
private: |
|
1817 |
INSN(i_fmovs, 0b000, 0b00, 0b000000); |
|
1818 |
public: |
|
1819 |
INSN(fabss, 0b000, 0b00, 0b000001); |
|
1820 |
INSN(fnegs, 0b000, 0b00, 0b000010); |
|
1821 |
INSN(fsqrts, 0b000, 0b00, 0b000011); |
|
1822 |
INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision |
|
1823 |
||
1824 |
private: |
|
1825 |
INSN(i_fmovd, 0b000, 0b01, 0b000000); |
|
1826 |
public: |
|
1827 |
INSN(fabsd, 0b000, 0b01, 0b000001); |
|
1828 |
INSN(fnegd, 0b000, 0b01, 0b000010); |
|
1829 |
INSN(fsqrtd, 0b000, 0b01, 0b000011); |
|
1830 |
INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision |
|
1831 |
||
1832 |
void fmovd(FloatRegister Vd, FloatRegister Vn) { |
|
1833 |
assert(Vd != Vn, "should be"); |
|
1834 |
i_fmovd(Vd, Vn); |
|
1835 |
} |
|
1836 |
||
1837 |
void fmovs(FloatRegister Vd, FloatRegister Vn) { |
|
1838 |
assert(Vd != Vn, "should be"); |
|
1839 |
i_fmovs(Vd, Vn); |
|
1840 |
} |
|
1841 |
||
1842 |
#undef INSN |
|
1843 |
||
1844 |
// Floating-point data-processing (2 source) |
|
1845 |
void data_processing(unsigned op31, unsigned type, unsigned opcode, |
|
1846 |
FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { |
|
1847 |
starti; |
|
1848 |
f(op31, 31, 29); |
|
1849 |
f(0b11110, 28, 24); |
|
1850 |
f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10); |
|
1851 |
rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); |
|
1852 |
} |
|
1853 |
||
1854 |
#define INSN(NAME, op31, type, opcode) \ |
|
1855 |
void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ |
|
1856 |
data_processing(op31, type, opcode, Vd, Vn, Vm); \ |
|
1857 |
} |
|
1858 |
||
1859 |
INSN(fmuls, 0b000, 0b00, 0b0000); |
|
1860 |
INSN(fdivs, 0b000, 0b00, 0b0001); |
|
1861 |
INSN(fadds, 0b000, 0b00, 0b0010); |
|
1862 |
INSN(fsubs, 0b000, 0b00, 0b0011); |
|
53041 | 1863 |
INSN(fmaxs, 0b000, 0b00, 0b0100); |
1864 |
INSN(fmins, 0b000, 0b00, 0b0101); |
|
29183 | 1865 |
INSN(fnmuls, 0b000, 0b00, 0b1000); |
1866 |
||
1867 |
INSN(fmuld, 0b000, 0b01, 0b0000); |
|
1868 |
INSN(fdivd, 0b000, 0b01, 0b0001); |
|
1869 |
INSN(faddd, 0b000, 0b01, 0b0010); |
|
1870 |
INSN(fsubd, 0b000, 0b01, 0b0011); |
|
53041 | 1871 |
INSN(fmaxd, 0b000, 0b01, 0b0100); |
1872 |
INSN(fmind, 0b000, 0b01, 0b0101); |
|
29183 | 1873 |
INSN(fnmuld, 0b000, 0b01, 0b1000); |
1874 |
||
1875 |
#undef INSN |
|
1876 |
||
1877 |
// Floating-point data-processing (3 source) |
|
1878 |
void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0, |
|
1879 |
FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, |
|
1880 |
FloatRegister Va) { |
|
1881 |
starti; |
|
1882 |
f(op31, 31, 29); |
|
1883 |
f(0b11111, 28, 24); |
|
1884 |
f(type, 23, 22), f(o1, 21), f(o0, 15); |
|
1885 |
rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); |
|
1886 |
} |
|
1887 |
||
1888 |
#define INSN(NAME, op31, type, o1, o0) \ |
|
1889 |
void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ |
|
1890 |
FloatRegister Va) { \ |
|
1891 |
data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ |
|
1892 |
} |
|
1893 |
||
1894 |
INSN(fmadds, 0b000, 0b00, 0, 0); |
|
1895 |
INSN(fmsubs, 0b000, 0b00, 0, 1); |
|
1896 |
INSN(fnmadds, 0b000, 0b00, 1, 0); |
|
1897 |
INSN(fnmsubs, 0b000, 0b00, 1, 1); |
|
1898 |
||
1899 |
INSN(fmaddd, 0b000, 0b01, 0, 0); |
|
1900 |
INSN(fmsubd, 0b000, 0b01, 0, 1); |
|
1901 |
INSN(fnmaddd, 0b000, 0b01, 1, 0); |
|
1902 |
INSN(fnmsub, 0b000, 0b01, 1, 1); |
|
1903 |
||
1904 |
#undef INSN |
|
1905 |
||
1906 |
// Floating-point conditional select |
|
1907 |
void fp_conditional_select(unsigned op31, unsigned type, |
|
1908 |
unsigned op1, unsigned op2, |
|
1909 |
Condition cond, FloatRegister Vd, |
|
1910 |
FloatRegister Vn, FloatRegister Vm) { |
|
1911 |
starti; |
|
1912 |
f(op31, 31, 29); |
|
1913 |
f(0b11110, 28, 24); |
|
1914 |
f(type, 23, 22); |
|
1915 |
f(op1, 21, 21); |
|
1916 |
f(op2, 11, 10); |
|
1917 |
f(cond, 15, 12); |
|
1918 |
rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); |
|
1919 |
} |
|
1920 |
||
1921 |
#define INSN(NAME, op31, type, op1, op2) \ |
|
1922 |
void NAME(FloatRegister Vd, FloatRegister Vn, \ |
|
1923 |
FloatRegister Vm, Condition cond) { \ |
|
1924 |
fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \ |
|
1925 |
} |
|
1926 |
||
1927 |
INSN(fcsels, 0b000, 0b00, 0b1, 0b11); |
|
1928 |
INSN(fcseld, 0b000, 0b01, 0b1, 0b11); |
|
1929 |
||
1930 |
#undef INSN |
|
1931 |
||
1932 |
// Floating-point<->integer conversions |
|
1933 |
void float_int_convert(unsigned op31, unsigned type, |
|
1934 |
unsigned rmode, unsigned opcode, |
|
1935 |
Register Rd, Register Rn) { |
|
1936 |
starti; |
|
1937 |
f(op31, 31, 29); |
|
1938 |
f(0b11110, 28, 24); |
|
1939 |
f(type, 23, 22), f(1, 21), f(rmode, 20, 19); |
|
1940 |
f(opcode, 18, 16), f(0b000000, 15, 10); |
|
1941 |
zrf(Rn, 5), zrf(Rd, 0); |
|
1942 |
} |
|
1943 |
||
1944 |
#define INSN(NAME, op31, type, rmode, opcode) \ |
|
1945 |
void NAME(Register Rd, FloatRegister Vn) { \ |
|
1946 |
float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ |
|
1947 |
} |
|
1948 |
||
1949 |
INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000); |
|
1950 |
INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000); |
|
1951 |
INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000); |
|
1952 |
INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000); |
|
1953 |
||
1954 |
INSN(fmovs, 0b000, 0b00, 0b00, 0b110); |
|
1955 |
INSN(fmovd, 0b100, 0b01, 0b00, 0b110); |
|
1956 |
||
1957 |
// INSN(fmovhid, 0b100, 0b10, 0b01, 0b110); |
|
1958 |
||
1959 |
#undef INSN |
|
1960 |
||
1961 |
#define INSN(NAME, op31, type, rmode, opcode) \ |
|
1962 |
void NAME(FloatRegister Vd, Register Rn) { \ |
|
1963 |
float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ |
|
1964 |
} |
|
1965 |
||
1966 |
INSN(fmovs, 0b000, 0b00, 0b00, 0b111); |
|
1967 |
INSN(fmovd, 0b100, 0b01, 0b00, 0b111); |
|
1968 |
||
1969 |
INSN(scvtfws, 0b000, 0b00, 0b00, 0b010); |
|
1970 |
INSN(scvtfs, 0b100, 0b00, 0b00, 0b010); |
|
1971 |
INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010); |
|
1972 |
INSN(scvtfd, 0b100, 0b01, 0b00, 0b010); |
|
1973 |
||
1974 |
// INSN(fmovhid, 0b100, 0b10, 0b01, 0b111); |
|
1975 |
||
1976 |
#undef INSN |
|
1977 |
||
1978 |
// Floating-point compare |
|
1979 |
void float_compare(unsigned op31, unsigned type, |
|
1980 |
unsigned op, unsigned op2, |
|
1981 |
FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { |
|
1982 |
starti; |
|
1983 |
f(op31, 31, 29); |
|
1984 |
f(0b11110, 28, 24); |
|
1985 |
f(type, 23, 22), f(1, 21); |
|
1986 |
f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0); |
|
1987 |
rf(Vn, 5), rf(Vm, 16); |
|
1988 |
} |
|
1989 |
||
1990 |
||
1991 |
#define INSN(NAME, op31, type, op, op2) \ |
|
1992 |
void NAME(FloatRegister Vn, FloatRegister Vm) { \ |
|
1993 |
float_compare(op31, type, op, op2, Vn, Vm); \ |
|
1994 |
} |
|
1995 |
||
1996 |
#define INSN1(NAME, op31, type, op, op2) \ |
|
1997 |
void NAME(FloatRegister Vn, double d) { \ |
|
1998 |
assert_cond(d == 0.0); \ |
|
1999 |
float_compare(op31, type, op, op2, Vn); \ |
|
2000 |
} |
|
2001 |
||
2002 |
INSN(fcmps, 0b000, 0b00, 0b00, 0b00000); |
|
2003 |
INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000); |
|
2004 |
// INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000); |
|
2005 |
// INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000); |
|
2006 |
||
2007 |
INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000); |
|
2008 |
INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000); |
|
2009 |
// INSN(fcmped, 0b000, 0b01, 0b00, 0b10000); |
|
2010 |
// INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000); |
|
2011 |
||
2012 |
#undef INSN |
|
2013 |
#undef INSN1 |
|
2014 |
||
2015 |
// Floating-point Move (immediate) |
|
2016 |
private: |
|
2017 |
unsigned pack(double value); |
|
2018 |
||
2019 |
void fmov_imm(FloatRegister Vn, double value, unsigned size) { |
|
2020 |
starti; |
|
2021 |
f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21); |
|
2022 |
f(pack(value), 20, 13), f(0b10000000, 12, 5); |
|
2023 |
rf(Vn, 0); |
|
2024 |
} |
|
2025 |
||
2026 |
public: |
|
2027 |
||
2028 |
void fmovs(FloatRegister Vn, double value) { |
|
2029 |
if (value) |
|
2030 |
fmov_imm(Vn, value, 0b00); |
|
2031 |
else |
|
2032 |
fmovs(Vn, zr); |
|
2033 |
} |
|
2034 |
void fmovd(FloatRegister Vn, double value) { |
|
2035 |
if (value) |
|
2036 |
fmov_imm(Vn, value, 0b01); |
|
2037 |
else |
|
2038 |
fmovd(Vn, zr); |
|
2039 |
} |
|
2040 |
||
50754
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2041 |
// Floating-point rounding |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2042 |
// type: half-precision = 11 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2043 |
// single = 00 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2044 |
// double = 01 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2045 |
// rmode: A = Away = 100 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2046 |
// I = current = 111 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2047 |
// M = MinusInf = 010 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2048 |
// N = eveN = 000 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2049 |
// P = PlusInf = 001 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2050 |
// X = eXact = 110 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2051 |
// Z = Zero = 011 |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2052 |
void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) { |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2053 |
starti; |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2054 |
f(0b00011110, 31, 24); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2055 |
f(type, 23, 22); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2056 |
f(0b1001, 21, 18); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2057 |
f(rmode, 17, 15); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2058 |
f(0b10000, 14, 10); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2059 |
rf(Rn, 5), rf(Rd, 0); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2060 |
} |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2061 |
#define INSN(NAME, type, rmode) \ |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2062 |
void NAME(FloatRegister Vd, FloatRegister Vn) { \ |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2063 |
float_round(type, rmode, Vd, Vn); \ |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2064 |
} |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2065 |
|
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2066 |
public: |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2067 |
INSN(frintah, 0b11, 0b100); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2068 |
INSN(frintih, 0b11, 0b111); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2069 |
INSN(frintmh, 0b11, 0b010); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2070 |
INSN(frintnh, 0b11, 0b000); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2071 |
INSN(frintph, 0b11, 0b001); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2072 |
INSN(frintxh, 0b11, 0b110); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2073 |
INSN(frintzh, 0b11, 0b011); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2074 |
|
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2075 |
INSN(frintas, 0b00, 0b100); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2076 |
INSN(frintis, 0b00, 0b111); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2077 |
INSN(frintms, 0b00, 0b010); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2078 |
INSN(frintns, 0b00, 0b000); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2079 |
INSN(frintps, 0b00, 0b001); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2080 |
INSN(frintxs, 0b00, 0b110); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2081 |
INSN(frintzs, 0b00, 0b011); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2082 |
|
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2083 |
INSN(frintad, 0b01, 0b100); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2084 |
INSN(frintid, 0b01, 0b111); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2085 |
INSN(frintmd, 0b01, 0b010); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2086 |
INSN(frintnd, 0b01, 0b000); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2087 |
INSN(frintpd, 0b01, 0b001); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2088 |
INSN(frintxd, 0b01, 0b110); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2089 |
INSN(frintzd, 0b01, 0b011); |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2090 |
#undef INSN |
ccb8aa083958
8189105: AARCH64: create intrinsic for sin and cos
dpochepk
parents:
50753
diff
changeset
|
2091 |
|
29183 | 2092 |
/* SIMD extensions |
2093 |
* |
|
2094 |
* We just use FloatRegister in the following. They are exactly the same |
|
2095 |
* as SIMD registers. |
|
2096 |
*/ |
|
2097 |
public: |
|
2098 |
||
2099 |
enum SIMD_Arrangement { |
|
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2100 |
T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q |
29183 | 2101 |
}; |
2102 |
||
2103 |
enum SIMD_RegVariant { |
|
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2104 |
B, H, S, D, Q |
29183 | 2105 |
}; |
2106 |
||
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2107 |
private: |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2108 |
static short SIMD_Size_in_bytes[]; |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2109 |
|
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2110 |
public: |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2111 |
#define INSN(NAME, op) \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2112 |
void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2113 |
ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2114 |
} \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2115 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2116 |
INSN(ldr, 1); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2117 |
INSN(str, 0); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2118 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2119 |
#undef INSN |
29183 | 2120 |
|
2121 |
private: |
|
2122 |
||
2123 |
void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) { |
|
2124 |
starti; |
|
2125 |
f(0,31), f((int)T & 1, 30); |
|
2126 |
f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12); |
|
49174
f842bb1e3885
8196868: AARCH64: ld/st instructions hit guarantee assert while using sp
dpochepk
parents:
48622
diff
changeset
|
2127 |
f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0); |
29183 | 2128 |
} |
2129 |
void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, |
|
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2130 |
int imm, int op1, int op2, int regs) { |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2131 |
|
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2132 |
bool replicate = op2 >> 2 == 3; |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2133 |
// post-index value (imm) is formed differently for replicate/non-replicate ld* instructions |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2134 |
int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs; |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2135 |
guarantee(T < T1Q , "incorrect arrangement"); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2136 |
guarantee(imm == expectedImmediate, "bad offset"); |
29183 | 2137 |
starti; |
2138 |
f(0,31), f((int)T & 1, 30); |
|
2139 |
f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12); |
|
49174
f842bb1e3885
8196868: AARCH64: ld/st instructions hit guarantee assert while using sp
dpochepk
parents:
48622
diff
changeset
|
2140 |
f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0); |
29183 | 2141 |
} |
2142 |
void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, |
|
2143 |
Register Xm, int op1, int op2) { |
|
2144 |
starti; |
|
2145 |
f(0,31), f((int)T & 1, 30); |
|
2146 |
f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12); |
|
49174
f842bb1e3885
8196868: AARCH64: ld/st instructions hit guarantee assert while using sp
dpochepk
parents:
48622
diff
changeset
|
2147 |
f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0); |
29183 | 2148 |
} |
2149 |
||
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2150 |
void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) { |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2151 |
switch (a.getMode()) { |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2152 |
case Address::base_plus_offset: |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2153 |
guarantee(a.offset() == 0, "no offset allowed here"); |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2154 |
ld_st(Vt, T, a.base(), op1, op2); |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2155 |
break; |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2156 |
case Address::post: |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2157 |
ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs); |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2158 |
break; |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2159 |
case Address::post_reg: |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2160 |
ld_st(Vt, T, a.base(), a.index(), op1, op2); |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2161 |
break; |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2162 |
default: |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2163 |
ShouldNotReachHere(); |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2164 |
} |
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2165 |
} |
29183 | 2166 |
|
2167 |
public: |
|
2168 |
||
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2169 |
#define INSN1(NAME, op1, op2) \ |
29183 | 2170 |
void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ |
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2171 |
ld_st(Vt, T, a, op1, op2, 1); \ |
29183 | 2172 |
} |
2173 |
||
2174 |
#define INSN2(NAME, op1, op2) \ |
|
2175 |
void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \ |
|
2176 |
assert(Vt->successor() == Vt2, "Registers must be ordered"); \ |
|
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2177 |
ld_st(Vt, T, a, op1, op2, 2); \ |
29183 | 2178 |
} |
2179 |
||
2180 |
#define INSN3(NAME, op1, op2) \ |
|
2181 |
void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ |
|
2182 |
SIMD_Arrangement T, const Address &a) { \ |
|
2183 |
assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ |
|
2184 |
"Registers must be ordered"); \ |
|
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2185 |
ld_st(Vt, T, a, op1, op2, 3); \ |
29183 | 2186 |
} |
2187 |
||
2188 |
#define INSN4(NAME, op1, op2) \ |
|
2189 |
void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ |
|
2190 |
FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ |
|
2191 |
assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ |
|
2192 |
Vt3->successor() == Vt4, "Registers must be ordered"); \ |
|
50640
a92d5b312116
8204473: AARCH64: register post-index addressing mode is not supported directly
dpochepk
parents:
50088
diff
changeset
|
2193 |
ld_st(Vt, T, a, op1, op2, 4); \ |
29183 | 2194 |
} |
2195 |
||
2196 |
INSN1(ld1, 0b001100010, 0b0111); |
|
2197 |
INSN2(ld1, 0b001100010, 0b1010); |
|
2198 |
INSN3(ld1, 0b001100010, 0b0110); |
|
2199 |
INSN4(ld1, 0b001100010, 0b0010); |
|
2200 |
||
2201 |
INSN2(ld2, 0b001100010, 0b1000); |
|
2202 |
INSN3(ld3, 0b001100010, 0b0100); |
|
2203 |
INSN4(ld4, 0b001100010, 0b0000); |
|
2204 |
||
2205 |
INSN1(st1, 0b001100000, 0b0111); |
|
2206 |
INSN2(st1, 0b001100000, 0b1010); |
|
2207 |
INSN3(st1, 0b001100000, 0b0110); |
|
2208 |
INSN4(st1, 0b001100000, 0b0010); |
|
2209 |
||
2210 |
INSN2(st2, 0b001100000, 0b1000); |
|
2211 |
INSN3(st3, 0b001100000, 0b0100); |
|
2212 |
INSN4(st4, 0b001100000, 0b0000); |
|
2213 |
||
2214 |
INSN1(ld1r, 0b001101010, 0b1100); |
|
2215 |
INSN2(ld2r, 0b001101011, 0b1100); |
|
2216 |
INSN3(ld3r, 0b001101010, 0b1110); |
|
2217 |
INSN4(ld4r, 0b001101011, 0b1110); |
|
2218 |
||
2219 |
#undef INSN1 |
|
2220 |
#undef INSN2 |
|
2221 |
#undef INSN3 |
|
2222 |
#undef INSN4 |
|
2223 |
||
2224 |
#define INSN(NAME, opc) \ |
|
2225 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ |
|
2226 |
starti; \ |
|
2227 |
assert(T == T8B || T == T16B, "must be T8B or T16B"); \ |
|
2228 |
f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \ |
|
2229 |
rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \ |
|
2230 |
} |
|
2231 |
||
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2232 |
INSN(eor, 0b101110001); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2233 |
INSN(orr, 0b001110101); |
29183 | 2234 |
INSN(andr, 0b001110001); |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2235 |
INSN(bic, 0b001110011); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2236 |
INSN(bif, 0b101110111); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2237 |
INSN(bit, 0b101110101); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2238 |
INSN(bsl, 0b101110011); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2239 |
INSN(orn, 0b001110111); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2240 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2241 |
#undef INSN |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2242 |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2243 |
#define INSN(NAME, opc, opc2, acceptT2D) \ |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2244 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2245 |
guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \ |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2246 |
if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement"); \ |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2247 |
starti; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2248 |
f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2249 |
f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2250 |
rf(Vn, 5), rf(Vd, 0); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2251 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2252 |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2253 |
INSN(addv, 0, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2254 |
INSN(subv, 1, 0b100001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2255 |
INSN(mulv, 0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2256 |
INSN(mlav, 0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2257 |
INSN(mlsv, 1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2258 |
INSN(sshl, 0, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2259 |
INSN(ushl, 1, 0b010001, true); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2260 |
INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2261 |
INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S |
29183 | 2262 |
|
2263 |
#undef INSN |
|
2264 |
||
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2265 |
#define INSN(NAME, opc, opc2, accepted) \ |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2266 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2267 |
guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \ |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2268 |
if (accepted < 2) guarantee(T != T2S && T != T2D, "incorrect arrangement"); \ |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2269 |
if (accepted == 0) guarantee(T == T8B || T == T16B, "incorrect arrangement"); \ |
29183 | 2270 |
starti; \ |
2271 |
f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ |
|
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2272 |
f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ |
29183 | 2273 |
rf(Vn, 5), rf(Vd, 0); \ |
2274 |
} |
|
2275 |
||
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2276 |
INSN(absr, 0, 0b100000101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2277 |
INSN(negr, 1, 0b100000101110, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2278 |
INSN(notr, 1, 0b100000010110, 0); // accepted arrangements: T8B, T16B |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2279 |
INSN(addv, 0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2280 |
INSN(cls, 0, 0b100000010010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2281 |
INSN(clz, 1, 0b100000010010, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2282 |
INSN(cnt, 0, 0b100000010110, 0); // accepted arrangements: T8B, T16B |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2283 |
INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H, T4S |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2284 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2285 |
#undef INSN |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2286 |
|
54066 | 2287 |
#define INSN(NAME, opc) \ |
2288 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ |
|
2289 |
starti; \ |
|
2290 |
assert(T == T4S, "arrangement must be T4S"); \ |
|
2291 |
f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23), \ |
|
2292 |
f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0); \ |
|
2293 |
} |
|
2294 |
||
2295 |
INSN(fmaxv, 0); |
|
2296 |
INSN(fminv, 1); |
|
2297 |
||
2298 |
#undef INSN |
|
2299 |
||
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2300 |
#define INSN(NAME, op0, cmode0) \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2301 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2302 |
unsigned cmode = cmode0; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2303 |
unsigned op = op0; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2304 |
starti; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2305 |
assert(lsl == 0 || \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2306 |
((T == T4H || T == T8H) && lsl == 8) || \ |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2307 |
((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\ |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2308 |
cmode |= lsl >> 2; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2309 |
if (T == T4H || T == T8H) cmode |= 0b1000; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2310 |
if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2311 |
assert(op == 0 && cmode0 == 0, "must be MOVI"); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2312 |
cmode = 0b1110; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2313 |
if (T == T1D || T == T2D) op = 1; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2314 |
} \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2315 |
f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2316 |
f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2317 |
rf(Vd, 0); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2318 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2319 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2320 |
INSN(movi, 0, 0); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2321 |
INSN(orri, 0, 1); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2322 |
INSN(mvni, 1, 0); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2323 |
INSN(bici, 1, 1); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2324 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2325 |
#undef INSN |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2326 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2327 |
#define INSN(NAME, op1, op2, op3) \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2328 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2329 |
starti; \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2330 |
assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2331 |
f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2332 |
f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2333 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2334 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2335 |
INSN(fadd, 0, 0, 0b110101); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2336 |
INSN(fdiv, 1, 0, 0b111111); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2337 |
INSN(fmul, 1, 0, 0b110111); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2338 |
INSN(fsub, 0, 1, 0b110101); |
46606 | 2339 |
INSN(fmla, 0, 0, 0b110011); |
2340 |
INSN(fmls, 0, 1, 0b110011); |
|
54066 | 2341 |
INSN(fmax, 0, 0, 0b111101); |
2342 |
INSN(fmin, 0, 1, 0b111101); |
|
29183 | 2343 |
|
2344 |
#undef INSN |
|
2345 |
||
2346 |
#define INSN(NAME, opc) \ |
|
2347 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ |
|
2348 |
starti; \ |
|
2349 |
assert(T == T4S, "arrangement must be T4S"); \ |
|
2350 |
f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ |
|
2351 |
} |
|
2352 |
||
2353 |
INSN(sha1c, 0b000000); |
|
2354 |
INSN(sha1m, 0b001000); |
|
2355 |
INSN(sha1p, 0b000100); |
|
2356 |
INSN(sha1su0, 0b001100); |
|
2357 |
INSN(sha256h2, 0b010100); |
|
2358 |
INSN(sha256h, 0b010000); |
|
2359 |
INSN(sha256su1, 0b011000); |
|
2360 |
||
2361 |
#undef INSN |
|
2362 |
||
2363 |
#define INSN(NAME, opc) \ |
|
2364 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ |
|
2365 |
starti; \ |
|
2366 |
assert(T == T4S, "arrangement must be T4S"); \ |
|
2367 |
f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ |
|
2368 |
} |
|
2369 |
||
2370 |
INSN(sha1h, 0b000010); |
|
2371 |
INSN(sha1su1, 0b000110); |
|
2372 |
INSN(sha256su0, 0b001010); |
|
2373 |
||
2374 |
#undef INSN |
|
2375 |
||
2376 |
#define INSN(NAME, opc) \ |
|
2377 |
void NAME(FloatRegister Vd, FloatRegister Vn) { \ |
|
2378 |
starti; \ |
|
2379 |
f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \ |
|
2380 |
} |
|
2381 |
||
2382 |
INSN(aese, 0b0100111000101000010010); |
|
2383 |
INSN(aesd, 0b0100111000101000010110); |
|
2384 |
INSN(aesmc, 0b0100111000101000011010); |
|
2385 |
INSN(aesimc, 0b0100111000101000011110); |
|
2386 |
||
2387 |
#undef INSN |
|
2388 |
||
50753 | 2389 |
#define INSN(NAME, op1, op2) \ |
2390 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \ |
|
2391 |
starti; \ |
|
2392 |
assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ |
|
2393 |
assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index"); \ |
|
2394 |
f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23); \ |
|
2395 |
f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16); \ |
|
2396 |
f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10); \ |
|
2397 |
rf(Vn, 5), rf(Vd, 0); \ |
|
2398 |
} |
|
2399 |
||
2400 |
// FMLA/FMLS - Vector - Scalar |
|
2401 |
INSN(fmlavs, 0, 0b0001); |
|
51707
8c7198cac800
8210578: AArch64: Invalid encoding for fmlsvs instruction
adinn
parents:
51383
diff
changeset
|
2402 |
INSN(fmlsvs, 0, 0b0101); |
50753 | 2403 |
// FMULX - Vector - Scalar |
2404 |
INSN(fmulxvs, 1, 0b1001); |
|
2405 |
||
2406 |
#undef INSN |
|
2407 |
||
2408 |
// Floating-point Reciprocal Estimate |
|
2409 |
void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) { |
|
2410 |
assert(type == D || type == S, "Wrong type for frecpe"); |
|
2411 |
starti; |
|
2412 |
f(0b010111101, 31, 23); |
|
2413 |
f(type == D ? 1 : 0, 22); |
|
2414 |
f(0b100001110110, 21, 10); |
|
2415 |
rf(Vn, 5), rf(Vd, 0); |
|
2416 |
} |
|
2417 |
||
2418 |
// (double) {a, b} -> (a + b) |
|
2419 |
void faddpd(FloatRegister Vd, FloatRegister Vn) { |
|
2420 |
starti; |
|
2421 |
f(0b0111111001110000110110, 31, 10); |
|
2422 |
rf(Vn, 5), rf(Vd, 0); |
|
2423 |
} |
|
2424 |
||
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2425 |
void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) { |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2426 |
starti; |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2427 |
assert(T != Q, "invalid register variant"); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2428 |
f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2429 |
f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2430 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2431 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2432 |
void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) { |
29183 | 2433 |
starti; |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2434 |
f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2435 |
f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2436 |
rf(Vn, 5), rf(Rd, 0); |
29183 | 2437 |
} |
2438 |
||
48622
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2439 |
#define INSN(NAME, opc, opc2, isSHR) \ |
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2440 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2441 |
starti; \ |
48622
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2442 |
/* The encodings for the immh:immb fields (bits 22:16) in *SHR are \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2443 |
* 0001 xxx 8B/16B, shift = 16 - UInt(immh:immb) \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2444 |
* 001x xxx 4H/8H, shift = 32 - UInt(immh:immb) \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2445 |
* 01xx xxx 2S/4S, shift = 64 - UInt(immh:immb) \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2446 |
* 1xxx xxx 1D/2D, shift = 128 - UInt(immh:immb) \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2447 |
* (1D is RESERVED) \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2448 |
* for SHL shift is calculated as: \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2449 |
* 0001 xxx 8B/16B, shift = UInt(immh:immb) - 8 \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2450 |
* 001x xxx 4H/8H, shift = UInt(immh:immb) - 16 \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2451 |
* 01xx xxx 2S/4S, shift = UInt(immh:immb) - 32 \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2452 |
* 1xxx xxx 1D/2D, shift = UInt(immh:immb) - 64 \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2453 |
* (1D is RESERVED) \ |
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2454 |
*/ \ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2455 |
assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \ |
48622
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2456 |
int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0))); \ |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2457 |
int encodedShift = isSHR ? cVal - shift : cVal + shift; \ |
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2458 |
f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \ |
48622
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2459 |
f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \ |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2460 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2461 |
|
48622
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2462 |
INSN(shl, 0, 0b010101, /* isSHR = */ false); |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2463 |
INSN(sshr, 0, 0b000001, /* isSHR = */ true); |
a92a5a71364a
8194256: AARCH64: SIMD shift instructions are incorrectly encoded
dpochepk
parents:
48487
diff
changeset
|
2464 |
INSN(ushr, 1, 0b000001, /* isSHR = */ true); |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2465 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2466 |
#undef INSN |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2467 |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2468 |
private: |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2469 |
void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { |
29183 | 2470 |
starti; |
2471 |
/* The encodings for the immh:immb fields (bits 22:16) are |
|
2472 |
* 0001 xxx 8H, 8B/16b shift = xxx |
|
2473 |
* 001x xxx 4S, 4H/8H shift = xxxx |
|
2474 |
* 01xx xxx 2D, 2S/4S shift = xxxxx |
|
2475 |
* 1xxx xxx RESERVED |
|
2476 |
*/ |
|
2477 |
assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement"); |
|
2478 |
assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value"); |
|
2479 |
f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16); |
|
2480 |
f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0); |
|
2481 |
} |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2482 |
|
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2483 |
public: |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2484 |
void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2485 |
assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement"); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2486 |
_ushll(Vd, Ta, Vn, Tb, shift); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2487 |
} |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2488 |
|
29183 | 2489 |
void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2490 |
assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement"); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2491 |
_ushll(Vd, Ta, Vn, Tb, shift); |
29183 | 2492 |
} |
2493 |
||
2494 |
// Move from general purpose register |
|
2495 |
// mov Vd.T[index], Rn |
|
2496 |
void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { |
|
2497 |
starti; |
|
2498 |
f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2499 |
f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0); |
29183 | 2500 |
} |
2501 |
||
2502 |
// Move to general purpose register |
|
2503 |
// mov Rd, Vn.T[index] |
|
2504 |
void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) { |
|
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2505 |
guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported"); |
29183 | 2506 |
starti; |
2507 |
f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21); |
|
2508 |
f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); |
|
2509 |
f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0); |
|
2510 |
} |
|
2511 |
||
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2512 |
private: |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2513 |
void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { |
29183 | 2514 |
starti; |
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2515 |
assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) || |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2516 |
(Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier"); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2517 |
int size = (Ta == T1Q) ? 0b11 : 0b00; |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2518 |
f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2519 |
f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0); |
29183 | 2520 |
} |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2521 |
|
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2522 |
public: |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2523 |
void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2524 |
assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier"); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2525 |
_pmull(Vd, Ta, Vn, Vm, Tb); |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2526 |
} |
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2527 |
|
29183 | 2528 |
void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { |
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2529 |
assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier"); |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2530 |
_pmull(Vd, Ta, Vn, Vm, Tb); |
29183 | 2531 |
} |
2532 |
||
2533 |
void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) { |
|
2534 |
starti; |
|
2535 |
int size_b = (int)Tb >> 1; |
|
2536 |
int size_a = (int)Ta >> 1; |
|
2537 |
assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier"); |
|
2538 |
f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22); |
|
2539 |
f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0); |
|
2540 |
} |
|
2541 |
||
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2542 |
void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs) |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2543 |
{ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2544 |
starti; |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2545 |
assert(T != T1D, "reserved encoding"); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2546 |
f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21); |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2547 |
f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0); |
30890
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2548 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2549 |
|
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2550 |
void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0) |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2551 |
{ |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2552 |
starti; |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2553 |
assert(T != T1D, "reserved encoding"); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2554 |
f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2555 |
f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2556 |
f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0); |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2557 |
} |
dbbc65d3cd40
8079565: aarch64: Add vectorization support for aarch64
enevill
parents:
30225
diff
changeset
|
2558 |
|
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2559 |
// AdvSIMD ZIP/UZP/TRN |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2560 |
#define INSN(NAME, opcode) \ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2561 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ |
55314
811df7c64724
8222412: AARCH64: multiple instructions encoding issues
dpochepk
parents:
55054
diff
changeset
|
2562 |
guarantee(T != T1D && T != T1Q, "invalid arrangement"); \ |
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2563 |
starti; \ |
50088
a2322c683d17
8202395: AARCH64: wrong encoding for SIMD instructions zip, trn, uzp
dpochepk
parents:
49723
diff
changeset
|
2564 |
f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15); \ |
a2322c683d17
8202395: AARCH64: wrong encoding for SIMD instructions zip, trn, uzp
dpochepk
parents:
49723
diff
changeset
|
2565 |
f(opcode, 14, 12), f(0b10, 11, 10); \ |
38003
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2566 |
rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2567 |
f(T & 1, 30), f(T >> 1, 23, 22); \ |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2568 |
} |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2569 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2570 |
INSN(uzp1, 0b001); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2571 |
INSN(trn1, 0b010); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2572 |
INSN(zip1, 0b011); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2573 |
INSN(uzp2, 0b101); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2574 |
INSN(trn2, 0b110); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2575 |
INSN(zip2, 0b111); |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2576 |
|
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2577 |
#undef INSN |
f84c8ee82ac8
8153310: AArch64: JEP 254: Implement byte_array_inflate
aph
parents:
37269
diff
changeset
|
2578 |
|
29183 | 2579 |
// CRC32 instructions |
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2580 |
#define INSN(NAME, c, sf, sz) \ |
29183 | 2581 |
void NAME(Register Rd, Register Rn, Register Rm) { \ |
2582 |
starti; \ |
|
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2583 |
f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \ |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2584 |
f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ |
29183 | 2585 |
} |
2586 |
||
31591
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2587 |
INSN(crc32b, 0, 0, 0b00); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2588 |
INSN(crc32h, 0, 0, 0b01); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2589 |
INSN(crc32w, 0, 0, 0b10); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2590 |
INSN(crc32x, 0, 1, 0b11); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2591 |
INSN(crc32cb, 1, 0, 0b00); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2592 |
INSN(crc32ch, 1, 0, 0b01); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2593 |
INSN(crc32cw, 1, 0, 0b10); |
82134a118aea
8130687: aarch64: add support for hardware crc32c
enevill
parents:
31517
diff
changeset
|
2594 |
INSN(crc32cx, 1, 1, 0b11); |
29183 | 2595 |
|
2596 |
#undef INSN |
|
2597 |
||
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2598 |
// Table vector lookup |
32574 | 2599 |
#define INSN(NAME, op) \ |
2600 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \ |
|
2601 |
starti; \ |
|
2602 |
assert(T == T8B || T == T16B, "invalid arrangement"); \ |
|
2603 |
assert(0 < registers && registers <= 4, "invalid number of registers"); \ |
|
2604 |
f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \ |
|
2605 |
f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \ |
|
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2606 |
} |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2607 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2608 |
INSN(tbl, 0); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2609 |
INSN(tbx, 1); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2610 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2611 |
#undef INSN |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2612 |
|
32574 | 2613 |
// AdvSIMD two-reg misc |
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2614 |
#define INSN(NAME, U, opcode) \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2615 |
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2616 |
starti; \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2617 |
assert((ASSERTION), MSG); \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2618 |
f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2619 |
f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2620 |
f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \ |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2621 |
} |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2622 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2623 |
#define MSG "invalid arrangement" |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2624 |
|
33085
32f5ee7f0ba8
8135231: aarch64: add support for vectorizing double precision sqrt
enevill
parents:
32574
diff
changeset
|
2625 |
#define ASSERTION (T == T2S || T == T4S || T == T2D) |
32f5ee7f0ba8
8135231: aarch64: add support for vectorizing double precision sqrt
enevill
parents:
32574
diff
changeset
|
2626 |
INSN(fsqrt, 1, 0b11111); |
33088
34fe49ecee13
8138583: aarch64: add support for vectorizing fabs/fneg
enevill
parents:
33085
diff
changeset
|
2627 |
INSN(fabs, 0, 0b01111); |
34fe49ecee13
8138583: aarch64: add support for vectorizing fabs/fneg
enevill
parents:
33085
diff
changeset
|
2628 |
INSN(fneg, 1, 0b01111); |
33085
32f5ee7f0ba8
8135231: aarch64: add support for vectorizing double precision sqrt
enevill
parents:
32574
diff
changeset
|
2629 |
#undef ASSERTION |
32f5ee7f0ba8
8135231: aarch64: add support for vectorizing double precision sqrt
enevill
parents:
32574
diff
changeset
|
2630 |
|
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2631 |
#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S) |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2632 |
INSN(rev64, 0, 0b00000); |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2633 |
#undef ASSERTION |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2634 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2635 |
#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H) |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2636 |
INSN(rev32, 1, 0b00000); |
32574 | 2637 |
private: |
2638 |
INSN(_rbit, 1, 0b00101); |
|
2639 |
public: |
|
2640 |
||
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2641 |
#undef ASSERTION |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2642 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2643 |
#define ASSERTION (T == T8B || T == T16B) |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2644 |
INSN(rev16, 0, 0b00001); |
32574 | 2645 |
// RBIT only allows T8B and T16B but encodes them oddly. Argh... |
2646 |
void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { |
|
2647 |
assert((ASSERTION), MSG); |
|
55398
e53ec3b362f4
8224851: AArch64: fix warnings and errors with Clang and GCC 8.3
ngasson
parents:
55314
diff
changeset
|
2648 |
_rbit(Vd, SIMD_Arrangement((T & 1) | 0b010), Vn); |
32574 | 2649 |
} |
31961
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2650 |
#undef ASSERTION |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2651 |
|
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2652 |
#undef MSG |
70adcff5840c
8131062: aarch64: add support for GHASH acceleration
enevill
parents:
31863
diff
changeset
|
2653 |
|
70adcff5840c
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|
2654 |
#undef INSN |
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8131062: aarch64: add support for GHASH acceleration
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|
2655 |
|
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|
2656 |
void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index) |
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8131062: aarch64: add support for GHASH acceleration
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|
2657 |
{ |
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8131062: aarch64: add support for GHASH acceleration
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|
2658 |
starti; |
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8131062: aarch64: add support for GHASH acceleration
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|
2659 |
assert(T == T8B || T == T16B, "invalid arrangement"); |
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|
2660 |
assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); |
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|
2661 |
f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); |
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|
2662 |
rf(Vm, 16), f(0, 15), f(index, 14, 11); |
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|
2663 |
f(0, 10), rf(Vn, 5), rf(Vd, 0); |
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|
2664 |
} |
29183 | 2665 |
|
2666 |
Assembler(CodeBuffer* code) : AbstractAssembler(code) { |
|
2667 |
} |
|
2668 |
||
2669 |
virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
|
2670 |
Register tmp, |
|
2671 |
int offset) { |
|
2672 |
ShouldNotCallThis(); |
|
2673 |
return RegisterOrConstant(); |
|
2674 |
} |
|
2675 |
||
2676 |
// Stack overflow checking |
|
2677 |
virtual void bang_stack_with_offset(int offset); |
|
2678 |
||
2679 |
static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm); |
|
2680 |
static bool operand_valid_for_add_sub_immediate(long imm); |
|
2681 |
static bool operand_valid_for_float_immediate(double imm); |
|
2682 |
||
2683 |
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
|
2684 |
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
|
2685 |
}; |
|
2686 |
||
2687 |
inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a, |
|
2688 |
Assembler::Membar_mask_bits b) { |
|
2689 |
return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b)); |
|
2690 |
} |
|
2691 |
||
2692 |
Instruction_aarch64::~Instruction_aarch64() { |
|
2693 |
assem->emit(); |
|
2694 |
} |
|
2695 |
||
2696 |
#undef starti |
|
2697 |
||
2698 |
// Invert a condition |
|
2699 |
inline const Assembler::Condition operator~(const Assembler::Condition cond) { |
|
2700 |
return Assembler::Condition(int(cond) ^ 1); |
|
2701 |
} |
|
2702 |
||
2703 |
class BiasedLockingCounters; |
|
2704 |
||
2705 |
extern "C" void das(uint64_t start, int len); |
|
2706 |
||
53244
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|
2707 |
#endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP |