/*

 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP

#define CPU_AARCH64_ASSEMBLER_AARCH64_HPP

#include "asm/register.hpp"

// definitions of various symbolic names for machine registers

// First intercalls between C and Java which use 8 general registers

// and 8 floating registers

// we also have to copy between x86 and ARM registers but that's a

// secondary complication -- not all code employing C call convention

// executes as x86 code though -- we generate some of it

class Argument {

 public:

  enum {

    n_int_register_parameters_c   = 8,  // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)

    n_float_register_parameters_c = 8,  // v0, v1, ... v7 (c_farg0, c_farg1, ... )

    n_int_register_parameters_j   = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...

    n_float_register_parameters_j = 8  // v0, v1, ... v7 (j_farg0, j_farg1, ...

  };

};

REGISTER_DECLARATION(Register, c_rarg0, r0);

REGISTER_DECLARATION(Register, c_rarg1, r1);

REGISTER_DECLARATION(Register, c_rarg2, r2);

REGISTER_DECLARATION(Register, c_rarg3, r3);

REGISTER_DECLARATION(Register, c_rarg4, r4);

REGISTER_DECLARATION(Register, c_rarg5, r5);

REGISTER_DECLARATION(Register, c_rarg6, r6);

REGISTER_DECLARATION(Register, c_rarg7, r7);

REGISTER_DECLARATION(FloatRegister, c_farg0, v0);

REGISTER_DECLARATION(FloatRegister, c_farg1, v1);

REGISTER_DECLARATION(FloatRegister, c_farg2, v2);

REGISTER_DECLARATION(FloatRegister, c_farg3, v3);

REGISTER_DECLARATION(FloatRegister, c_farg4, v4);

REGISTER_DECLARATION(FloatRegister, c_farg5, v5);

REGISTER_DECLARATION(FloatRegister, c_farg6, v6);

REGISTER_DECLARATION(FloatRegister, c_farg7, v7);

// Symbolically name the register arguments used by the Java calling convention.

// We have control over the convention for java so we can do what we please.

// What pleases us is to offset the java calling convention so that when

// we call a suitable jni method the arguments are lined up and we don't

// have to do much shuffling. A suitable jni method is non-static and a

// small number of arguments

//

//  |--------------------------------------------------------------------|

//  | c_rarg0  c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7  |

//  |--------------------------------------------------------------------|

//  | r0       r1       r2      r3      r4      r5      r6      r7       |

//  |--------------------------------------------------------------------|

//  | j_rarg7  j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6  |

//  |--------------------------------------------------------------------|

REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);

REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);

REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);

REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);

REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);

REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);

REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);

REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);

// Java floating args are passed as per C

REGISTER_DECLARATION(FloatRegister, j_farg0, v0);

REGISTER_DECLARATION(FloatRegister, j_farg1, v1);

REGISTER_DECLARATION(FloatRegister, j_farg2, v2);

REGISTER_DECLARATION(FloatRegister, j_farg3, v3);

REGISTER_DECLARATION(FloatRegister, j_farg4, v4);

REGISTER_DECLARATION(FloatRegister, j_farg5, v5);

REGISTER_DECLARATION(FloatRegister, j_farg6, v6);

REGISTER_DECLARATION(FloatRegister, j_farg7, v7);

// registers used to hold VM data either temporarily within a method

// or across method calls

// volatile (caller-save) registers

// r8 is used for indirect result location return

// we use it and r9 as scratch registers

REGISTER_DECLARATION(Register, rscratch1, r8);

REGISTER_DECLARATION(Register, rscratch2, r9);

// current method -- must be in a call-clobbered register

REGISTER_DECLARATION(Register, rmethod,   r12);

// non-volatile (callee-save) registers are r16-29

// of which the following are dedicated global state

// link register

REGISTER_DECLARATION(Register, lr,        r30);

// frame pointer

REGISTER_DECLARATION(Register, rfp,       r29);

// current thread

REGISTER_DECLARATION(Register, rthread,   r28);

// base of heap

REGISTER_DECLARATION(Register, rheapbase, r27);

// constant pool cache

REGISTER_DECLARATION(Register, rcpool,    r26);

// monitors allocated on stack

REGISTER_DECLARATION(Register, rmonitors, r25);

// locals on stack

REGISTER_DECLARATION(Register, rlocals,   r24);

// bytecode pointer

REGISTER_DECLARATION(Register, rbcp,      r22);

// Dispatch table base

REGISTER_DECLARATION(Register, rdispatch, r21);

// Java stack pointer

REGISTER_DECLARATION(Register, esp,      r20);

#define assert_cond(ARG1) assert(ARG1, #ARG1)

namespace asm_util {

  uint32_t encode_logical_immediate(bool is32, uint64_t imm);

};

using namespace asm_util;

class Assembler;

class Instruction_aarch64 {

  unsigned insn;

#ifdef ASSERT

  unsigned bits;

#endif

  Assembler *assem;

public:

  Instruction_aarch64(class Assembler *as) {

#ifdef ASSERT

    bits = 0;

#endif

    insn = 0;

    assem = as;

  }

  inline ~Instruction_aarch64();

  unsigned &get_insn() { return insn; }

#ifdef ASSERT

  unsigned &get_bits() { return bits; }

#endif

  static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {

    union {

      unsigned u;

      int n;

    };

    u = val << (31 - hi);

    n = n >> (31 - hi + lo);

    return n;

  }

  static inline uint32_t extract(uint32_t val, int msb, int lsb) {

    int nbits = msb - lsb + 1;

    assert_cond(msb >= lsb);

    uint32_t mask = (1U << nbits) - 1;

    uint32_t result = val >> lsb;

    result &= mask;

    return result;

  }

  static inline int32_t sextract(uint32_t val, int msb, int lsb) {

    uint32_t uval = extract(val, msb, lsb);

    return extend(uval, msb - lsb);

  }

  static void patch(address a, int msb, int lsb, unsigned long val) {

    int nbits = msb - lsb + 1;

    guarantee(val < (1U << nbits), "Field too big for insn");

    assert_cond(msb >= lsb);

    unsigned mask = (1U << nbits) - 1;

    val <<= lsb;

    mask <<= lsb;

    unsigned target = *(unsigned *)a;

    target &= ~mask;

    target |= val;

    *(unsigned *)a = target;

  }

  static void spatch(address a, int msb, int lsb, long val) {

    int nbits = msb - lsb + 1;

    long chk = val >> (nbits - 1);

    guarantee (chk == -1 || chk == 0, "Field too big for insn");

    unsigned uval = val;

    unsigned mask = (1U << nbits) - 1;

    uval &= mask;

    uval <<= lsb;

    mask <<= lsb;

    unsigned target = *(unsigned *)a;

    target &= ~mask;

    target |= uval;

    *(unsigned *)a = target;

  }

  void f(unsigned val, int msb, int lsb) {

    int nbits = msb - lsb + 1;

    guarantee(val < (1U << nbits), "Field too big for insn");

    assert_cond(msb >= lsb);

    unsigned mask = (1U << nbits) - 1;

    val <<= lsb;

    mask <<= lsb;

    insn |= val;

    assert_cond((bits & mask) == 0);

#ifdef ASSERT

    bits |= mask;

#endif

  }

  void f(unsigned val, int bit) {

    f(val, bit, bit);

  }

  void sf(long val, int msb, int lsb) {

    int nbits = msb - lsb + 1;

    long chk = val >> (nbits - 1);

    guarantee (chk == -1 || chk == 0, "Field too big for insn");

    unsigned uval = val;

    unsigned mask = (1U << nbits) - 1;

    uval &= mask;

    f(uval, lsb + nbits - 1, lsb);

  }

  void rf(Register r, int lsb) {

    f(r->encoding_nocheck(), lsb + 4, lsb);

  }

  // reg|ZR

  void zrf(Register r, int lsb) {

    f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);

  }

  // reg|SP

  void srf(Register r, int lsb) {

    f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);

  }

  void rf(FloatRegister r, int lsb) {

    f(r->encoding_nocheck(), lsb + 4, lsb);

  }

  unsigned get(int msb = 31, int lsb = 0) {

    int nbits = msb - lsb + 1;

    unsigned mask = ((1U << nbits) - 1) << lsb;

    assert_cond(bits & mask == mask);

    return (insn & mask) >> lsb;

  }

  void fixed(unsigned value, unsigned mask) {

    assert_cond ((mask & bits) == 0);

#ifdef ASSERT

    bits |= mask;

#endif

    insn |= value;

  }

};

#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)

class PrePost {

  int _offset;

  Register _r;

public:

  PrePost(Register reg, int o) : _offset(o), _r(reg) { }

  int offset() { return _offset; }

  Register reg() { return _r; }

};

class Pre : public PrePost {

public:

  Pre(Register reg, int o) : PrePost(reg, o) { }

};

class Post : public PrePost {

  Register _idx;

public:

  Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; }

  Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; }

  Register idx_reg() { return _idx; }

};

namespace ext

{

  enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };

};

// Addressing modes

class Address {

 public:

  enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,

              base_plus_offset_reg, literal };

  // Shift and extend for base reg + reg offset addressing

  class extend {

    int _option, _shift;

    ext::operation _op;

  public:

    extend() { }

    extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }

    int option() const{ return _option; }

    int shift() const { return _shift; }

    ext::operation op() const { return _op; }

  };

  class uxtw : public extend {

  public:

    uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }

  };

  class lsl : public extend {

  public:

    lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }

  };

  class sxtw : public extend {

  public:

    sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }

  };

  class sxtx : public extend {

  public:

    sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }

  };

 private:

  Register _base;

  Register _index;

  long _offset;

  enum mode _mode;

  extend _ext;

  RelocationHolder _rspec;

  // Typically we use AddressLiterals we want to use their rval

  // However in some situations we want the lval (effect address) of

  // the item.  We provide a special factory for making those lvals.

  bool _is_lval;

  // If the target is far we'll need to load the ea of this to a

  // register to reach it. Otherwise if near we can do PC-relative

  // addressing.

  address          _target;

 public:

  Address()

    : _mode(no_mode) { }

  Address(Register r)

    : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }

  Address(Register r, int o)

    : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }

  Address(Register r, long o)

    : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }

  Address(Register r, unsigned long o)

    : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }

#ifdef ASSERT

  Address(Register r, ByteSize disp)

    : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }

#endif

  Address(Register r, Register r1, extend ext = lsl())

    : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),

      _ext(ext), _target(0) { }

  Address(Pre p)

    : _base(p.reg()), _offset(p.offset()), _mode(pre) { }

  Address(Post p)

    : _base(p.reg()),  _index(p.idx_reg()), _offset(p.offset()),

      _mode(p.idx_reg() == NULL ? post : post_reg), _target(0) { }

  Address(address target, RelocationHolder const& rspec)

    : _mode(literal),

      _rspec(rspec),

      _is_lval(false),

      _target(target)  { }

  Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);

  Address(Register base, RegisterOrConstant index, extend ext = lsl())

    : _base (base),

      _offset(0), _ext(ext), _target(0) {

    if (index.is_register()) {

      _mode = base_plus_offset_reg;

      _index = index.as_register();

    } else {

      guarantee(ext.option() == ext::uxtx, "should be");

      assert(index.is_constant(), "should be");

      _mode = base_plus_offset;

      _offset = index.as_constant() << ext.shift();

    }

  }

  Register base() const {

    guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg

               | _mode == post | _mode == post_reg),

              "wrong mode");

    return _base;

  }

  long offset() const {

    return _offset;

  }

  Register index() const {

    return _index;

  }

  mode getMode() const {

    return _mode;

  }

  bool uses(Register reg) const { return _base == reg || _index == reg; }

  address target() const { return _target; }

  const RelocationHolder& rspec() const { return _rspec; }

  void encode(Instruction_aarch64 *i) const {

    i->f(0b111, 29, 27);

    i->srf(_base, 5);

    switch(_mode) {

    case base_plus_offset:

      {

        unsigned size = i->get(31, 30);

        if (i->get(26, 26) && i->get(23, 23)) {

          // SIMD Q Type - Size = 128 bits

          assert(size == 0, "bad size");

          size = 0b100;

        }

        unsigned mask = (1 << size) - 1;

        if (_offset < 0 || _offset & mask)

          {

            i->f(0b00, 25, 24);

            i->f(0, 21), i->f(0b00, 11, 10);

            i->sf(_offset, 20, 12);

          } else {

            i->f(0b01, 25, 24);

            i->f(_offset >> size, 21, 10);

          }

      }

      break;

    case base_plus_offset_reg:

      {

        i->f(0b00, 25, 24);

        i->f(1, 21);

        i->rf(_index, 16);

        i->f(_ext.option(), 15, 13);

        unsigned size = i->get(31, 30);

        if (i->get(26, 26) && i->get(23, 23)) {

          // SIMD Q Type - Size = 128 bits

          assert(size == 0, "bad size");

          size = 0b100;

        }

        if (size == 0) // It's a byte

          i->f(_ext.shift() >= 0, 12);

        else {

          if (_ext.shift() > 0)

            assert(_ext.shift() == (int)size, "bad shift");

          i->f(_ext.shift() > 0, 12);

        }

        i->f(0b10, 11, 10);

      }

      break;

    case pre:

      i->f(0b00, 25, 24);

      i->f(0, 21), i->f(0b11, 11, 10);

      i->sf(_offset, 20, 12);

      break;

    case post:

      i->f(0b00, 25, 24);

      i->f(0, 21), i->f(0b01, 11, 10);

      i->sf(_offset, 20, 12);

      break;

    default:

      ShouldNotReachHere();

    }

  }

  void encode_pair(Instruction_aarch64 *i) const {

    switch(_mode) {

    case base_plus_offset:

      i->f(0b010, 25, 23);

      break;

    case pre:

      i->f(0b011, 25, 23);

      break;

    case post:

      i->f(0b001, 25, 23);

      break;

    default:

      ShouldNotReachHere();

    }

    unsigned size; // Operand shift in 32-bit words

    if (i->get(26, 26)) { // float

      switch(i->get(31, 30)) {

      case 0b10:

        size = 2; break;

      case 0b01: