hotspot/src/cpu/aarch64/vm/assembler_aarch64.hpp
author enevill
Tue, 21 Jul 2015 13:36:28 +0000
changeset 31961 70adcff5840c
parent 31863 22ea3a456610
child 32395 13b0caf18153
permissions -rw-r--r--
8131062: aarch64: add support for GHASH acceleration Summary: Add support for GHASH using pmull Reviewed-by: kvn, goetz, aph Contributed-by: alexander.alexeev@caviumnetworks.com
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/*
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 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
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#define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
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#include "asm/register.hpp"
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// definitions of various symbolic names for machine registers
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// First intercalls between C and Java which use 8 general registers
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// and 8 floating registers
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// we also have to copy between x86 and ARM registers but that's a
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// secondary complication -- not all code employing C call convention
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// executes as x86 code though -- we generate some of it
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class Argument VALUE_OBJ_CLASS_SPEC {
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 public:
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  enum {
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    n_int_register_parameters_c   = 8,  // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
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    n_float_register_parameters_c = 8,  // v0, v1, ... v7 (c_farg0, c_farg1, ... )
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    n_int_register_parameters_j   = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
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    n_float_register_parameters_j = 8  // v0, v1, ... v7 (j_farg0, j_farg1, ...
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  };
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};
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REGISTER_DECLARATION(Register, c_rarg0, r0);
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REGISTER_DECLARATION(Register, c_rarg1, r1);
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REGISTER_DECLARATION(Register, c_rarg2, r2);
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REGISTER_DECLARATION(Register, c_rarg3, r3);
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REGISTER_DECLARATION(Register, c_rarg4, r4);
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REGISTER_DECLARATION(Register, c_rarg5, r5);
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REGISTER_DECLARATION(Register, c_rarg6, r6);
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REGISTER_DECLARATION(Register, c_rarg7, r7);
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REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
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REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
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REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
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REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
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REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
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REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
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REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
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REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
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// Symbolically name the register arguments used by the Java calling convention.
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// We have control over the convention for java so we can do what we please.
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// What pleases us is to offset the java calling convention so that when
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// we call a suitable jni method the arguments are lined up and we don't
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// have to do much shuffling. A suitable jni method is non-static and a
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// small number of arguments
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//
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//  |--------------------------------------------------------------------|
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//  | c_rarg0  c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7  |
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//  |--------------------------------------------------------------------|
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//  | r0       r1       r2      r3      r4      r5      r6      r7       |
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//  |--------------------------------------------------------------------|
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//  | j_rarg7  j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6  |
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//  |--------------------------------------------------------------------|
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REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
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REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
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REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
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REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
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REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
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REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
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REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
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REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
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// Java floating args are passed as per C
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REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
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REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
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REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
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REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
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REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
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REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
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REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
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REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
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// registers used to hold VM data either temporarily within a method
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// or across method calls
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// volatile (caller-save) registers
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// r8 is used for indirect result location return
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// we use it and r9 as scratch registers
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REGISTER_DECLARATION(Register, rscratch1, r8);
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REGISTER_DECLARATION(Register, rscratch2, r9);
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// current method -- must be in a call-clobbered register
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REGISTER_DECLARATION(Register, rmethod,   r12);
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// non-volatile (callee-save) registers are r16-29
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// of which the following are dedicated global state
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// link register
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REGISTER_DECLARATION(Register, lr,        r30);
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// frame pointer
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REGISTER_DECLARATION(Register, rfp,       r29);
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// current thread
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REGISTER_DECLARATION(Register, rthread,   r28);
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// base of heap
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REGISTER_DECLARATION(Register, rheapbase, r27);
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// constant pool cache
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REGISTER_DECLARATION(Register, rcpool,    r26);
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// monitors allocated on stack
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REGISTER_DECLARATION(Register, rmonitors, r25);
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// locals on stack
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REGISTER_DECLARATION(Register, rlocals,   r24);
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// bytecode pointer
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REGISTER_DECLARATION(Register, rbcp,      r22);
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// Dispatch table base
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REGISTER_DECLARATION(Register, rdispatch,      r21);
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// Java stack pointer
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REGISTER_DECLARATION(Register, esp,      r20);
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// TODO : x86 uses rbp to save SP in method handle code
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// we may need to do the same with fp
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// JSR 292 fixed register usages:
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//REGISTER_DECLARATION(Register, r_mh_SP_save, r29);
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#define assert_cond(ARG1) assert(ARG1, #ARG1)
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namespace asm_util {
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  uint32_t encode_logical_immediate(bool is32, uint64_t imm);
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};
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using namespace asm_util;
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class Assembler;
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class Instruction_aarch64 {
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  unsigned insn;
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#ifdef ASSERT
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  unsigned bits;
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#endif
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  Assembler *assem;
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public:
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  Instruction_aarch64(class Assembler *as) {
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#ifdef ASSERT
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    bits = 0;
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#endif
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    insn = 0;
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    assem = as;
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  }
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  inline ~Instruction_aarch64();
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  unsigned &get_insn() { return insn; }
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#ifdef ASSERT
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  unsigned &get_bits() { return bits; }
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#endif
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  static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
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    union {
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      unsigned u;
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      int n;
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    };
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    u = val << (31 - hi);
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    n = n >> (31 - hi + lo);
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    return n;
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  }
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  static inline uint32_t extract(uint32_t val, int msb, int lsb) {
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    int nbits = msb - lsb + 1;
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    assert_cond(msb >= lsb);
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    uint32_t mask = (1U << nbits) - 1;
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    uint32_t result = val >> lsb;
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    result &= mask;
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    return result;
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  }
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  static inline int32_t sextract(uint32_t val, int msb, int lsb) {
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    uint32_t uval = extract(val, msb, lsb);
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    return extend(uval, msb - lsb);
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  }
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  static void patch(address a, int msb, int lsb, unsigned long val) {
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    int nbits = msb - lsb + 1;
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    guarantee(val < (1U << nbits), "Field too big for insn");
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    assert_cond(msb >= lsb);
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    unsigned mask = (1U << nbits) - 1;
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    val <<= lsb;
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    mask <<= lsb;
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    unsigned target = *(unsigned *)a;
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    target &= ~mask;
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    target |= val;
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    *(unsigned *)a = target;
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  }
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  static void spatch(address a, int msb, int lsb, long val) {
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    int nbits = msb - lsb + 1;
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    long chk = val >> (nbits - 1);
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    guarantee (chk == -1 || chk == 0, "Field too big for insn");
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    unsigned uval = val;
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    unsigned mask = (1U << nbits) - 1;
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    uval &= mask;
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    uval <<= lsb;
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    mask <<= lsb;
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    unsigned target = *(unsigned *)a;
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    target &= ~mask;
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    target |= uval;
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    *(unsigned *)a = target;
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  }
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  void f(unsigned val, int msb, int lsb) {
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    int nbits = msb - lsb + 1;
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    guarantee(val < (1U << nbits), "Field too big for insn");
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    assert_cond(msb >= lsb);
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    unsigned mask = (1U << nbits) - 1;
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    val <<= lsb;
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    mask <<= lsb;
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    insn |= val;
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    assert_cond((bits & mask) == 0);
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#ifdef ASSERT
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    bits |= mask;
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#endif
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  }
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  void f(unsigned val, int bit) {
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    f(val, bit, bit);
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  }
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  void sf(long val, int msb, int lsb) {
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    int nbits = msb - lsb + 1;
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    long chk = val >> (nbits - 1);
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    guarantee (chk == -1 || chk == 0, "Field too big for insn");
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    unsigned uval = val;
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    unsigned mask = (1U << nbits) - 1;
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    uval &= mask;
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    f(uval, lsb + nbits - 1, lsb);
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  }
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  void rf(Register r, int lsb) {
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    f(r->encoding_nocheck(), lsb + 4, lsb);
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  }
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  // reg|ZR
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  void zrf(Register r, int lsb) {
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    f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
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  }
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  // reg|SP
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  void srf(Register r, int lsb) {
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    f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
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  }
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  void rf(FloatRegister r, int lsb) {
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    f(r->encoding_nocheck(), lsb + 4, lsb);
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  }
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  unsigned get(int msb = 31, int lsb = 0) {
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    int nbits = msb - lsb + 1;
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    unsigned mask = ((1U << nbits) - 1) << lsb;
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    assert_cond(bits & mask == mask);
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    return (insn & mask) >> lsb;
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  }
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  void fixed(unsigned value, unsigned mask) {
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    assert_cond ((mask & bits) == 0);
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#ifdef ASSERT
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    bits |= mask;
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#endif
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    insn |= value;
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  }
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};
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#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
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class PrePost {
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  int _offset;
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  Register _r;
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public:
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  PrePost(Register reg, int o) : _r(reg), _offset(o) { }
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  int offset() { return _offset; }
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  Register reg() { return _r; }
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};
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aph
parents:
diff changeset
   307
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   308
class Pre : public PrePost {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   309
public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   310
  Pre(Register reg, int o) : PrePost(reg, o) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   311
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   312
class Post : public PrePost {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   313
public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   314
  Post(Register reg, int o) : PrePost(reg, o) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   315
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   316
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   317
namespace ext
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   318
{
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   319
  enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   320
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   321
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   322
// abs methods which cannot overflow and so are well-defined across
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   323
// the entire domain of integer types.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   324
static inline unsigned int uabs(unsigned int n) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   325
  union {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   326
    unsigned int result;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   327
    int value;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   328
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   329
  result = n;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   330
  if (value < 0) result = -result;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   331
  return result;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   332
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   333
static inline unsigned long uabs(unsigned long n) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   334
  union {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   335
    unsigned long result;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   336
    long value;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   337
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   338
  result = n;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   339
  if (value < 0) result = -result;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   340
  return result;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   341
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   342
static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   343
static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   344
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   345
// Addressing modes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   346
class Address VALUE_OBJ_CLASS_SPEC {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   347
 public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   348
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   349
  enum mode { no_mode, base_plus_offset, pre, post, pcrel,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   350
              base_plus_offset_reg, literal };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   351
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   352
  // Shift and extend for base reg + reg offset addressing
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   353
  class extend {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   354
    int _option, _shift;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   355
    ext::operation _op;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   356
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   357
    extend() { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   358
    extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   359
    int option() const{ return _option; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   360
    int shift() const { return _shift; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   361
    ext::operation op() const { return _op; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   362
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   363
  class uxtw : public extend {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   364
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   365
    uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   366
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   367
  class lsl : public extend {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   368
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   369
    lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   370
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   371
  class sxtw : public extend {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   372
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   373
    sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   374
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   375
  class sxtx : public extend {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   376
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   377
    sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   378
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   379
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   380
 private:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   381
  Register _base;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   382
  Register _index;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   383
  long _offset;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   384
  enum mode _mode;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   385
  extend _ext;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   386
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   387
  RelocationHolder _rspec;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   388
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   389
  // Typically we use AddressLiterals we want to use their rval
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   390
  // However in some situations we want the lval (effect address) of
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   391
  // the item.  We provide a special factory for making those lvals.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   392
  bool _is_lval;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   393
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   394
  // If the target is far we'll need to load the ea of this to a
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   395
  // register to reach it. Otherwise if near we can do PC-relative
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   396
  // addressing.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   397
  address          _target;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   398
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   399
 public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   400
  Address()
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   401
    : _mode(no_mode) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   402
  Address(Register r)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   403
    : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   404
  Address(Register r, int o)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   405
    : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   406
  Address(Register r, long o)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   407
    : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   408
  Address(Register r, unsigned long o)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   409
    : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   410
#ifdef ASSERT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   411
  Address(Register r, ByteSize disp)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   412
    : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   413
      _index(noreg), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   414
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   415
  Address(Register r, Register r1, extend ext = lsl())
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   416
    : _mode(base_plus_offset_reg), _base(r), _index(r1),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   417
    _ext(ext), _offset(0), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   418
  Address(Pre p)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   419
    : _mode(pre), _base(p.reg()), _offset(p.offset()) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   420
  Address(Post p)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   421
    : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   422
  Address(address target, RelocationHolder const& rspec)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   423
    : _mode(literal),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   424
      _rspec(rspec),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   425
      _is_lval(false),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   426
      _target(target)  { }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   427
  Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   428
  Address(Register base, RegisterOrConstant index, extend ext = lsl())
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   429
    : _base (base),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   430
      _ext(ext), _offset(0), _target(0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   431
    if (index.is_register()) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   432
      _mode = base_plus_offset_reg;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   433
      _index = index.as_register();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   434
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   435
      guarantee(ext.option() == ext::uxtx, "should be");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   436
      assert(index.is_constant(), "should be");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   437
      _mode = base_plus_offset;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   438
      _offset = index.as_constant() << ext.shift();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   439
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   440
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   441
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   442
  Register base() const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   443
    guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   444
               | _mode == post),
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   445
              "wrong mode");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   446
    return _base;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   447
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   448
  long offset() const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   449
    return _offset;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   450
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   451
  Register index() const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   452
    return _index;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   453
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   454
  mode getMode() const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   455
    return _mode;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   456
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   457
  bool uses(Register reg) const { return _base == reg || _index == reg; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   458
  address target() const { return _target; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   459
  const RelocationHolder& rspec() const { return _rspec; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   460
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   461
  void encode(Instruction_aarch64 *i) const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   462
    i->f(0b111, 29, 27);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   463
    i->srf(_base, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   464
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   465
    switch(_mode) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   466
    case base_plus_offset:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   467
      {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   468
        unsigned size = i->get(31, 30);
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
   469
        if (i->get(26, 26) && i->get(23, 23)) {
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
   470
          // SIMD Q Type - Size = 128 bits
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
   471
          assert(size == 0, "bad size");
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
   472
          size = 0b100;
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
   473
        }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   474
        unsigned mask = (1 << size) - 1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   475
        if (_offset < 0 || _offset & mask)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   476
          {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   477
            i->f(0b00, 25, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   478
            i->f(0, 21), i->f(0b00, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   479
            i->sf(_offset, 20, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   480
          } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   481
            i->f(0b01, 25, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   482
            i->f(_offset >> size, 21, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   483
          }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   484
      }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   485
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   486
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   487
    case base_plus_offset_reg:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   488
      {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   489
        i->f(0b00, 25, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   490
        i->f(1, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   491
        i->rf(_index, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   492
        i->f(_ext.option(), 15, 13);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   493
        unsigned size = i->get(31, 30);
31227
964d24a82077 8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents: 30890
diff changeset
   494
        if (i->get(26, 26) && i->get(23, 23)) {
964d24a82077 8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents: 30890
diff changeset
   495
          // SIMD Q Type - Size = 128 bits
964d24a82077 8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents: 30890
diff changeset
   496
          assert(size == 0, "bad size");
964d24a82077 8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents: 30890
diff changeset
   497
          size = 0b100;
964d24a82077 8129551: aarch64: some regressions introduced by addition of vectorisation code
enevill
parents: 30890
diff changeset
   498
        }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   499
        if (size == 0) // It's a byte
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   500
          i->f(_ext.shift() >= 0, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   501
        else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   502
          if (_ext.shift() > 0)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   503
            assert(_ext.shift() == (int)size, "bad shift");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   504
          i->f(_ext.shift() > 0, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   505
        }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   506
        i->f(0b10, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   507
      }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   508
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   509
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   510
    case pre:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   511
      i->f(0b00, 25, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   512
      i->f(0, 21), i->f(0b11, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   513
      i->sf(_offset, 20, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   514
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   515
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   516
    case post:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   517
      i->f(0b00, 25, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   518
      i->f(0, 21), i->f(0b01, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   519
      i->sf(_offset, 20, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   520
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   521
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   522
    default:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   523
      ShouldNotReachHere();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   524
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   525
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   526
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   527
  void encode_pair(Instruction_aarch64 *i) const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   528
    switch(_mode) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   529
    case base_plus_offset:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   530
      i->f(0b010, 25, 23);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   531
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   532
    case pre:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   533
      i->f(0b011, 25, 23);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   534
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   535
    case post:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   536
      i->f(0b001, 25, 23);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   537
      break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   538
    default:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   539
      ShouldNotReachHere();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   540
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   541
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   542
    unsigned size; // Operand shift in 32-bit words
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   543
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   544
    if (i->get(26, 26)) { // float
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   545
      switch(i->get(31, 30)) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   546
      case 0b10:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   547
        size = 2; break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   548
      case 0b01:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   549
        size = 1; break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   550
      case 0b00:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   551
        size = 0; break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   552
      default:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   553
        ShouldNotReachHere();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   554
      }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   555
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   556
      size = i->get(31, 31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   557
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   558
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   559
    size = 4 << size;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   560
    guarantee(_offset % size == 0, "bad offset");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   561
    i->sf(_offset / size, 21, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   562
    i->srf(_base, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   563
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   564
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   565
  void encode_nontemporal_pair(Instruction_aarch64 *i) const {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   566
    // Only base + offset is allowed
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   567
    i->f(0b000, 25, 23);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   568
    unsigned size = i->get(31, 31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   569
    size = 4 << size;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   570
    guarantee(_offset % size == 0, "bad offset");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   571
    i->sf(_offset / size, 21, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   572
    i->srf(_base, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   573
    guarantee(_mode == Address::base_plus_offset,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   574
              "Bad addressing mode for non-temporal op");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   575
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   576
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   577
  void lea(MacroAssembler *, Register) const;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   578
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   579
  static bool offset_ok_for_immed(long offset, int shift = 0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   580
    unsigned mask = (1 << shift) - 1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   581
    if (offset < 0 || offset & mask) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   582
      return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   583
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   584
      return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   585
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   586
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   587
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   588
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   589
// Convience classes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   590
class RuntimeAddress: public Address {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   591
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   592
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   593
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   594
  RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   595
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   596
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   597
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   598
class OopAddress: public Address {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   599
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   600
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   601
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   602
  OopAddress(address target) : Address(target, relocInfo::oop_type){}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   603
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   604
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   605
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   606
class ExternalAddress: public Address {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   607
 private:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   608
  static relocInfo::relocType reloc_for_target(address target) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   609
    // Sometimes ExternalAddress is used for values which aren't
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   610
    // exactly addresses, like the card table base.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   611
    // external_word_type can't be used for values in the first page
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   612
    // so just skip the reloc in that case.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   613
    return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   614
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   615
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   616
 public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   617
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   618
  ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   619
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   620
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   621
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   622
class InternalAddress: public Address {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   623
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   624
  public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   625
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   626
  InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   627
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   628
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   629
const int FPUStateSizeInWords = 32 * 2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   630
typedef enum {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   631
  PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   632
  PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   633
  PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   634
} prfop;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   635
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   636
class Assembler : public AbstractAssembler {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   637
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   638
#ifndef PRODUCT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   639
  static const unsigned long asm_bp;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   640
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   641
  void emit_long(jint x) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   642
    if ((unsigned long)pc() == asm_bp)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   643
      asm volatile ("nop");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   644
    AbstractAssembler::emit_int32(x);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   645
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   646
#else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   647
  void emit_long(jint x) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   648
    AbstractAssembler::emit_int32(x);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   649
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   650
#endif
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   651
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   652
public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   653
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   654
  enum { instruction_size = 4 };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   655
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   656
  Address adjust(Register base, int offset, bool preIncrement) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   657
    if (preIncrement)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   658
      return Address(Pre(base, offset));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   659
    else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   660
      return Address(Post(base, offset));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   661
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   662
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   663
  Address pre(Register base, int offset) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   664
    return adjust(base, offset, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   665
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   666
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   667
  Address post (Register base, int offset) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   668
    return adjust(base, offset, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   669
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   670
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   671
  Instruction_aarch64* current;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   672
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   673
  void set_current(Instruction_aarch64* i) { current = i; }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   674
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   675
  void f(unsigned val, int msb, int lsb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   676
    current->f(val, msb, lsb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   677
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   678
  void f(unsigned val, int msb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   679
    current->f(val, msb, msb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   680
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   681
  void sf(long val, int msb, int lsb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   682
    current->sf(val, msb, lsb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   683
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   684
  void rf(Register reg, int lsb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   685
    current->rf(reg, lsb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   686
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   687
  void srf(Register reg, int lsb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   688
    current->srf(reg, lsb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   689
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   690
  void zrf(Register reg, int lsb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   691
    current->zrf(reg, lsb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   692
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   693
  void rf(FloatRegister reg, int lsb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   694
    current->rf(reg, lsb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   695
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   696
  void fixed(unsigned value, unsigned mask) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   697
    current->fixed(value, mask);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   698
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   699
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   700
  void emit() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   701
    emit_long(current->get_insn());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   702
    assert_cond(current->get_bits() == 0xffffffff);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   703
    current = NULL;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   704
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   705
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   706
  typedef void (Assembler::* uncond_branch_insn)(address dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   707
  typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   708
  typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   709
  typedef void (Assembler::* prefetch_insn)(address target, prfop);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   710
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   711
  void wrap_label(Label &L, uncond_branch_insn insn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   712
  void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   713
  void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   714
  void wrap_label(Label &L, prfop, prefetch_insn insn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   715
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   716
  // PC-rel. addressing
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   717
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   718
  void adr(Register Rd, address dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   719
  void _adrp(Register Rd, address dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   720
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   721
  void adr(Register Rd, const Address &dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   722
  void _adrp(Register Rd, const Address &dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   723
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   724
  void adr(Register Rd, Label &L) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   725
    wrap_label(Rd, L, &Assembler::Assembler::adr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   726
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   727
  void _adrp(Register Rd, Label &L) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   728
    wrap_label(Rd, L, &Assembler::_adrp);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   729
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   730
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   731
  void adrp(Register Rd, const Address &dest, unsigned long &offset);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   732
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   733
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   734
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   735
  void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   736
                         int negated_op);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   737
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   738
  // Add/subtract (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   739
#define INSN(NAME, decode, negated)                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   740
  void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   741
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   742
    f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   743
    zrf(Rd, 0), srf(Rn, 5);                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   744
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   745
                                                                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   746
  void NAME(Register Rd, Register Rn, unsigned imm) {                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   747
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   748
    add_sub_immediate(Rd, Rn, imm, decode, negated);                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   749
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   750
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   751
  INSN(addsw, 0b001, 0b011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   752
  INSN(subsw, 0b011, 0b001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   753
  INSN(adds,  0b101, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   754
  INSN(subs,  0b111, 0b101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   755
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   756
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   757
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   758
#define INSN(NAME, decode, negated)                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   759
  void NAME(Register Rd, Register Rn, unsigned imm) {   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   760
    starti;                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   761
    add_sub_immediate(Rd, Rn, imm, decode, negated);    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   762
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   763
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   764
  INSN(addw, 0b000, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   765
  INSN(subw, 0b010, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   766
  INSN(add,  0b100, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   767
  INSN(sub,  0b110, 0b100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   768
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   769
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   770
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   771
 // Logical (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   772
#define INSN(NAME, decode, is32)                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   773
  void NAME(Register Rd, Register Rn, uint64_t imm) {           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   774
    starti;                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   775
    uint32_t val = encode_logical_immediate(is32, imm);         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   776
    f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   777
    srf(Rd, 0), zrf(Rn, 5);                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   778
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   779
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   780
  INSN(andw, 0b000, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   781
  INSN(orrw, 0b001, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   782
  INSN(eorw, 0b010, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   783
  INSN(andr,  0b100, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   784
  INSN(orr,  0b101, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   785
  INSN(eor,  0b110, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   786
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   787
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   788
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   789
#define INSN(NAME, decode, is32)                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   790
  void NAME(Register Rd, Register Rn, uint64_t imm) {           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   791
    starti;                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   792
    uint32_t val = encode_logical_immediate(is32, imm);         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   793
    f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   794
    zrf(Rd, 0), zrf(Rn, 5);                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   795
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   796
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   797
  INSN(ands, 0b111, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   798
  INSN(andsw, 0b011, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   799
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   800
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   801
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   802
  // Move wide (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   803
#define INSN(NAME, opcode)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   804
  void NAME(Register Rd, unsigned imm, unsigned shift = 0) {            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   805
    assert_cond((shift/16)*16 == shift);                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   806
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   807
    f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21),        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   808
      f(imm, 20, 5);                                                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   809
    rf(Rd, 0);                                                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   810
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   811
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   812
  INSN(movnw, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   813
  INSN(movzw, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   814
  INSN(movkw, 0b011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   815
  INSN(movn, 0b100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   816
  INSN(movz, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   817
  INSN(movk, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   818
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   819
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   820
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   821
  // Bitfield
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   822
#define INSN(NAME, opcode)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   823
  void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) {   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   824
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   825
    f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10);                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   826
    rf(Rn, 5), rf(Rd, 0);                                               \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   827
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   828
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   829
  INSN(sbfmw, 0b0001001100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   830
  INSN(bfmw,  0b0011001100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   831
  INSN(ubfmw, 0b0101001100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   832
  INSN(sbfm,  0b1001001101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   833
  INSN(bfm,   0b1011001101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   834
  INSN(ubfm,  0b1101001101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   835
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   836
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   837
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   838
  // Extract
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   839
#define INSN(NAME, opcode)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   840
  void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) {     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   841
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   842
    f(opcode, 31, 21), f(imms, 15, 10);                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   843
    rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   844
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   845
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   846
  INSN(extrw, 0b00010011100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   847
  INSN(extr,  0b10010011110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   848
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   849
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   850
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   851
  // The maximum range of a branch is fixed for the AArch64
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   852
  // architecture.  In debug mode we shrink it in order to test
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   853
  // trampolines, but not so small that branches in the interpreter
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   854
  // are out of range.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   855
  static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   856
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   857
  static bool reachable_from_branch_at(address branch, address target) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   858
    return uabs(target - branch) < branch_range;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   859
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   860
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   861
  // Unconditional branch (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   862
#define INSN(NAME, opcode)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   863
  void NAME(address dest) {                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   864
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   865
    long offset = (dest - pc()) >> 2;                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   866
    DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   867
    f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0);               \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   868
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   869
  void NAME(Label &L) {                                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   870
    wrap_label(L, &Assembler::NAME);                                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   871
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   872
  void NAME(const Address &dest);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   873
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   874
  INSN(b, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   875
  INSN(bl, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   876
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   877
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   878
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   879
  // Compare & branch (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   880
#define INSN(NAME, opcode)                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   881
  void NAME(Register Rt, address dest) {                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   882
    long offset = (dest - pc()) >> 2;                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   883
    starti;                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   884
    f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0);    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   885
  }                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   886
  void NAME(Register Rt, Label &L) {                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   887
    wrap_label(Rt, L, &Assembler::NAME);                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   888
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   889
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   890
  INSN(cbzw,  0b00110100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   891
  INSN(cbnzw, 0b00110101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   892
  INSN(cbz,   0b10110100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   893
  INSN(cbnz,  0b10110101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   894
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   895
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   896
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   897
  // Test & branch (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   898
#define INSN(NAME, opcode)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   899
  void NAME(Register Rt, int bitpos, address dest) {                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   900
    long offset = (dest - pc()) >> 2;                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   901
    int b5 = bitpos >> 5;                                               \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   902
    bitpos &= 0x1f;                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   903
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   904
    f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   905
    rf(Rt, 0);                                                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   906
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   907
  void NAME(Register Rt, int bitpos, Label &L) {                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   908
    wrap_label(Rt, bitpos, L, &Assembler::NAME);                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   909
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   910
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   911
  INSN(tbz,  0b0110110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   912
  INSN(tbnz, 0b0110111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   913
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   914
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   915
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   916
  // Conditional branch (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   917
  enum Condition
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   918
    {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   919
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   920
  void br(Condition  cond, address dest) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   921
    long offset = (dest - pc()) >> 2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   922
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   923
    f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   924
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   925
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   926
#define INSN(NAME, cond)                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   927
  void NAME(address dest) {                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   928
    br(cond, dest);                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   929
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   930
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   931
  INSN(beq, EQ);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   932
  INSN(bne, NE);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   933
  INSN(bhs, HS);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   934
  INSN(bcs, CS);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   935
  INSN(blo, LO);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   936
  INSN(bcc, CC);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   937
  INSN(bmi, MI);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   938
  INSN(bpl, PL);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   939
  INSN(bvs, VS);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   940
  INSN(bvc, VC);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   941
  INSN(bhi, HI);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   942
  INSN(bls, LS);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   943
  INSN(bge, GE);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   944
  INSN(blt, LT);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   945
  INSN(bgt, GT);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   946
  INSN(ble, LE);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   947
  INSN(bal, AL);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   948
  INSN(bnv, NV);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   949
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   950
  void br(Condition cc, Label &L);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   951
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   952
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   953
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   954
  // Exception generation
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   955
  void generate_exception(int opc, int op2, int LL, unsigned imm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   956
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   957
    f(0b11010100, 31, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   958
    f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   959
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   960
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   961
#define INSN(NAME, opc, op2, LL)                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   962
  void NAME(unsigned imm) {                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   963
    generate_exception(opc, op2, LL, imm);      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   964
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   965
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   966
  INSN(svc, 0b000, 0, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   967
  INSN(hvc, 0b000, 0, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   968
  INSN(smc, 0b000, 0, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   969
  INSN(brk, 0b001, 0, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   970
  INSN(hlt, 0b010, 0, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   971
  INSN(dpcs1, 0b101, 0, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   972
  INSN(dpcs2, 0b101, 0, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   973
  INSN(dpcs3, 0b101, 0, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   974
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   975
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   976
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   977
  // System
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   978
  void system(int op0, int op1, int CRn, int CRm, int op2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   979
              Register rt = (Register)0b11111)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   980
  {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   981
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   982
    f(0b11010101000, 31, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   983
    f(op0, 20, 19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   984
    f(op1, 18, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   985
    f(CRn, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   986
    f(CRm, 11, 8);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   987
    f(op2, 7, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   988
    rf(rt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   989
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   990
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   991
  void hint(int imm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   992
    system(0b00, 0b011, 0b0010, imm, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   993
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   994
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   995
  void nop() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   996
    hint(0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   997
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   998
  // we only provide mrs and msr for the special purpose system
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
   999
  // registers where op1 (instr[20:19]) == 11 and, (currently) only
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1000
  // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1001
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1002
  void msr(int op1, int CRn, int CRm, int op2, Register rt) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1003
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1004
    f(0b1101010100011, 31, 19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1005
    f(op1, 18, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1006
    f(CRn, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1007
    f(CRm, 11, 8);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1008
    f(op2, 7, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1009
    // writing zr is ok
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1010
    zrf(rt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1011
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1012
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1013
  void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1014
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1015
    f(0b1101010100111, 31, 19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1016
    f(op1, 18, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1017
    f(CRn, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1018
    f(CRm, 11, 8);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1019
    f(op2, 7, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1020
    // reading to zr is a mistake
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1021
    rf(rt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1022
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1023
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1024
  enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1025
                ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1026
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1027
  void dsb(barrier imm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1028
    system(0b00, 0b011, 0b00011, imm, 0b100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1029
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1030
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1031
  void dmb(barrier imm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1032
    system(0b00, 0b011, 0b00011, imm, 0b101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1033
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1034
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1035
  void isb() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1036
    system(0b00, 0b011, 0b00011, SY, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1037
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1038
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1039
  void dc(Register Rt) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1040
    system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1041
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1042
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1043
  void ic(Register Rt) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1044
    system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1045
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1046
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1047
  // A more convenient access to dmb for our purposes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1048
  enum Membar_mask_bits {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1049
    // We can use ISH for a barrier because the ARM ARM says "This
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1050
    // architecture assumes that all Processing Elements that use the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1051
    // same operating system or hypervisor are in the same Inner
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1052
    // Shareable shareability domain."
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1053
    StoreStore = ISHST,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1054
    LoadStore  = ISHLD,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1055
    LoadLoad   = ISHLD,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1056
    StoreLoad  = ISH,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1057
    AnyAny     = ISH
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1058
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1059
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1060
  void membar(Membar_mask_bits order_constraint) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1061
    dmb(Assembler::barrier(order_constraint));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1062
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1063
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1064
  // Unconditional branch (register)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1065
  void branch_reg(Register R, int opc) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1066
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1067
    f(0b1101011, 31, 25);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1068
    f(opc, 24, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1069
    f(0b11111000000, 20, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1070
    rf(R, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1071
    f(0b00000, 4, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1072
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1073
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1074
#define INSN(NAME, opc)                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1075
  void NAME(Register R) {                       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1076
    branch_reg(R, opc);                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1077
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1078
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1079
  INSN(br, 0b0000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1080
  INSN(blr, 0b0001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1081
  INSN(ret, 0b0010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1082
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1083
  void ret(void *p); // This forces a compile-time error for ret(0)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1084
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1085
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1086
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1087
#define INSN(NAME, opc)                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1088
  void NAME() {                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1089
    branch_reg((Register)0b11111, opc);         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1090
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1091
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1092
  INSN(eret, 0b0100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1093
  INSN(drps, 0b0101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1094
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1095
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1096
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1097
  // Load/store exclusive
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1098
  enum operand_size { byte, halfword, word, xword };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1099
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1100
  void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1101
    Register Rn, enum operand_size sz, int op, int o0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1102
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1103
    f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1104
    rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1105
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1106
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1107
#define INSN4(NAME, sz, op, o0) /* Four registers */                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1108
  void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
31863
22ea3a456610 8131483: aarch64: illegal stlxr instructions
enevill
parents: 31591
diff changeset
  1109
    assert(Rs != Rn, "unpredictable instruction");                  \
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1110
    load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1111
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1112
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1113
#define INSN3(NAME, sz, op, o0) /* Three registers */                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1114
  void NAME(Register Rs, Register Rt, Register Rn) {                    \
31863
22ea3a456610 8131483: aarch64: illegal stlxr instructions
enevill
parents: 31591
diff changeset
  1115
    assert(Rs != Rn, "unpredictable instruction");                  \
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1116
    load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0);    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1117
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1118
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1119
#define INSN2(NAME, sz, op, o0) /* Two registers */                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1120
  void NAME(Register Rt, Register Rn) {                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1121
    load_store_exclusive((Register)0b11111, Rt, (Register)0b11111,      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1122
                         Rn, sz, op, o0);                               \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1123
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1124
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1125
#define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1126
  void NAME(Register Rt1, Register Rt2, Register Rn) {                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1127
    load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0);  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1128
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1129
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1130
  // bytes
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1131
  INSN3(stxrb, byte, 0b000, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1132
  INSN3(stlxrb, byte, 0b000, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1133
  INSN2(ldxrb, byte, 0b010, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1134
  INSN2(ldaxrb, byte, 0b010, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1135
  INSN2(stlrb, byte, 0b100, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1136
  INSN2(ldarb, byte, 0b110, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1137
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1138
  // halfwords
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1139
  INSN3(stxrh, halfword, 0b000, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1140
  INSN3(stlxrh, halfword, 0b000, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1141
  INSN2(ldxrh, halfword, 0b010, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1142
  INSN2(ldaxrh, halfword, 0b010, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1143
  INSN2(stlrh, halfword, 0b100, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1144
  INSN2(ldarh, halfword, 0b110, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1145
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1146
  // words
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1147
  INSN3(stxrw, word, 0b000, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1148
  INSN3(stlxrw, word, 0b000, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1149
  INSN4(stxpw, word, 0b001, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1150
  INSN4(stlxpw, word, 0b001, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1151
  INSN2(ldxrw, word, 0b010, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1152
  INSN2(ldaxrw, word, 0b010, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1153
  INSN_FOO(ldxpw, word, 0b011, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1154
  INSN_FOO(ldaxpw, word, 0b011, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1155
  INSN2(stlrw, word, 0b100, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1156
  INSN2(ldarw, word, 0b110, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1157
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1158
  // xwords
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1159
  INSN3(stxr, xword, 0b000, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1160
  INSN3(stlxr, xword, 0b000, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1161
  INSN4(stxp, xword, 0b001, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1162
  INSN4(stlxp, xword, 0b001, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1163
  INSN2(ldxr, xword, 0b010, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1164
  INSN2(ldaxr, xword, 0b010, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1165
  INSN_FOO(ldxp, xword, 0b011, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1166
  INSN_FOO(ldaxp, xword, 0b011, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1167
  INSN2(stlr, xword, 0b100, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1168
  INSN2(ldar, xword, 0b110, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1169
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1170
#undef INSN2
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1171
#undef INSN3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1172
#undef INSN4
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1173
#undef INSN_FOO
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1174
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1175
  // Load register (literal)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1176
#define INSN(NAME, opc, V)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1177
  void NAME(Register Rt, address dest) {                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1178
    long offset = (dest - pc()) >> 2;                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1179
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1180
    f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1181
      sf(offset, 23, 5);                                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1182
    rf(Rt, 0);                                                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1183
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1184
  void NAME(Register Rt, address dest, relocInfo::relocType rtype) {    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1185
    InstructionMark im(this);                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1186
    guarantee(rtype == relocInfo::internal_word_type,                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1187
              "only internal_word_type relocs make sense here");        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1188
    code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1189
    NAME(Rt, dest);                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1190
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1191
  void NAME(Register Rt, Label &L) {                                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1192
    wrap_label(Rt, L, &Assembler::NAME);                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1193
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1194
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1195
  INSN(ldrw, 0b00, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1196
  INSN(ldr, 0b01, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1197
  INSN(ldrsw, 0b10, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1198
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1199
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1200
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1201
#define INSN(NAME, opc, V)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1202
  void NAME(FloatRegister Rt, address dest) {                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1203
    long offset = (dest - pc()) >> 2;                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1204
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1205
    f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1206
      sf(offset, 23, 5);                                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1207
    rf((Register)Rt, 0);                                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1208
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1209
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1210
  INSN(ldrs, 0b00, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1211
  INSN(ldrd, 0b01, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1212
  INSN(ldrq, 0x10, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1213
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1214
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1215
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1216
#define INSN(NAME, opc, V)                                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1217
  void NAME(address dest, prfop op = PLDL1KEEP) {                       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1218
    long offset = (dest - pc()) >> 2;                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1219
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1220
    f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1221
      sf(offset, 23, 5);                                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1222
    f(op, 4, 0);                                                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1223
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1224
  void NAME(Label &L, prfop op = PLDL1KEEP) {                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1225
    wrap_label(L, op, &Assembler::NAME);                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1226
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1227
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1228
  INSN(prfm, 0b11, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1229
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1230
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1231
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1232
  // Load/store
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1233
  void ld_st1(int opc, int p1, int V, int L,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1234
              Register Rt1, Register Rt2, Address adr, bool no_allocate) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1235
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1236
    f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1237
    zrf(Rt2, 10), zrf(Rt1, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1238
    if (no_allocate) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1239
      adr.encode_nontemporal_pair(current);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1240
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1241
      adr.encode_pair(current);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1242
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1243
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1244
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1245
  // Load/store register pair (offset)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1246
#define INSN(NAME, size, p1, V, L, no_allocate)         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1247
  void NAME(Register Rt1, Register Rt2, Address adr) {  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1248
    ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1249
   }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1250
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1251
  INSN(stpw, 0b00, 0b101, 0, 0, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1252
  INSN(ldpw, 0b00, 0b101, 0, 1, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1253
  INSN(ldpsw, 0b01, 0b101, 0, 1, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1254
  INSN(stp, 0b10, 0b101, 0, 0, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1255
  INSN(ldp, 0b10, 0b101, 0, 1, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1256
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1257
  // Load/store no-allocate pair (offset)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1258
  INSN(stnpw, 0b00, 0b101, 0, 0, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1259
  INSN(ldnpw, 0b00, 0b101, 0, 1, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1260
  INSN(stnp, 0b10, 0b101, 0, 0, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1261
  INSN(ldnp, 0b10, 0b101, 0, 1, true);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1262
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1263
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1264
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1265
#define INSN(NAME, size, p1, V, L, no_allocate)                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1266
  void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) {        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1267
    ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1268
   }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1269
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1270
  INSN(stps, 0b00, 0b101, 1, 0, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1271
  INSN(ldps, 0b00, 0b101, 1, 1, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1272
  INSN(stpd, 0b01, 0b101, 1, 0, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1273
  INSN(ldpd, 0b01, 0b101, 1, 1, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1274
  INSN(stpq, 0b10, 0b101, 1, 0, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1275
  INSN(ldpq, 0b10, 0b101, 1, 1, false);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1276
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1277
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1278
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1279
  // Load/store register (all modes)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1280
  void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1281
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1282
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1283
    f(V, 26); // general reg?
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1284
    zrf(Rt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1285
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1286
    // Encoding for literal loads is done here (rather than pushed
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1287
    // down into Address::encode) because the encoding of this
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1288
    // instruction is too different from all of the other forms to
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1289
    // make it worth sharing.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1290
    if (adr.getMode() == Address::literal) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1291
      assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1292
      assert(op == 0b01, "literal form can only be used with loads");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1293
      f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1294
      long offset = (adr.target() - pc()) >> 2;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1295
      sf(offset, 23, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1296
      code_section()->relocate(pc(), adr.rspec());
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1297
      return;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1298
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1299
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1300
    f(size, 31, 30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1301
    f(op, 23, 22); // str
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1302
    adr.encode(current);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1303
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1304
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1305
#define INSN(NAME, size, op)                            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1306
  void NAME(Register Rt, const Address &adr) {          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1307
    ld_st2(Rt, adr, size, op);                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1308
  }                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1309
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1310
  INSN(str, 0b11, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1311
  INSN(strw, 0b10, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1312
  INSN(strb, 0b00, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1313
  INSN(strh, 0b01, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1314
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1315
  INSN(ldr, 0b11, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1316
  INSN(ldrw, 0b10, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1317
  INSN(ldrb, 0b00, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1318
  INSN(ldrh, 0b01, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1319
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1320
  INSN(ldrsb, 0b00, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1321
  INSN(ldrsbw, 0b00, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1322
  INSN(ldrsh, 0b01, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1323
  INSN(ldrshw, 0b01, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1324
  INSN(ldrsw, 0b10, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1325
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1326
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1327
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1328
#define INSN(NAME, size, op)                                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1329
  void NAME(const Address &adr, prfop pfop = PLDL1KEEP) {       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1330
    ld_st2((Register)pfop, adr, size, op);                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1331
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1332
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1333
  INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1334
                          // writeback modes, but the assembler
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1335
                          // doesn't enfore that.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1336
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1337
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1338
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1339
#define INSN(NAME, size, op)                            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1340
  void NAME(FloatRegister Rt, const Address &adr) {     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1341
    ld_st2((Register)Rt, adr, size, op, 1);             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1342
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1343
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1344
  INSN(strd, 0b11, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1345
  INSN(strs, 0b10, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1346
  INSN(ldrd, 0b11, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1347
  INSN(ldrs, 0b10, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1348
  INSN(strq, 0b00, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1349
  INSN(ldrq, 0x00, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1350
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1351
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1352
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1353
  enum shift_kind { LSL, LSR, ASR, ROR };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1354
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1355
  void op_shifted_reg(unsigned decode,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1356
                      enum shift_kind kind, unsigned shift,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1357
                      unsigned size, unsigned op) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1358
    f(size, 31);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1359
    f(op, 30, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1360
    f(decode, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1361
    f(shift, 15, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1362
    f(kind, 23, 22);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1363
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1364
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1365
  // Logical (shifted register)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1366
#define INSN(NAME, size, op, N)                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1367
  void NAME(Register Rd, Register Rn, Register Rm,              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1368
            enum shift_kind kind = LSL, unsigned shift = 0) {   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1369
    starti;                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1370
    f(N, 21);                                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1371
    zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1372
    op_shifted_reg(0b01010, kind, shift, size, op);             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1373
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1374
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1375
  INSN(andr, 1, 0b00, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1376
  INSN(orr, 1, 0b01, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1377
  INSN(eor, 1, 0b10, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1378
  INSN(ands, 1, 0b11, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1379
  INSN(andw, 0, 0b00, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1380
  INSN(orrw, 0, 0b01, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1381
  INSN(eorw, 0, 0b10, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1382
  INSN(andsw, 0, 0b11, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1383
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1384
  INSN(bic, 1, 0b00, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1385
  INSN(orn, 1, 0b01, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1386
  INSN(eon, 1, 0b10, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1387
  INSN(bics, 1, 0b11, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1388
  INSN(bicw, 0, 0b00, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1389
  INSN(ornw, 0, 0b01, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1390
  INSN(eonw, 0, 0b10, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1391
  INSN(bicsw, 0, 0b11, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1392
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1393
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1394
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1395
  // Add/subtract (shifted register)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1396
#define INSN(NAME, size, op)                            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1397
  void NAME(Register Rd, Register Rn, Register Rm,      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1398
            enum shift_kind kind, unsigned shift = 0) { \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1399
    starti;                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1400
    f(0, 21);                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1401
    assert_cond(kind != ROR);                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1402
    zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16);                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1403
    op_shifted_reg(0b01011, kind, shift, size, op);     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1404
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1405
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1406
  INSN(add, 1, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1407
  INSN(sub, 1, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1408
  INSN(addw, 0, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1409
  INSN(subw, 0, 0b10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1410
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1411
  INSN(adds, 1, 0b001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1412
  INSN(subs, 1, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1413
  INSN(addsw, 0, 0b001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1414
  INSN(subsw, 0, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1415
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1416
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1417
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1418
  // Add/subtract (extended register)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1419
#define INSN(NAME, op)                                                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1420
  void NAME(Register Rd, Register Rn, Register Rm,                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1421
           ext::operation option, int amount = 0) {                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1422
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1423
    zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0);                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1424
    add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1425
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1426
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1427
  void add_sub_extended_reg(unsigned op, unsigned decode,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1428
    Register Rd, Register Rn, Register Rm,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1429
    unsigned opt, ext::operation option, unsigned imm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1430
    guarantee(imm <= 4, "shift amount must be < 4");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1431
    f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1432
    f(option, 15, 13), f(imm, 12, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1433
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1434
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1435
  INSN(addw, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1436
  INSN(subw, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1437
  INSN(add, 0b100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1438
  INSN(sub, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1439
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1440
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1441
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1442
#define INSN(NAME, op)                                                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1443
  void NAME(Register Rd, Register Rn, Register Rm,                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1444
           ext::operation option, int amount = 0) {                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1445
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1446
    zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0);                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1447
    add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1448
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1449
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1450
  INSN(addsw, 0b001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1451
  INSN(subsw, 0b011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1452
  INSN(adds, 0b101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1453
  INSN(subs, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1454
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1455
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1456
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1457
  // Aliases for short forms of add and sub
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1458
#define INSN(NAME)                                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1459
  void NAME(Register Rd, Register Rn, Register Rm) {    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1460
    if (Rd == sp || Rn == sp)                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1461
      NAME(Rd, Rn, Rm, ext::uxtx);                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1462
    else                                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1463
      NAME(Rd, Rn, Rm, LSL);                            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1464
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1465
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1466
  INSN(addw);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1467
  INSN(subw);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1468
  INSN(add);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1469
  INSN(sub);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1470
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1471
  INSN(addsw);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1472
  INSN(subsw);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1473
  INSN(adds);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1474
  INSN(subs);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1475
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1476
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1477
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1478
  // Add/subtract (with carry)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1479
  void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1480
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1481
    f(op, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1482
    f(0b11010000, 28, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1483
    f(0b000000, 15, 10);
30225
e9722ea461d4 8077615: AARCH64: Add C2 intrinsic for BigInteger::multiplyToLen() method
aph
parents: 29183
diff changeset
  1484
    zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1485
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1486
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1487
  #define INSN(NAME, op)                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1488
    void NAME(Register Rd, Register Rn, Register Rm) {  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1489
      add_sub_carry(op, Rd, Rn, Rm);                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1490
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1491
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1492
  INSN(adcw, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1493
  INSN(adcsw, 0b001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1494
  INSN(sbcw, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1495
  INSN(sbcsw, 0b011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1496
  INSN(adc, 0b100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1497
  INSN(adcs, 0b101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1498
  INSN(sbc,0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1499
  INSN(sbcs, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1500
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1501
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1502
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1503
  // Conditional compare (both kinds)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1504
  void conditional_compare(unsigned op, int o2, int o3,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1505
                           Register Rn, unsigned imm5, unsigned nzcv,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1506
                           unsigned cond) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1507
    f(op, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1508
    f(0b11010010, 28, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1509
    f(cond, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1510
    f(o2, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1511
    f(o3, 4);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1512
    f(nzcv, 3, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1513
    f(imm5, 20, 16), rf(Rn, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1514
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1515
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1516
#define INSN(NAME, op)                                                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1517
  void NAME(Register Rn, Register Rm, int imm, Condition cond) {        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1518
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1519
    f(0, 11);                                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1520
    conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond);        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1521
  }                                                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1522
                                                                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1523
  void NAME(Register Rn, int imm5, int imm, Condition cond) {   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1524
    starti;                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1525
    f(1, 11);                                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1526
    conditional_compare(op, 0, 0, Rn, imm5, imm, cond);                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1527
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1528
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1529
  INSN(ccmnw, 0b001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1530
  INSN(ccmpw, 0b011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1531
  INSN(ccmn, 0b101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1532
  INSN(ccmp, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1533
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1534
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1535
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1536
  // Conditional select
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1537
  void conditional_select(unsigned op, unsigned op2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1538
                          Register Rd, Register Rn, Register Rm,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1539
                          unsigned cond) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1540
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1541
    f(op, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1542
    f(0b11010100, 28, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1543
    f(cond, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1544
    f(op2, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1545
    zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1546
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1547
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1548
#define INSN(NAME, op, op2)                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1549
  void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1550
    conditional_select(op, op2, Rd, Rn, Rm, cond);                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1551
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1552
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1553
  INSN(cselw, 0b000, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1554
  INSN(csincw, 0b000, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1555
  INSN(csinvw, 0b010, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1556
  INSN(csnegw, 0b010, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1557
  INSN(csel, 0b100, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1558
  INSN(csinc, 0b100, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1559
  INSN(csinv, 0b110, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1560
  INSN(csneg, 0b110, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1561
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1562
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1563
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1564
  // Data processing
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1565
  void data_processing(unsigned op29, unsigned opcode,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1566
                       Register Rd, Register Rn) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1567
    f(op29, 31, 29), f(0b11010110, 28, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1568
    f(opcode, 15, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1569
    rf(Rn, 5), rf(Rd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1570
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1571
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1572
  // (1 source)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1573
#define INSN(NAME, op29, opcode2, opcode)       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1574
  void NAME(Register Rd, Register Rn) {         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1575
    starti;                                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1576
    f(opcode2, 20, 16);                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1577
    data_processing(op29, opcode, Rd, Rn);      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1578
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1579
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1580
  INSN(rbitw,  0b010, 0b00000, 0b00000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1581
  INSN(rev16w, 0b010, 0b00000, 0b00001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1582
  INSN(revw,   0b010, 0b00000, 0b00010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1583
  INSN(clzw,   0b010, 0b00000, 0b00100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1584
  INSN(clsw,   0b010, 0b00000, 0b00101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1585
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1586
  INSN(rbit,   0b110, 0b00000, 0b00000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1587
  INSN(rev16,  0b110, 0b00000, 0b00001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1588
  INSN(rev32,  0b110, 0b00000, 0b00010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1589
  INSN(rev,    0b110, 0b00000, 0b00011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1590
  INSN(clz,    0b110, 0b00000, 0b00100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1591
  INSN(cls,    0b110, 0b00000, 0b00101);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1592
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1593
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1594
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1595
  // (2 sources)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1596
#define INSN(NAME, op29, opcode)                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1597
  void NAME(Register Rd, Register Rn, Register Rm) {    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1598
    starti;                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1599
    rf(Rm, 16);                                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1600
    data_processing(op29, opcode, Rd, Rn);              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1601
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1602
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1603
  INSN(udivw, 0b000, 0b000010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1604
  INSN(sdivw, 0b000, 0b000011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1605
  INSN(lslvw, 0b000, 0b001000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1606
  INSN(lsrvw, 0b000, 0b001001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1607
  INSN(asrvw, 0b000, 0b001010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1608
  INSN(rorvw, 0b000, 0b001011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1609
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1610
  INSN(udiv, 0b100, 0b000010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1611
  INSN(sdiv, 0b100, 0b000011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1612
  INSN(lslv, 0b100, 0b001000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1613
  INSN(lsrv, 0b100, 0b001001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1614
  INSN(asrv, 0b100, 0b001010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1615
  INSN(rorv, 0b100, 0b001011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1616
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1617
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1618
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1619
  // (3 sources)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1620
  void data_processing(unsigned op54, unsigned op31, unsigned o0,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1621
                       Register Rd, Register Rn, Register Rm,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1622
                       Register Ra) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1623
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1624
    f(op54, 31, 29), f(0b11011, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1625
    f(op31, 23, 21), f(o0, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1626
    zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1627
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1628
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1629
#define INSN(NAME, op54, op31, o0)                                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1630
  void NAME(Register Rd, Register Rn, Register Rm, Register Ra) {       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1631
    data_processing(op54, op31, o0, Rd, Rn, Rm, Ra);                    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1632
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1633
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1634
  INSN(maddw, 0b000, 0b000, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1635
  INSN(msubw, 0b000, 0b000, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1636
  INSN(madd, 0b100, 0b000, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1637
  INSN(msub, 0b100, 0b000, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1638
  INSN(smaddl, 0b100, 0b001, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1639
  INSN(smsubl, 0b100, 0b001, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1640
  INSN(umaddl, 0b100, 0b101, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1641
  INSN(umsubl, 0b100, 0b101, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1642
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1643
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1644
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1645
#define INSN(NAME, op54, op31, o0)                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1646
  void NAME(Register Rd, Register Rn, Register Rm) {    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1647
    data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31);  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1648
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1649
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1650
  INSN(smulh, 0b100, 0b010, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1651
  INSN(umulh, 0b100, 0b110, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1652
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1653
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1654
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1655
  // Floating-point data-processing (1 source)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1656
  void data_processing(unsigned op31, unsigned type, unsigned opcode,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1657
                       FloatRegister Vd, FloatRegister Vn) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1658
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1659
    f(op31, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1660
    f(0b11110, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1661
    f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1662
    rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1663
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1664
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1665
#define INSN(NAME, op31, type, opcode)                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1666
  void NAME(FloatRegister Vd, FloatRegister Vn) {       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1667
    data_processing(op31, type, opcode, Vd, Vn);        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1668
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1669
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1670
private:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1671
  INSN(i_fmovs, 0b000, 0b00, 0b000000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1672
public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1673
  INSN(fabss, 0b000, 0b00, 0b000001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1674
  INSN(fnegs, 0b000, 0b00, 0b000010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1675
  INSN(fsqrts, 0b000, 0b00, 0b000011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1676
  INSN(fcvts, 0b000, 0b00, 0b000101);   // Single-precision to double-precision
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1677
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1678
private:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1679
  INSN(i_fmovd, 0b000, 0b01, 0b000000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1680
public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1681
  INSN(fabsd, 0b000, 0b01, 0b000001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1682
  INSN(fnegd, 0b000, 0b01, 0b000010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1683
  INSN(fsqrtd, 0b000, 0b01, 0b000011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1684
  INSN(fcvtd, 0b000, 0b01, 0b000100);   // Double-precision to single-precision
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1685
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1686
  void fmovd(FloatRegister Vd, FloatRegister Vn) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1687
    assert(Vd != Vn, "should be");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1688
    i_fmovd(Vd, Vn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1689
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1690
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1691
  void fmovs(FloatRegister Vd, FloatRegister Vn) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1692
    assert(Vd != Vn, "should be");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1693
    i_fmovs(Vd, Vn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1694
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1695
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1696
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1697
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1698
  // Floating-point data-processing (2 source)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1699
  void data_processing(unsigned op31, unsigned type, unsigned opcode,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1700
                       FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1701
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1702
    f(op31, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1703
    f(0b11110, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1704
    f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1705
    rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1706
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1707
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1708
#define INSN(NAME, op31, type, opcode)                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1709
  void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1710
    data_processing(op31, type, opcode, Vd, Vn, Vm);    \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1711
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1712
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1713
  INSN(fmuls, 0b000, 0b00, 0b0000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1714
  INSN(fdivs, 0b000, 0b00, 0b0001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1715
  INSN(fadds, 0b000, 0b00, 0b0010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1716
  INSN(fsubs, 0b000, 0b00, 0b0011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1717
  INSN(fnmuls, 0b000, 0b00, 0b1000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1718
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1719
  INSN(fmuld, 0b000, 0b01, 0b0000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1720
  INSN(fdivd, 0b000, 0b01, 0b0001);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1721
  INSN(faddd, 0b000, 0b01, 0b0010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1722
  INSN(fsubd, 0b000, 0b01, 0b0011);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1723
  INSN(fnmuld, 0b000, 0b01, 0b1000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1724
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1725
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1726
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1727
   // Floating-point data-processing (3 source)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1728
  void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1729
                       FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1730
                       FloatRegister Va) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1731
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1732
    f(op31, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1733
    f(0b11111, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1734
    f(type, 23, 22), f(o1, 21), f(o0, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1735
    rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1736
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1737
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1738
#define INSN(NAME, op31, type, o1, o0)                                  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1739
  void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1740
            FloatRegister Va) {                                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1741
    data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1742
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1743
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1744
  INSN(fmadds, 0b000, 0b00, 0, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1745
  INSN(fmsubs, 0b000, 0b00, 0, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1746
  INSN(fnmadds, 0b000, 0b00, 1, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1747
  INSN(fnmsubs, 0b000, 0b00, 1, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1748
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1749
  INSN(fmaddd, 0b000, 0b01, 0, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1750
  INSN(fmsubd, 0b000, 0b01, 0, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1751
  INSN(fnmaddd, 0b000, 0b01, 1, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1752
  INSN(fnmsub, 0b000, 0b01, 1, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1753
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1754
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1755
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1756
   // Floating-point conditional select
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1757
  void fp_conditional_select(unsigned op31, unsigned type,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1758
                             unsigned op1, unsigned op2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1759
                             Condition cond, FloatRegister Vd,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1760
                             FloatRegister Vn, FloatRegister Vm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1761
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1762
    f(op31, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1763
    f(0b11110, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1764
    f(type, 23, 22);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1765
    f(op1, 21, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1766
    f(op2, 11, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1767
    f(cond, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1768
    rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1769
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1770
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1771
#define INSN(NAME, op31, type, op1, op2)                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1772
  void NAME(FloatRegister Vd, FloatRegister Vn,                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1773
            FloatRegister Vm, Condition cond) {                         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1774
    fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm);      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1775
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1776
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1777
  INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1778
  INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1779
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1780
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1781
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1782
   // Floating-point<->integer conversions
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1783
  void float_int_convert(unsigned op31, unsigned type,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1784
                         unsigned rmode, unsigned opcode,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1785
                         Register Rd, Register Rn) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1786
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1787
    f(op31, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1788
    f(0b11110, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1789
    f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1790
    f(opcode, 18, 16), f(0b000000, 15, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1791
    zrf(Rn, 5), zrf(Rd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1792
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1793
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1794
#define INSN(NAME, op31, type, rmode, opcode)                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1795
  void NAME(Register Rd, FloatRegister Vn) {                            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1796
    float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn);     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1797
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1798
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1799
  INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1800
  INSN(fcvtzs,  0b100, 0b00, 0b11, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1801
  INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1802
  INSN(fcvtzd,  0b100, 0b01, 0b11, 0b000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1803
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1804
  INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1805
  INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1806
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1807
  // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1808
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1809
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1810
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1811
#define INSN(NAME, op31, type, rmode, opcode)                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1812
  void NAME(FloatRegister Vd, Register Rn) {                            \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1813
    float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn);     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1814
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1815
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1816
  INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1817
  INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1818
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1819
  INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1820
  INSN(scvtfs,  0b100, 0b00, 0b00, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1821
  INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1822
  INSN(scvtfd,  0b100, 0b01, 0b00, 0b010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1823
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1824
  // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1825
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1826
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1827
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1828
  // Floating-point compare
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1829
  void float_compare(unsigned op31, unsigned type,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1830
                     unsigned op, unsigned op2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1831
                     FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1832
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1833
    f(op31, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1834
    f(0b11110, 28, 24);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1835
    f(type, 23, 22), f(1, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1836
    f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1837
    rf(Vn, 5), rf(Vm, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1838
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1839
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1840
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1841
#define INSN(NAME, op31, type, op, op2)                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1842
  void NAME(FloatRegister Vn, FloatRegister Vm) {       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1843
    float_compare(op31, type, op, op2, Vn, Vm);         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1844
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1845
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1846
#define INSN1(NAME, op31, type, op, op2)        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1847
  void NAME(FloatRegister Vn, double d) {       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1848
    assert_cond(d == 0.0);                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1849
    float_compare(op31, type, op, op2, Vn);     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1850
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1851
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1852
  INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1853
  INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1854
  // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1855
  // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1856
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1857
  INSN(fcmpd, 0b000,   0b01, 0b00, 0b00000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1858
  INSN1(fcmpd, 0b000,  0b01, 0b00, 0b01000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1859
  // INSN(fcmped, 0b000,  0b01, 0b00, 0b10000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1860
  // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1861
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1862
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1863
#undef INSN1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1864
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1865
  // Floating-point Move (immediate)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1866
private:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1867
  unsigned pack(double value);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1868
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1869
  void fmov_imm(FloatRegister Vn, double value, unsigned size) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1870
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1871
    f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1872
    f(pack(value), 20, 13), f(0b10000000, 12, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1873
    rf(Vn, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1874
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1875
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1876
public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1877
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1878
  void fmovs(FloatRegister Vn, double value) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1879
    if (value)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1880
      fmov_imm(Vn, value, 0b00);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1881
    else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1882
      fmovs(Vn, zr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1883
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1884
  void fmovd(FloatRegister Vn, double value) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1885
    if (value)
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1886
      fmov_imm(Vn, value, 0b01);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1887
    else
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1888
      fmovd(Vn, zr);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1889
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1890
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1891
/* SIMD extensions
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1892
 *
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1893
 * We just use FloatRegister in the following. They are exactly the same
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1894
 * as SIMD registers.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1895
 */
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1896
 public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1897
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1898
  enum SIMD_Arrangement {
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  1899
       T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1900
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1901
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1902
  enum SIMD_RegVariant {
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1903
       B, H, S, D, Q
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1904
  };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1905
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1906
#define INSN(NAME, op)                                            \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1907
  void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) {   \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1908
    ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1909
  }                                                                      \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1910
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1911
  INSN(ldr, 1);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1912
  INSN(str, 0);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1913
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  1914
#undef INSN
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1915
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1916
 private:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1917
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1918
  void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1919
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1920
    f(0,31), f((int)T & 1, 30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1921
    f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1922
    f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1923
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1924
  void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1925
             int imm, int op1, int op2) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1926
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1927
    f(0,31), f((int)T & 1, 30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1928
    f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1929
    f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1930
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1931
  void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1932
             Register Xm, int op1, int op2) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1933
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1934
    f(0,31), f((int)T & 1, 30);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1935
    f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1936
    f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1937
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1938
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1939
 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1940
   switch (a.getMode()) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1941
   case Address::base_plus_offset:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1942
     guarantee(a.offset() == 0, "no offset allowed here");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1943
     ld_st(Vt, T, a.base(), op1, op2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1944
     break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1945
   case Address::post:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1946
     ld_st(Vt, T, a.base(), a.offset(), op1, op2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1947
     break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1948
   case Address::base_plus_offset_reg:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1949
     ld_st(Vt, T, a.base(), a.index(), op1, op2);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1950
     break;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1951
   default:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1952
     ShouldNotReachHere();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1953
   }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1954
 }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1955
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1956
 public:
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1957
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1958
#define INSN1(NAME, op1, op2)                                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1959
  void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) {   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1960
   ld_st(Vt, T, a, op1, op2);                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1961
 }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1962
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1963
#define INSN2(NAME, op1, op2)                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1964
  void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1965
    assert(Vt->successor() == Vt2, "Registers must be ordered");        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1966
    ld_st(Vt, T, a, op1, op2);                                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1967
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1968
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1969
#define INSN3(NAME, op1, op2)                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1970
  void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1971
            SIMD_Arrangement T, const Address &a) {                     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1972
    assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3,           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1973
           "Registers must be ordered");                                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1974
    ld_st(Vt, T, a, op1, op2);                                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1975
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1976
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1977
#define INSN4(NAME, op1, op2)                                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1978
  void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1979
            FloatRegister Vt4, SIMD_Arrangement T, const Address &a) {  \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1980
    assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1981
           Vt3->successor() == Vt4, "Registers must be ordered");       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1982
    ld_st(Vt, T, a, op1, op2);                                          \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1983
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1984
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1985
  INSN1(ld1,  0b001100010, 0b0111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1986
  INSN2(ld1,  0b001100010, 0b1010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1987
  INSN3(ld1,  0b001100010, 0b0110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1988
  INSN4(ld1,  0b001100010, 0b0010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1989
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1990
  INSN2(ld2,  0b001100010, 0b1000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1991
  INSN3(ld3,  0b001100010, 0b0100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1992
  INSN4(ld4,  0b001100010, 0b0000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1993
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1994
  INSN1(st1,  0b001100000, 0b0111);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1995
  INSN2(st1,  0b001100000, 0b1010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1996
  INSN3(st1,  0b001100000, 0b0110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1997
  INSN4(st1,  0b001100000, 0b0010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1998
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  1999
  INSN2(st2,  0b001100000, 0b1000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2000
  INSN3(st3,  0b001100000, 0b0100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2001
  INSN4(st4,  0b001100000, 0b0000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2002
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2003
  INSN1(ld1r, 0b001101010, 0b1100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2004
  INSN2(ld2r, 0b001101011, 0b1100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2005
  INSN3(ld3r, 0b001101010, 0b1110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2006
  INSN4(ld4r, 0b001101011, 0b1110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2007
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2008
#undef INSN1
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2009
#undef INSN2
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2010
#undef INSN3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2011
#undef INSN4
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2012
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2013
#define INSN(NAME, opc)                                                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2014
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2015
    starti;                                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2016
    assert(T == T8B || T == T16B, "must be T8B or T16B");                               \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2017
    f(0, 31), f((int)T & 1, 30), f(opc, 29, 21);                                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2018
    rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);                              \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2019
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2020
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2021
  INSN(eor,  0b101110001);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2022
  INSN(orr,  0b001110101);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2023
  INSN(andr, 0b001110001);
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2024
  INSN(bic,  0b001110011);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2025
  INSN(bif,  0b101110111);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2026
  INSN(bit,  0b101110101);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2027
  INSN(bsl,  0b101110011);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2028
  INSN(orn,  0b001110111);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2029
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2030
#undef INSN
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2031
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2032
#define INSN(NAME, opc, opc2)                                                                 \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2033
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2034
    starti;                                                                             \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2035
    f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2036
    f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10);                      \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2037
    rf(Vn, 5), rf(Vd, 0);                                                               \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2038
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2039
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2040
  INSN(addv, 0, 0b100001);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2041
  INSN(subv, 1, 0b100001);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2042
  INSN(mulv, 0, 0b100111);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2043
  INSN(sshl, 0, 0b010001);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2044
  INSN(ushl, 1, 0b010001);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2045
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2046
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2047
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2048
#define INSN(NAME, opc, opc2) \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2049
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2050
    starti;                                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2051
    f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2052
    f((int)T >> 1, 23, 22), f(opc2, 21, 10);                                            \
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2053
    rf(Vn, 5), rf(Vd, 0);                                                               \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2054
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2055
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2056
  INSN(absr,  0, 0b100000101110);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2057
  INSN(negr,  1, 0b100000101110);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2058
  INSN(notr,  1, 0b100000010110);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2059
  INSN(addv,  0, 0b110001101110);
31517
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31227
diff changeset
  2060
  INSN(cls,   0, 0b100000010010);
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31227
diff changeset
  2061
  INSN(clz,   1, 0b100000010010);
f1dc80fd7748 8129426: aarch64: add support for PopCount in C2
enevill
parents: 31227
diff changeset
  2062
  INSN(cnt,   0, 0b100000010110);
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2063
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2064
#undef INSN
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2065
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2066
#define INSN(NAME, op0, cmode0) \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2067
  void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) {   \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2068
    unsigned cmode = cmode0;                                                           \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2069
    unsigned op = op0;                                                                 \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2070
    starti;                                                                            \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2071
    assert(lsl == 0 ||                                                                 \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2072
           ((T == T4H || T == T8H) && lsl == 8) ||                                     \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2073
           ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift");             \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2074
    cmode |= lsl >> 2;                                                                 \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2075
    if (T == T4H || T == T8H) cmode |= 0b1000;                                         \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2076
    if (!(T == T4H || T == T8H || T == T2S || T == T4S)) {                             \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2077
      assert(op == 0 && cmode0 == 0, "must be MOVI");                                  \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2078
      cmode = 0b1110;                                                                  \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2079
      if (T == T1D || T == T2D) op = 1;                                                \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2080
    }                                                                                  \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2081
    f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19);                   \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2082
    f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5);  \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2083
    rf(Vd, 0);                                                                         \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2084
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2085
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2086
  INSN(movi, 0, 0);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2087
  INSN(orri, 0, 1);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2088
  INSN(mvni, 1, 0);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2089
  INSN(bici, 1, 1);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2090
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2091
#undef INSN
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2092
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2093
#define INSN(NAME, op1, op2, op3) \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2094
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2095
    starti;                                                                             \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2096
    assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                    \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2097
    f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23);            \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2098
    f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0);    \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2099
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2100
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2101
  INSN(fadd, 0, 0, 0b110101);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2102
  INSN(fdiv, 1, 0, 0b111111);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2103
  INSN(fmul, 1, 0, 0b110111);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2104
  INSN(fsub, 0, 1, 0b110101);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2105
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2106
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2107
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2108
#define INSN(NAME, opc)                                                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2109
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2110
    starti;                                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2111
    assert(T == T4S, "arrangement must be T4S");                                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2112
    f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2113
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2114
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2115
  INSN(sha1c,     0b000000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2116
  INSN(sha1m,     0b001000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2117
  INSN(sha1p,     0b000100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2118
  INSN(sha1su0,   0b001100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2119
  INSN(sha256h2,  0b010100);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2120
  INSN(sha256h,   0b010000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2121
  INSN(sha256su1, 0b011000);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2122
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2123
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2124
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2125
#define INSN(NAME, opc)                                                                 \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2126
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2127
    starti;                                                                             \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2128
    assert(T == T4S, "arrangement must be T4S");                                        \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2129
    f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);                \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2130
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2131
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2132
  INSN(sha1h,     0b000010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2133
  INSN(sha1su1,   0b000110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2134
  INSN(sha256su0, 0b001010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2135
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2136
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2137
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2138
#define INSN(NAME, opc)                           \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2139
  void NAME(FloatRegister Vd, FloatRegister Vn) { \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2140
    starti;                                       \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2141
    f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);         \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2142
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2143
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2144
  INSN(aese, 0b0100111000101000010010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2145
  INSN(aesd, 0b0100111000101000010110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2146
  INSN(aesmc, 0b0100111000101000011010);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2147
  INSN(aesimc, 0b0100111000101000011110);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2148
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2149
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2150
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2151
  void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2152
    starti;
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2153
    assert(T != Q, "invalid register variant");
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2154
    f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2155
    f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2156
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2157
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2158
  void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2159
    starti;
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2160
    f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2161
    f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2162
    rf(Vn, 5), rf(Rd, 0);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2163
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2164
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2165
#define INSN(NAME, opc, opc2) \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2166
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){         \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2167
    starti;                                                                             \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2168
    /* The encodings for the immh:immb fields (bits 22:16) are                          \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2169
     *   0001 xxx       8B/16B, shift = xxx                                             \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2170
     *   001x xxx       4H/8H,  shift = xxxx                                            \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2171
     *   01xx xxx       2S/4S,  shift = xxxxx                                           \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2172
     *   1xxx xxx       1D/2D,  shift = xxxxxx (1D is RESERVED)                         \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2173
     */                                                                                 \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2174
    assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value");                           \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2175
    f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23),                            \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2176
    f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0);          \
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2177
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2178
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2179
  INSN(shl,  0, 0b010101);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2180
  INSN(sshr, 0, 0b000001);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2181
  INSN(ushr, 1, 0b000001);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2182
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2183
#undef INSN
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2184
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2185
  void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2186
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2187
    /* The encodings for the immh:immb fields (bits 22:16) are
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2188
     *   0001 xxx       8H, 8B/16b shift = xxx
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2189
     *   001x xxx       4S, 4H/8H  shift = xxxx
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2190
     *   01xx xxx       2D, 2S/4S  shift = xxxxx
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2191
     *   1xxx xxx       RESERVED
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2192
     */
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2193
    assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2194
    assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2195
    f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2196
    f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2197
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2198
  void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2199
    ushll(Vd, Ta, Vn, Tb, shift);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2200
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2201
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2202
  void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,  SIMD_Arrangement T, int op = 0){
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2203
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2204
    f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2205
    rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2206
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2207
  void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,  SIMD_Arrangement T){
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2208
    uzp1(Vd, Vn, Vm, T, 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2209
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2210
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2211
  // Move from general purpose register
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2212
  //   mov  Vd.T[index], Rn
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2213
  void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2214
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2215
    f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2216
    f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2217
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2218
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2219
  // Move to general purpose register
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2220
  //   mov  Rd, Vn.T[index]
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2221
  void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2222
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2223
    f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2224
    f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2225
    f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2226
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2227
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2228
  void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2229
    starti;
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2230
    assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2231
           (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2232
    int size = (Ta == T1Q) ? 0b11 : 0b00;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2233
    f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2234
    f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2235
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2236
  void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2237
    assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2238
    pmull(Vd, Ta, Vn, Vm, Tb);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2239
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2240
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2241
  void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2242
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2243
    int size_b = (int)Tb >> 1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2244
    int size_a = (int)Ta >> 1;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2245
    assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2246
    f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2247
    f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2248
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2249
30890
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2250
  void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2251
  {
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2252
    starti;
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2253
    assert(T != T1D, "reserved encoding");
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2254
    f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2255
    f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2256
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2257
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2258
  void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2259
  {
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2260
    starti;
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2261
    assert(T != T1D, "reserved encoding");
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2262
    f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2263
    f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2264
    f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2265
  }
dbbc65d3cd40 8079565: aarch64: Add vectorization support for aarch64
enevill
parents: 30225
diff changeset
  2266
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2267
  // CRC32 instructions
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2268
#define INSN(NAME, c, sf, sz)                                             \
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2269
  void NAME(Register Rd, Register Rn, Register Rm) {                      \
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2270
    starti;                                                               \
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2271
    f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12);       \
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2272
    f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                      \
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2273
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2274
31591
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2275
  INSN(crc32b,  0, 0, 0b00);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2276
  INSN(crc32h,  0, 0, 0b01);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2277
  INSN(crc32w,  0, 0, 0b10);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2278
  INSN(crc32x,  0, 1, 0b11);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2279
  INSN(crc32cb, 1, 0, 0b00);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2280
  INSN(crc32ch, 1, 0, 0b01);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2281
  INSN(crc32cw, 1, 0, 0b10);
82134a118aea 8130687: aarch64: add support for hardware crc32c
enevill
parents: 31517
diff changeset
  2282
  INSN(crc32cx, 1, 1, 0b11);
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2283
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2284
#undef INSN
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2285
31961
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2286
  // Table vector lookup
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2287
#define INSN(NAME, op)                                                                                       \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2288
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) {  \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2289
    starti;                                                                                                  \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2290
    assert(T == T8B || T == T16B, "invalid arrangement");                                                    \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2291
    assert(0 < registers && registers <= 4, "invalid number of registers");                                  \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2292
    f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15);                               \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2293
    f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0);                               \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2294
  }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2295
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2296
  INSN(tbl, 0);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2297
  INSN(tbx, 1);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2298
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2299
#undef INSN
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2300
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2301
#define INSN(NAME, U, opcode)                                                       \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2302
  void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2303
       starti;                                                                      \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2304
       assert((ASSERTION), MSG);                                                    \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2305
       f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2306
       f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12);             \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2307
       f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                                       \
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2308
 }
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2309
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2310
#define MSG "invalid arrangement"
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2311
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2312
#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2313
  INSN(rev64, 0, 0b00000);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2314
#undef ASSERTION
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2315
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2316
#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2317
  INSN(rev32, 1, 0b00000);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2318
#undef ASSERTION
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2319
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2320
#define ASSERTION (T == T8B || T == T16B)
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2321
  INSN(rev16, 0, 0b00001);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2322
#undef ASSERTION
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2323
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2324
#undef MSG
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2325
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2326
#undef INSN
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2327
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2328
void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2329
  {
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2330
    starti;
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2331
    assert(T == T8B || T == T16B, "invalid arrangement");
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2332
    assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2333
    f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2334
    rf(Vm, 16), f(0, 15), f(index, 14, 11);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2335
    f(0, 10), rf(Vn, 5), rf(Vd, 0);
70adcff5840c 8131062: aarch64: add support for GHASH acceleration
enevill
parents: 31863
diff changeset
  2336
  }
29183
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2337
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2338
/* Simulator extensions to the ISA
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2339
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2340
   haltsim
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2341
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2342
   takes no arguments, causes the sim to enter a debug break and then
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2343
   return from the simulator run() call with STATUS_HALT? The linking
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2344
   code will call fatal() when it sees STATUS_HALT.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2345
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2346
   blrt Xn, Wm
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2347
   blrt Xn, #gpargs, #fpargs, #type
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2348
   Xn holds the 64 bit x86 branch_address
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2349
   call format is encoded either as immediate data in the call
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2350
   or in register Wm. In the latter case
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2351
     Wm[13..6] = #gpargs,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2352
     Wm[5..2] = #fpargs,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2353
     Wm[1,0] = #type
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2354
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2355
   calls the x86 code address 'branch_address' supplied in Xn passing
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2356
   arguments taken from the general and floating point registers according
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2357
   to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2358
   or v0 according to the the return type #type' where
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2359
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2360
   address branch_address;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2361
   uimm4 gpargs;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2362
   uimm4 fpargs;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2363
   enum ReturnType type;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2364
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2365
   enum ReturnType
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2366
     {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2367
       void_ret = 0,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2368
       int_ret = 1,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2369
       long_ret = 1,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2370
       obj_ret = 1, // i.e. same as long
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2371
       float_ret = 2,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2372
       double_ret = 3
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2373
     }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2374
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2375
   notify
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2376
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2377
   notifies the simulator of a transfer of control. instr[14:0]
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2378
   identifies the type of change of control.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2379
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2380
   0 ==> initial entry to a method.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2381
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2382
   1 ==> return into a method from a submethod call.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2383
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2384
   2 ==> exit out of Java method code.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2385
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2386
   3 ==> start execution for a new bytecode.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2387
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2388
   in cases 1 and 2 the simulator is expected to use a JVM callback to
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2389
   identify the name of the specific method being executed. in case 4
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2390
   the simulator is expected to use a JVM callback to identify the
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2391
   bytecode index.
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2392
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2393
   Instruction encodings
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2394
   ---------------------
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2395
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2396
   These are encoded in the space with instr[28:25] = 00 which is
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2397
   unallocated. Encodings are
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2398
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2399
                     10987654321098765432109876543210
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2400
   PSEUDO_HALT   = 0x11100000000000000000000000000000
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2401
   PSEUDO_BLRT  = 0x11000000000000000_______________
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2402
   PSEUDO_BLRTR = 0x1100000000000000100000__________
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2403
   PSEUDO_NOTIFY = 0x10100000000000000_______________
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2404
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2405
   instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2406
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2407
   for BLRT
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2408
     instr[14,11] = #gpargs, instr[10,7] = #fpargs
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2409
     instr[6,5] = #type, instr[4,0] = Rn
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2410
   for BLRTR
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2411
     instr[9,5] = Rm, instr[4,0] = Rn
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2412
   for NOTIFY
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2413
     instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2414
*/
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2415
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2416
  enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2417
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2418
  virtual void notify(int type) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2419
    if (UseBuiltinSim) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2420
      starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2421
      //  109
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2422
      f(0b101, 31, 29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2423
      //  87654321098765
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2424
      f(0b00000000000000, 28, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2425
      f(type, 14, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2426
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2427
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2428
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2429
  void blrt(Register Rn, int gpargs, int fpargs, int type) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2430
    if (UseBuiltinSim) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2431
      starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2432
      f(0b110, 31 ,29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2433
      f(0b00, 28, 25);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2434
      //  4321098765
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2435
      f(0b0000000000, 24, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2436
      f(gpargs, 14, 11);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2437
      f(fpargs, 10, 7);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2438
      f(type, 6, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2439
      rf(Rn, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2440
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2441
      blr(Rn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2442
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2443
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2444
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2445
  void blrt(Register Rn, Register Rm) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2446
    if (UseBuiltinSim) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2447
      starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2448
      f(0b110, 31 ,29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2449
      f(0b00, 28, 25);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2450
      //  4321098765
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2451
      f(0b0000000001, 24, 15);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2452
      //  43210
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2453
      f(0b00000, 14, 10);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2454
      rf(Rm, 5);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2455
      rf(Rn, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2456
    } else {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2457
      blr(Rn);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2458
    }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2459
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2460
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2461
  void haltsim() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2462
    starti;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2463
    f(0b111, 31 ,29);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2464
    f(0b00, 28, 27);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2465
    //  654321098765432109876543210
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2466
    f(0b000000000000000000000000000, 26, 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2467
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2468
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2469
  Assembler(CodeBuffer* code) : AbstractAssembler(code) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2470
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2471
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2472
  virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2473
                                                Register tmp,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2474
                                                int offset) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2475
    ShouldNotCallThis();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2476
    return RegisterOrConstant();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2477
  }
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2478
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2479
  // Stack overflow checking
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2480
  virtual void bang_stack_with_offset(int offset);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2481
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2482
  static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2483
  static bool operand_valid_for_add_sub_immediate(long imm);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2484
  static bool operand_valid_for_float_immediate(double imm);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2485
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2486
  void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2487
  void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2488
};
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2489
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2490
inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2491
                                             Assembler::Membar_mask_bits b) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2492
  return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2493
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2494
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2495
Instruction_aarch64::~Instruction_aarch64() {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2496
  assem->emit();
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2497
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2498
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2499
#undef starti
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2500
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2501
// Invert a condition
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2502
inline const Assembler::Condition operator~(const Assembler::Condition cond) {
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2503
  return Assembler::Condition(int(cond) ^ 1);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2504
}
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2505
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2506
class BiasedLockingCounters;
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2507
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2508
extern "C" void das(uint64_t start, int len);
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2509
0cc8699f7372 8068054: AARCH64: Assembler interpreter, shared runtime
aph
parents:
diff changeset
  2510
#endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP