author | dholmes |
Mon, 30 Apr 2018 20:29:19 -0400 | |
changeset 49933 | c63bdf53a1a7 |
parent 49906 | 4bb58f644e4e |
child 50153 | 9010b580d8a9 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved. |
1 | 3 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
7397 | 25 |
#include "precompiled.hpp" |
26 |
#include "c1/c1_Compilation.hpp" |
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27 |
#include "c1/c1_FrameMap.hpp" |
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28 |
#include "c1/c1_Instruction.hpp" |
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#include "c1/c1_LIRAssembler.hpp" |
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30 |
#include "c1/c1_LIRGenerator.hpp" |
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31 |
#include "c1/c1_Runtime1.hpp" |
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#include "c1/c1_ValueStack.hpp" |
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33 |
#include "ci/ciArray.hpp" |
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34 |
#include "ci/ciObjArrayKlass.hpp" |
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35 |
#include "ci/ciTypeArrayKlass.hpp" |
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49906 | 36 |
#include "gc/shared/c1/barrierSetC1.hpp" |
7397 | 37 |
#include "runtime/sharedRuntime.hpp" |
38 |
#include "runtime/stubRoutines.hpp" |
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#include "vmreg_x86.inline.hpp" |
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|
41 |
#ifdef ASSERT |
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42 |
#define __ gen()->lir(__FILE__, __LINE__)-> |
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43 |
#else |
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44 |
#define __ gen()->lir()-> |
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45 |
#endif |
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46 |
||
47 |
// Item will be loaded into a byte register; Intel only |
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48 |
void LIRItem::load_byte_item() { |
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49 |
load_item(); |
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LIR_Opr res = result(); |
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51 |
||
52 |
if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) { |
|
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// make sure that it is a byte register |
|
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assert(!value()->type()->is_float() && !value()->type()->is_double(), |
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"can't load floats in byte register"); |
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LIR_Opr reg = _gen->rlock_byte(T_BYTE); |
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__ move(res, reg); |
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_result = reg; |
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} |
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} |
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void LIRItem::load_nonconstant() { |
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LIR_Opr r = value()->operand(); |
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if (r->is_constant()) { |
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_result = r; |
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} else { |
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load_item(); |
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} |
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} |
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||
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//-------------------------------------------------------------- |
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// LIRGenerator |
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//-------------------------------------------------------------- |
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LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::rax_oop_opr; } |
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LIR_Opr LIRGenerator::exceptionPcOpr() { return FrameMap::rdx_opr; } |
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LIR_Opr LIRGenerator::divInOpr() { return FrameMap::rax_opr; } |
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LIR_Opr LIRGenerator::divOutOpr() { return FrameMap::rax_opr; } |
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LIR_Opr LIRGenerator::remOutOpr() { return FrameMap::rdx_opr; } |
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LIR_Opr LIRGenerator::shiftCountOpr() { return FrameMap::rcx_opr; } |
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LIR_Opr LIRGenerator::syncLockOpr() { return new_register(T_INT); } |
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LIR_Opr LIRGenerator::syncTempOpr() { return FrameMap::rax_opr; } |
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LIR_Opr LIRGenerator::getThreadTemp() { return LIR_OprFact::illegalOpr; } |
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LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) { |
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LIR_Opr opr; |
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switch (type->tag()) { |
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case intTag: opr = FrameMap::rax_opr; break; |
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case objectTag: opr = FrameMap::rax_oop_opr; break; |
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case longTag: opr = FrameMap::long0_opr; break; |
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case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break; |
96 |
case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break; |
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case addressTag: |
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default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr; |
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} |
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102 |
assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch"); |
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return opr; |
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} |
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LIR_Opr LIRGenerator::rlock_byte(BasicType type) { |
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108 |
LIR_Opr reg = new_register(T_INT); |
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set_vreg_flag(reg, LIRGenerator::byte_reg); |
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return reg; |
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111 |
} |
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||
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//--------- loading items into registers -------------------------------- |
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// i486 instructions can inline constants |
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bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const { |
|
119 |
if (type == T_SHORT || type == T_CHAR) { |
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// there is no immediate move of word values in asembler_i486.?pp |
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return false; |
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122 |
} |
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Constant* c = v->as_Constant(); |
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if (c && c->state_before() == NULL) { |
1 | 125 |
// constants of any type can be stored directly, except for |
126 |
// unloaded object constants. |
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return true; |
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128 |
} |
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return false; |
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} |
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131 |
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bool LIRGenerator::can_inline_as_constant(Value v) const { |
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if (v->type()->tag() == longTag) return false; |
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return v->type()->tag() != objectTag || |
136 |
(v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object()); |
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} |
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138 |
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bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const { |
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if (c->type() == T_LONG) return false; |
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return c->type() != T_OBJECT || c->as_jobject() == NULL; |
143 |
} |
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LIR_Opr LIRGenerator::safepoint_poll_register() { |
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NOT_LP64( if (SafepointMechanism::uses_thread_local_poll()) { return new_register(T_ADDRESS); } ) |
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return LIR_OprFact::illegalOpr; |
149 |
} |
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150 |
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151 |
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152 |
LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index, |
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153 |
int shift, int disp, BasicType type) { |
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154 |
assert(base->is_register(), "must be"); |
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if (index->is_constant()) { |
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49906 | 156 |
LIR_Const *constant = index->as_constant_ptr(); |
157 |
#ifdef _LP64 |
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158 |
jlong c; |
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159 |
if (constant->type() == T_INT) { |
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160 |
c = (jlong(index->as_jint()) << shift) + disp; |
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} else { |
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assert(constant->type() == T_LONG, "should be"); |
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c = (index->as_jlong() << shift) + disp; |
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164 |
} |
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165 |
if ((jlong)((jint)c) == c) { |
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return new LIR_Address(base, (jint)c, type); |
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} else { |
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LIR_Opr tmp = new_register(T_LONG); |
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169 |
__ move(index, tmp); |
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170 |
return new LIR_Address(base, tmp, type); |
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171 |
} |
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172 |
#else |
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return new LIR_Address(base, |
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((intx)(constant->as_jint()) << shift) + disp, |
1 | 175 |
type); |
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#endif |
1 | 177 |
} else { |
178 |
return new LIR_Address(base, index, (LIR_Address::Scale)shift, disp, type); |
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179 |
} |
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180 |
} |
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181 |
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183 |
LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr, |
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49906 | 184 |
BasicType type) { |
1 | 185 |
int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type); |
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187 |
LIR_Address* addr; |
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188 |
if (index_opr->is_constant()) { |
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int elem_size = type2aelembytes(type); |
1 | 190 |
addr = new LIR_Address(array_opr, |
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offset_in_bytes + (intx)(index_opr->as_jint()) * elem_size, type); |
1 | 192 |
} else { |
1066 | 193 |
#ifdef _LP64 |
194 |
if (index_opr->type() == T_INT) { |
|
195 |
LIR_Opr tmp = new_register(T_LONG); |
|
196 |
__ convert(Bytecodes::_i2l, index_opr, tmp); |
|
197 |
index_opr = tmp; |
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198 |
} |
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199 |
#endif // _LP64 |
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1 | 200 |
addr = new LIR_Address(array_opr, |
201 |
index_opr, |
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202 |
LIR_Address::scale(type), |
|
203 |
offset_in_bytes, type); |
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204 |
} |
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49906 | 205 |
return addr; |
1 | 206 |
} |
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LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) { |
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LIR_Opr r = NULL; |
6453 | 211 |
if (type == T_LONG) { |
212 |
r = LIR_OprFact::longConst(x); |
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213 |
} else if (type == T_INT) { |
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214 |
r = LIR_OprFact::intConst(x); |
|
215 |
} else { |
|
216 |
ShouldNotReachHere(); |
|
217 |
} |
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218 |
return r; |
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219 |
} |
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221 |
void LIRGenerator::increment_counter(address counter, BasicType type, int step) { |
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1066 | 222 |
LIR_Opr pointer = new_pointer_register(); |
223 |
__ move(LIR_OprFact::intptrConst(counter), pointer); |
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LIR_Address* addr = new LIR_Address(pointer, type); |
1 | 225 |
increment_counter(addr, step); |
226 |
} |
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227 |
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229 |
void LIRGenerator::increment_counter(LIR_Address* addr, int step) { |
|
230 |
__ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr); |
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231 |
} |
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232 |
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233 |
void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { |
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234 |
__ cmp_mem_int(condition, base, disp, c, info); |
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235 |
} |
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236 |
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237 |
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238 |
void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) { |
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239 |
__ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info); |
|
240 |
} |
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241 |
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bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { |
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if (tmp->is_valid() && c > 0 && c < max_jint) { |
1 | 245 |
if (is_power_of_2(c + 1)) { |
246 |
__ move(left, tmp); |
|
247 |
__ shift_left(left, log2_intptr(c + 1), left); |
|
248 |
__ sub(left, tmp, result); |
|
249 |
return true; |
|
250 |
} else if (is_power_of_2(c - 1)) { |
|
251 |
__ move(left, tmp); |
|
252 |
__ shift_left(left, log2_intptr(c - 1), left); |
|
253 |
__ add(left, tmp, result); |
|
254 |
return true; |
|
255 |
} |
|
256 |
} |
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257 |
return false; |
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258 |
} |
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259 |
||
260 |
||
261 |
void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) { |
|
262 |
BasicType type = item->type(); |
|
263 |
__ store(item, new LIR_Address(FrameMap::rsp_opr, in_bytes(offset_from_sp), type)); |
|
264 |
} |
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265 |
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49906 | 266 |
void LIRGenerator::array_store_check(LIR_Opr value, LIR_Opr array, CodeEmitInfo* store_check_info, ciMethod* profiled_method, int profiled_bci) { |
267 |
LIR_Opr tmp1 = new_register(objectType); |
|
268 |
LIR_Opr tmp2 = new_register(objectType); |
|
269 |
LIR_Opr tmp3 = new_register(objectType); |
|
270 |
__ store_check(value, array, tmp1, tmp2, tmp3, store_check_info, profiled_method, profiled_bci); |
|
271 |
} |
|
272 |
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1 | 273 |
//---------------------------------------------------------------------- |
274 |
// visitor functions |
|
275 |
//---------------------------------------------------------------------- |
|
276 |
||
277 |
void LIRGenerator::do_MonitorEnter(MonitorEnter* x) { |
|
6745 | 278 |
assert(x->is_pinned(),""); |
1 | 279 |
LIRItem obj(x->obj(), this); |
280 |
obj.load_item(); |
|
281 |
||
282 |
set_no_result(x); |
|
283 |
||
284 |
// "lock" stores the address of the monitor stack slot, so this is not an oop |
|
285 |
LIR_Opr lock = new_register(T_INT); |
|
286 |
// Need a scratch register for biased locking on x86 |
|
287 |
LIR_Opr scratch = LIR_OprFact::illegalOpr; |
|
288 |
if (UseBiasedLocking) { |
|
289 |
scratch = new_register(T_INT); |
|
290 |
} |
|
291 |
||
292 |
CodeEmitInfo* info_for_exception = NULL; |
|
293 |
if (x->needs_null_check()) { |
|
6745 | 294 |
info_for_exception = state_for(x); |
1 | 295 |
} |
296 |
// this CodeEmitInfo must not have the xhandlers because here the |
|
297 |
// object is already locked (xhandlers expect object to be unlocked) |
|
298 |
CodeEmitInfo* info = state_for(x, x->state(), true); |
|
299 |
monitor_enter(obj.result(), lock, syncTempOpr(), scratch, |
|
300 |
x->monitor_no(), info_for_exception, info); |
|
301 |
} |
|
302 |
||
303 |
||
304 |
void LIRGenerator::do_MonitorExit(MonitorExit* x) { |
|
6745 | 305 |
assert(x->is_pinned(),""); |
1 | 306 |
|
307 |
LIRItem obj(x->obj(), this); |
|
308 |
obj.dont_load_item(); |
|
309 |
||
310 |
LIR_Opr lock = new_register(T_INT); |
|
311 |
LIR_Opr obj_temp = new_register(T_INT); |
|
312 |
set_no_result(x); |
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monitor_exit(obj_temp, lock, syncTempOpr(), LIR_OprFact::illegalOpr, x->monitor_no()); |
1 | 314 |
} |
315 |
||
316 |
||
317 |
// _ineg, _lneg, _fneg, _dneg |
|
318 |
void LIRGenerator::do_NegateOp(NegateOp* x) { |
|
319 |
LIRItem value(x->x(), this); |
|
320 |
value.set_destroys_register(); |
|
321 |
value.load_item(); |
|
322 |
LIR_Opr reg = rlock(x); |
|
323 |
__ negate(value.result(), reg); |
|
324 |
||
325 |
set_result(x, round_item(reg)); |
|
326 |
} |
|
327 |
||
328 |
||
329 |
// for _fadd, _fmul, _fsub, _fdiv, _frem |
|
330 |
// _dadd, _dmul, _dsub, _ddiv, _drem |
|
331 |
void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) { |
|
332 |
LIRItem left(x->x(), this); |
|
333 |
LIRItem right(x->y(), this); |
|
334 |
LIRItem* left_arg = &left; |
|
335 |
LIRItem* right_arg = &right; |
|
336 |
assert(!left.is_stack() || !right.is_stack(), "can't both be memory operands"); |
|
337 |
bool must_load_both = (x->op() == Bytecodes::_frem || x->op() == Bytecodes::_drem); |
|
338 |
if (left.is_register() || x->x()->type()->is_constant() || must_load_both) { |
|
339 |
left.load_item(); |
|
340 |
} else { |
|
341 |
left.dont_load_item(); |
|
342 |
} |
|
343 |
||
344 |
// do not load right operand if it is a constant. only 0 and 1 are |
|
345 |
// loaded because there are special instructions for loading them |
|
346 |
// without memory access (not needed for SSE2 instructions) |
|
347 |
bool must_load_right = false; |
|
348 |
if (right.is_constant()) { |
|
349 |
LIR_Const* c = right.result()->as_constant_ptr(); |
|
350 |
assert(c != NULL, "invalid constant"); |
|
351 |
assert(c->type() == T_FLOAT || c->type() == T_DOUBLE, "invalid type"); |
|
352 |
||
353 |
if (c->type() == T_FLOAT) { |
|
354 |
must_load_right = UseSSE < 1 && (c->is_one_float() || c->is_zero_float()); |
|
355 |
} else { |
|
356 |
must_load_right = UseSSE < 2 && (c->is_one_double() || c->is_zero_double()); |
|
357 |
} |
|
358 |
} |
|
359 |
||
360 |
if (must_load_both) { |
|
361 |
// frem and drem destroy also right operand, so move it to a new register |
|
362 |
right.set_destroys_register(); |
|
363 |
right.load_item(); |
|
364 |
} else if (right.is_register() || must_load_right) { |
|
365 |
right.load_item(); |
|
366 |
} else { |
|
367 |
right.dont_load_item(); |
|
368 |
} |
|
369 |
LIR_Opr reg = rlock(x); |
|
370 |
LIR_Opr tmp = LIR_OprFact::illegalOpr; |
|
371 |
if (x->is_strictfp() && (x->op() == Bytecodes::_dmul || x->op() == Bytecodes::_ddiv)) { |
|
372 |
tmp = new_register(T_DOUBLE); |
|
373 |
} |
|
374 |
||
375 |
if ((UseSSE >= 1 && x->op() == Bytecodes::_frem) || (UseSSE >= 2 && x->op() == Bytecodes::_drem)) { |
|
376 |
// special handling for frem and drem: no SSE instruction, so must use FPU with temporary fpu stack slots |
|
377 |
LIR_Opr fpu0, fpu1; |
|
378 |
if (x->op() == Bytecodes::_frem) { |
|
379 |
fpu0 = LIR_OprFact::single_fpu(0); |
|
380 |
fpu1 = LIR_OprFact::single_fpu(1); |
|
381 |
} else { |
|
382 |
fpu0 = LIR_OprFact::double_fpu(0); |
|
383 |
fpu1 = LIR_OprFact::double_fpu(1); |
|
384 |
} |
|
385 |
__ move(right.result(), fpu1); // order of left and right operand is important! |
|
386 |
__ move(left.result(), fpu0); |
|
387 |
__ rem (fpu0, fpu1, fpu0); |
|
388 |
__ move(fpu0, reg); |
|
389 |
||
390 |
} else { |
|
391 |
arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp(), tmp); |
|
392 |
} |
|
393 |
||
394 |
set_result(x, round_item(reg)); |
|
395 |
} |
|
396 |
||
397 |
||
398 |
// for _ladd, _lmul, _lsub, _ldiv, _lrem |
|
399 |
void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) { |
|
400 |
if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem ) { |
|
401 |
// long division is implemented as a direct call into the runtime |
|
402 |
LIRItem left(x->x(), this); |
|
403 |
LIRItem right(x->y(), this); |
|
404 |
||
405 |
// the check for division by zero destroys the right operand |
|
406 |
right.set_destroys_register(); |
|
407 |
||
408 |
BasicTypeList signature(2); |
|
409 |
signature.append(T_LONG); |
|
410 |
signature.append(T_LONG); |
|
411 |
CallingConvention* cc = frame_map()->c_calling_convention(&signature); |
|
412 |
||
413 |
// check for division by zero (destroys registers of right operand!) |
|
414 |
CodeEmitInfo* info = state_for(x); |
|
415 |
||
416 |
const LIR_Opr result_reg = result_register_for(x->type()); |
|
417 |
left.load_item_force(cc->at(1)); |
|
418 |
right.load_item(); |
|
419 |
||
420 |
__ move(right.result(), cc->at(0)); |
|
421 |
||
422 |
__ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0)); |
|
423 |
__ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info)); |
|
424 |
||
33589
7cbd1b2c139b
8139040: Fix initializations before ShouldNotReachHere() etc. and enable -Wuninitialized on linux.
goetz
parents:
33089
diff
changeset
|
425 |
address entry = NULL; |
1 | 426 |
switch (x->op()) { |
427 |
case Bytecodes::_lrem: |
|
428 |
entry = CAST_FROM_FN_PTR(address, SharedRuntime::lrem); |
|
429 |
break; // check if dividend is 0 is done elsewhere |
|
430 |
case Bytecodes::_ldiv: |
|
431 |
entry = CAST_FROM_FN_PTR(address, SharedRuntime::ldiv); |
|
432 |
break; // check if dividend is 0 is done elsewhere |
|
433 |
case Bytecodes::_lmul: |
|
434 |
entry = CAST_FROM_FN_PTR(address, SharedRuntime::lmul); |
|
435 |
break; |
|
436 |
default: |
|
437 |
ShouldNotReachHere(); |
|
438 |
} |
|
439 |
||
440 |
LIR_Opr result = rlock_result(x); |
|
441 |
__ call_runtime_leaf(entry, getThreadTemp(), result_reg, cc->args()); |
|
442 |
__ move(result_reg, result); |
|
443 |
} else if (x->op() == Bytecodes::_lmul) { |
|
444 |
// missing test if instr is commutative and if we should swap |
|
445 |
LIRItem left(x->x(), this); |
|
446 |
LIRItem right(x->y(), this); |
|
447 |
||
448 |
// right register is destroyed by the long mul, so it must be |
|
449 |
// copied to a new register. |
|
450 |
right.set_destroys_register(); |
|
451 |
||
452 |
left.load_item(); |
|
453 |
right.load_item(); |
|
454 |
||
1066 | 455 |
LIR_Opr reg = FrameMap::long0_opr; |
1 | 456 |
arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL); |
457 |
LIR_Opr result = rlock_result(x); |
|
458 |
__ move(reg, result); |
|
459 |
} else { |
|
460 |
// missing test if instr is commutative and if we should swap |
|
461 |
LIRItem left(x->x(), this); |
|
462 |
LIRItem right(x->y(), this); |
|
463 |
||
464 |
left.load_item(); |
|
2131 | 465 |
// don't load constants to save register |
1 | 466 |
right.load_nonconstant(); |
467 |
rlock_result(x); |
|
468 |
arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL); |
|
469 |
} |
|
470 |
} |
|
471 |
||
472 |
||
473 |
||
474 |
// for: _iadd, _imul, _isub, _idiv, _irem |
|
475 |
void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) { |
|
476 |
if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) { |
|
477 |
// The requirements for division and modulo |
|
478 |
// input : rax,: dividend min_int |
|
479 |
// reg: divisor (may not be rax,/rdx) -1 |
|
480 |
// |
|
481 |
// output: rax,: quotient (= rax, idiv reg) min_int |
|
482 |
// rdx: remainder (= rax, irem reg) 0 |
|
483 |
||
484 |
// rax, and rdx will be destroyed |
|
485 |
||
486 |
// Note: does this invalidate the spec ??? |
|
487 |
LIRItem right(x->y(), this); |
|
488 |
LIRItem left(x->x() , this); // visit left second, so that the is_register test is valid |
|
489 |
||
490 |
// call state_for before load_item_force because state_for may |
|
491 |
// force the evaluation of other instructions that are needed for |
|
492 |
// correct debug info. Otherwise the live range of the fix |
|
493 |
// register might be too long. |
|
494 |
CodeEmitInfo* info = state_for(x); |
|
495 |
||
496 |
left.load_item_force(divInOpr()); |
|
497 |
||
498 |
right.load_item(); |
|
499 |
||
500 |
LIR_Opr result = rlock_result(x); |
|
501 |
LIR_Opr result_reg; |
|
502 |
if (x->op() == Bytecodes::_idiv) { |
|
503 |
result_reg = divOutOpr(); |
|
504 |
} else { |
|
505 |
result_reg = remOutOpr(); |
|
506 |
} |
|
507 |
||
508 |
if (!ImplicitDiv0Checks) { |
|
509 |
__ cmp(lir_cond_equal, right.result(), LIR_OprFact::intConst(0)); |
|
510 |
__ branch(lir_cond_equal, T_INT, new DivByZeroStub(info)); |
|
48807
fd8ccb37fce9
8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents:
47216
diff
changeset
|
511 |
// Idiv/irem cannot trap (passing info would generate an assertion). |
fd8ccb37fce9
8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents:
47216
diff
changeset
|
512 |
info = NULL; |
1 | 513 |
} |
514 |
LIR_Opr tmp = FrameMap::rdx_opr; // idiv and irem use rdx in their implementation |
|
515 |
if (x->op() == Bytecodes::_irem) { |
|
516 |
__ irem(left.result(), right.result(), result_reg, tmp, info); |
|
517 |
} else if (x->op() == Bytecodes::_idiv) { |
|
518 |
__ idiv(left.result(), right.result(), result_reg, tmp, info); |
|
519 |
} else { |
|
520 |
ShouldNotReachHere(); |
|
521 |
} |
|
522 |
||
523 |
__ move(result_reg, result); |
|
524 |
} else { |
|
525 |
// missing test if instr is commutative and if we should swap |
|
526 |
LIRItem left(x->x(), this); |
|
527 |
LIRItem right(x->y(), this); |
|
528 |
LIRItem* left_arg = &left; |
|
529 |
LIRItem* right_arg = &right; |
|
530 |
if (x->is_commutative() && left.is_stack() && right.is_register()) { |
|
531 |
// swap them if left is real stack (or cached) and right is real register(not cached) |
|
532 |
left_arg = &right; |
|
533 |
right_arg = &left; |
|
534 |
} |
|
535 |
||
536 |
left_arg->load_item(); |
|
537 |
||
538 |
// do not need to load right, as we can handle stack and constants |
|
539 |
if (x->op() == Bytecodes::_imul ) { |
|
540 |
// check if we can use shift instead |
|
541 |
bool use_constant = false; |
|
542 |
bool use_tmp = false; |
|
543 |
if (right_arg->is_constant()) { |
|
45632
e56cfcaea55c
8181872: C1: possible overflow when strength reducing integer multiply by constant
vlivanov
parents:
44738
diff
changeset
|
544 |
jint iconst = right_arg->get_jint_constant(); |
e56cfcaea55c
8181872: C1: possible overflow when strength reducing integer multiply by constant
vlivanov
parents:
44738
diff
changeset
|
545 |
if (iconst > 0 && iconst < max_jint) { |
1 | 546 |
if (is_power_of_2(iconst)) { |
547 |
use_constant = true; |
|
548 |
} else if (is_power_of_2(iconst - 1) || is_power_of_2(iconst + 1)) { |
|
549 |
use_constant = true; |
|
550 |
use_tmp = true; |
|
551 |
} |
|
552 |
} |
|
553 |
} |
|
554 |
if (use_constant) { |
|
555 |
right_arg->dont_load_item(); |
|
556 |
} else { |
|
557 |
right_arg->load_item(); |
|
558 |
} |
|
559 |
LIR_Opr tmp = LIR_OprFact::illegalOpr; |
|
560 |
if (use_tmp) { |
|
561 |
tmp = new_register(T_INT); |
|
562 |
} |
|
563 |
rlock_result(x); |
|
564 |
||
565 |
arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp); |
|
566 |
} else { |
|
567 |
right_arg->dont_load_item(); |
|
568 |
rlock_result(x); |
|
569 |
LIR_Opr tmp = LIR_OprFact::illegalOpr; |
|
570 |
arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp); |
|
571 |
} |
|
572 |
} |
|
573 |
} |
|
574 |
||
575 |
||
576 |
void LIRGenerator::do_ArithmeticOp(ArithmeticOp* x) { |
|
577 |
// when an operand with use count 1 is the left operand, then it is |
|
578 |
// likely that no move for 2-operand-LIR-form is necessary |
|
579 |
if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) { |
|
580 |
x->swap_operands(); |
|
581 |
} |
|
582 |
||
583 |
ValueTag tag = x->type()->tag(); |
|
584 |
assert(x->x()->type()->tag() == tag && x->y()->type()->tag() == tag, "wrong parameters"); |
|
585 |
switch (tag) { |
|
586 |
case floatTag: |
|
587 |
case doubleTag: do_ArithmeticOp_FPU(x); return; |
|
588 |
case longTag: do_ArithmeticOp_Long(x); return; |
|
589 |
case intTag: do_ArithmeticOp_Int(x); return; |
|
46630
75aa3e39d02c
8182299: Enable disabled clang warnings, build on OSX 10 + Xcode 8
jwilhelm
parents:
44738
diff
changeset
|
590 |
default: ShouldNotReachHere(); return; |
1 | 591 |
} |
592 |
} |
|
593 |
||
594 |
||
595 |
// _ishl, _lshl, _ishr, _lshr, _iushr, _lushr |
|
596 |
void LIRGenerator::do_ShiftOp(ShiftOp* x) { |
|
597 |
// count must always be in rcx |
|
598 |
LIRItem value(x->x(), this); |
|
599 |
LIRItem count(x->y(), this); |
|
600 |
||
601 |
ValueTag elemType = x->type()->tag(); |
|
602 |
bool must_load_count = !count.is_constant() || elemType == longTag; |
|
603 |
if (must_load_count) { |
|
604 |
// count for long must be in register |
|
605 |
count.load_item_force(shiftCountOpr()); |
|
606 |
} else { |
|
607 |
count.dont_load_item(); |
|
608 |
} |
|
609 |
value.load_item(); |
|
610 |
LIR_Opr reg = rlock_result(x); |
|
611 |
||
612 |
shift_op(x->op(), reg, value.result(), count.result(), LIR_OprFact::illegalOpr); |
|
613 |
} |
|
614 |
||
615 |
||
616 |
// _iand, _land, _ior, _lor, _ixor, _lxor |
|
617 |
void LIRGenerator::do_LogicOp(LogicOp* x) { |
|
618 |
// when an operand with use count 1 is the left operand, then it is |
|
619 |
// likely that no move for 2-operand-LIR-form is necessary |
|
620 |
if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) { |
|
621 |
x->swap_operands(); |
|
622 |
} |
|
623 |
||
624 |
LIRItem left(x->x(), this); |
|
625 |
LIRItem right(x->y(), this); |
|
626 |
||
627 |
left.load_item(); |
|
628 |
right.load_nonconstant(); |
|
629 |
LIR_Opr reg = rlock_result(x); |
|
630 |
||
631 |
logic_op(x->op(), reg, left.result(), right.result()); |
|
632 |
} |
|
633 |
||
634 |
||
635 |
||
636 |
// _lcmp, _fcmpl, _fcmpg, _dcmpl, _dcmpg |
|
637 |
void LIRGenerator::do_CompareOp(CompareOp* x) { |
|
638 |
LIRItem left(x->x(), this); |
|
639 |
LIRItem right(x->y(), this); |
|
640 |
ValueTag tag = x->x()->type()->tag(); |
|
641 |
if (tag == longTag) { |
|
642 |
left.set_destroys_register(); |
|
643 |
} |
|
644 |
left.load_item(); |
|
645 |
right.load_item(); |
|
646 |
LIR_Opr reg = rlock_result(x); |
|
647 |
||
648 |
if (x->x()->type()->is_float_kind()) { |
|
649 |
Bytecodes::Code code = x->op(); |
|
650 |
__ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl)); |
|
651 |
} else if (x->x()->type()->tag() == longTag) { |
|
652 |
__ lcmp2int(left.result(), right.result(), reg); |
|
653 |
} else { |
|
654 |
Unimplemented(); |
|
655 |
} |
|
656 |
} |
|
657 |
||
49906 | 658 |
LIR_Opr LIRGenerator::atomic_cmpxchg(BasicType type, LIR_Opr addr, LIRItem& cmp_value, LIRItem& new_value) { |
659 |
LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience |
|
660 |
if (type == T_OBJECT || type == T_ARRAY) { |
|
661 |
cmp_value.load_item_force(FrameMap::rax_oop_opr); |
|
662 |
new_value.load_item(); |
|
663 |
__ cas_obj(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill); |
|
664 |
} else if (type == T_INT) { |
|
665 |
cmp_value.load_item_force(FrameMap::rax_opr); |
|
666 |
new_value.load_item(); |
|
667 |
__ cas_int(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill); |
|
668 |
} else if (type == T_LONG) { |
|
669 |
cmp_value.load_item_force(FrameMap::long0_opr); |
|
670 |
new_value.load_item_force(FrameMap::long1_opr); |
|
671 |
__ cas_long(addr->as_address_ptr()->base(), cmp_value.result(), new_value.result(), ill, ill); |
|
4430 | 672 |
} else { |
49906 | 673 |
Unimplemented(); |
4430 | 674 |
} |
49906 | 675 |
LIR_Opr result = new_register(T_INT); |
676 |
__ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), |
|
677 |
result, type); |
|
678 |
return result; |
|
679 |
} |
|
1 | 680 |
|
49906 | 681 |
LIR_Opr LIRGenerator::atomic_xchg(BasicType type, LIR_Opr addr, LIRItem& value) { |
682 |
bool is_oop = type == T_OBJECT || type == T_ARRAY; |
|
683 |
LIR_Opr result = new_register(type); |
|
684 |
value.load_item(); |
|
685 |
// Because we want a 2-arg form of xchg and xadd |
|
686 |
__ move(value.result(), result); |
|
687 |
assert(type == T_INT || is_oop LP64_ONLY( || type == T_LONG ), "unexpected type"); |
|
688 |
__ xchg(addr, result, result, LIR_OprFact::illegalOpr); |
|
689 |
return result; |
|
690 |
} |
|
35094
1e623555b98d
8143930: C1 LinearScan asserts when compiling two back-to-back CompareAndSwapLongs
roland
parents:
34201
diff
changeset
|
691 |
|
49906 | 692 |
LIR_Opr LIRGenerator::atomic_add(BasicType type, LIR_Opr addr, LIRItem& value) { |
693 |
LIR_Opr result = new_register(type); |
|
694 |
value.load_item(); |
|
695 |
// Because we want a 2-arg form of xchg and xadd |
|
696 |
__ move(value.result(), result); |
|
697 |
assert(type == T_INT LP64_ONLY( || type == T_LONG ), "unexpected type"); |
|
698 |
__ xadd(addr, result, result, LIR_OprFact::illegalOpr); |
|
699 |
return result; |
|
1 | 700 |
} |
701 |
||
41323 | 702 |
void LIRGenerator::do_FmaIntrinsic(Intrinsic* x) { |
703 |
assert(x->number_of_arguments() == 3, "wrong type"); |
|
704 |
assert(UseFMA, "Needs FMA instructions support."); |
|
705 |
LIRItem value(x->argument_at(0), this); |
|
706 |
LIRItem value1(x->argument_at(1), this); |
|
707 |
LIRItem value2(x->argument_at(2), this); |
|
708 |
||
709 |
value2.set_destroys_register(); |
|
710 |
||
711 |
value.load_item(); |
|
712 |
value1.load_item(); |
|
713 |
value2.load_item(); |
|
714 |
||
715 |
LIR_Opr calc_input = value.result(); |
|
716 |
LIR_Opr calc_input1 = value1.result(); |
|
717 |
LIR_Opr calc_input2 = value2.result(); |
|
718 |
LIR_Opr calc_result = rlock_result(x); |
|
719 |
||
720 |
switch (x->id()) { |
|
721 |
case vmIntrinsics::_fmaD: __ fmad(calc_input, calc_input1, calc_input2, calc_result); break; |
|
722 |
case vmIntrinsics::_fmaF: __ fmaf(calc_input, calc_input1, calc_input2, calc_result); break; |
|
723 |
default: ShouldNotReachHere(); |
|
724 |
} |
|
725 |
||
726 |
} |
|
727 |
||
1 | 728 |
|
729 |
void LIRGenerator::do_MathIntrinsic(Intrinsic* x) { |
|
12739
09f26b73ae66
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
10562
diff
changeset
|
730 |
assert(x->number_of_arguments() == 1 || (x->number_of_arguments() == 2 && x->id() == vmIntrinsics::_dpow), "wrong type"); |
33089 | 731 |
|
35146 | 732 |
if (x->id() == vmIntrinsics::_dexp || x->id() == vmIntrinsics::_dlog || |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
733 |
x->id() == vmIntrinsics::_dpow || x->id() == vmIntrinsics::_dcos || |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
734 |
x->id() == vmIntrinsics::_dsin || x->id() == vmIntrinsics::_dtan || |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
735 |
x->id() == vmIntrinsics::_dlog10) { |
33465 | 736 |
do_LibmIntrinsic(x); |
33089 | 737 |
return; |
738 |
} |
|
739 |
||
1 | 740 |
LIRItem value(x->argument_at(0), this); |
741 |
||
742 |
bool use_fpu = false; |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
743 |
if (UseSSE < 2) { |
1 | 744 |
value.set_destroys_register(); |
745 |
} |
|
746 |
value.load_item(); |
|
747 |
||
748 |
LIR_Opr calc_input = value.result(); |
|
749 |
LIR_Opr calc_result = rlock_result(x); |
|
750 |
||
751 |
switch(x->id()) { |
|
752 |
case vmIntrinsics::_dabs: __ abs (calc_input, calc_result, LIR_OprFact::illegalOpr); break; |
|
753 |
case vmIntrinsics::_dsqrt: __ sqrt (calc_input, calc_result, LIR_OprFact::illegalOpr); break; |
|
754 |
default: ShouldNotReachHere(); |
|
755 |
} |
|
756 |
||
757 |
if (use_fpu) { |
|
758 |
__ move(calc_result, x->operand()); |
|
759 |
} |
|
760 |
} |
|
761 |
||
33465 | 762 |
void LIRGenerator::do_LibmIntrinsic(Intrinsic* x) { |
33089 | 763 |
LIRItem value(x->argument_at(0), this); |
764 |
value.set_destroys_register(); |
|
765 |
||
766 |
LIR_Opr calc_result = rlock_result(x); |
|
767 |
LIR_Opr result_reg = result_register_for(x->type()); |
|
768 |
||
35146 | 769 |
CallingConvention* cc = NULL; |
770 |
||
771 |
if (x->id() == vmIntrinsics::_dpow) { |
|
772 |
LIRItem value1(x->argument_at(1), this); |
|
773 |
||
774 |
value1.set_destroys_register(); |
|
33089 | 775 |
|
35146 | 776 |
BasicTypeList signature(2); |
777 |
signature.append(T_DOUBLE); |
|
778 |
signature.append(T_DOUBLE); |
|
779 |
cc = frame_map()->c_calling_convention(&signature); |
|
780 |
value.load_item_force(cc->at(0)); |
|
781 |
value1.load_item_force(cc->at(1)); |
|
782 |
} else { |
|
783 |
BasicTypeList signature(1); |
|
784 |
signature.append(T_DOUBLE); |
|
785 |
cc = frame_map()->c_calling_convention(&signature); |
|
786 |
value.load_item_force(cc->at(0)); |
|
787 |
} |
|
33089 | 788 |
|
789 |
#ifndef _LP64 |
|
790 |
LIR_Opr tmp = FrameMap::fpu0_double_opr; |
|
791 |
result_reg = tmp; |
|
33465 | 792 |
switch(x->id()) { |
793 |
case vmIntrinsics::_dexp: |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
794 |
if (StubRoutines::dexp() != NULL) { |
33465 | 795 |
__ call_runtime_leaf(StubRoutines::dexp(), getThreadTemp(), result_reg, cc->args()); |
796 |
} else { |
|
797 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dexp), getThreadTemp(), result_reg, cc->args()); |
|
798 |
} |
|
799 |
break; |
|
800 |
case vmIntrinsics::_dlog: |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
801 |
if (StubRoutines::dlog() != NULL) { |
33465 | 802 |
__ call_runtime_leaf(StubRoutines::dlog(), getThreadTemp(), result_reg, cc->args()); |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
803 |
} else { |
33465 | 804 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog), getThreadTemp(), result_reg, cc->args()); |
805 |
} |
|
806 |
break; |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
807 |
case vmIntrinsics::_dlog10: |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
808 |
if (StubRoutines::dlog10() != NULL) { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
809 |
__ call_runtime_leaf(StubRoutines::dlog10(), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
810 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
811 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog10), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
812 |
} |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
813 |
break; |
35146 | 814 |
case vmIntrinsics::_dpow: |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
815 |
if (StubRoutines::dpow() != NULL) { |
35146 | 816 |
__ call_runtime_leaf(StubRoutines::dpow(), getThreadTemp(), result_reg, cc->args()); |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
817 |
} else { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
818 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), getThreadTemp(), result_reg, cc->args()); |
35146 | 819 |
} |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
820 |
break; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
821 |
case vmIntrinsics::_dsin: |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
822 |
if (VM_Version::supports_sse2() && StubRoutines::dsin() != NULL) { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
823 |
__ call_runtime_leaf(StubRoutines::dsin(), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
824 |
} else { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
825 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
826 |
} |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
827 |
break; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
828 |
case vmIntrinsics::_dcos: |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
829 |
if (VM_Version::supports_sse2() && StubRoutines::dcos() != NULL) { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
830 |
__ call_runtime_leaf(StubRoutines::dcos(), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
831 |
} else { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
832 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), getThreadTemp(), result_reg, cc->args()); |
35146 | 833 |
} |
834 |
break; |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
835 |
case vmIntrinsics::_dtan: |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
836 |
if (StubRoutines::dtan() != NULL) { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
837 |
__ call_runtime_leaf(StubRoutines::dtan(), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
838 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
839 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
840 |
} |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
841 |
break; |
33465 | 842 |
default: ShouldNotReachHere(); |
33089 | 843 |
} |
844 |
#else |
|
33465 | 845 |
switch (x->id()) { |
846 |
case vmIntrinsics::_dexp: |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
847 |
if (StubRoutines::dexp() != NULL) { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
848 |
__ call_runtime_leaf(StubRoutines::dexp(), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
849 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
850 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dexp), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
851 |
} |
33465 | 852 |
break; |
853 |
case vmIntrinsics::_dlog: |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
854 |
if (StubRoutines::dlog() != NULL) { |
33465 | 855 |
__ call_runtime_leaf(StubRoutines::dlog(), getThreadTemp(), result_reg, cc->args()); |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
856 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
857 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
858 |
} |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
859 |
break; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
860 |
case vmIntrinsics::_dlog10: |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
861 |
if (StubRoutines::dlog10() != NULL) { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
862 |
__ call_runtime_leaf(StubRoutines::dlog10(), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
863 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
864 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog10), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
865 |
} |
33465 | 866 |
break; |
35146 | 867 |
case vmIntrinsics::_dpow: |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
868 |
if (StubRoutines::dpow() != NULL) { |
35146 | 869 |
__ call_runtime_leaf(StubRoutines::dpow(), getThreadTemp(), result_reg, cc->args()); |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
870 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
871 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
872 |
} |
35146 | 873 |
break; |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
874 |
case vmIntrinsics::_dsin: |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
875 |
if (StubRoutines::dsin() != NULL) { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
876 |
__ call_runtime_leaf(StubRoutines::dsin(), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
877 |
} else { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
878 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
879 |
} |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
880 |
break; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
881 |
case vmIntrinsics::_dcos: |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
882 |
if (StubRoutines::dcos() != NULL) { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
883 |
__ call_runtime_leaf(StubRoutines::dcos(), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
884 |
} else { |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
885 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), getThreadTemp(), result_reg, cc->args()); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
886 |
} |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
887 |
break; |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
888 |
case vmIntrinsics::_dtan: |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
889 |
if (StubRoutines::dtan() != NULL) { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
890 |
__ call_runtime_leaf(StubRoutines::dtan(), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
891 |
} else { |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
892 |
__ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), getThreadTemp(), result_reg, cc->args()); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
893 |
} |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
35540
diff
changeset
|
894 |
break; |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
895 |
default: ShouldNotReachHere(); |
33465 | 896 |
} |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35146
diff
changeset
|
897 |
#endif // _LP64 |
33089 | 898 |
__ move(result_reg, calc_result); |
899 |
} |
|
1 | 900 |
|
901 |
void LIRGenerator::do_ArrayCopy(Intrinsic* x) { |
|
902 |
assert(x->number_of_arguments() == 5, "wrong type"); |
|
7430
169d2a85b41b
6875026: CTW failure jdk6_18/hotspot/src/share/vm/c1/c1_LinearScan.cpp:5486
never
parents:
7427
diff
changeset
|
903 |
|
169d2a85b41b
6875026: CTW failure jdk6_18/hotspot/src/share/vm/c1/c1_LinearScan.cpp:5486
never
parents:
7427
diff
changeset
|
904 |
// Make all state_for calls early since they can emit code |
169d2a85b41b
6875026: CTW failure jdk6_18/hotspot/src/share/vm/c1/c1_LinearScan.cpp:5486
never
parents:
7427
diff
changeset
|
905 |
CodeEmitInfo* info = state_for(x, x->state()); |
169d2a85b41b
6875026: CTW failure jdk6_18/hotspot/src/share/vm/c1/c1_LinearScan.cpp:5486
never
parents:
7427
diff
changeset
|
906 |
|
1 | 907 |
LIRItem src(x->argument_at(0), this); |
908 |
LIRItem src_pos(x->argument_at(1), this); |
|
909 |
LIRItem dst(x->argument_at(2), this); |
|
910 |
LIRItem dst_pos(x->argument_at(3), this); |
|
911 |
LIRItem length(x->argument_at(4), this); |
|
912 |
||
913 |
// operands for arraycopy must use fixed registers, otherwise |
|
914 |
// LinearScan will fail allocation (because arraycopy always needs a |
|
915 |
// call) |
|
1066 | 916 |
|
917 |
#ifndef _LP64 |
|
1 | 918 |
src.load_item_force (FrameMap::rcx_oop_opr); |
919 |
src_pos.load_item_force (FrameMap::rdx_opr); |
|
920 |
dst.load_item_force (FrameMap::rax_oop_opr); |
|
921 |
dst_pos.load_item_force (FrameMap::rbx_opr); |
|
922 |
length.load_item_force (FrameMap::rdi_opr); |
|
923 |
LIR_Opr tmp = (FrameMap::rsi_opr); |
|
1066 | 924 |
#else |
925 |
||
926 |
// The java calling convention will give us enough registers |
|
927 |
// so that on the stub side the args will be perfect already. |
|
928 |
// On the other slow/special case side we call C and the arg |
|
929 |
// positions are not similar enough to pick one as the best. |
|
930 |
// Also because the java calling convention is a "shifted" version |
|
931 |
// of the C convention we can process the java args trivially into C |
|
932 |
// args without worry of overwriting during the xfer |
|
933 |
||
934 |
src.load_item_force (FrameMap::as_oop_opr(j_rarg0)); |
|
935 |
src_pos.load_item_force (FrameMap::as_opr(j_rarg1)); |
|
936 |
dst.load_item_force (FrameMap::as_oop_opr(j_rarg2)); |
|
937 |
dst_pos.load_item_force (FrameMap::as_opr(j_rarg3)); |
|
938 |
length.load_item_force (FrameMap::as_opr(j_rarg4)); |
|
939 |
||
940 |
LIR_Opr tmp = FrameMap::as_opr(j_rarg5); |
|
941 |
#endif // LP64 |
|
942 |
||
1 | 943 |
set_no_result(x); |
944 |
||
945 |
int flags; |
|
946 |
ciArrayKlass* expected_type; |
|
947 |
arraycopy_helper(x, &flags, &expected_type); |
|
948 |
||
949 |
__ arraycopy(src.result(), src_pos.result(), dst.result(), dst_pos.result(), length.result(), tmp, expected_type, flags, info); // does add_safepoint |
|
950 |
} |
|
951 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
952 |
void LIRGenerator::do_update_CRC32(Intrinsic* x) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
953 |
assert(UseCRC32Intrinsics, "need AVX and LCMUL instructions support"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
954 |
// Make all state_for calls early since they can emit code |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
955 |
LIR_Opr result = rlock_result(x); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
956 |
int flags = 0; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
957 |
switch (x->id()) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
958 |
case vmIntrinsics::_updateCRC32: { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
959 |
LIRItem crc(x->argument_at(0), this); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
960 |
LIRItem val(x->argument_at(1), this); |
22508
4f8b051ff895
8022395: java.util.zip.ZipException: Not in GZIP format in JT_JDK/test/java/util/zip/GZIP tests
twisti
parents:
21210
diff
changeset
|
961 |
// val is destroyed by update_crc32 |
4f8b051ff895
8022395: java.util.zip.ZipException: Not in GZIP format in JT_JDK/test/java/util/zip/GZIP tests
twisti
parents:
21210
diff
changeset
|
962 |
val.set_destroys_register(); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
963 |
crc.load_item(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
964 |
val.load_item(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
965 |
__ update_crc32(crc.result(), val.result(), result); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
966 |
break; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
967 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
968 |
case vmIntrinsics::_updateBytesCRC32: |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
969 |
case vmIntrinsics::_updateByteBufferCRC32: { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
970 |
bool is_updateBytes = (x->id() == vmIntrinsics::_updateBytesCRC32); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
971 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
972 |
LIRItem crc(x->argument_at(0), this); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
973 |
LIRItem buf(x->argument_at(1), this); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
974 |
LIRItem off(x->argument_at(2), this); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
975 |
LIRItem len(x->argument_at(3), this); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
976 |
buf.load_item(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
977 |
off.load_nonconstant(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
978 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
979 |
LIR_Opr index = off.result(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
980 |
int offset = is_updateBytes ? arrayOopDesc::base_offset_in_bytes(T_BYTE) : 0; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
981 |
if(off.result()->is_constant()) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
982 |
index = LIR_OprFact::illegalOpr; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
983 |
offset += off.result()->as_jint(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
984 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
985 |
LIR_Opr base_op = buf.result(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
986 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
987 |
#ifndef _LP64 |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
988 |
if (!is_updateBytes) { // long b raw address |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
989 |
base_op = new_register(T_INT); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
990 |
__ convert(Bytecodes::_l2i, buf.result(), base_op); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
991 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
992 |
#else |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
993 |
if (index->is_valid()) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
994 |
LIR_Opr tmp = new_register(T_LONG); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
995 |
__ convert(Bytecodes::_i2l, index, tmp); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
996 |
index = tmp; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
997 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
998 |
#endif |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
999 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1000 |
LIR_Address* a = new LIR_Address(base_op, |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1001 |
index, |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1002 |
offset, |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1003 |
T_BYTE); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1004 |
BasicTypeList signature(3); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1005 |
signature.append(T_INT); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1006 |
signature.append(T_ADDRESS); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1007 |
signature.append(T_INT); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1008 |
CallingConvention* cc = frame_map()->c_calling_convention(&signature); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1009 |
const LIR_Opr result_reg = result_register_for(x->type()); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1010 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1011 |
LIR_Opr addr = new_pointer_register(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1012 |
__ leal(LIR_OprFact::address(a), addr); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1013 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1014 |
crc.load_item_force(cc->at(0)); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1015 |
__ move(addr, cc->at(1)); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1016 |
len.load_item_force(cc->at(2)); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1017 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1018 |
__ call_runtime_leaf(StubRoutines::updateBytesCRC32(), getThreadTemp(), result_reg, cc->args()); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1019 |
__ move(result_reg, result); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1020 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1021 |
break; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1022 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1023 |
default: { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1024 |
ShouldNotReachHere(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1025 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1026 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
16611
diff
changeset
|
1027 |
} |
1 | 1028 |
|
38237
d972e3a2df53
8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents:
38031
diff
changeset
|
1029 |
void LIRGenerator::do_update_CRC32C(Intrinsic* x) { |
d972e3a2df53
8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents:
38031
diff
changeset
|
1030 |
Unimplemented(); |
d972e3a2df53
8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents:
38031
diff
changeset
|
1031 |
} |
d972e3a2df53
8155162: java.util.zip.CRC32C Interpreter/C1 intrinsics support on SPARC
kvn
parents:
38031
diff
changeset
|
1032 |
|
38238
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1033 |
void LIRGenerator::do_vectorizedMismatch(Intrinsic* x) { |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1034 |
assert(UseVectorizedMismatchIntrinsic, "need AVX instruction support"); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1035 |
|
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1036 |
// Make all state_for calls early since they can emit code |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1037 |
LIR_Opr result = rlock_result(x); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1038 |
|
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1039 |
LIRItem a(x->argument_at(0), this); // Object |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1040 |
LIRItem aOffset(x->argument_at(1), this); // long |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1041 |
LIRItem b(x->argument_at(2), this); // Object |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1042 |
LIRItem bOffset(x->argument_at(3), this); // long |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1043 |
LIRItem length(x->argument_at(4), this); // int |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1044 |
LIRItem log2ArrayIndexScale(x->argument_at(5), this); // int |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1045 |
|
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1046 |
a.load_item(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1047 |
aOffset.load_nonconstant(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1048 |
b.load_item(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1049 |
bOffset.load_nonconstant(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1050 |
|
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1051 |
long constant_aOffset = 0; |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1052 |
LIR_Opr result_aOffset = aOffset.result(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1053 |
if (result_aOffset->is_constant()) { |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1054 |
constant_aOffset = result_aOffset->as_jlong(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1055 |
result_aOffset = LIR_OprFact::illegalOpr; |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1056 |
} |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1057 |
LIR_Opr result_a = a.result(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1058 |
|
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1059 |
long constant_bOffset = 0; |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1060 |
LIR_Opr result_bOffset = bOffset.result(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38237
diff
changeset
|
1061 |
if (result_bOffset->is_constant()) { |
1bbcc430c78d
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|
1062 |
constant_bOffset = result_bOffset->as_jlong(); |
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|
1063 |
result_bOffset = LIR_OprFact::illegalOpr; |
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changeset
|
1064 |
} |
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changeset
|
1065 |
LIR_Opr result_b = b.result(); |
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changeset
|
1066 |
|
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changeset
|
1067 |
#ifndef _LP64 |
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|
1068 |
result_a = new_register(T_INT); |
1bbcc430c78d
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changeset
|
1069 |
__ convert(Bytecodes::_l2i, a.result(), result_a); |
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changeset
|
1070 |
result_b = new_register(T_INT); |
1bbcc430c78d
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changeset
|
1071 |
__ convert(Bytecodes::_l2i, b.result(), result_b); |
1bbcc430c78d
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changeset
|
1072 |
#endif |
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8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
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changeset
|
1073 |
|
1bbcc430c78d
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changeset
|
1074 |
|
1bbcc430c78d
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changeset
|
1075 |
LIR_Address* addr_a = new LIR_Address(result_a, |
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changeset
|
1076 |
result_aOffset, |
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changeset
|
1077 |
constant_aOffset, |
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changeset
|
1078 |
T_BYTE); |
1bbcc430c78d
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changeset
|
1079 |
|
1bbcc430c78d
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changeset
|
1080 |
LIR_Address* addr_b = new LIR_Address(result_b, |
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changeset
|
1081 |
result_bOffset, |
1bbcc430c78d
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changeset
|
1082 |
constant_bOffset, |
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changeset
|
1083 |
T_BYTE); |
1bbcc430c78d
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changeset
|
1084 |
|
1bbcc430c78d
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changeset
|
1085 |
BasicTypeList signature(4); |
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changeset
|
1086 |
signature.append(T_ADDRESS); |
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changeset
|
1087 |
signature.append(T_ADDRESS); |
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changeset
|
1088 |
signature.append(T_INT); |
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changeset
|
1089 |
signature.append(T_INT); |
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changeset
|
1090 |
CallingConvention* cc = frame_map()->c_calling_convention(&signature); |
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changeset
|
1091 |
const LIR_Opr result_reg = result_register_for(x->type()); |
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changeset
|
1092 |
|
1bbcc430c78d
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changeset
|
1093 |
LIR_Opr ptr_addr_a = new_pointer_register(); |
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changeset
|
1094 |
__ leal(LIR_OprFact::address(addr_a), ptr_addr_a); |
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changeset
|
1095 |
|
1bbcc430c78d
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changeset
|
1096 |
LIR_Opr ptr_addr_b = new_pointer_register(); |
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parents:
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changeset
|
1097 |
__ leal(LIR_OprFact::address(addr_b), ptr_addr_b); |
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changeset
|
1098 |
|
1bbcc430c78d
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changeset
|
1099 |
__ move(ptr_addr_a, cc->at(0)); |
1bbcc430c78d
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parents:
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changeset
|
1100 |
__ move(ptr_addr_b, cc->at(1)); |
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changeset
|
1101 |
length.load_item_force(cc->at(2)); |
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changeset
|
1102 |
log2ArrayIndexScale.load_item_force(cc->at(3)); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
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changeset
|
1103 |
|
1bbcc430c78d
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changeset
|
1104 |
__ call_runtime_leaf(StubRoutines::vectorizedMismatch(), getThreadTemp(), result_reg, cc->args()); |
1bbcc430c78d
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changeset
|
1105 |
__ move(result_reg, result); |
1bbcc430c78d
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changeset
|
1106 |
} |
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changeset
|
1107 |
|
1 | 1108 |
// _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f |
1109 |
// _i2b, _i2c, _i2s |
|
1110 |
LIR_Opr fixed_register_for(BasicType type) { |
|
1111 |
switch (type) { |
|
1112 |
case T_FLOAT: return FrameMap::fpu0_float_opr; |
|
1113 |
case T_DOUBLE: return FrameMap::fpu0_double_opr; |
|
1114 |
case T_INT: return FrameMap::rax_opr; |
|
1066 | 1115 |
case T_LONG: return FrameMap::long0_opr; |
1 | 1116 |
default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr; |
1117 |
} |
|
1118 |
} |
|
1119 |
||
1120 |
void LIRGenerator::do_Convert(Convert* x) { |
|
1121 |
// flags that vary for the different operations and different SSE-settings |
|
33589
7cbd1b2c139b
8139040: Fix initializations before ShouldNotReachHere() etc. and enable -Wuninitialized on linux.
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diff
changeset
|
1122 |
bool fixed_input = false, fixed_result = false, round_result = false, needs_stub = false; |
1 | 1123 |
|
1124 |
switch (x->op()) { |
|
1125 |
case Bytecodes::_i2l: // fall through |
|
1126 |
case Bytecodes::_l2i: // fall through |
|
1127 |
case Bytecodes::_i2b: // fall through |
|
1128 |
case Bytecodes::_i2c: // fall through |
|
1129 |
case Bytecodes::_i2s: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break; |
|
1130 |
||
1131 |
case Bytecodes::_f2d: fixed_input = UseSSE == 1; fixed_result = false; round_result = false; needs_stub = false; break; |
|
1132 |
case Bytecodes::_d2f: fixed_input = false; fixed_result = UseSSE == 1; round_result = UseSSE < 1; needs_stub = false; break; |
|
1133 |
case Bytecodes::_i2f: fixed_input = false; fixed_result = false; round_result = UseSSE < 1; needs_stub = false; break; |
|
1134 |
case Bytecodes::_i2d: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break; |
|
1135 |
case Bytecodes::_f2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break; |
|
1136 |
case Bytecodes::_d2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break; |
|
1137 |
case Bytecodes::_l2f: fixed_input = false; fixed_result = UseSSE >= 1; round_result = UseSSE < 1; needs_stub = false; break; |
|
1138 |
case Bytecodes::_l2d: fixed_input = false; fixed_result = UseSSE >= 2; round_result = UseSSE < 2; needs_stub = false; break; |
|
1139 |
case Bytecodes::_f2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break; |
|
1140 |
case Bytecodes::_d2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break; |
|
1141 |
default: ShouldNotReachHere(); |
|
1142 |
} |
|
1143 |
||
1144 |
LIRItem value(x->value(), this); |
|
1145 |
value.load_item(); |
|
1146 |
LIR_Opr input = value.result(); |
|
1147 |
LIR_Opr result = rlock(x); |
|
1148 |
||
1149 |
// arguments of lir_convert |
|
1150 |
LIR_Opr conv_input = input; |
|
1151 |
LIR_Opr conv_result = result; |
|
1152 |
ConversionStub* stub = NULL; |
|
1153 |
||
1154 |
if (fixed_input) { |
|
1155 |
conv_input = fixed_register_for(input->type()); |
|
1156 |
__ move(input, conv_input); |
|
1157 |
} |
|
1158 |
||
1159 |
assert(fixed_result == false || round_result == false, "cannot set both"); |
|
1160 |
if (fixed_result) { |
|
1161 |
conv_result = fixed_register_for(result->type()); |
|
1162 |
} else if (round_result) { |
|
1163 |
result = new_register(result->type()); |
|
1164 |
set_vreg_flag(result, must_start_in_memory); |
|
1165 |
} |
|
1166 |
||
1167 |
if (needs_stub) { |
|
1168 |
stub = new ConversionStub(x->op(), conv_input, conv_result); |
|
1169 |
} |
|
1170 |
||
1171 |
__ convert(x->op(), conv_input, conv_result, stub); |
|
1172 |
||
1173 |
if (result != conv_result) { |
|
1174 |
__ move(conv_result, result); |
|
1175 |
} |
|
1176 |
||
1177 |
assert(result->is_virtual(), "result must be virtual register"); |
|
1178 |
set_result(x, result); |
|
1179 |
} |
|
1180 |
||
1181 |
||
1182 |
void LIRGenerator::do_NewInstance(NewInstance* x) { |
|
24933
c16c7a4ac386
8031994: java/lang/Character/CheckProp test times out
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parents:
22508
diff
changeset
|
1183 |
print_if_not_loaded(x); |
c16c7a4ac386
8031994: java/lang/Character/CheckProp test times out
rbackman
parents:
22508
diff
changeset
|
1184 |
|
1 | 1185 |
CodeEmitInfo* info = state_for(x, x->state()); |
1186 |
LIR_Opr reg = result_register_for(x->type()); |
|
24933
c16c7a4ac386
8031994: java/lang/Character/CheckProp test times out
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parents:
22508
diff
changeset
|
1187 |
new_instance(reg, x->klass(), x->is_unresolved(), |
1 | 1188 |
FrameMap::rcx_oop_opr, |
1189 |
FrameMap::rdi_oop_opr, |
|
1190 |
FrameMap::rsi_oop_opr, |
|
1191 |
LIR_OprFact::illegalOpr, |
|
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
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parents:
13728
diff
changeset
|
1192 |
FrameMap::rdx_metadata_opr, info); |
1 | 1193 |
LIR_Opr result = rlock_result(x); |
1194 |
__ move(reg, result); |
|
1195 |
} |
|
1196 |
||
1197 |
||
1198 |
void LIRGenerator::do_NewTypeArray(NewTypeArray* x) { |
|
1199 |
CodeEmitInfo* info = state_for(x, x->state()); |
|
1200 |
||
1201 |
LIRItem length(x->length(), this); |
|
1202 |
length.load_item_force(FrameMap::rbx_opr); |
|
1203 |
||
1204 |
LIR_Opr reg = result_register_for(x->type()); |
|
1205 |
LIR_Opr tmp1 = FrameMap::rcx_oop_opr; |
|
1206 |
LIR_Opr tmp2 = FrameMap::rsi_oop_opr; |
|
1207 |
LIR_Opr tmp3 = FrameMap::rdi_oop_opr; |
|
1208 |
LIR_Opr tmp4 = reg; |
|
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1209 |
LIR_Opr klass_reg = FrameMap::rdx_metadata_opr; |
1 | 1210 |
LIR_Opr len = length.result(); |
1211 |
BasicType elem_type = x->elt_type(); |
|
1212 |
||
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1213 |
__ metadata2reg(ciTypeArrayKlass::make(elem_type)->constant_encoding(), klass_reg); |
1 | 1214 |
|
1215 |
CodeStub* slow_path = new NewTypeArrayStub(klass_reg, len, reg, info); |
|
1216 |
__ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, elem_type, klass_reg, slow_path); |
|
1217 |
||
1218 |
LIR_Opr result = rlock_result(x); |
|
1219 |
__ move(reg, result); |
|
1220 |
} |
|
1221 |
||
1222 |
||
1223 |
void LIRGenerator::do_NewObjectArray(NewObjectArray* x) { |
|
1224 |
LIRItem length(x->length(), this); |
|
1225 |
// in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction |
|
1226 |
// and therefore provide the state before the parameters have been consumed |
|
1227 |
CodeEmitInfo* patching_info = NULL; |
|
1228 |
if (!x->klass()->is_loaded() || PatchALot) { |
|
1229 |
patching_info = state_for(x, x->state_before()); |
|
1230 |
} |
|
1231 |
||
1232 |
CodeEmitInfo* info = state_for(x, x->state()); |
|
1233 |
||
1234 |
const LIR_Opr reg = result_register_for(x->type()); |
|
1235 |
LIR_Opr tmp1 = FrameMap::rcx_oop_opr; |
|
1236 |
LIR_Opr tmp2 = FrameMap::rsi_oop_opr; |
|
1237 |
LIR_Opr tmp3 = FrameMap::rdi_oop_opr; |
|
1238 |
LIR_Opr tmp4 = reg; |
|
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
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parents:
13728
diff
changeset
|
1239 |
LIR_Opr klass_reg = FrameMap::rdx_metadata_opr; |
1 | 1240 |
|
1241 |
length.load_item_force(FrameMap::rbx_opr); |
|
1242 |
LIR_Opr len = length.result(); |
|
1243 |
||
1244 |
CodeStub* slow_path = new NewObjectArrayStub(klass_reg, len, reg, info); |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
12959
diff
changeset
|
1245 |
ciKlass* obj = (ciKlass*) ciObjArrayKlass::make(x->klass()); |
1 | 1246 |
if (obj == ciEnv::unloaded_ciobjarrayklass()) { |
1247 |
BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error"); |
|
1248 |
} |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
12959
diff
changeset
|
1249 |
klass2reg_with_patching(klass_reg, obj, patching_info); |
1 | 1250 |
__ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, T_OBJECT, klass_reg, slow_path); |
1251 |
||
1252 |
LIR_Opr result = rlock_result(x); |
|
1253 |
__ move(reg, result); |
|
1254 |
} |
|
1255 |
||
1256 |
||
1257 |
void LIRGenerator::do_NewMultiArray(NewMultiArray* x) { |
|
1258 |
Values* dims = x->dims(); |
|
1259 |
int i = dims->length(); |
|
38031
e0b822facc03
8149374: Replace C1-specific collection classes with universal collection classes
fzhinkin
parents:
38018
diff
changeset
|
1260 |
LIRItemList* items = new LIRItemList(i, i, NULL); |
1 | 1261 |
while (i-- > 0) { |
1262 |
LIRItem* size = new LIRItem(dims->at(i), this); |
|
1263 |
items->at_put(i, size); |
|
1264 |
} |
|
1265 |
||
3688
22b55d147bc1
6875329: fix for 6795465 broke exception handler cloning
never
parents:
2131
diff
changeset
|
1266 |
// Evaluate state_for early since it may emit code. |
1 | 1267 |
CodeEmitInfo* patching_info = NULL; |
1268 |
if (!x->klass()->is_loaded() || PatchALot) { |
|
1269 |
patching_info = state_for(x, x->state_before()); |
|
1270 |
||
12959
4d33f9be7e87
7174928: JSR 292: unresolved invokedynamic call sites deopt and osr infinitely
twisti
parents:
12957
diff
changeset
|
1271 |
// Cannot re-use same xhandlers for multiple CodeEmitInfos, so |
4d33f9be7e87
7174928: JSR 292: unresolved invokedynamic call sites deopt and osr infinitely
twisti
parents:
12957
diff
changeset
|
1272 |
// clone all handlers (NOTE: Usually this is handled transparently |
4d33f9be7e87
7174928: JSR 292: unresolved invokedynamic call sites deopt and osr infinitely
twisti
parents:
12957
diff
changeset
|
1273 |
// by the CodeEmitInfo cloning logic in CodeStub constructors but |
4d33f9be7e87
7174928: JSR 292: unresolved invokedynamic call sites deopt and osr infinitely
twisti
parents:
12957
diff
changeset
|
1274 |
// is done explicitly here because a stub isn't being used). |
1 | 1275 |
x->set_exception_handlers(new XHandlers(x->exception_handlers())); |
1276 |
} |
|
1277 |
CodeEmitInfo* info = state_for(x, x->state()); |
|
1278 |
||
1279 |
i = dims->length(); |
|
1280 |
while (i-- > 0) { |
|
1281 |
LIRItem* size = items->at(i); |
|
1282 |
size->load_nonconstant(); |
|
1283 |
||
1284 |
store_stack_parameter(size->result(), in_ByteSize(i*4)); |
|
1285 |
} |
|
1286 |
||
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1287 |
LIR_Opr klass_reg = FrameMap::rax_metadata_opr; |
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1288 |
klass2reg_with_patching(klass_reg, x->klass(), patching_info); |
1 | 1289 |
|
1290 |
LIR_Opr rank = FrameMap::rbx_opr; |
|
1291 |
__ move(LIR_OprFact::intConst(x->rank()), rank); |
|
1292 |
LIR_Opr varargs = FrameMap::rcx_opr; |
|
1293 |
__ move(FrameMap::rsp_opr, varargs); |
|
1294 |
LIR_OprList* args = new LIR_OprList(3); |
|
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1295 |
args->append(klass_reg); |
1 | 1296 |
args->append(rank); |
1297 |
args->append(varargs); |
|
13742
9180987e305d
7195816: NPG: Crash in c1_ValueType - ShouldNotReachHere
roland
parents:
13728
diff
changeset
|
1298 |
LIR_Opr reg = result_register_for(x->type()); |
1 | 1299 |
__ call_runtime(Runtime1::entry_for(Runtime1::new_multi_array_id), |
1300 |
LIR_OprFact::illegalOpr, |
|
1301 |
reg, args, info); |
|
1302 |
||
1303 |
LIR_Opr result = rlock_result(x); |
|
1304 |
__ move(reg, result); |
|
1305 |
} |
|
1306 |
||
1307 |
||
1308 |
void LIRGenerator::do_BlockBegin(BlockBegin* x) { |
|
1309 |
// nothing to do for now |
|
1310 |
} |
|
1311 |
||
1312 |
||
1313 |
void LIRGenerator::do_CheckCast(CheckCast* x) { |
|
1314 |
LIRItem obj(x->obj(), this); |
|
1315 |
||
1316 |
CodeEmitInfo* patching_info = NULL; |
|
49933
c63bdf53a1a7
8202399: [C1] LIRGenerator::do_CheckCast needs to exclude is_invokespecial_receiver_check() when using PatchAlot
dholmes
parents:
49906
diff
changeset
|
1317 |
if (!x->klass()->is_loaded() || (PatchALot && !x->is_incompatible_class_change_check() && !x->is_invokespecial_receiver_check())) { |
1 | 1318 |
// must do this before locking the destination register as an oop register, |
1319 |
// and before the obj is loaded (the latter is for deoptimization) |
|
1320 |
patching_info = state_for(x, x->state_before()); |
|
1321 |
} |
|
1322 |
obj.load_item(); |
|
1323 |
||
1324 |
// info for exceptions |
|
44738 | 1325 |
CodeEmitInfo* info_for_exception = |
1326 |
(x->needs_exception_state() ? state_for(x) : |
|
1327 |
state_for(x, x->state_before(), true /*ignore_xhandler*/)); |
|
1 | 1328 |
|
1329 |
CodeStub* stub; |
|
1330 |
if (x->is_incompatible_class_change_check()) { |
|
1331 |
assert(patching_info == NULL, "can't patch this"); |
|
1332 |
stub = new SimpleExceptionStub(Runtime1::throw_incompatible_class_change_error_id, LIR_OprFact::illegalOpr, info_for_exception); |
|
44738 | 1333 |
} else if (x->is_invokespecial_receiver_check()) { |
1334 |
assert(patching_info == NULL, "can't patch this"); |
|
1335 |
stub = new DeoptimizeStub(info_for_exception, Deoptimization::Reason_class_check, Deoptimization::Action_none); |
|
1 | 1336 |
} else { |
1337 |
stub = new SimpleExceptionStub(Runtime1::throw_class_cast_exception_id, obj.result(), info_for_exception); |
|
1338 |
} |
|
1339 |
LIR_Opr reg = rlock_result(x); |
|
7427 | 1340 |
LIR_Opr tmp3 = LIR_OprFact::illegalOpr; |
19979
ebe1dbb6e1aa
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
18507
diff
changeset
|
1341 |
if (!x->klass()->is_loaded() || UseCompressedClassPointers) { |
7427 | 1342 |
tmp3 = new_register(objectType); |
1343 |
} |
|
1 | 1344 |
__ checkcast(reg, obj.result(), x->klass(), |
7427 | 1345 |
new_register(objectType), new_register(objectType), tmp3, |
1 | 1346 |
x->direct_compare(), info_for_exception, patching_info, stub, |
1347 |
x->profiled_method(), x->profiled_bci()); |
|
1348 |
} |
|
1349 |
||
1350 |
||
1351 |
void LIRGenerator::do_InstanceOf(InstanceOf* x) { |
|
1352 |
LIRItem obj(x->obj(), this); |
|
1353 |
||
1354 |
// result and test object may not be in same register |
|
1355 |
LIR_Opr reg = rlock_result(x); |
|
1356 |
CodeEmitInfo* patching_info = NULL; |
|
1357 |
if ((!x->klass()->is_loaded() || PatchALot)) { |
|
1358 |
// must do this before locking the destination register as an oop register |
|
1359 |
patching_info = state_for(x, x->state_before()); |
|
1360 |
} |
|
1361 |
obj.load_item(); |
|
7427 | 1362 |
LIR_Opr tmp3 = LIR_OprFact::illegalOpr; |
19979
ebe1dbb6e1aa
8015107: NPG: Use consistent naming for metaspace concepts
ehelin
parents:
18507
diff
changeset
|
1363 |
if (!x->klass()->is_loaded() || UseCompressedClassPointers) { |
7427 | 1364 |
tmp3 = new_register(objectType); |
1365 |
} |
|
1 | 1366 |
__ instanceof(reg, obj.result(), x->klass(), |
7427 | 1367 |
new_register(objectType), new_register(objectType), tmp3, |
6461
cfc616b49f58
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
6453
diff
changeset
|
1368 |
x->direct_compare(), patching_info, x->profiled_method(), x->profiled_bci()); |
1 | 1369 |
} |
1370 |
||
1371 |
||
1372 |
void LIRGenerator::do_If(If* x) { |
|
1373 |
assert(x->number_of_sux() == 2, "inconsistency"); |
|
1374 |
ValueTag tag = x->x()->type()->tag(); |
|
1375 |
bool is_safepoint = x->is_safepoint(); |
|
1376 |
||
1377 |
If::Condition cond = x->cond(); |
|
1378 |
||
1379 |
LIRItem xitem(x->x(), this); |
|
1380 |
LIRItem yitem(x->y(), this); |
|
1381 |
LIRItem* xin = &xitem; |
|
1382 |
LIRItem* yin = &yitem; |
|
1383 |
||
1384 |
if (tag == longTag) { |
|
1385 |
// for longs, only conditions "eql", "neq", "lss", "geq" are valid; |
|
1386 |
// mirror for other conditions |
|
1387 |
if (cond == If::gtr || cond == If::leq) { |
|
1388 |
cond = Instruction::mirror(cond); |
|
1389 |
xin = &yitem; |
|
1390 |
yin = &xitem; |
|
1391 |
} |
|
1392 |
xin->set_destroys_register(); |
|
1393 |
} |
|
1394 |
xin->load_item(); |
|
1395 |
if (tag == longTag && yin->is_constant() && yin->get_jlong_constant() == 0 && (cond == If::eql || cond == If::neq)) { |
|
1396 |
// inline long zero |
|
1397 |
yin->dont_load_item(); |
|
1398 |
} else if (tag == longTag || tag == floatTag || tag == doubleTag) { |
|
1399 |
// longs cannot handle constants at right side |
|
1400 |
yin->load_item(); |
|
1401 |
} else { |
|
1402 |
yin->dont_load_item(); |
|
1403 |
} |
|
1404 |
||
1405 |
// add safepoint before generating condition code so it can be recomputed |
|
1406 |
if (x->is_safepoint()) { |
|
1407 |
// increment backedge counter if needed |
|
6453 | 1408 |
increment_backedge_counter(state_for(x, x->state_before()), x->profiled_bci()); |
49027
8dc742d9bbab
8195112: x86 (32 bit): implementation for Thread-local handshakes
mdoerr
parents:
48807
diff
changeset
|
1409 |
__ safepoint(safepoint_poll_register(), state_for(x, x->state_before())); |
1 | 1410 |
} |
1411 |
set_no_result(x); |
|
1412 |
||
1413 |
LIR_Opr left = xin->result(); |
|
1414 |
LIR_Opr right = yin->result(); |
|
1415 |
__ cmp(lir_cond(cond), left, right); |
|
6453 | 1416 |
// Generate branch profiling. Profiling code doesn't kill flags. |
1 | 1417 |
profile_branch(x, cond); |
1418 |
move_to_phi(x->state()); |
|
1419 |
if (x->x()->type()->is_float_kind()) { |
|
1420 |
__ branch(lir_cond(cond), right->type(), x->tsux(), x->usux()); |
|
1421 |
} else { |
|
1422 |
__ branch(lir_cond(cond), right->type(), x->tsux()); |
|
1423 |
} |
|
1424 |
assert(x->default_sux() == x->fsux(), "wrong destination above"); |
|
1425 |
__ jump(x->default_sux()); |
|
1426 |
} |
|
1427 |
||
1428 |
||
1429 |
LIR_Opr LIRGenerator::getThreadPointer() { |
|
1066 | 1430 |
#ifdef _LP64 |
1431 |
return FrameMap::as_pointer_opr(r15_thread); |
|
1432 |
#else |
|
1 | 1433 |
LIR_Opr result = new_register(T_INT); |
1434 |
__ get_thread(result); |
|
1435 |
return result; |
|
1066 | 1436 |
#endif // |
1 | 1437 |
} |
1438 |
||
1439 |
void LIRGenerator::trace_block_entry(BlockBegin* block) { |
|
1440 |
store_stack_parameter(LIR_OprFact::intConst(block->block_id()), in_ByteSize(0)); |
|
1441 |
LIR_OprList* args = new LIR_OprList(); |
|
1442 |
address func = CAST_FROM_FN_PTR(address, Runtime1::trace_block_entry); |
|
1443 |
__ call_runtime_leaf(func, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, args); |
|
1444 |
} |
|
1445 |
||
1446 |
||
1447 |
void LIRGenerator::volatile_field_store(LIR_Opr value, LIR_Address* address, |
|
1448 |
CodeEmitInfo* info) { |
|
1449 |
if (address->type() == T_LONG) { |
|
1450 |
address = new LIR_Address(address->base(), |
|
1451 |
address->index(), address->scale(), |
|
1452 |
address->disp(), T_DOUBLE); |
|
1453 |
// Transfer the value atomically by using FP moves. This means |
|
1454 |
// the value has to be moved between CPU and FPU registers. It |
|
1455 |
// always has to be moved through spill slot since there's no |
|
1456 |
// quick way to pack the value into an SSE register. |
|
1457 |
LIR_Opr temp_double = new_register(T_DOUBLE); |
|
1458 |
LIR_Opr spill = new_register(T_LONG); |
|
1459 |
set_vreg_flag(spill, must_start_in_memory); |
|
1460 |
__ move(value, spill); |
|
1461 |
__ volatile_move(spill, temp_double, T_LONG); |
|
1462 |
__ volatile_move(temp_double, LIR_OprFact::address(address), T_LONG, info); |
|
1463 |
} else { |
|
1464 |
__ store(value, address, info); |
|
1465 |
} |
|
1466 |
} |
|
1467 |
||
1468 |
void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result, |
|
1469 |
CodeEmitInfo* info) { |
|
1470 |
if (address->type() == T_LONG) { |
|
1471 |
address = new LIR_Address(address->base(), |
|
1472 |
address->index(), address->scale(), |
|
1473 |
address->disp(), T_DOUBLE); |
|
1474 |
// Transfer the value atomically by using FP moves. This means |
|
1475 |
// the value has to be moved between CPU and FPU registers. In |
|
1476 |
// SSE0 and SSE1 mode it has to be moved through spill slot but in |
|
1477 |
// SSE2+ mode it can be moved directly. |
|
1478 |
LIR_Opr temp_double = new_register(T_DOUBLE); |
|
1479 |
__ volatile_move(LIR_OprFact::address(address), temp_double, T_LONG, info); |
|
1480 |
__ volatile_move(temp_double, result, T_LONG); |
|
1481 |
if (UseSSE < 2) { |
|
1482 |
// no spill slot needed in SSE2 mode because xmm->cpu register move is possible |
|
1483 |
set_vreg_flag(result, must_start_in_memory); |
|
1484 |
} |
|
1485 |
} else { |
|
1486 |
__ load(address, result, info); |
|
1487 |
} |
|
1488 |
} |