author | kvn |
Fri, 23 Dec 2011 15:24:36 -0800 | |
changeset 11434 | c50976508b6b |
parent 11429 | e894217a5d94 |
child 11791 | 3be8cae67887 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
26 |
#define CPU_X86_VM_ASSEMBLER_X86_HPP |
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||
1 | 28 |
class BiasedLockingCounters; |
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||
30 |
// Contains all the definitions needed for x86 assembly code generation. |
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31 |
||
32 |
// Calling convention |
|
33 |
class Argument VALUE_OBJ_CLASS_SPEC { |
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public: |
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enum { |
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#ifdef _LP64 |
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#ifdef _WIN64 |
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38 |
n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) |
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#else |
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n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
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n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) |
|
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#endif // _WIN64 |
|
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n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
|
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n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... |
|
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#else |
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n_register_parameters = 0 // 0 registers used to pass arguments |
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#endif // _LP64 |
|
49 |
}; |
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}; |
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51 |
||
52 |
||
53 |
#ifdef _LP64 |
|
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// Symbolically name the register arguments used by the c calling convention. |
|
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// Windows is different from linux/solaris. So much for standards... |
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56 |
||
57 |
#ifdef _WIN64 |
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||
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REGISTER_DECLARATION(Register, c_rarg0, rcx); |
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REGISTER_DECLARATION(Register, c_rarg1, rdx); |
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REGISTER_DECLARATION(Register, c_rarg2, r8); |
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REGISTER_DECLARATION(Register, c_rarg3, r9); |
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||
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REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
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REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
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#else |
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||
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REGISTER_DECLARATION(Register, c_rarg0, rdi); |
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REGISTER_DECLARATION(Register, c_rarg1, rsi); |
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REGISTER_DECLARATION(Register, c_rarg2, rdx); |
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REGISTER_DECLARATION(Register, c_rarg3, rcx); |
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REGISTER_DECLARATION(Register, c_rarg4, r8); |
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REGISTER_DECLARATION(Register, c_rarg5, r9); |
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REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
79 |
REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); |
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REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); |
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REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); |
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REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); |
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REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); |
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REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); |
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#endif // _WIN64 |
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||
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// Symbolically name the register arguments used by the Java calling convention. |
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// We have control over the convention for java so we can do what we please. |
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// What pleases us is to offset the java calling convention so that when |
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// we call a suitable jni method the arguments are lined up and we don't |
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// have to do little shuffling. A suitable jni method is non-static and a |
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// small number of arguments (two fewer args on windows) |
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// |
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// |-------------------------------------------------------| |
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// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | |
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// |-------------------------------------------------------| |
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// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) |
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// | rdi rsi rdx rcx r8 r9 | solaris/linux |
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// |-------------------------------------------------------| |
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// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | |
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// |-------------------------------------------------------| |
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||
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REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); |
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REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); |
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REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); |
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// Windows runs out of register args here |
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#ifdef _WIN64 |
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REGISTER_DECLARATION(Register, j_rarg3, rdi); |
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REGISTER_DECLARATION(Register, j_rarg4, rsi); |
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#else |
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REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); |
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114 |
REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); |
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115 |
#endif /* _WIN64 */ |
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116 |
REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
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REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
119 |
REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); |
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120 |
REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); |
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REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); |
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REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); |
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REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); |
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REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); |
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125 |
REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); |
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REGISTER_DECLARATION(Register, rscratch1, r10); // volatile |
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REGISTER_DECLARATION(Register, rscratch2, r11); // volatile |
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REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
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REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
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#else |
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// rscratch1 will apear in 32bit code that is dead but of course must compile |
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135 |
// Using noreg ensures if the dead code is incorrectly live and executed it |
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136 |
// will cause an assertion failure |
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#define rscratch1 noreg |
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#define rscratch2 noreg |
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1 | 140 |
#endif // _LP64 |
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||
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// JSR 292 fixed register usages: |
143 |
REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); |
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144 |
||
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// Address is an abstraction used to represent a memory location |
146 |
// using any of the amd64 addressing modes with one object. |
|
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// |
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// Note: A register location is represented via a Register, not |
|
149 |
// via an address for efficiency & simplicity reasons. |
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150 |
||
151 |
class ArrayAddress; |
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152 |
||
153 |
class Address VALUE_OBJ_CLASS_SPEC { |
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public: |
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155 |
enum ScaleFactor { |
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156 |
no_scale = -1, |
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times_1 = 0, |
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times_2 = 1, |
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times_4 = 2, |
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times_8 = 3, |
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times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) |
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}; |
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static ScaleFactor times(int size) { |
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assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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if (size == 8) return times_8; |
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if (size == 4) return times_4; |
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if (size == 2) return times_2; |
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return times_1; |
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} |
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static int scale_size(ScaleFactor scale) { |
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assert(scale != no_scale, ""); |
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assert(((1 << (int)times_1) == 1 && |
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(1 << (int)times_2) == 2 && |
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(1 << (int)times_4) == 4 && |
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(1 << (int)times_8) == 8), ""); |
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return (1 << (int)scale); |
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} |
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private: |
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180 |
Register _base; |
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181 |
Register _index; |
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182 |
ScaleFactor _scale; |
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183 |
int _disp; |
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184 |
RelocationHolder _rspec; |
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185 |
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1066 | 186 |
// Easily misused constructors make them private |
187 |
// %%% can we make these go away? |
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188 |
NOT_LP64(Address(address loc, RelocationHolder spec);) |
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189 |
Address(int disp, address loc, relocInfo::relocType rtype); |
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190 |
Address(int disp, address loc, RelocationHolder spec); |
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1 | 191 |
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192 |
public: |
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1066 | 193 |
|
194 |
int disp() { return _disp; } |
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1 | 195 |
// creation |
196 |
Address() |
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197 |
: _base(noreg), |
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198 |
_index(noreg), |
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199 |
_scale(no_scale), |
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200 |
_disp(0) { |
|
201 |
} |
|
202 |
||
203 |
// No default displacement otherwise Register can be implicitly |
|
204 |
// converted to 0(Register) which is quite a different animal. |
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205 |
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206 |
Address(Register base, int disp) |
|
207 |
: _base(base), |
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208 |
_index(noreg), |
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209 |
_scale(no_scale), |
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210 |
_disp(disp) { |
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211 |
} |
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212 |
||
213 |
Address(Register base, Register index, ScaleFactor scale, int disp = 0) |
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214 |
: _base (base), |
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215 |
_index(index), |
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216 |
_scale(scale), |
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217 |
_disp (disp) { |
|
218 |
assert(!index->is_valid() == (scale == Address::no_scale), |
|
219 |
"inconsistent address"); |
|
220 |
} |
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221 |
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Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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: _base (base), |
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_index(index.register_or_noreg()), |
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_scale(scale), |
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_disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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if (!index.is_register()) scale = Address::no_scale; |
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assert(!_index->is_valid() == (scale == Address::no_scale), |
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"inconsistent address"); |
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} |
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|
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Address plus_disp(int disp) const { |
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Address a = (*this); |
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a._disp += disp; |
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return a; |
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236 |
} |
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Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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238 |
Address a = (*this); |
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a._disp += disp.constant_or_zero() * scale_size(scale); |
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240 |
if (disp.is_register()) { |
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assert(!a.index()->is_valid(), "competing indexes"); |
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a._index = disp.as_register(); |
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a._scale = scale; |
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} |
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return a; |
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246 |
} |
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bool is_same_address(Address a) const { |
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// disregard _rspec |
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return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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} |
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|
1 | 252 |
// The following two overloads are used in connection with the |
253 |
// ByteSize type (see sizes.hpp). They simplify the use of |
|
254 |
// ByteSize'd arguments in assembly code. Note that their equivalent |
|
255 |
// for the optimized build are the member functions with int disp |
|
256 |
// argument since ByteSize is mapped to an int type in that case. |
|
257 |
// |
|
258 |
// Note: DO NOT introduce similar overloaded functions for WordSize |
|
259 |
// arguments as in the optimized mode, both ByteSize and WordSize |
|
260 |
// are mapped to the same type and thus the compiler cannot make a |
|
261 |
// distinction anymore (=> compiler errors). |
|
262 |
||
263 |
#ifdef ASSERT |
|
264 |
Address(Register base, ByteSize disp) |
|
265 |
: _base(base), |
|
266 |
_index(noreg), |
|
267 |
_scale(no_scale), |
|
268 |
_disp(in_bytes(disp)) { |
|
269 |
} |
|
270 |
||
271 |
Address(Register base, Register index, ScaleFactor scale, ByteSize disp) |
|
272 |
: _base(base), |
|
273 |
_index(index), |
|
274 |
_scale(scale), |
|
275 |
_disp(in_bytes(disp)) { |
|
276 |
assert(!index->is_valid() == (scale == Address::no_scale), |
|
277 |
"inconsistent address"); |
|
278 |
} |
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Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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: _base (base), |
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6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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diff
changeset
|
282 |
_index(index.register_or_noreg()), |
09c7f703773b
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diff
changeset
|
283 |
_scale(scale), |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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diff
changeset
|
284 |
_disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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parents:
1500
diff
changeset
|
285 |
if (!index.is_register()) scale = Address::no_scale; |
09c7f703773b
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diff
changeset
|
286 |
assert(!_index->is_valid() == (scale == Address::no_scale), |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
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parents:
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diff
changeset
|
287 |
"inconsistent address"); |
09c7f703773b
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jrose
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diff
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|
288 |
} |
09c7f703773b
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changeset
|
289 |
|
1 | 290 |
#endif // ASSERT |
291 |
||
292 |
// accessors |
|
1374
4c24294029a9
6711316: Open source the Garbage-First garbage collector
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diff
changeset
|
293 |
bool uses(Register reg) const { return _base == reg || _index == reg; } |
4c24294029a9
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diff
changeset
|
294 |
Register base() const { return _base; } |
4c24294029a9
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|
295 |
Register index() const { return _index; } |
4c24294029a9
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|
296 |
ScaleFactor scale() const { return _scale; } |
4c24294029a9
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changeset
|
297 |
int disp() const { return _disp; } |
1 | 298 |
|
299 |
// Convert the raw encoding form into the form expected by the constructor for |
|
300 |
// Address. An index of 4 (rsp) corresponds to having no index, so convert |
|
301 |
// that to noreg for the Address constructor. |
|
2150 | 302 |
static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
1 | 303 |
|
304 |
static Address make_array(ArrayAddress); |
|
305 |
||
306 |
private: |
|
307 |
bool base_needs_rex() const { |
|
308 |
return _base != noreg && _base->encoding() >= 8; |
|
309 |
} |
|
310 |
||
311 |
bool index_needs_rex() const { |
|
312 |
return _index != noreg &&_index->encoding() >= 8; |
|
313 |
} |
|
314 |
||
315 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
|
316 |
||
317 |
friend class Assembler; |
|
318 |
friend class MacroAssembler; |
|
319 |
friend class LIR_Assembler; // base/index/scale/disp |
|
320 |
}; |
|
321 |
||
322 |
// |
|
323 |
// AddressLiteral has been split out from Address because operands of this type |
|
324 |
// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out |
|
325 |
// the few instructions that need to deal with address literals are unique and the |
|
326 |
// MacroAssembler does not have to implement every instruction in the Assembler |
|
327 |
// in order to search for address literals that may need special handling depending |
|
328 |
// on the instruction and the platform. As small step on the way to merging i486/amd64 |
|
329 |
// directories. |
|
330 |
// |
|
331 |
class AddressLiteral VALUE_OBJ_CLASS_SPEC { |
|
332 |
friend class ArrayAddress; |
|
333 |
RelocationHolder _rspec; |
|
334 |
// Typically we use AddressLiterals we want to use their rval |
|
335 |
// However in some situations we want the lval (effect address) of the item. |
|
336 |
// We provide a special factory for making those lvals. |
|
337 |
bool _is_lval; |
|
338 |
||
339 |
// If the target is far we'll need to load the ea of this to |
|
340 |
// a register to reach it. Otherwise if near we can do rip |
|
341 |
// relative addressing. |
|
342 |
||
343 |
address _target; |
|
344 |
||
345 |
protected: |
|
346 |
// creation |
|
347 |
AddressLiteral() |
|
348 |
: _is_lval(false), |
|
349 |
_target(NULL) |
|
350 |
{} |
|
351 |
||
352 |
public: |
|
353 |
||
354 |
||
355 |
AddressLiteral(address target, relocInfo::relocType rtype); |
|
356 |
||
357 |
AddressLiteral(address target, RelocationHolder const& rspec) |
|
358 |
: _rspec(rspec), |
|
359 |
_is_lval(false), |
|
360 |
_target(target) |
|
361 |
{} |
|
362 |
||
363 |
AddressLiteral addr() { |
|
364 |
AddressLiteral ret = *this; |
|
365 |
ret._is_lval = true; |
|
366 |
return ret; |
|
367 |
} |
|
368 |
||
369 |
||
370 |
private: |
|
371 |
||
372 |
address target() { return _target; } |
|
373 |
bool is_lval() { return _is_lval; } |
|
374 |
||
375 |
relocInfo::relocType reloc() const { return _rspec.type(); } |
|
376 |
const RelocationHolder& rspec() const { return _rspec; } |
|
377 |
||
378 |
friend class Assembler; |
|
379 |
friend class MacroAssembler; |
|
380 |
friend class Address; |
|
381 |
friend class LIR_Assembler; |
|
382 |
}; |
|
383 |
||
384 |
// Convience classes |
|
385 |
class RuntimeAddress: public AddressLiteral { |
|
386 |
||
387 |
public: |
|
388 |
||
389 |
RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} |
|
390 |
||
391 |
}; |
|
392 |
||
393 |
class OopAddress: public AddressLiteral { |
|
394 |
||
395 |
public: |
|
396 |
||
397 |
OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} |
|
398 |
||
399 |
}; |
|
400 |
||
401 |
class ExternalAddress: public AddressLiteral { |
|
9111
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
402 |
private: |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
403 |
static relocInfo::relocType reloc_for_target(address target) { |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
404 |
// Sometimes ExternalAddress is used for values which aren't |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
405 |
// exactly addresses, like the card table base. |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
406 |
// external_word_type can't be used for values in the first page |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
407 |
// so just skip the reloc in that case. |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
408 |
return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
409 |
} |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
410 |
|
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
411 |
public: |
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
412 |
|
c100c09c66f2
6777083: assert(target != __null,"must not be null")
never
parents:
8882
diff
changeset
|
413 |
ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
1 | 414 |
|
415 |
}; |
|
416 |
||
417 |
class InternalAddress: public AddressLiteral { |
|
418 |
||
419 |
public: |
|
420 |
||
421 |
InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} |
|
422 |
||
423 |
}; |
|
424 |
||
425 |
// x86 can do array addressing as a single operation since disp can be an absolute |
|
426 |
// address amd64 can't. We create a class that expresses the concept but does extra |
|
427 |
// magic on amd64 to get the final result |
|
428 |
||
429 |
class ArrayAddress VALUE_OBJ_CLASS_SPEC { |
|
430 |
private: |
|
431 |
||
432 |
AddressLiteral _base; |
|
433 |
Address _index; |
|
434 |
||
435 |
public: |
|
436 |
||
437 |
ArrayAddress() {}; |
|
438 |
ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; |
|
439 |
AddressLiteral base() { return _base; } |
|
440 |
Address index() { return _index; } |
|
441 |
||
442 |
}; |
|
443 |
||
1066 | 444 |
const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
1 | 445 |
|
446 |
// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction |
|
447 |
// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write |
|
448 |
// is what you get. The Assembler is generating code into a CodeBuffer. |
|
449 |
||
450 |
class Assembler : public AbstractAssembler { |
|
451 |
friend class AbstractAssembler; // for the non-virtual hack |
|
452 |
friend class LIR_Assembler; // as_Address() |
|
1066 | 453 |
friend class StubGenerator; |
1 | 454 |
|
455 |
public: |
|
456 |
enum Condition { // The x86 condition codes used for conditional jumps/moves. |
|
457 |
zero = 0x4, |
|
458 |
notZero = 0x5, |
|
459 |
equal = 0x4, |
|
460 |
notEqual = 0x5, |
|
461 |
less = 0xc, |
|
462 |
lessEqual = 0xe, |
|
463 |
greater = 0xf, |
|
464 |
greaterEqual = 0xd, |
|
465 |
below = 0x2, |
|
466 |
belowEqual = 0x6, |
|
467 |
above = 0x7, |
|
468 |
aboveEqual = 0x3, |
|
469 |
overflow = 0x0, |
|
470 |
noOverflow = 0x1, |
|
471 |
carrySet = 0x2, |
|
472 |
carryClear = 0x3, |
|
473 |
negative = 0x8, |
|
474 |
positive = 0x9, |
|
475 |
parity = 0xa, |
|
476 |
noParity = 0xb |
|
477 |
}; |
|
478 |
||
479 |
enum Prefix { |
|
480 |
// segment overrides |
|
481 |
CS_segment = 0x2e, |
|
482 |
SS_segment = 0x36, |
|
483 |
DS_segment = 0x3e, |
|
484 |
ES_segment = 0x26, |
|
485 |
FS_segment = 0x64, |
|
486 |
GS_segment = 0x65, |
|
487 |
||
488 |
REX = 0x40, |
|
489 |
||
490 |
REX_B = 0x41, |
|
491 |
REX_X = 0x42, |
|
492 |
REX_XB = 0x43, |
|
493 |
REX_R = 0x44, |
|
494 |
REX_RB = 0x45, |
|
495 |
REX_RX = 0x46, |
|
496 |
REX_RXB = 0x47, |
|
497 |
||
498 |
REX_W = 0x48, |
|
499 |
||
500 |
REX_WB = 0x49, |
|
501 |
REX_WX = 0x4A, |
|
502 |
REX_WXB = 0x4B, |
|
503 |
REX_WR = 0x4C, |
|
504 |
REX_WRB = 0x4D, |
|
505 |
REX_WRX = 0x4E, |
|
11427 | 506 |
REX_WRXB = 0x4F, |
507 |
||
508 |
VEX_3bytes = 0xC4, |
|
509 |
VEX_2bytes = 0xC5 |
|
510 |
}; |
|
511 |
||
512 |
enum VexPrefix { |
|
513 |
VEX_B = 0x20, |
|
514 |
VEX_X = 0x40, |
|
515 |
VEX_R = 0x80, |
|
516 |
VEX_W = 0x80 |
|
517 |
}; |
|
518 |
||
519 |
enum VexSimdPrefix { |
|
520 |
VEX_SIMD_NONE = 0x0, |
|
521 |
VEX_SIMD_66 = 0x1, |
|
522 |
VEX_SIMD_F3 = 0x2, |
|
523 |
VEX_SIMD_F2 = 0x3 |
|
524 |
}; |
|
525 |
||
526 |
enum VexOpcode { |
|
527 |
VEX_OPCODE_NONE = 0x0, |
|
528 |
VEX_OPCODE_0F = 0x1, |
|
529 |
VEX_OPCODE_0F_38 = 0x2, |
|
530 |
VEX_OPCODE_0F_3A = 0x3 |
|
1 | 531 |
}; |
532 |
||
533 |
enum WhichOperand { |
|
534 |
// input to locate_operand, and format code for relocations |
|
1066 | 535 |
imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
1 | 536 |
disp32_operand = 1, // embedded 32-bit displacement or address |
537 |
call32_operand = 2, // embedded 32-bit self-relative displacement |
|
1066 | 538 |
#ifndef _LP64 |
1 | 539 |
_WhichOperand_limit = 3 |
1066 | 540 |
#else |
541 |
narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop |
|
542 |
_WhichOperand_limit = 4 |
|
543 |
#endif |
|
1 | 544 |
}; |
545 |
||
1066 | 546 |
|
547 |
||
548 |
// NOTE: The general philopsophy of the declarations here is that 64bit versions |
|
549 |
// of instructions are freely declared without the need for wrapping them an ifdef. |
|
550 |
// (Some dangerous instructions are ifdef's out of inappropriate jvm's.) |
|
551 |
// In the .cpp file the implementations are wrapped so that they are dropped out |
|
552 |
// of the resulting jvm. This is done mostly to keep the footprint of KERNEL |
|
553 |
// to the size it was prior to merging up the 32bit and 64bit assemblers. |
|
554 |
// |
|
555 |
// This does mean you'll get a linker/runtime error if you use a 64bit only instruction |
|
556 |
// in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. |
|
557 |
||
558 |
private: |
|
559 |
||
560 |
||
561 |
// 64bit prefixes |
|
562 |
int prefix_and_encode(int reg_enc, bool byteinst = false); |
|
563 |
int prefixq_and_encode(int reg_enc); |
|
564 |
||
565 |
int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); |
|
566 |
int prefixq_and_encode(int dst_enc, int src_enc); |
|
567 |
||
568 |
void prefix(Register reg); |
|
569 |
void prefix(Address adr); |
|
570 |
void prefixq(Address adr); |
|
571 |
||
572 |
void prefix(Address adr, Register reg, bool byteinst = false); |
|
11427 | 573 |
void prefix(Address adr, XMMRegister reg); |
1066 | 574 |
void prefixq(Address adr, Register reg); |
11427 | 575 |
void prefixq(Address adr, XMMRegister reg); |
1066 | 576 |
|
577 |
void prefetch_prefix(Address src); |
|
578 |
||
11427 | 579 |
void rex_prefix(Address adr, XMMRegister xreg, |
580 |
VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
|
581 |
int rex_prefix_and_encode(int dst_enc, int src_enc, |
|
582 |
VexSimdPrefix pre, VexOpcode opc, bool rex_w); |
|
583 |
||
584 |
void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, |
|
585 |
int nds_enc, VexSimdPrefix pre, VexOpcode opc, |
|
586 |
bool vector256); |
|
587 |
||
588 |
void vex_prefix(Address adr, int nds_enc, int xreg_enc, |
|
589 |
VexSimdPrefix pre, VexOpcode opc, |
|
590 |
bool vex_w, bool vector256); |
|
591 |
||
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
592 |
void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
593 |
VexSimdPrefix pre, bool vector256 = false) { |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
594 |
vex_prefix(src, nds->encoding(), dst->encoding(), |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
595 |
pre, VEX_OPCODE_0F, false, vector256); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
596 |
} |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
597 |
|
11427 | 598 |
int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, |
599 |
VexSimdPrefix pre, VexOpcode opc, |
|
600 |
bool vex_w, bool vector256); |
|
601 |
||
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
602 |
int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
603 |
VexSimdPrefix pre, bool vector256 = false) { |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
604 |
return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
605 |
pre, VEX_OPCODE_0F, false, vector256); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
606 |
} |
11427 | 607 |
|
608 |
void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, |
|
609 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, |
|
610 |
bool rex_w = false, bool vector256 = false); |
|
611 |
||
612 |
void simd_prefix(XMMRegister dst, Address src, |
|
613 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
614 |
simd_prefix(dst, xnoreg, src, pre, opc); |
|
615 |
} |
|
616 |
void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { |
|
617 |
simd_prefix(src, dst, pre); |
|
618 |
} |
|
619 |
void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, |
|
620 |
VexSimdPrefix pre) { |
|
621 |
bool rex_w = true; |
|
622 |
simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); |
|
623 |
} |
|
624 |
||
625 |
||
626 |
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, |
|
627 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, |
|
628 |
bool rex_w = false, bool vector256 = false); |
|
629 |
||
630 |
int simd_prefix_and_encode(XMMRegister dst, XMMRegister src, |
|
631 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
632 |
return simd_prefix_and_encode(dst, xnoreg, src, pre, opc); |
|
633 |
} |
|
634 |
||
635 |
// Move/convert 32-bit integer value. |
|
636 |
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, |
|
637 |
VexSimdPrefix pre) { |
|
638 |
// It is OK to cast from Register to XMMRegister to pass argument here |
|
639 |
// since only encoding is used in simd_prefix_and_encode() and number of |
|
640 |
// Gen and Xmm registers are the same. |
|
641 |
return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); |
|
642 |
} |
|
643 |
int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { |
|
644 |
return simd_prefix_and_encode(dst, xnoreg, src, pre); |
|
645 |
} |
|
646 |
int simd_prefix_and_encode(Register dst, XMMRegister src, |
|
647 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
648 |
return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); |
|
649 |
} |
|
650 |
||
651 |
// Move/convert 64-bit integer value. |
|
652 |
int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, |
|
653 |
VexSimdPrefix pre) { |
|
654 |
bool rex_w = true; |
|
655 |
return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); |
|
656 |
} |
|
657 |
int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { |
|
658 |
return simd_prefix_and_encode_q(dst, xnoreg, src, pre); |
|
659 |
} |
|
660 |
int simd_prefix_and_encode_q(Register dst, XMMRegister src, |
|
661 |
VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { |
|
662 |
bool rex_w = true; |
|
663 |
return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); |
|
664 |
} |
|
665 |
||
1066 | 666 |
// Helper functions for groups of instructions |
667 |
void emit_arith_b(int op1, int op2, Register dst, int imm8); |
|
668 |
||
669 |
void emit_arith(int op1, int op2, Register dst, int32_t imm32); |
|
670 |
// only 32bit?? |
|
671 |
void emit_arith(int op1, int op2, Register dst, jobject obj); |
|
672 |
void emit_arith(int op1, int op2, Register dst, Register src); |
|
673 |
||
674 |
void emit_operand(Register reg, |
|
675 |
Register base, Register index, Address::ScaleFactor scale, |
|
676 |
int disp, |
|
677 |
RelocationHolder const& rspec, |
|
678 |
int rip_relative_correction = 0); |
|
679 |
||
680 |
void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); |
|
681 |
||
682 |
// operands that only take the original 32bit registers |
|
683 |
void emit_operand32(Register reg, Address adr); |
|
684 |
||
685 |
void emit_operand(XMMRegister reg, |
|
686 |
Register base, Register index, Address::ScaleFactor scale, |
|
687 |
int disp, |
|
688 |
RelocationHolder const& rspec); |
|
689 |
||
690 |
void emit_operand(XMMRegister reg, Address adr); |
|
691 |
||
692 |
void emit_operand(MMXRegister reg, Address adr); |
|
693 |
||
694 |
// workaround gcc (3.2.1-7) bug |
|
695 |
void emit_operand(Address adr, MMXRegister reg); |
|
696 |
||
697 |
||
698 |
// Immediate-to-memory forms |
|
699 |
void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); |
|
700 |
||
701 |
void emit_farith(int b1, int b2, int i); |
|
702 |
||
703 |
||
704 |
protected: |
|
705 |
#ifdef ASSERT |
|
706 |
void check_relocation(RelocationHolder const& rspec, int format); |
|
707 |
#endif |
|
708 |
||
709 |
inline void emit_long64(jlong x); |
|
710 |
||
711 |
void emit_data(jint data, relocInfo::relocType rtype, int format); |
|
712 |
void emit_data(jint data, RelocationHolder const& rspec, int format); |
|
713 |
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); |
|
714 |
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); |
|
715 |
||
716 |
bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); |
|
717 |
||
718 |
// These are all easily abused and hence protected |
|
719 |
||
720 |
// 32BIT ONLY SECTION |
|
721 |
#ifndef _LP64 |
|
722 |
// Make these disappear in 64bit mode since they would never be correct |
|
723 |
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
724 |
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
725 |
||
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
726 |
void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
1066 | 727 |
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
728 |
||
729 |
void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
|
730 |
#else |
|
731 |
// 64BIT ONLY SECTION |
|
732 |
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
733 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
734 |
void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
735 |
void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
736 |
|
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
737 |
void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
738 |
void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
1066 | 739 |
#endif // _LP64 |
740 |
||
741 |
// These are unique in that we are ensured by the caller that the 32bit |
|
742 |
// relative in these instructions will always be able to reach the potentially |
|
743 |
// 64bit address described by entry. Since they can take a 64bit address they |
|
744 |
// don't have the 32 suffix like the other instructions in this class. |
|
745 |
||
746 |
void call_literal(address entry, RelocationHolder const& rspec); |
|
747 |
void jmp_literal(address entry, RelocationHolder const& rspec); |
|
748 |
||
749 |
// Avoid using directly section |
|
750 |
// Instructions in this section are actually usable by anyone without danger |
|
751 |
// of failure but have performance issues that are addressed my enhanced |
|
752 |
// instructions which will do the proper thing base on the particular cpu. |
|
753 |
// We protect them because we don't trust you... |
|
754 |
||
755 |
// Don't use next inc() and dec() methods directly. INC & DEC instructions |
|
756 |
// could cause a partial flag stall since they don't set CF flag. |
|
757 |
// Use MacroAssembler::decrement() & MacroAssembler::increment() methods |
|
758 |
// which call inc() & dec() or add() & sub() in accordance with |
|
759 |
// the product flag UseIncDec value. |
|
760 |
||
761 |
void decl(Register dst); |
|
762 |
void decl(Address dst); |
|
763 |
void decq(Register dst); |
|
764 |
void decq(Address dst); |
|
765 |
||
766 |
void incl(Register dst); |
|
767 |
void incl(Address dst); |
|
768 |
void incq(Register dst); |
|
769 |
void incq(Address dst); |
|
770 |
||
771 |
// New cpus require use of movsd and movss to avoid partial register stall |
|
772 |
// when loading from memory. But for old Opteron use movlpd instead of movsd. |
|
773 |
// The selection is done in MacroAssembler::movdbl() and movflt(). |
|
774 |
||
775 |
// Move Scalar Single-Precision Floating-Point Values |
|
776 |
void movss(XMMRegister dst, Address src); |
|
777 |
void movss(XMMRegister dst, XMMRegister src); |
|
778 |
void movss(Address dst, XMMRegister src); |
|
779 |
||
780 |
// Move Scalar Double-Precision Floating-Point Values |
|
781 |
void movsd(XMMRegister dst, Address src); |
|
782 |
void movsd(XMMRegister dst, XMMRegister src); |
|
783 |
void movsd(Address dst, XMMRegister src); |
|
784 |
void movlpd(XMMRegister dst, Address src); |
|
785 |
||
786 |
// New cpus require use of movaps and movapd to avoid partial register stall |
|
787 |
// when moving between registers. |
|
788 |
void movaps(XMMRegister dst, XMMRegister src); |
|
789 |
void movapd(XMMRegister dst, XMMRegister src); |
|
790 |
||
791 |
// End avoid using directly |
|
792 |
||
793 |
||
794 |
// Instruction prefixes |
|
795 |
void prefix(Prefix p); |
|
796 |
||
1 | 797 |
public: |
798 |
||
799 |
// Creation |
|
800 |
Assembler(CodeBuffer* code) : AbstractAssembler(code) {} |
|
801 |
||
802 |
// Decoding |
|
803 |
static address locate_operand(address inst, WhichOperand which); |
|
804 |
static address locate_next_instruction(address inst); |
|
805 |
||
1066 | 806 |
// Utilities |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8494
diff
changeset
|
807 |
static bool is_polling_page_far() NOT_LP64({ return false;}); |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
8494
diff
changeset
|
808 |
|
1066 | 809 |
// Generic instructions |
810 |
// Does 32bit or 64bit as needed for the platform. In some sense these |
|
811 |
// belong in macro assembler but there is no need for both varieties to exist |
|
812 |
||
813 |
void lea(Register dst, Address src); |
|
814 |
||
815 |
void mov(Register dst, Register src); |
|
816 |
||
817 |
void pusha(); |
|
818 |
void popa(); |
|
819 |
||
820 |
void pushf(); |
|
821 |
void popf(); |
|
822 |
||
823 |
void push(int32_t imm32); |
|
824 |
||
825 |
void push(Register src); |
|
826 |
||
827 |
void pop(Register dst); |
|
828 |
||
829 |
// These are dummies to prevent surprise implicit conversions to Register |
|
830 |
void push(void* v); |
|
831 |
void pop(void* v); |
|
832 |
||
833 |
// These do register sized moves/scans |
|
834 |
void rep_mov(); |
|
835 |
void rep_set(); |
|
836 |
void repne_scan(); |
|
837 |
#ifdef _LP64 |
|
838 |
void repne_scanl(); |
|
839 |
#endif |
|
840 |
||
841 |
// Vanilla instructions in lexical order |
|
842 |
||
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
843 |
void adcl(Address dst, int32_t imm32); |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
844 |
void adcl(Address dst, Register src); |
1066 | 845 |
void adcl(Register dst, int32_t imm32); |
1 | 846 |
void adcl(Register dst, Address src); |
847 |
void adcl(Register dst, Register src); |
|
848 |
||
1066 | 849 |
void adcq(Register dst, int32_t imm32); |
850 |
void adcq(Register dst, Address src); |
|
851 |
void adcq(Register dst, Register src); |
|
852 |
||
853 |
void addl(Address dst, int32_t imm32); |
|
1 | 854 |
void addl(Address dst, Register src); |
1066 | 855 |
void addl(Register dst, int32_t imm32); |
1 | 856 |
void addl(Register dst, Address src); |
857 |
void addl(Register dst, Register src); |
|
858 |
||
1066 | 859 |
void addq(Address dst, int32_t imm32); |
860 |
void addq(Address dst, Register src); |
|
861 |
void addq(Register dst, int32_t imm32); |
|
862 |
void addq(Register dst, Address src); |
|
863 |
void addq(Register dst, Register src); |
|
864 |
||
1 | 865 |
void addr_nop_4(); |
866 |
void addr_nop_5(); |
|
867 |
void addr_nop_7(); |
|
868 |
void addr_nop_8(); |
|
869 |
||
1066 | 870 |
// Add Scalar Double-Precision Floating-Point Values |
871 |
void addsd(XMMRegister dst, Address src); |
|
872 |
void addsd(XMMRegister dst, XMMRegister src); |
|
873 |
||
874 |
// Add Scalar Single-Precision Floating-Point Values |
|
875 |
void addss(XMMRegister dst, Address src); |
|
876 |
void addss(XMMRegister dst, XMMRegister src); |
|
877 |
||
11427 | 878 |
void andl(Address dst, int32_t imm32); |
1066 | 879 |
void andl(Register dst, int32_t imm32); |
880 |
void andl(Register dst, Address src); |
|
881 |
void andl(Register dst, Register src); |
|
882 |
||
10006 | 883 |
void andq(Address dst, int32_t imm32); |
1066 | 884 |
void andq(Register dst, int32_t imm32); |
885 |
void andq(Register dst, Address src); |
|
886 |
void andq(Register dst, Register src); |
|
887 |
||
888 |
// Bitwise Logical AND of Packed Double-Precision Floating-Point Values |
|
889 |
void andpd(XMMRegister dst, XMMRegister src); |
|
890 |
||
11427 | 891 |
// Bitwise Logical AND of Packed Single-Precision Floating-Point Values |
892 |
void andps(XMMRegister dst, XMMRegister src); |
|
893 |
||
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
894 |
void bsfl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
895 |
void bsrl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
896 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
897 |
#ifdef _LP64 |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
898 |
void bsfq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
899 |
void bsrq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
900 |
#endif |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
901 |
|
1066 | 902 |
void bswapl(Register reg); |
903 |
||
904 |
void bswapq(Register reg); |
|
905 |
||
1 | 906 |
void call(Label& L, relocInfo::relocType rtype); |
907 |
void call(Register reg); // push pc; pc <- reg |
|
908 |
void call(Address adr); // push pc; pc <- adr |
|
909 |
||
1066 | 910 |
void cdql(); |
911 |
||
912 |
void cdqq(); |
|
913 |
||
914 |
void cld() { emit_byte(0xfc); } |
|
915 |
||
916 |
void clflush(Address adr); |
|
917 |
||
918 |
void cmovl(Condition cc, Register dst, Register src); |
|
919 |
void cmovl(Condition cc, Register dst, Address src); |
|
920 |
||
921 |
void cmovq(Condition cc, Register dst, Register src); |
|
922 |
void cmovq(Condition cc, Register dst, Address src); |
|
923 |
||
924 |
||
925 |
void cmpb(Address dst, int imm8); |
|
926 |
||
927 |
void cmpl(Address dst, int32_t imm32); |
|
928 |
||
929 |
void cmpl(Register dst, int32_t imm32); |
|
930 |
void cmpl(Register dst, Register src); |
|
931 |
void cmpl(Register dst, Address src); |
|
932 |
||
933 |
void cmpq(Address dst, int32_t imm32); |
|
934 |
void cmpq(Address dst, Register src); |
|
935 |
||
936 |
void cmpq(Register dst, int32_t imm32); |
|
937 |
void cmpq(Register dst, Register src); |
|
938 |
void cmpq(Register dst, Address src); |
|
939 |
||
940 |
// these are dummies used to catch attempting to convert NULL to Register |
|
941 |
void cmpl(Register dst, void* junk); // dummy |
|
942 |
void cmpq(Register dst, void* junk); // dummy |
|
943 |
||
944 |
void cmpw(Address dst, int imm16); |
|
945 |
||
946 |
void cmpxchg8 (Address adr); |
|
947 |
||
948 |
void cmpxchgl(Register reg, Address adr); |
|
949 |
||
950 |
void cmpxchgq(Register reg, Address adr); |
|
951 |
||
952 |
// Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
|
953 |
void comisd(XMMRegister dst, Address src); |
|
11427 | 954 |
void comisd(XMMRegister dst, XMMRegister src); |
1066 | 955 |
|
956 |
// Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
|
957 |
void comiss(XMMRegister dst, Address src); |
|
11427 | 958 |
void comiss(XMMRegister dst, XMMRegister src); |
1066 | 959 |
|
960 |
// Identify processor type and features |
|
961 |
void cpuid() { |
|
962 |
emit_byte(0x0F); |
|
963 |
emit_byte(0xA2); |
|
964 |
} |
|
965 |
||
966 |
// Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value |
|
967 |
void cvtsd2ss(XMMRegister dst, XMMRegister src); |
|
11427 | 968 |
void cvtsd2ss(XMMRegister dst, Address src); |
1066 | 969 |
|
970 |
// Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value |
|
971 |
void cvtsi2sdl(XMMRegister dst, Register src); |
|
11427 | 972 |
void cvtsi2sdl(XMMRegister dst, Address src); |
1066 | 973 |
void cvtsi2sdq(XMMRegister dst, Register src); |
11427 | 974 |
void cvtsi2sdq(XMMRegister dst, Address src); |
1066 | 975 |
|
976 |
// Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value |
|
977 |
void cvtsi2ssl(XMMRegister dst, Register src); |
|
11427 | 978 |
void cvtsi2ssl(XMMRegister dst, Address src); |
1066 | 979 |
void cvtsi2ssq(XMMRegister dst, Register src); |
11427 | 980 |
void cvtsi2ssq(XMMRegister dst, Address src); |
1066 | 981 |
|
982 |
// Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value |
|
983 |
void cvtdq2pd(XMMRegister dst, XMMRegister src); |
|
984 |
||
985 |
// Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value |
|
986 |
void cvtdq2ps(XMMRegister dst, XMMRegister src); |
|
987 |
||
988 |
// Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value |
|
989 |
void cvtss2sd(XMMRegister dst, XMMRegister src); |
|
11427 | 990 |
void cvtss2sd(XMMRegister dst, Address src); |
1066 | 991 |
|
992 |
// Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer |
|
993 |
void cvttsd2sil(Register dst, Address src); |
|
994 |
void cvttsd2sil(Register dst, XMMRegister src); |
|
995 |
void cvttsd2siq(Register dst, XMMRegister src); |
|
996 |
||
997 |
// Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer |
|
998 |
void cvttss2sil(Register dst, XMMRegister src); |
|
999 |
void cvttss2siq(Register dst, XMMRegister src); |
|
1000 |
||
1001 |
// Divide Scalar Double-Precision Floating-Point Values |
|
1002 |
void divsd(XMMRegister dst, Address src); |
|
1003 |
void divsd(XMMRegister dst, XMMRegister src); |
|
1004 |
||
1005 |
// Divide Scalar Single-Precision Floating-Point Values |
|
1006 |
void divss(XMMRegister dst, Address src); |
|
1007 |
void divss(XMMRegister dst, XMMRegister src); |
|
1008 |
||
1009 |
void emms(); |
|
1010 |
||
1011 |
void fabs(); |
|
1012 |
||
1013 |
void fadd(int i); |
|
1014 |
||
1015 |
void fadd_d(Address src); |
|
1016 |
void fadd_s(Address src); |
|
1017 |
||
1018 |
// "Alternate" versions of x87 instructions place result down in FPU |
|
1019 |
// stack instead of on TOS |
|
1020 |
||
1021 |
void fadda(int i); // "alternate" fadd |
|
1022 |
void faddp(int i = 1); |
|
1023 |
||
1024 |
void fchs(); |
|
1025 |
||
1026 |
void fcom(int i); |
|
1027 |
||
1028 |
void fcomp(int i = 1); |
|
1029 |
void fcomp_d(Address src); |
|
1030 |
void fcomp_s(Address src); |
|
1031 |
||
1032 |
void fcompp(); |
|
1033 |
||
1034 |
void fcos(); |
|
1035 |
||
1036 |
void fdecstp(); |
|
1037 |
||
1038 |
void fdiv(int i); |
|
1039 |
void fdiv_d(Address src); |
|
1040 |
void fdivr_s(Address src); |
|
1041 |
void fdiva(int i); // "alternate" fdiv |
|
1042 |
void fdivp(int i = 1); |
|
1043 |
||
1044 |
void fdivr(int i); |
|
1045 |
void fdivr_d(Address src); |
|
1046 |
void fdiv_s(Address src); |
|
1047 |
||
1048 |
void fdivra(int i); // "alternate" reversed fdiv |
|
1049 |
||
1050 |
void fdivrp(int i = 1); |
|
1051 |
||
1052 |
void ffree(int i = 0); |
|
1053 |
||
1054 |
void fild_d(Address adr); |
|
1055 |
void fild_s(Address adr); |
|
1056 |
||
1057 |
void fincstp(); |
|
1058 |
||
1059 |
void finit(); |
|
1060 |
||
1061 |
void fist_s (Address adr); |
|
1062 |
void fistp_d(Address adr); |
|
1063 |
void fistp_s(Address adr); |
|
1064 |
||
1065 |
void fld1(); |
|
1066 |
||
1067 |
void fld_d(Address adr); |
|
1068 |
void fld_s(Address adr); |
|
1069 |
void fld_s(int index); |
|
1070 |
void fld_x(Address adr); // extended-precision (80-bit) format |
|
1071 |
||
1072 |
void fldcw(Address src); |
|
1073 |
||
1074 |
void fldenv(Address src); |
|
1075 |
||
1076 |
void fldlg2(); |
|
1077 |
||
1078 |
void fldln2(); |
|
1079 |
||
1080 |
void fldz(); |
|
1081 |
||
1082 |
void flog(); |
|
1083 |
void flog10(); |
|
1084 |
||
1085 |
void fmul(int i); |
|
1086 |
||
1087 |
void fmul_d(Address src); |
|
1088 |
void fmul_s(Address src); |
|
1089 |
||
1090 |
void fmula(int i); // "alternate" fmul |
|
1091 |
||
1092 |
void fmulp(int i = 1); |
|
1093 |
||
1094 |
void fnsave(Address dst); |
|
1095 |
||
1096 |
void fnstcw(Address src); |
|
1097 |
||
1098 |
void fnstsw_ax(); |
|
1099 |
||
1100 |
void fprem(); |
|
1101 |
void fprem1(); |
|
1102 |
||
1103 |
void frstor(Address src); |
|
1104 |
||
1105 |
void fsin(); |
|
1106 |
||
1107 |
void fsqrt(); |
|
1108 |
||
1109 |
void fst_d(Address adr); |
|
1110 |
void fst_s(Address adr); |
|
1111 |
||
1112 |
void fstp_d(Address adr); |
|
1113 |
void fstp_d(int index); |
|
1114 |
void fstp_s(Address adr); |
|
1115 |
void fstp_x(Address adr); // extended-precision (80-bit) format |
|
1116 |
||
1117 |
void fsub(int i); |
|
1118 |
void fsub_d(Address src); |
|
1119 |
void fsub_s(Address src); |
|
1120 |
||
1121 |
void fsuba(int i); // "alternate" fsub |
|
1122 |
||
1123 |
void fsubp(int i = 1); |
|
1124 |
||
1125 |
void fsubr(int i); |
|
1126 |
void fsubr_d(Address src); |
|
1127 |
void fsubr_s(Address src); |
|
1128 |
||
1129 |
void fsubra(int i); // "alternate" reversed fsub |
|
1130 |
||
1131 |
void fsubrp(int i = 1); |
|
1132 |
||
1133 |
void ftan(); |
|
1134 |
||
1135 |
void ftst(); |
|
1136 |
||
1137 |
void fucomi(int i = 1); |
|
1138 |
void fucomip(int i = 1); |
|
1139 |
||
1140 |
void fwait(); |
|
1141 |
||
1142 |
void fxch(int i = 1); |
|
1143 |
||
1144 |
void fxrstor(Address src); |
|
1145 |
||
1146 |
void fxsave(Address dst); |
|
1147 |
||
1148 |
void fyl2x(); |
|
1149 |
||
1150 |
void hlt(); |
|
1151 |
||
1152 |
void idivl(Register src); |
|
7121 | 1153 |
void divl(Register src); // Unsigned division |
1066 | 1154 |
|
1155 |
void idivq(Register src); |
|
1156 |
||
1157 |
void imull(Register dst, Register src); |
|
1158 |
void imull(Register dst, Register src, int value); |
|
1159 |
||
1160 |
void imulq(Register dst, Register src); |
|
1161 |
void imulq(Register dst, Register src, int value); |
|
1162 |
||
1 | 1163 |
|
1164 |
// jcc is the generic conditional branch generator to run- |
|
1165 |
// time routines, jcc is used for branches to labels. jcc |
|
1166 |
// takes a branch opcode (cc) and a label (L) and generates |
|
1167 |
// either a backward branch or a forward branch and links it |
|
1168 |
// to the label fixup chain. Usage: |
|
1169 |
// |
|
1170 |
// Label L; // unbound label |
|
1171 |
// jcc(cc, L); // forward branch to unbound label |
|
1172 |
// bind(L); // bind label to the current pc |
|
1173 |
// jcc(cc, L); // backward branch to bound label |
|
1174 |
// bind(L); // illegal: a label may be bound only once |
|
1175 |
// |
|
1176 |
// Note: The same Label can be used for forward and backward branches |
|
1177 |
// but it may be bound only once. |
|
1178 |
||
10264 | 1179 |
void jcc(Condition cc, Label& L, bool maybe_short = true); |
1 | 1180 |
|
1181 |
// Conditional jump to a 8-bit offset to L. |
|
1182 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
1183 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
1184 |
// will occur. |
|
1185 |
void jccb(Condition cc, Label& L); |
|
1186 |
||
1066 | 1187 |
void jmp(Address entry); // pc <- entry |
1188 |
||
1189 |
// Label operations & relative jumps (PPUM Appendix D) |
|
10264 | 1190 |
void jmp(Label& L, bool maybe_short = true); // unconditional jump to L |
1066 | 1191 |
|
1192 |
void jmp(Register entry); // pc <- entry |
|
1193 |
||
1194 |
// Unconditional 8-bit offset jump to L. |
|
1195 |
// WARNING: be very careful using this for forward jumps. If the label is |
|
1196 |
// not bound within an 8-bit offset of this instruction, a run-time error |
|
1197 |
// will occur. |
|
1198 |
void jmpb(Label& L); |
|
1199 |
||
1200 |
void ldmxcsr( Address src ); |
|
1201 |
||
1202 |
void leal(Register dst, Address src); |
|
1203 |
||
1204 |
void leaq(Register dst, Address src); |
|
1205 |
||
1206 |
void lfence() { |
|
1207 |
emit_byte(0x0F); |
|
1208 |
emit_byte(0xAE); |
|
1209 |
emit_byte(0xE8); |
|
1210 |
} |
|
1211 |
||
1212 |
void lock(); |
|
1213 |
||
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1214 |
void lzcntl(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1215 |
|
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1216 |
#ifdef _LP64 |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1217 |
void lzcntq(Register dst, Register src); |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1218 |
#endif |
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2534
diff
changeset
|
1219 |
|
1066 | 1220 |
enum Membar_mask_bits { |
1221 |
StoreStore = 1 << 3, |
|
1222 |
LoadStore = 1 << 2, |
|
1223 |
StoreLoad = 1 << 1, |
|
1224 |
LoadLoad = 1 << 0 |
|
1225 |
}; |
|
1226 |
||
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1227 |
// Serializes memory and blows flags |
1066 | 1228 |
void membar(Membar_mask_bits order_constraint) { |
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1229 |
if (os::is_MP()) { |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1230 |
// We only have to handle StoreLoad |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1231 |
if (order_constraint & StoreLoad) { |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1232 |
// All usable chips support "locked" instructions which suffice |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1233 |
// as barriers, and are much faster than the alternative of |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1234 |
// using cpuid instruction. We use here a locked add [esp],0. |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1235 |
// This is conveniently otherwise a no-op except for blowing |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1236 |
// flags. |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1237 |
// Any change to this code may need to revisit other places in |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1238 |
// the code where this idiom is used, in particular the |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1239 |
// orderAccess code. |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1240 |
lock(); |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1241 |
addl(Address(rsp, 0), 0);// Assert the lock# signal here |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1242 |
} |
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2332
diff
changeset
|
1243 |
} |
1066 | 1244 |
} |
1245 |
||
1246 |
void mfence(); |
|
1247 |
||
1248 |
// Moves |
|
1249 |
||
1250 |
void mov64(Register dst, int64_t imm64); |
|
1251 |
||
1252 |
void movb(Address dst, Register src); |
|
1253 |
void movb(Address dst, int imm8); |
|
1254 |
void movb(Register dst, Address src); |
|
1255 |
||
1256 |
void movdl(XMMRegister dst, Register src); |
|
1257 |
void movdl(Register dst, XMMRegister src); |
|
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1258 |
void movdl(XMMRegister dst, Address src); |
1066 | 1259 |
|
1260 |
// Move Double Quadword |
|
1261 |
void movdq(XMMRegister dst, Register src); |
|
1262 |
void movdq(Register dst, XMMRegister src); |
|
1263 |
||
1264 |
// Move Aligned Double Quadword |
|
1265 |
void movdqa(XMMRegister dst, XMMRegister src); |
|
1266 |
||
1437 | 1267 |
// Move Unaligned Double Quadword |
1268 |
void movdqu(Address dst, XMMRegister src); |
|
1269 |
void movdqu(XMMRegister dst, Address src); |
|
1270 |
void movdqu(XMMRegister dst, XMMRegister src); |
|
1271 |
||
1066 | 1272 |
void movl(Register dst, int32_t imm32); |
1273 |
void movl(Address dst, int32_t imm32); |
|
1274 |
void movl(Register dst, Register src); |
|
1275 |
void movl(Register dst, Address src); |
|
1276 |
void movl(Address dst, Register src); |
|
1277 |
||
1278 |
// These dummies prevent using movl from converting a zero (like NULL) into Register |
|
1279 |
// by giving the compiler two choices it can't resolve |
|
1280 |
||
1281 |
void movl(Address dst, void* junk); |
|
1282 |
void movl(Register dst, void* junk); |
|
1283 |
||
1284 |
#ifdef _LP64 |
|
1285 |
void movq(Register dst, Register src); |
|
1286 |
void movq(Register dst, Address src); |
|
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
1287 |
void movq(Address dst, Register src); |
1066 | 1288 |
#endif |
1289 |
||
1290 |
void movq(Address dst, MMXRegister src ); |
|
1291 |
void movq(MMXRegister dst, Address src ); |
|
1292 |
||
1293 |
#ifdef _LP64 |
|
1294 |
// These dummies prevent using movq from converting a zero (like NULL) into Register |
|
1295 |
// by giving the compiler two choices it can't resolve |
|
1296 |
||
1297 |
void movq(Address dst, void* dummy); |
|
1298 |
void movq(Register dst, void* dummy); |
|
1299 |
#endif |
|
1300 |
||
1301 |
// Move Quadword |
|
1302 |
void movq(Address dst, XMMRegister src); |
|
1303 |
void movq(XMMRegister dst, Address src); |
|
1304 |
||
1305 |
void movsbl(Register dst, Address src); |
|
1306 |
void movsbl(Register dst, Register src); |
|
1307 |
||
1308 |
#ifdef _LP64 |
|
2150 | 1309 |
void movsbq(Register dst, Address src); |
1310 |
void movsbq(Register dst, Register src); |
|
1311 |
||
1066 | 1312 |
// Move signed 32bit immediate to 64bit extending sign |
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
1313 |
void movslq(Address dst, int32_t imm64); |
1066 | 1314 |
void movslq(Register dst, int32_t imm64); |
1315 |
||
1316 |
void movslq(Register dst, Address src); |
|
1317 |
void movslq(Register dst, Register src); |
|
1318 |
void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous |
|
1319 |
#endif |
|
1320 |
||
1321 |
void movswl(Register dst, Address src); |
|
1322 |
void movswl(Register dst, Register src); |
|
1323 |
||
2150 | 1324 |
#ifdef _LP64 |
1325 |
void movswq(Register dst, Address src); |
|
1326 |
void movswq(Register dst, Register src); |
|
1327 |
#endif |
|
1328 |
||
1066 | 1329 |
void movw(Address dst, int imm16); |
1330 |
void movw(Register dst, Address src); |
|
1331 |
void movw(Address dst, Register src); |
|
1332 |
||
1333 |
void movzbl(Register dst, Address src); |
|
1334 |
void movzbl(Register dst, Register src); |
|
1335 |
||
2150 | 1336 |
#ifdef _LP64 |
1337 |
void movzbq(Register dst, Address src); |
|
1338 |
void movzbq(Register dst, Register src); |
|
1339 |
#endif |
|
1340 |
||
1066 | 1341 |
void movzwl(Register dst, Address src); |
1342 |
void movzwl(Register dst, Register src); |
|
1343 |
||
2150 | 1344 |
#ifdef _LP64 |
1345 |
void movzwq(Register dst, Address src); |
|
1346 |
void movzwq(Register dst, Register src); |
|
1347 |
#endif |
|
1348 |
||
1066 | 1349 |
void mull(Address src); |
1350 |
void mull(Register src); |
|
1351 |
||
1352 |
// Multiply Scalar Double-Precision Floating-Point Values |
|
1353 |
void mulsd(XMMRegister dst, Address src); |
|
1354 |
void mulsd(XMMRegister dst, XMMRegister src); |
|
1355 |
||
1356 |
// Multiply Scalar Single-Precision Floating-Point Values |
|
1357 |
void mulss(XMMRegister dst, Address src); |
|
1358 |
void mulss(XMMRegister dst, XMMRegister src); |
|
1359 |
||
1360 |
void negl(Register dst); |
|
1361 |
||
1362 |
#ifdef _LP64 |
|
1363 |
void negq(Register dst); |
|
1364 |
#endif |
|
1365 |
||
1366 |
void nop(int i = 1); |
|
1367 |
||
1368 |
void notl(Register dst); |
|
1369 |
||
1370 |
#ifdef _LP64 |
|
1371 |
void notq(Register dst); |
|
1372 |
#endif |
|
1373 |
||
1374 |
void orl(Address dst, int32_t imm32); |
|
1375 |
void orl(Register dst, int32_t imm32); |
|
1376 |
void orl(Register dst, Address src); |
|
1377 |
void orl(Register dst, Register src); |
|
1378 |
||
1379 |
void orq(Address dst, int32_t imm32); |
|
1380 |
void orq(Register dst, int32_t imm32); |
|
1381 |
void orq(Register dst, Address src); |
|
1382 |
void orq(Register dst, Register src); |
|
1383 |
||
11427 | 1384 |
// Pack with unsigned saturation |
1385 |
void packuswb(XMMRegister dst, XMMRegister src); |
|
1386 |
void packuswb(XMMRegister dst, Address src); |
|
1387 |
||
2348 | 1388 |
// SSE4.2 string instructions |
1389 |
void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); |
|
1390 |
void pcmpestri(XMMRegister xmm1, Address src, int imm8); |
|
1391 |
||
11427 | 1392 |
// SSE4.1 packed move |
1393 |
void pmovzxbw(XMMRegister dst, XMMRegister src); |
|
1394 |
void pmovzxbw(XMMRegister dst, Address src); |
|
1395 |
||
4430 | 1396 |
#ifndef _LP64 // no 32bit push/pop on amd64 |
1066 | 1397 |
void popl(Address dst); |
4430 | 1398 |
#endif |
1066 | 1399 |
|
1400 |
#ifdef _LP64 |
|
1401 |
void popq(Address dst); |
|
1402 |
#endif |
|
1403 |
||
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1404 |
void popcntl(Register dst, Address src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1405 |
void popcntl(Register dst, Register src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1406 |
|
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1407 |
#ifdef _LP64 |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1408 |
void popcntq(Register dst, Address src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1409 |
void popcntq(Register dst, Register src); |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1410 |
#endif |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2254
diff
changeset
|
1411 |
|
1066 | 1412 |
// Prefetches (SSE, SSE2, 3DNOW only) |
1413 |
||
1414 |
void prefetchnta(Address src); |
|
1415 |
void prefetchr(Address src); |
|
1416 |
void prefetcht0(Address src); |
|
1417 |
void prefetcht1(Address src); |
|
1418 |
void prefetcht2(Address src); |
|
1419 |
void prefetchw(Address src); |
|
1420 |
||
8332 | 1421 |
// POR - Bitwise logical OR |
1422 |
void por(XMMRegister dst, XMMRegister src); |
|
11427 | 1423 |
void por(XMMRegister dst, Address src); |
8332 | 1424 |
|
1066 | 1425 |
// Shuffle Packed Doublewords |
1426 |
void pshufd(XMMRegister dst, XMMRegister src, int mode); |
|
1427 |
void pshufd(XMMRegister dst, Address src, int mode); |
|
1428 |
||
1429 |
// Shuffle Packed Low Words |
|
1430 |
void pshuflw(XMMRegister dst, XMMRegister src, int mode); |
|
1431 |
void pshuflw(XMMRegister dst, Address src, int mode); |
|
1432 |
||
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1433 |
// Shift Right by bits Logical Quadword Immediate |
1066 | 1434 |
void psrlq(XMMRegister dst, int shift); |
1435 |
||
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1436 |
// Shift Right by bytes Logical DoubleQuadword Immediate |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1437 |
void psrldq(XMMRegister dst, int shift); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
1438 |
|
2348 | 1439 |
// Logical Compare Double Quadword |
1440 |
void ptest(XMMRegister dst, XMMRegister src); |
|
1441 |
void ptest(XMMRegister dst, Address src); |
|
1442 |
||
1066 | 1443 |
// Interleave Low Bytes |
1444 |
void punpcklbw(XMMRegister dst, XMMRegister src); |
|
11427 | 1445 |
void punpcklbw(XMMRegister dst, Address src); |
1446 |
||
1447 |
// Interleave Low Doublewords |
|
1448 |
void punpckldq(XMMRegister dst, XMMRegister src); |
|
1449 |
void punpckldq(XMMRegister dst, Address src); |
|
1066 | 1450 |
|
4430 | 1451 |
#ifndef _LP64 // no 32bit push/pop on amd64 |
1066 | 1452 |
void pushl(Address src); |
4430 | 1453 |
#endif |
1066 | 1454 |
|
1455 |
void pushq(Address src); |
|
1456 |
||
1457 |
// Xor Packed Byte Integer Values |
|
1458 |
void pxor(XMMRegister dst, Address src); |
|
1459 |
void pxor(XMMRegister dst, XMMRegister src); |
|
1460 |
||
1461 |
void rcll(Register dst, int imm8); |
|
1462 |
||
1463 |
void rclq(Register dst, int imm8); |
|
1464 |
||
1465 |
void ret(int imm16); |
|
1 | 1466 |
|
1467 |
void sahf(); |
|
1468 |
||
1066 | 1469 |
void sarl(Register dst, int imm8); |
1470 |
void sarl(Register dst); |
|
1471 |
||
1472 |
void sarq(Register dst, int imm8); |
|
1473 |
void sarq(Register dst); |
|
1474 |
||
1475 |
void sbbl(Address dst, int32_t imm32); |
|
1476 |
void sbbl(Register dst, int32_t imm32); |
|
1477 |
void sbbl(Register dst, Address src); |
|
1478 |
void sbbl(Register dst, Register src); |
|
1479 |
||
1480 |
void sbbq(Address dst, int32_t imm32); |
|
1481 |
void sbbq(Register dst, int32_t imm32); |
|
1482 |
void sbbq(Register dst, Address src); |
|
1483 |
void sbbq(Register dst, Register src); |
|
1484 |
||
1485 |
void setb(Condition cc, Register dst); |
|
1486 |
||
1487 |
void shldl(Register dst, Register src); |
|
1488 |
||
1489 |
void shll(Register dst, int imm8); |
|
1490 |
void shll(Register dst); |
|
1491 |
||
1492 |
void shlq(Register dst, int imm8); |
|
1493 |
void shlq(Register dst); |
|
1494 |
||
1495 |
void shrdl(Register dst, Register src); |
|
1496 |
||
1497 |
void shrl(Register dst, int imm8); |
|
1498 |
void shrl(Register dst); |
|
1499 |
||
1500 |
void shrq(Register dst, int imm8); |
|
1501 |
void shrq(Register dst); |
|
1502 |
||
1503 |
void smovl(); // QQQ generic? |
|
1504 |
||
1505 |
// Compute Square Root of Scalar Double-Precision Floating-Point Value |
|
1506 |
void sqrtsd(XMMRegister dst, Address src); |
|
1507 |
void sqrtsd(XMMRegister dst, XMMRegister src); |
|
1508 |
||
7433 | 1509 |
// Compute Square Root of Scalar Single-Precision Floating-Point Value |
1510 |
void sqrtss(XMMRegister dst, Address src); |
|
1511 |
void sqrtss(XMMRegister dst, XMMRegister src); |
|
1512 |
||
1066 | 1513 |
void std() { emit_byte(0xfd); } |
1514 |
||
1515 |
void stmxcsr( Address dst ); |
|
1516 |
||
1517 |
void subl(Address dst, int32_t imm32); |
|
1518 |
void subl(Address dst, Register src); |
|
1519 |
void subl(Register dst, int32_t imm32); |
|
1520 |
void subl(Register dst, Address src); |
|
1521 |
void subl(Register dst, Register src); |
|
1522 |
||
1523 |
void subq(Address dst, int32_t imm32); |
|
1524 |
void subq(Address dst, Register src); |
|
1525 |
void subq(Register dst, int32_t imm32); |
|
1526 |
void subq(Register dst, Address src); |
|
1527 |
void subq(Register dst, Register src); |
|
1528 |
||
1529 |
||
1530 |
// Subtract Scalar Double-Precision Floating-Point Values |
|
1531 |
void subsd(XMMRegister dst, Address src); |
|
1 | 1532 |
void subsd(XMMRegister dst, XMMRegister src); |
1533 |
||
1066 | 1534 |
// Subtract Scalar Single-Precision Floating-Point Values |
1535 |
void subss(XMMRegister dst, Address src); |
|
1536 |
void subss(XMMRegister dst, XMMRegister src); |
|
1537 |
||
1538 |
void testb(Register dst, int imm8); |
|
1539 |
||
1540 |
void testl(Register dst, int32_t imm32); |
|
1541 |
void testl(Register dst, Register src); |
|
1542 |
void testl(Register dst, Address src); |
|
1543 |
||
1544 |
void testq(Register dst, int32_t imm32); |
|
1545 |
void testq(Register dst, Register src); |
|
1546 |
||
1547 |
||
1548 |
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS |
|
1549 |
void ucomisd(XMMRegister dst, Address src); |
|
1 | 1550 |
void ucomisd(XMMRegister dst, XMMRegister src); |
1551 |
||
1066 | 1552 |
// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1553 |
void ucomiss(XMMRegister dst, Address src); |
|
1554 |
void ucomiss(XMMRegister dst, XMMRegister src); |
|
1555 |
||
1556 |
void xaddl(Address dst, Register src); |
|
1557 |
||
1558 |
void xaddq(Address dst, Register src); |
|
1559 |
||
1560 |
void xchgl(Register reg, Address adr); |
|
1561 |
void xchgl(Register dst, Register src); |
|
1562 |
||
1563 |
void xchgq(Register reg, Address adr); |
|
1564 |
void xchgq(Register dst, Register src); |
|
1565 |
||
11427 | 1566 |
// Get Value of Extended Control Register |
1567 |
void xgetbv() { |
|
1568 |
emit_byte(0x0F); |
|
1569 |
emit_byte(0x01); |
|
1570 |
emit_byte(0xD0); |
|
1571 |
} |
|
1572 |
||
1066 | 1573 |
void xorl(Register dst, int32_t imm32); |
1574 |
void xorl(Register dst, Address src); |
|
1575 |
void xorl(Register dst, Register src); |
|
1576 |
||
1577 |
void xorq(Register dst, Address src); |
|
1578 |
void xorq(Register dst, Register src); |
|
1579 |
||
1580 |
// Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
|
1581 |
void xorpd(XMMRegister dst, XMMRegister src); |
|
1582 |
||
1583 |
// Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
|
1 | 1584 |
void xorps(XMMRegister dst, XMMRegister src); |
1066 | 1585 |
|
1586 |
void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 |
|
11427 | 1587 |
|
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1588 |
// AVX 3-operands instructions (encoded with VEX prefix) |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1589 |
void vaddsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1590 |
void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1591 |
void vaddss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1592 |
void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1593 |
void vandpd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1594 |
void vandps(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1595 |
void vdivsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1596 |
void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1597 |
void vdivss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1598 |
void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1599 |
void vmulsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1600 |
void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1601 |
void vmulss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1602 |
void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1603 |
void vsubsd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1604 |
void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1605 |
void vsubss(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1606 |
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1607 |
void vxorpd(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1608 |
void vxorps(XMMRegister dst, XMMRegister nds, Address src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1609 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
1610 |
|
11427 | 1611 |
protected: |
1612 |
// Next instructions require address alignment 16 bytes SSE mode. |
|
1613 |
// They should be called only from corresponding MacroAssembler instructions. |
|
1614 |
void andpd(XMMRegister dst, Address src); |
|
1615 |
void andps(XMMRegister dst, Address src); |
|
1616 |
void xorpd(XMMRegister dst, Address src); |
|
1617 |
void xorps(XMMRegister dst, Address src); |
|
1618 |
||
1 | 1619 |
}; |
1620 |
||
1621 |
||
1622 |
// MacroAssembler extends Assembler by frequently used macros. |
|
1623 |
// |
|
1624 |
// Instructions for which a 'better' code sequence exists depending |
|
1625 |
// on arguments should also go in here. |
|
1626 |
||
1627 |
class MacroAssembler: public Assembler { |
|
1374
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
1628 |
friend class LIR_Assembler; |
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
1629 |
friend class Runtime1; // as_Address() |
9176
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1630 |
|
1 | 1631 |
protected: |
1632 |
||
1633 |
Address as_Address(AddressLiteral adr); |
|
1634 |
Address as_Address(ArrayAddress adr); |
|
1635 |
||
1636 |
// Support for VM calls |
|
1637 |
// |
|
1638 |
// This is the base routine called by the different versions of call_VM_leaf. The interpreter |
|
1639 |
// may customize this version by overriding it for its purposes (e.g., to save/restore |
|
1640 |
// additional registers when doing a VM call). |
|
1641 |
#ifdef CC_INTERP |
|
1642 |
// c++ interpreter never wants to use interp_masm version of call_VM |
|
1643 |
#define VIRTUAL |
|
1644 |
#else |
|
1645 |
#define VIRTUAL virtual |
|
1646 |
#endif |
|
1647 |
||
1648 |
VIRTUAL void call_VM_leaf_base( |
|
1649 |
address entry_point, // the entry point |
|
1650 |
int number_of_arguments // the number of arguments to pop after the call |
|
1651 |
); |
|
1652 |
||
1653 |
// This is the base routine called by the different versions of call_VM. The interpreter |
|
1654 |
// may customize this version by overriding it for its purposes (e.g., to save/restore |
|
1655 |
// additional registers when doing a VM call). |
|
1656 |
// |
|
1657 |
// If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base |
|
1658 |
// returns the register which contains the thread upon return. If a thread register has been |
|
1659 |
// specified, the return value will correspond to that register. If no last_java_sp is specified |
|
1660 |
// (noreg) than rsp will be used instead. |
|
1661 |
VIRTUAL void call_VM_base( // returns the register containing the thread upon return |
|
1662 |
Register oop_result, // where an oop-result ends up if any; use noreg otherwise |
|
1663 |
Register java_thread, // the thread if computed before ; use noreg otherwise |
|
1664 |
Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise |
|
1665 |
address entry_point, // the entry point |
|
1666 |
int number_of_arguments, // the number of arguments (w/o thread) to pop after the call |
|
1667 |
bool check_exceptions // whether to check for pending exceptions after return |
|
1668 |
); |
|
1669 |
||
1670 |
// These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. |
|
1671 |
// The implementation is only non-empty for the InterpreterMacroAssembler, |
|
1672 |
// as only the interpreter handles PopFrame and ForceEarlyReturn requests. |
|
1673 |
virtual void check_and_handle_popframe(Register java_thread); |
|
1674 |
virtual void check_and_handle_earlyret(Register java_thread); |
|
1675 |
||
1676 |
void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); |
|
1677 |
||
1678 |
// helpers for FPU flag access |
|
1679 |
// tmp is a temporary register, if none is available use noreg |
|
1680 |
void save_rax (Register tmp); |
|
1681 |
void restore_rax(Register tmp); |
|
1682 |
||
1683 |
public: |
|
1684 |
MacroAssembler(CodeBuffer* code) : Assembler(code) {} |
|
1685 |
||
1686 |
// Support for NULL-checks |
|
1687 |
// |
|
1688 |
// Generates code that causes a NULL OS exception if the content of reg is NULL. |
|
1689 |
// If the accessed location is M[reg + offset] and the offset is known, provide the |
|
1690 |
// offset. No explicit code generation is needed if the offset is within a certain |
|
1691 |
// range (0 <= offset <= page_size). |
|
1692 |
||
1693 |
void null_check(Register reg, int offset = -1); |
|
594
9f4474e5dbaf
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
244
diff
changeset
|
1694 |
static bool needs_explicit_null_check(intptr_t offset); |
1 | 1695 |
|
1696 |
// Required platform-specific helpers for Label::patch_instructions. |
|
1697 |
// They _shadow_ the declarations in AbstractAssembler, which are undefined. |
|
1698 |
void pd_patch_instruction(address branch, address target); |
|
1699 |
#ifndef PRODUCT |
|
1700 |
static void pd_print_patched_instruction(address branch); |
|
1701 |
#endif |
|
1702 |
||
1703 |
// The following 4 methods return the offset of the appropriate move instruction |
|
1704 |
||
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
1705 |
// Support for fast byte/short loading with zero extension (depending on particular CPU) |
1 | 1706 |
int load_unsigned_byte(Register dst, Address src); |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
1707 |
int load_unsigned_short(Register dst, Address src); |
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
1708 |
|
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
1709 |
// Support for fast byte/short loading with sign extension (depending on particular CPU) |
1 | 1710 |
int load_signed_byte(Register dst, Address src); |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
1711 |
int load_signed_short(Register dst, Address src); |
1 | 1712 |
|
1713 |
// Support for sign-extension (hi:lo = extend_sign(lo)) |
|
1714 |
void extend_sign(Register hi, Register lo); |
|
1715 |
||
8328
478a1d29e5a3
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
7724
diff
changeset
|
1716 |
// Load and store values by size and signed-ness |
478a1d29e5a3
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
7724
diff
changeset
|
1717 |
void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); |
478a1d29e5a3
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
7724
diff
changeset
|
1718 |
void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
1719 |
|
1 | 1720 |
// Support for inc/dec with optimal instruction selection depending on value |
1066 | 1721 |
|
1722 |
void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } |
|
1723 |
void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } |
|
1724 |
||
1725 |
void decrementl(Address dst, int value = 1); |
|
1726 |
void decrementl(Register reg, int value = 1); |
|
1727 |
||
1728 |
void decrementq(Register reg, int value = 1); |
|
1729 |
void decrementq(Address dst, int value = 1); |
|
1730 |
||
1731 |
void incrementl(Address dst, int value = 1); |
|
1732 |
void incrementl(Register reg, int value = 1); |
|
1733 |
||
1734 |
void incrementq(Register reg, int value = 1); |
|
1735 |
void incrementq(Address dst, int value = 1); |
|
1736 |
||
1 | 1737 |
|
1738 |
// Support optimal SSE move instructions. |
|
1739 |
void movflt(XMMRegister dst, XMMRegister src) { |
|
1740 |
if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } |
|
1741 |
else { movss (dst, src); return; } |
|
1742 |
} |
|
1743 |
void movflt(XMMRegister dst, Address src) { movss(dst, src); } |
|
1744 |
void movflt(XMMRegister dst, AddressLiteral src); |
|
1745 |
void movflt(Address dst, XMMRegister src) { movss(dst, src); } |
|
1746 |
||
1747 |
void movdbl(XMMRegister dst, XMMRegister src) { |
|
1748 |
if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } |
|
1749 |
else { movsd (dst, src); return; } |
|
1750 |
} |
|
1751 |
||
1752 |
void movdbl(XMMRegister dst, AddressLiteral src); |
|
1753 |
||
1754 |
void movdbl(XMMRegister dst, Address src) { |
|
1755 |
if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } |
|
1756 |
else { movlpd(dst, src); return; } |
|
1757 |
} |
|
1758 |
void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } |
|
1759 |
||
1066 | 1760 |
void incrementl(AddressLiteral dst); |
1761 |
void incrementl(ArrayAddress dst); |
|
1 | 1762 |
|
1763 |
// Alignment |
|
1764 |
void align(int modulus); |
|
1765 |
||
1766 |
// Misc |
|
1767 |
void fat_nop(); // 5 byte nop |
|
1768 |
||
1769 |
// Stack frame creation/removal |
|
1770 |
void enter(); |
|
1771 |
void leave(); |
|
1772 |
||
1773 |
// Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) |
|
1774 |
// The pointer will be loaded into the thread register. |
|
1775 |
void get_thread(Register thread); |
|
1776 |
||
1394 | 1777 |
|
1 | 1778 |
// Support for VM calls |
1779 |
// |
|
1780 |
// It is imperative that all calls into the VM are handled via the call_VM macros. |
|
1781 |
// They make sure that the stack linkage is setup correctly. call_VM's correspond |
|
1782 |
// to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. |
|
1783 |
||
1066 | 1784 |
|
1785 |
void call_VM(Register oop_result, |
|
1786 |
address entry_point, |
|
1787 |
bool check_exceptions = true); |
|
1788 |
void call_VM(Register oop_result, |
|
1789 |
address entry_point, |
|
1790 |
Register arg_1, |
|
1791 |
bool check_exceptions = true); |
|
1792 |
void call_VM(Register oop_result, |
|
1793 |
address entry_point, |
|
1794 |
Register arg_1, Register arg_2, |
|
1795 |
bool check_exceptions = true); |
|
1796 |
void call_VM(Register oop_result, |
|
1797 |
address entry_point, |
|
1798 |
Register arg_1, Register arg_2, Register arg_3, |
|
1799 |
bool check_exceptions = true); |
|
1800 |
||
1801 |
// Overloadings with last_Java_sp |
|
1802 |
void call_VM(Register oop_result, |
|
1803 |
Register last_java_sp, |
|
1804 |
address entry_point, |
|
1805 |
int number_of_arguments = 0, |
|
1806 |
bool check_exceptions = true); |
|
1807 |
void call_VM(Register oop_result, |
|
1808 |
Register last_java_sp, |
|
1809 |
address entry_point, |
|
1810 |
Register arg_1, bool |
|
1811 |
check_exceptions = true); |
|
1812 |
void call_VM(Register oop_result, |
|
1813 |
Register last_java_sp, |
|
1814 |
address entry_point, |
|
1815 |
Register arg_1, Register arg_2, |
|
1816 |
bool check_exceptions = true); |
|
1817 |
void call_VM(Register oop_result, |
|
1818 |
Register last_java_sp, |
|
1819 |
address entry_point, |
|
1820 |
Register arg_1, Register arg_2, Register arg_3, |
|
1821 |
bool check_exceptions = true); |
|
1822 |
||
9978
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1823 |
// These always tightly bind to MacroAssembler::call_VM_base |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1824 |
// bypassing the virtual implementation |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1825 |
void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1826 |
void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1827 |
void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1828 |
void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1829 |
void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); |
80c391c46474
7047697: MethodHandle.invokeExact call for wrong method causes VM failure if run with -Xcomp
jrose
parents:
9630
diff
changeset
|
1830 |
|
1066 | 1831 |
void call_VM_leaf(address entry_point, |
1832 |
int number_of_arguments = 0); |
|
1833 |
void call_VM_leaf(address entry_point, |
|
1834 |
Register arg_1); |
|
1835 |
void call_VM_leaf(address entry_point, |
|
1836 |
Register arg_1, Register arg_2); |
|
1837 |
void call_VM_leaf(address entry_point, |
|
1838 |
Register arg_1, Register arg_2, Register arg_3); |
|
1 | 1839 |
|
9437
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1840 |
// These always tightly bind to MacroAssembler::call_VM_leaf_base |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1841 |
// bypassing the virtual implementation |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1842 |
void super_call_VM_leaf(address entry_point); |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1843 |
void super_call_VM_leaf(address entry_point, Register arg_1); |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1844 |
void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1845 |
void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1846 |
void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); |
9981851b4b8c
7009361: JSR 292 Invalid value on stack on solaris-sparc with -Xcomp
never
parents:
9182
diff
changeset
|
1847 |
|
1 | 1848 |
// last Java Frame (fills frame anchor) |
1066 | 1849 |
void set_last_Java_frame(Register thread, |
1850 |
Register last_java_sp, |
|
1851 |
Register last_java_fp, |
|
1852 |
address last_java_pc); |
|
1853 |
||
1854 |
// thread in the default location (r15_thread on 64bit) |
|
1855 |
void set_last_Java_frame(Register last_java_sp, |
|
1856 |
Register last_java_fp, |
|
1857 |
address last_java_pc); |
|
1858 |
||
1 | 1859 |
void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
1860 |
||
1066 | 1861 |
// thread in the default location (r15_thread on 64bit) |
1862 |
void reset_last_Java_frame(bool clear_fp, bool clear_pc); |
|
1863 |
||
1 | 1864 |
// Stores |
1865 |
void store_check(Register obj); // store check for obj - register is destroyed afterwards |
|
1866 |
void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) |
|
1867 |
||
9176
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1868 |
#ifndef SERIALGC |
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1869 |
|
1394 | 1870 |
void g1_write_barrier_pre(Register obj, |
9176
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1871 |
Register pre_val, |
1394 | 1872 |
Register thread, |
1873 |
Register tmp, |
|
9176
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1874 |
bool tosca_live, |
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1875 |
bool expand_call); |
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1876 |
|
1394 | 1877 |
void g1_write_barrier_post(Register store_addr, |
1878 |
Register new_val, |
|
1879 |
Register thread, |
|
1880 |
Register tmp, |
|
1881 |
Register tmp2); |
|
1374
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
1882 |
|
9176
42d9d1010f38
7009266: G1: assert(obj->is_oop_or_null(true )) failed: Error
johnc
parents:
8494
diff
changeset
|
1883 |
#endif // SERIALGC |
1374
4c24294029a9
6711316: Open source the Garbage-First garbage collector
ysr
parents:
244
diff
changeset
|
1884 |
|
1 | 1885 |
// split store_check(Register obj) to enhance instruction interleaving |
1886 |
void store_check_part_1(Register obj); |
|
1887 |
void store_check_part_2(Register obj); |
|
1888 |
||
1889 |
// C 'boolean' to Java boolean: x == 0 ? 0 : 1 |
|
1890 |
void c2bool(Register x); |
|
1891 |
||
1892 |
// C++ bool manipulation |
|
1893 |
||
1894 |
void movbool(Register dst, Address src); |
|
1895 |
void movbool(Address dst, bool boolconst); |
|
1896 |
void movbool(Address dst, Register src); |
|
1897 |
void testbool(Register dst); |
|
1898 |
||
1066 | 1899 |
// oop manipulations |
1900 |
void load_klass(Register dst, Register src); |
|
1901 |
void store_klass(Register dst, Register src); |
|
1902 |
||
6772 | 1903 |
void load_heap_oop(Register dst, Address src); |
9120
3606dd709168
7034967: C1: assert(false) failed: error (assembler_sparc.cpp:2043)
iveresov
parents:
9111
diff
changeset
|
1904 |
void load_heap_oop_not_null(Register dst, Address src); |
6772 | 1905 |
void store_heap_oop(Address dst, Register src); |
1906 |
||
1907 |
// Used for storing NULL. All other oop constants should be |
|
1908 |
// stored using routines that take a jobject. |
|
1909 |
void store_heap_oop_null(Address dst); |
|
1910 |
||
1066 | 1911 |
void load_prototype_header(Register dst, Register src); |
1912 |
||
1913 |
#ifdef _LP64 |
|
1914 |
void store_klass_gap(Register dst, Register src); |
|
1915 |
||
4102
11d514e508d9
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
3905
diff
changeset
|
1916 |
// This dummy is to prevent a call to store_heap_oop from |
11d514e508d9
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
3905
diff
changeset
|
1917 |
// converting a zero (like NULL) into a Register by giving |
11d514e508d9
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
3905
diff
changeset
|
1918 |
// the compiler two choices it can't resolve |
11d514e508d9
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
3905
diff
changeset
|
1919 |
|
11d514e508d9
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
3905
diff
changeset
|
1920 |
void store_heap_oop(Address dst, void* dummy); |
11d514e508d9
6889740: G1: OpenDS fails with "unhandled exception in compiled code"
johnc
parents:
3905
diff
changeset
|
1921 |
|
1066 | 1922 |
void encode_heap_oop(Register r); |
1923 |
void decode_heap_oop(Register r); |
|
1924 |
void encode_heap_oop_not_null(Register r); |
|
1925 |
void decode_heap_oop_not_null(Register r); |
|
1926 |
void encode_heap_oop_not_null(Register dst, Register src); |
|
1927 |
void decode_heap_oop_not_null(Register dst, Register src); |
|
1928 |
||
1929 |
void set_narrow_oop(Register dst, jobject obj); |
|
2254
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
1930 |
void set_narrow_oop(Address dst, jobject obj); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
1931 |
void cmp_narrow_oop(Register dst, jobject obj); |
f13dda645a4b
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
2150
diff
changeset
|
1932 |
void cmp_narrow_oop(Address dst, jobject obj); |
1066 | 1933 |
|
1934 |
// if heap base register is used - reinit it with the correct value |
|
1935 |
void reinit_heapbase(); |
|
6179
4846648c4b7b
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
5702
diff
changeset
|
1936 |
|
4846648c4b7b
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
5702
diff
changeset
|
1937 |
DEBUG_ONLY(void verify_heapbase(const char* msg);) |
4846648c4b7b
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
5702
diff
changeset
|
1938 |
|
1066 | 1939 |
#endif // _LP64 |
1940 |
||
1941 |
// Int division/remainder for Java |
|
1 | 1942 |
// (as idivl, but checks for special case as described in JVM spec.) |
1943 |
// returns idivl instruction offset for implicit exception handling |
|
1944 |
int corrected_idivl(Register reg); |
|
1945 |
||
1066 | 1946 |
// Long division/remainder for Java |
1947 |
// (as idivq, but checks for special case as described in JVM spec.) |
|
1948 |
// returns idivq instruction offset for implicit exception handling |
|
1949 |
int corrected_idivq(Register reg); |
|
1950 |
||
1 | 1951 |
void int3(); |
1952 |
||
1066 | 1953 |
// Long operation macros for a 32bit cpu |
1 | 1954 |
// Long negation for Java |
1955 |
void lneg(Register hi, Register lo); |
|
1956 |
||
1957 |
// Long multiplication for Java |
|
1066 | 1958 |
// (destroys contents of eax, ebx, ecx and edx) |
1 | 1959 |
void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
1960 |
||
1961 |
// Long shifts for Java |
|
1962 |
// (semantics as described in JVM spec.) |
|
1963 |
void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) |
|
1964 |
void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) |
|
1965 |
||
1966 |
// Long compare for Java |
|
1967 |
// (semantics as described in JVM spec.) |
|
1968 |
void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) |
|
1969 |
||
1066 | 1970 |
|
1971 |
// misc |
|
1972 |
||
1973 |
// Sign extension |
|
1974 |
void sign_extend_short(Register reg); |
|
1975 |
void sign_extend_byte(Register reg); |
|
1976 |
||
1977 |
// Division by power of 2, rounding towards 0 |
|
1978 |
void division_with_shift(Register reg, int shift_value); |
|
1979 |
||
1 | 1980 |
// Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
1981 |
// |
|
1982 |
// CF (corresponds to C0) if x < y |
|
1983 |
// PF (corresponds to C2) if unordered |
|
1984 |
// ZF (corresponds to C3) if x = y |
|
1985 |
// |
|
1986 |
// The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
|
1987 |
// tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) |
|
1988 |
void fcmp(Register tmp); |
|
1989 |
// Variant of the above which allows y to be further down the stack |
|
1990 |
// and which only pops x and y if specified. If pop_right is |
|
1991 |
// specified then pop_left must also be specified. |
|
1992 |
void fcmp(Register tmp, int index, bool pop_left, bool pop_right); |
|
1993 |
||
1994 |
// Floating-point comparison for Java |
|
1995 |
// Compares the top-most stack entries on the FPU stack and stores the result in dst. |
|
1996 |
// The arguments are in reversed order on the stack (i.e., top of stack is first argument). |
|
1997 |
// (semantics as described in JVM spec.) |
|
1998 |
void fcmp2int(Register dst, bool unordered_is_less); |
|
1999 |
// Variant of the above which allows y to be further down the stack |
|
2000 |
// and which only pops x and y if specified. If pop_right is |
|
2001 |
// specified then pop_left must also be specified. |
|
2002 |
void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); |
|
2003 |
||
2004 |
// Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) |
|
2005 |
// tmp is a temporary register, if none is available use noreg |
|
2006 |
void fremr(Register tmp); |
|
2007 |
||
2008 |
||
2009 |
// same as fcmp2int, but using SSE2 |
|
2010 |
void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
|
2011 |
void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); |
|
2012 |
||
2013 |
// Inlined sin/cos generator for Java; must not use CPU instruction |
|
2014 |
// directly on Intel as it does not have high enough precision |
|
2015 |
// outside of the range [-pi/4, pi/4]. Extra argument indicate the |
|
2016 |
// number of FPU stack slots in use; all but the topmost will |
|
2017 |
// require saving if a slow case is necessary. Assumes argument is |
|
2018 |
// on FP TOS; result is on FP TOS. No cpu registers are changed by |
|
2019 |
// this code. |
|
2020 |
void trigfunc(char trig, int num_fpu_regs_in_use = 1); |
|
2021 |
||
2022 |
// branch to L if FPU flag C2 is set/not set |
|
2023 |
// tmp is a temporary register, if none is available use noreg |
|
2024 |
void jC2 (Register tmp, Label& L); |
|
2025 |
void jnC2(Register tmp, Label& L); |
|
2026 |
||
2027 |
// Pop ST (ffree & fincstp combined) |
|
2028 |
void fpop(); |
|
2029 |
||
2030 |
// pushes double TOS element of FPU stack on CPU stack; pops from FPU stack |
|
2031 |
void push_fTOS(); |
|
2032 |
||
2033 |
// pops double TOS element from CPU stack and pushes on FPU stack |
|
2034 |
void pop_fTOS(); |
|
2035 |
||
2036 |
void empty_FPU_stack(); |
|
2037 |
||
2038 |
void push_IU_state(); |
|
2039 |
void pop_IU_state(); |
|
2040 |
||
2041 |
void push_FPU_state(); |
|
2042 |
void pop_FPU_state(); |
|
2043 |
||
2044 |
void push_CPU_state(); |
|
2045 |
void pop_CPU_state(); |
|
2046 |
||
2047 |
// Round up to a power of two |
|
2048 |
void round_to(Register reg, int modulus); |
|
2049 |
||
2050 |
// Callee saved registers handling |
|
2051 |
void push_callee_saved_registers(); |
|
2052 |
void pop_callee_saved_registers(); |
|
2053 |
||
2054 |
// allocation |
|
2055 |
void eden_allocate( |
|
2056 |
Register obj, // result: pointer to object after successful allocation |
|
2057 |
Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
|
2058 |
int con_size_in_bytes, // object size in bytes if known at compile time |
|
2059 |
Register t1, // temp register |
|
2060 |
Label& slow_case // continuation point if fast allocation fails |
|
2061 |
); |
|
2062 |
void tlab_allocate( |
|
2063 |
Register obj, // result: pointer to object after successful allocation |
|
2064 |
Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise |
|
2065 |
int con_size_in_bytes, // object size in bytes if known at compile time |
|
2066 |
Register t1, // temp register |
|
2067 |
Register t2, // temp register |
|
2068 |
Label& slow_case // continuation point if fast allocation fails |
|
2069 |
); |
|
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
2070 |
Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
2071 |
void incr_allocated_bytes(Register thread, |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
2072 |
Register var_size_in_bytes, int con_size_in_bytes, |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
2073 |
Register t1 = noreg); |
1 | 2074 |
|
2149
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2075 |
// interface method calling |
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2076 |
void lookup_interface_method(Register recv_klass, |
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2077 |
Register intf_klass, |
2332
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
2078 |
RegisterOrConstant itable_index, |
2149
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2079 |
Register method_result, |
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2080 |
Register scan_temp, |
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2081 |
Label& no_such_interface); |
3d362637b307
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
2148
diff
changeset
|
2082 |
|
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2083 |
// Test sub_klass against super_klass, with fast and slow paths. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2084 |
|
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2085 |
// The fast path produces a tri-state answer: yes / no / maybe-slow. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2086 |
// One of the three labels can be NULL, meaning take the fall-through. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2087 |
// If super_check_offset is -1, the value is loaded up from super_klass. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2088 |
// No registers are killed, except temp_reg. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2089 |
void check_klass_subtype_fast_path(Register sub_klass, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2090 |
Register super_klass, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2091 |
Register temp_reg, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2092 |
Label* L_success, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2093 |
Label* L_failure, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2094 |
Label* L_slow_path, |
2332
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
2095 |
RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2096 |
|
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2097 |
// The rest of the type check; must be wired to a corresponding fast path. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2098 |
// It does not repeat the fast path logic, so don't use it standalone. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2099 |
// The temp_reg and temp2_reg can be noreg, if no temps are available. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2100 |
// Updates the sub's secondary super cache as necessary. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2101 |
// If set_cond_codes, condition codes will be Z on success, NZ on failure. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2102 |
void check_klass_subtype_slow_path(Register sub_klass, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2103 |
Register super_klass, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2104 |
Register temp_reg, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2105 |
Register temp2_reg, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2106 |
Label* L_success, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2107 |
Label* L_failure, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2108 |
bool set_cond_codes = false); |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2109 |
|
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2110 |
// Simplified, combined version, good for typical uses. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2111 |
// Falls through on failure. |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2112 |
void check_klass_subtype(Register sub_klass, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2113 |
Register super_klass, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2114 |
Register temp_reg, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2115 |
Label& L_success); |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
2255
diff
changeset
|
2116 |
|
2534 | 2117 |
// method handles (JSR 292) |
2118 |
void check_method_handle_type(Register mtype_reg, Register mh_reg, |
|
2119 |
Register temp_reg, |
|
2120 |
Label& wrong_method_type); |
|
2121 |
void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, |
|
2122 |
Register temp_reg); |
|
2123 |
void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); |
|
2124 |
Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); |
|
2125 |
||
2126 |
||
1 | 2127 |
//---- |
2128 |
void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 |
|
2129 |
||
2130 |
// Debugging |
|
1066 | 2131 |
|
2132 |
// only if +VerifyOops |
|
2133 |
void verify_oop(Register reg, const char* s = "broken oop"); |
|
1 | 2134 |
void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
2135 |
||
1066 | 2136 |
// only if +VerifyFPU |
2137 |
void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); |
|
2138 |
||
2139 |
// prints msg, dumps registers and stops execution |
|
2140 |
void stop(const char* msg); |
|
2141 |
||
2142 |
// prints msg and continues |
|
2143 |
void warn(const char* msg); |
|
2144 |
||
2145 |
static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); |
|
2146 |
static void debug64(char* msg, int64_t pc, int64_t regs[]); |
|
2147 |
||
1 | 2148 |
void os_breakpoint(); |
1066 | 2149 |
|
1 | 2150 |
void untested() { stop("untested"); } |
1066 | 2151 |
|
6772 | 2152 |
void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
1066 | 2153 |
|
1 | 2154 |
void should_not_reach_here() { stop("should not reach here"); } |
1066 | 2155 |
|
1 | 2156 |
void print_CPU_state(); |
2157 |
||
2158 |
// Stack overflow checking |
|
2159 |
void bang_stack_with_offset(int offset) { |
|
2160 |
// stack grows down, caller passes positive offset |
|
2161 |
assert(offset > 0, "must bang with negative offset"); |
|
2162 |
movl(Address(rsp, (-offset)), rax); |
|
2163 |
} |
|
2164 |
||
2165 |
// Writes to stack successive pages until offset reached to check for |
|
2166 |
// stack overflow + shadow pages. Also, clobbers tmp |
|
2167 |
void bang_stack_size(Register size, Register tmp); |
|
2168 |
||
2332
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
2169 |
virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
2170 |
Register tmp, |
5c7b6f4ce0a1
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
2256
diff
changeset
|
2171 |
int offset); |
2148
09c7f703773b
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
1500
diff
changeset
|
2172 |
|
1 | 2173 |
// Support for serializing memory accesses between threads |
2174 |
void serialize_memory(Register thread, Register tmp); |
|
2175 |
||
2176 |
void verify_tlab(); |
|
2177 |
||
2178 |
// Biased locking support |
|
2179 |
// lock_reg and obj_reg must be loaded up with the appropriate values. |
|
2180 |
// swap_reg must be rax, and is killed. |
|
2181 |
// tmp_reg is optional. If it is supplied (i.e., != noreg) it will |
|
2182 |
// be killed; if not supplied, push/pop will be used internally to |
|
2183 |
// allocate a temporary (inefficient, avoid if possible). |
|
2184 |
// Optional slow case is for implementations (interpreter and C1) which branch to |
|
2185 |
// slow case directly. Leaves condition codes set for C2's Fast_Lock node. |
|
2186 |
// Returns offset of first potentially-faulting instruction for null |
|
2187 |
// check info (currently consumed only by C1). If |
|
2188 |
// swap_reg_contains_mark is true then returns -1 as it is assumed |
|
2189 |
// the calling code has already passed any potential faults. |
|
1500
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1437
diff
changeset
|
2190 |
int biased_locking_enter(Register lock_reg, Register obj_reg, |
bea9a90f3e8f
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
1437
diff
changeset
|
2191 |
Register swap_reg, Register tmp_reg, |
1 | 2192 |
bool swap_reg_contains_mark, |
2193 |
Label& done, Label* slow_case = NULL, |
|
2194 |
BiasedLockingCounters* counters = NULL); |
|
2195 |
void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); |
|
2196 |
||
2197 |
||
2198 |
Condition negate_condition(Condition cond); |
|
2199 |
||
2200 |
// Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit |
|
2201 |
// operands. In general the names are modified to avoid hiding the instruction in Assembler |
|
2202 |
// so that we don't need to implement all the varieties in the Assembler with trivial wrappers |
|
2203 |
// here in MacroAssembler. The major exception to this rule is call |
|
2204 |
||
2205 |
// Arithmetics |
|
2206 |
||
1066 | 2207 |
|
2208 |
void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } |
|
2209 |
void addptr(Address dst, Register src); |
|
2210 |
||
2211 |
void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } |
|
2212 |
void addptr(Register dst, int32_t src); |
|
2213 |
void addptr(Register dst, Register src); |
|
9630
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2214 |
void addptr(Register dst, RegisterOrConstant src) { |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2215 |
if (src.is_constant()) addptr(dst, (int) src.as_constant()); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2216 |
else addptr(dst, src.as_register()); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2217 |
} |
1066 | 2218 |
|
2219 |
void andptr(Register dst, int32_t src); |
|
2220 |
void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } |
|
2221 |
||
2222 |
void cmp8(AddressLiteral src1, int imm); |
|
2223 |
||
2224 |
// renamed to drag out the casting of address to int32_t/intptr_t |
|
1 | 2225 |
void cmp32(Register src1, int32_t imm); |
2226 |
||
2227 |
void cmp32(AddressLiteral src1, int32_t imm); |
|
2228 |
// compare reg - mem, or reg - &mem |
|
2229 |
void cmp32(Register src1, AddressLiteral src2); |
|
2230 |
||
2231 |
void cmp32(Register src1, Address src2); |
|
2232 |
||
1066 | 2233 |
#ifndef _LP64 |
2234 |
void cmpoop(Address dst, jobject obj); |
|
2235 |
void cmpoop(Register dst, jobject obj); |
|
2236 |
#endif // _LP64 |
|
2237 |
||
1 | 2238 |
// NOTE src2 must be the lval. This is NOT an mem-mem compare |
2239 |
void cmpptr(Address src1, AddressLiteral src2); |
|
2240 |
||
2241 |
void cmpptr(Register src1, AddressLiteral src2); |
|
2242 |
||
1066 | 2243 |
void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
2244 |
void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
|
2245 |
// void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
|
2246 |
||
2247 |
void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
|
2248 |
void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
|
2249 |
||
2250 |
// cmp64 to avoild hiding cmpq |
|
2251 |
void cmp64(Register src1, AddressLiteral src); |
|
2252 |
||
2253 |
void cmpxchgptr(Register reg, Address adr); |
|
2254 |
||
2255 |
void locked_cmpxchgptr(Register reg, AddressLiteral adr); |
|
2256 |
||
2257 |
||
2258 |
void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } |
|
2259 |
||
2260 |
||
2261 |
void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } |
|
2262 |
||
2263 |
void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } |
|
2264 |
||
2265 |
void shlptr(Register dst, int32_t shift); |
|
2266 |
void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } |
|
2267 |
||
2268 |
void shrptr(Register dst, int32_t shift); |
|
2269 |
void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } |
|
2270 |
||
2271 |
void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } |
|
2272 |
void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } |
|
2273 |
||
2274 |
void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } |
|
2275 |
||
2276 |
void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } |
|
2277 |
void subptr(Register dst, int32_t src); |
|
2278 |
void subptr(Register dst, Register src); |
|
9630
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diff
changeset
|
2279 |
void subptr(Register dst, RegisterOrConstant src) { |
d6419e4395e3
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parents:
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diff
changeset
|
2280 |
if (src.is_constant()) subptr(dst, (int) src.as_constant()); |
d6419e4395e3
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parents:
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diff
changeset
|
2281 |
else subptr(dst, src.as_register()); |
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diff
changeset
|
2282 |
} |
1066 | 2283 |
|
2284 |
void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } |
|
2285 |
void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } |
|
2286 |
||
2287 |
void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } |
|
2288 |
void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } |
|
2289 |
||
2290 |
void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } |
|
2291 |
||
2292 |
||
1 | 2293 |
|
2294 |
// Helper functions for statistics gathering. |
|
2295 |
// Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. |
|
2296 |
void cond_inc32(Condition cond, AddressLiteral counter_addr); |
|
2297 |
// Unconditional atomic increment. |
|
2298 |
void atomic_incl(AddressLiteral counter_addr); |
|
2299 |
||
2300 |
void lea(Register dst, AddressLiteral adr); |
|
2301 |
void lea(Address dst, AddressLiteral adr); |
|
1066 | 2302 |
void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
2303 |
||
2304 |
void leal32(Register dst, Address src) { leal(dst, src); } |
|
2305 |
||
8871
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diff
changeset
|
2306 |
// Import other testl() methods from the parent class or else |
5c3b26c4119e
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diff
changeset
|
2307 |
// they will be hidden by the following overriding declaration. |
5c3b26c4119e
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diff
changeset
|
2308 |
using Assembler::testl; |
5c3b26c4119e
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iveresov
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diff
changeset
|
2309 |
void testl(Register dst, AddressLiteral src); |
1066 | 2310 |
|
2311 |
void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
|
2312 |
void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
|
2313 |
void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } |
|
2314 |
||
2315 |
void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } |
|
2316 |
void testptr(Register src1, Register src2); |
|
2317 |
||
2318 |
void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } |
|
2319 |
void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } |
|
1 | 2320 |
|
2321 |
// Calls |
|
2322 |
||
2323 |
void call(Label& L, relocInfo::relocType rtype); |
|
2324 |
void call(Register entry); |
|
2325 |
||
2326 |
// NOTE: this call tranfers to the effective address of entry NOT |
|
2327 |
// the address contained by entry. This is because this is more natural |
|
2328 |
// for jumps/calls. |
|
2329 |
void call(AddressLiteral entry); |
|
2330 |
||
2331 |
// Jumps |
|
2332 |
||
2333 |
// NOTE: these jumps tranfer to the effective address of dst NOT |
|
2334 |
// the address contained by dst. This is because this is more natural |
|
2335 |
// for jumps/calls. |
|
2336 |
void jump(AddressLiteral dst); |
|
2337 |
void jump_cc(Condition cc, AddressLiteral dst); |
|
2338 |
||
2339 |
// 32bit can do a case table jump in one instruction but we no longer allow the base |
|
2340 |
// to be installed in the Address class. This jump will tranfers to the address |
|
2341 |
// contained in the location described by entry (not the address of entry) |
|
2342 |
void jump(ArrayAddress entry); |
|
2343 |
||
2344 |
// Floating |
|
2345 |
||
2346 |
void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } |
|
2347 |
void andpd(XMMRegister dst, AddressLiteral src); |
|
2348 |
||
11427 | 2349 |
void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } |
2350 |
void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } |
|
2351 |
void andps(XMMRegister dst, AddressLiteral src); |
|
2352 |
||
2353 |
void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } |
|
1 | 2354 |
void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } |
2355 |
void comiss(XMMRegister dst, AddressLiteral src); |
|
2356 |
||
11427 | 2357 |
void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } |
1 | 2358 |
void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } |
2359 |
void comisd(XMMRegister dst, AddressLiteral src); |
|
2360 |
||
7433 | 2361 |
void fadd_s(Address src) { Assembler::fadd_s(src); } |
2362 |
void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } |
|
2363 |
||
1 | 2364 |
void fldcw(Address src) { Assembler::fldcw(src); } |
2365 |
void fldcw(AddressLiteral src); |
|
2366 |
||
2367 |
void fld_s(int index) { Assembler::fld_s(index); } |
|
2368 |
void fld_s(Address src) { Assembler::fld_s(src); } |
|
2369 |
void fld_s(AddressLiteral src); |
|
2370 |
||
2371 |
void fld_d(Address src) { Assembler::fld_d(src); } |
|
2372 |
void fld_d(AddressLiteral src); |
|
2373 |
||
2374 |
void fld_x(Address src) { Assembler::fld_x(src); } |
|
2375 |
void fld_x(AddressLiteral src); |
|
2376 |
||
7433 | 2377 |
void fmul_s(Address src) { Assembler::fmul_s(src); } |
2378 |
void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } |
|
2379 |
||
1 | 2380 |
void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
2381 |
void ldmxcsr(AddressLiteral src); |
|
2382 |
||
1066 | 2383 |
private: |
2384 |
// these are private because users should be doing movflt/movdbl |
|
2385 |
||
1 | 2386 |
void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
2387 |
void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } |
|
2388 |
void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } |
|
2389 |
void movss(XMMRegister dst, AddressLiteral src); |
|
2390 |
||
11427 | 2391 |
void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
1066 | 2392 |
void movlpd(XMMRegister dst, AddressLiteral src); |
2393 |
||
2394 |
public: |
|
2395 |
||
7433 | 2396 |
void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
2397 |
void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } |
|
11427 | 2398 |
void addsd(XMMRegister dst, AddressLiteral src); |
7433 | 2399 |
|
2400 |
void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } |
|
2401 |
void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } |
|
11427 | 2402 |
void addss(XMMRegister dst, AddressLiteral src); |
7433 | 2403 |
|
2404 |
void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } |
|
2405 |
void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } |
|
11427 | 2406 |
void divsd(XMMRegister dst, AddressLiteral src); |
7433 | 2407 |
|
2408 |
void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } |
|
2409 |
void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } |
|
11427 | 2410 |
void divss(XMMRegister dst, AddressLiteral src); |
7433 | 2411 |
|
7724
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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7433
diff
changeset
|
2412 |
void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
2413 |
void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
a92d706dbdd5
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
7433
diff
changeset
|
2414 |
void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
11427 | 2415 |
void movsd(XMMRegister dst, AddressLiteral src); |
7433 | 2416 |
|
2417 |
void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } |
|
2418 |
void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } |
|
11427 | 2419 |
void mulsd(XMMRegister dst, AddressLiteral src); |
7433 | 2420 |
|
2421 |
void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } |
|
2422 |
void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } |
|
11427 | 2423 |
void mulss(XMMRegister dst, AddressLiteral src); |
7433 | 2424 |
|
2425 |
void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } |
|
2426 |
void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } |
|
11427 | 2427 |
void sqrtsd(XMMRegister dst, AddressLiteral src); |
7433 | 2428 |
|
2429 |
void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } |
|
2430 |
void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } |
|
11427 | 2431 |
void sqrtss(XMMRegister dst, AddressLiteral src); |
7433 | 2432 |
|
2433 |
void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } |
|
2434 |
void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } |
|
11427 | 2435 |
void subsd(XMMRegister dst, AddressLiteral src); |
7433 | 2436 |
|
2437 |
void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } |
|
2438 |
void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } |
|
11427 | 2439 |
void subss(XMMRegister dst, AddressLiteral src); |
1 | 2440 |
|
2441 |
void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } |
|
11427 | 2442 |
void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } |
1 | 2443 |
void ucomiss(XMMRegister dst, AddressLiteral src); |
2444 |
||
2445 |
void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } |
|
11427 | 2446 |
void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } |
1 | 2447 |
void ucomisd(XMMRegister dst, AddressLiteral src); |
2448 |
||
2449 |
// Bitwise Logical XOR of Packed Double-Precision Floating-Point Values |
|
2450 |
void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } |
|
2451 |
void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } |
|
2452 |
void xorpd(XMMRegister dst, AddressLiteral src); |
|
2453 |
||
2454 |
// Bitwise Logical XOR of Packed Single-Precision Floating-Point Values |
|
2455 |
void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } |
|
2456 |
void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } |
|
2457 |
void xorps(XMMRegister dst, AddressLiteral src); |
|
2458 |
||
11429
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2459 |
// AVX 3-operands instructions |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2460 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2461 |
void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2462 |
void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2463 |
void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2464 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2465 |
void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2466 |
void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2467 |
void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2468 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2469 |
void vandpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandpd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2470 |
void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2471 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2472 |
void vandps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandps(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2473 |
void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2474 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2475 |
void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2476 |
void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2477 |
void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2478 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2479 |
void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2480 |
void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2481 |
void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2482 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2483 |
void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2484 |
void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2485 |
void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2486 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2487 |
void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2488 |
void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2489 |
void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2490 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2491 |
void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2492 |
void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2493 |
void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2494 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2495 |
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2496 |
void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2497 |
void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2498 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2499 |
void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2500 |
void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2501 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2502 |
void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); } |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2503 |
void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src); |
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2504 |
|
e894217a5d94
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
11427
diff
changeset
|
2505 |
|
1 | 2506 |
// Data |
2507 |
||
8882
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2508 |
void cmov32( Condition cc, Register dst, Address src); |
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2509 |
void cmov32( Condition cc, Register dst, Register src); |
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2510 |
|
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2511 |
void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } |
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2512 |
|
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2513 |
void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
f852635a6383
7032388: guarantee(VM_Version::supports_cmov()) failed: illegal instruction on i586 after 6919934
twisti
parents:
8871
diff
changeset
|
2514 |
void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
1066 | 2515 |
|
1 | 2516 |
void movoop(Register dst, jobject obj); |
2517 |
void movoop(Address dst, jobject obj); |
|
2518 |
||
2519 |
void movptr(ArrayAddress dst, Register src); |
|
2520 |
// can this do an lea? |
|
2521 |
void movptr(Register dst, ArrayAddress src); |
|
2522 |
||
1066 | 2523 |
void movptr(Register dst, Address src); |
2524 |
||
1 | 2525 |
void movptr(Register dst, AddressLiteral src); |
2526 |
||
1066 | 2527 |
void movptr(Register dst, intptr_t src); |
2528 |
void movptr(Register dst, Register src); |
|
2529 |
void movptr(Address dst, intptr_t src); |
|
2530 |
||
2531 |
void movptr(Address dst, Register src); |
|
2532 |
||
9630
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2533 |
void movptr(Register dst, RegisterOrConstant src) { |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2534 |
if (src.is_constant()) movptr(dst, src.as_constant()); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2535 |
else movptr(dst, src.as_register()); |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2536 |
} |
d6419e4395e3
6939861: JVM should handle more conversion operations
never
parents:
9437
diff
changeset
|
2537 |
|
1066 | 2538 |
#ifdef _LP64 |
2539 |
// Generally the next two are only used for moving NULL |
|
2540 |
// Although there are situations in initializing the mark word where |
|
2541 |
// they could be used. They are dangerous. |
|
2542 |
||
2543 |
// They only exist on LP64 so that int32_t and intptr_t are not the same |
|
2544 |
// and we have ambiguous declarations. |
|
2545 |
||
2546 |
void movptr(Address dst, int32_t imm32); |
|
2547 |
void movptr(Register dst, int32_t imm32); |
|
2548 |
#endif // _LP64 |
|
2549 |
||
1 | 2550 |
// to avoid hiding movl |
2551 |
void mov32(AddressLiteral dst, Register src); |
|
2552 |
void mov32(Register dst, AddressLiteral src); |
|
1066 | 2553 |
|
1 | 2554 |
// to avoid hiding movb |
2555 |
void movbyte(ArrayAddress dst, int src); |
|
2556 |
||
2557 |
// Can push value or effective address |
|
2558 |
void pushptr(AddressLiteral src); |
|
2559 |
||
1066 | 2560 |
void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
2561 |
void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } |
|
2562 |
||
2563 |
void pushoop(jobject obj); |
|
2564 |
||
2565 |
// sign extend as need a l to ptr sized element |
|
2566 |
void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } |
|
2567 |
void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } |
|
2568 |
||
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2569 |
// IndexOf strings. |
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2570 |
// Small strings are loaded through stack if they cross page boundary. |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2571 |
void string_indexof(Register str1, Register str2, |
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2572 |
Register cnt1, Register cnt2, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2573 |
int int_cnt2, Register result, |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2574 |
XMMRegister vec, Register tmp); |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2575 |
|
8494
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2576 |
// IndexOf for constant substrings with size >= 8 elements |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2577 |
// which don't need to be loaded through stack. |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2578 |
void string_indexofC8(Register str1, Register str2, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2579 |
Register cnt1, Register cnt2, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2580 |
int int_cnt2, Register result, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2581 |
XMMRegister vec, Register tmp); |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2582 |
|
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2583 |
// Smallest code: we don't need to load through stack, |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2584 |
// check string tail. |
4258c78226d9
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
8332
diff
changeset
|
2585 |
|
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2586 |
// Compare strings. |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2587 |
void string_compare(Register str1, Register str2, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2588 |
Register cnt1, Register cnt2, Register result, |
8332 | 2589 |
XMMRegister vec1); |
3905
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2590 |
|
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2591 |
// Compare char[] arrays. |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2592 |
void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2593 |
Register limit, Register result, Register chr, |
7d725029ac85
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
2862
diff
changeset
|
2594 |
XMMRegister vec1, XMMRegister vec2); |
1066 | 2595 |
|
6433 | 2596 |
// Fill primitive arrays |
2597 |
void generate_fill(BasicType t, bool aligned, |
|
2598 |
Register to, Register value, Register count, |
|
2599 |
Register rtmp, XMMRegister xtmp); |
|
2600 |
||
1 | 2601 |
#undef VIRTUAL |
2602 |
||
2603 |
}; |
|
2604 |
||
2605 |
/** |
|
2606 |
* class SkipIfEqual: |
|
2607 |
* |
|
2608 |
* Instantiating this class will result in assembly code being output that will |
|
2609 |
* jump around any code emitted between the creation of the instance and it's |
|
2610 |
* automatic destruction at the end of a scope block, depending on the value of |
|
2611 |
* the flag passed to the constructor, which will be checked at run-time. |
|
2612 |
*/ |
|
2613 |
class SkipIfEqual { |
|
2614 |
private: |
|
2615 |
MacroAssembler* _masm; |
|
2616 |
Label _label; |
|
2617 |
||
2618 |
public: |
|
2619 |
SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); |
|
2620 |
~SkipIfEqual(); |
|
2621 |
}; |
|
2622 |
||
2623 |
#ifdef ASSERT |
|
2624 |
inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } |
|
2625 |
#endif |
|
7397 | 2626 |
|
2627 |
#endif // CPU_X86_VM_ASSEMBLER_X86_HPP |