--- a/hotspot/src/cpu/x86/vm/assembler_x86.hpp Wed Jul 05 16:41:01 2017 +0200
+++ b/hotspot/src/cpu/x86/vm/assembler_x86.hpp Wed Sep 17 16:49:18 2008 +0400
@@ -227,9 +227,11 @@
#endif // ASSERT
// accessors
- bool uses(Register reg) const {
- return _base == reg || _index == reg;
- }
+ bool uses(Register reg) const { return _base == reg || _index == reg; }
+ Register base() const { return _base; }
+ Register index() const { return _index; }
+ ScaleFactor scale() const { return _scale; }
+ int disp() const { return _disp; }
// Convert the raw encoding form into the form expected by the constructor for
// Address. An index of 4 (rsp) corresponds to having no index, so convert
@@ -1310,7 +1312,8 @@
// on arguments should also go in here.
class MacroAssembler: public Assembler {
- friend class LIR_Assembler;
+ friend class LIR_Assembler;
+ friend class Runtime1; // as_Address()
protected:
Address as_Address(AddressLiteral adr);
@@ -1453,6 +1456,7 @@
// The pointer will be loaded into the thread register.
void get_thread(Register thread);
+
// Support for VM calls
//
// It is imperative that all calls into the VM are handled via the call_VM macros.
@@ -1527,6 +1531,22 @@
void store_check(Register obj); // store check for obj - register is destroyed afterwards
void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
+ void g1_write_barrier_pre(Register obj,
+#ifndef _LP64
+ Register thread,
+#endif
+ Register tmp,
+ Register tmp2,
+ bool tosca_live);
+ void g1_write_barrier_post(Register store_addr,
+ Register new_val,
+#ifndef _LP64
+ Register thread,
+#endif
+ Register tmp,
+ Register tmp2);
+
+
// split store_check(Register obj) to enhance instruction interleaving
void store_check_part_1(Register obj);
void store_check_part_2(Register obj);