/*

 * Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2014, Red Hat Inc. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "interp_masm_aarch64.hpp"

#include "interpreter/interpreter.hpp"

#include "interpreter/interpreterRuntime.hpp"

#include "oops/arrayOop.hpp"

#include "oops/markOop.hpp"

#include "oops/methodData.hpp"

#include "oops/method.hpp"

#include "prims/jvmtiExport.hpp"

#include "prims/jvmtiThreadState.hpp"

#include "runtime/basicLock.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/thread.inline.hpp"

void InterpreterMacroAssembler::narrow(Register result) {

  // Get method->_constMethod->_result_type

  ldr(rscratch1, Address(rfp, frame::interpreter_frame_method_offset * wordSize));

  ldr(rscratch1, Address(rscratch1, Method::const_offset()));

  ldrb(rscratch1, Address(rscratch1, ConstMethod::result_type_offset()));

  Label done, notBool, notByte, notChar;

  // common case first

  cmpw(rscratch1, T_INT);

  br(Assembler::EQ, done);

  // mask integer result to narrower return type.

  cmpw(rscratch1, T_BOOLEAN);

  br(Assembler::NE, notBool);

  andw(result, result, 0x1);

  b(done);

  bind(notBool);

  cmpw(rscratch1, T_BYTE);

  br(Assembler::NE, notByte);

  sbfx(result, result, 0, 8);

  b(done);

  bind(notByte);

  cmpw(rscratch1, T_CHAR);

  br(Assembler::NE, notChar);

  ubfx(result, result, 0, 16);  // truncate upper 16 bits

  b(done);

  bind(notChar);

  sbfx(result, result, 0, 16);     // sign-extend short

  // Nothing to do for T_INT

  bind(done);

}

void InterpreterMacroAssembler::jump_to_entry(address entry) {

  assert(entry, "Entry must have been generated by now");

  b(entry);

}

void InterpreterMacroAssembler::check_and_handle_popframe(Register java_thread) {

  if (JvmtiExport::can_pop_frame()) {

    Label L;

    // Initiate popframe handling only if it is not already being

    // processed.  If the flag has the popframe_processing bit set, it

    // means that this code is called *during* popframe handling - we

    // don't want to reenter.

    // This method is only called just after the call into the vm in

    // call_VM_base, so the arg registers are available.

    ldrw(rscratch1, Address(rthread, JavaThread::popframe_condition_offset()));

    tstw(rscratch1, JavaThread::popframe_pending_bit);

    br(Assembler::EQ, L);

    tstw(rscratch1, JavaThread::popframe_processing_bit);

    br(Assembler::NE, L);

    // Call Interpreter::remove_activation_preserving_args_entry() to get the

    // address of the same-named entrypoint in the generated interpreter code.

    call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry));

    br(r0);

    bind(L);

  }

}

void InterpreterMacroAssembler::load_earlyret_value(TosState state) {

  ldr(r2, Address(rthread, JavaThread::jvmti_thread_state_offset()));

  const Address tos_addr(r2, JvmtiThreadState::earlyret_tos_offset());

  const Address oop_addr(r2, JvmtiThreadState::earlyret_oop_offset());

  const Address val_addr(r2, JvmtiThreadState::earlyret_value_offset());

  switch (state) {

    case atos: ldr(r0, oop_addr);

               str(zr, oop_addr);

               verify_oop(r0, state);               break;

    case ltos: ldr(r0, val_addr);                   break;

    case btos:                                   // fall through

    case ztos:                                   // fall through

    case ctos:                                   // fall through

    case stos:                                   // fall through

    case itos: ldrw(r0, val_addr);                  break;

    case ftos: ldrs(v0, val_addr);                  break;

    case dtos: ldrd(v0, val_addr);                  break;

    case vtos: /* nothing to do */                  break;

    default  : ShouldNotReachHere();

  }

  // Clean up tos value in the thread object

  movw(rscratch1, (int) ilgl);

  strw(rscratch1, tos_addr);

  strw(zr, val_addr);

}

void InterpreterMacroAssembler::check_and_handle_earlyret(Register java_thread) {

  if (JvmtiExport::can_force_early_return()) {

    Label L;

    ldr(rscratch1, Address(rthread, JavaThread::jvmti_thread_state_offset()));

    cbz(rscratch1, L); // if (thread->jvmti_thread_state() == NULL) exit;

    // Initiate earlyret handling only if it is not already being processed.

    // If the flag has the earlyret_processing bit set, it means that this code

    // is called *during* earlyret handling - we don't want to reenter.

    ldrw(rscratch1, Address(rscratch1, JvmtiThreadState::earlyret_state_offset()));

    cmpw(rscratch1, JvmtiThreadState::earlyret_pending);

    br(Assembler::NE, L);

    // Call Interpreter::remove_activation_early_entry() to get the address of the

    // same-named entrypoint in the generated interpreter code.

    ldr(rscratch1, Address(rthread, JavaThread::jvmti_thread_state_offset()));

    ldrw(rscratch1, Address(rscratch1, JvmtiThreadState::earlyret_tos_offset()));

    call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), rscratch1);

    br(r0);

    bind(L);

  }

}

void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(

  Register reg,

  int bcp_offset) {

  assert(bcp_offset >= 0, "bcp is still pointing to start of bytecode");

  ldrh(reg, Address(rbcp, bcp_offset));

  rev16(reg, reg);

}

void InterpreterMacroAssembler::get_dispatch() {

  unsigned long offset;

  adrp(rdispatch, ExternalAddress((address)Interpreter::dispatch_table()), offset);

  lea(rdispatch, Address(rdispatch, offset));

}

void InterpreterMacroAssembler::get_cache_index_at_bcp(Register index,

                                                       int bcp_offset,

                                                       size_t index_size) {

  assert(bcp_offset > 0, "bcp is still pointing to start of bytecode");

  if (index_size == sizeof(u2)) {

    load_unsigned_short(index, Address(rbcp, bcp_offset));

  } else if (index_size == sizeof(u4)) {

    // assert(EnableInvokeDynamic, "giant index used only for JSR 292");

    ldrw(index, Address(rbcp, bcp_offset));

    // Check if the secondary index definition is still ~x, otherwise

    // we have to change the following assembler code to calculate the

    // plain index.

    assert(ConstantPool::decode_invokedynamic_index(~123) == 123, "else change next line");

    eonw(index, index, zr);  // convert to plain index

  } else if (index_size == sizeof(u1)) {

    load_unsigned_byte(index, Address(rbcp, bcp_offset));

  } else {

    ShouldNotReachHere();

  }

}

// Return

// Rindex: index into constant pool

// Rcache: address of cache entry - ConstantPoolCache::base_offset()

//

// A caller must add ConstantPoolCache::base_offset() to Rcache to get

// the true address of the cache entry.

//

void InterpreterMacroAssembler::get_cache_and_index_at_bcp(Register cache,

                                                           Register index,

                                                           int bcp_offset,

                                                           size_t index_size) {

  assert_different_registers(cache, index);

  assert_different_registers(cache, rcpool);

  get_cache_index_at_bcp(index, bcp_offset, index_size);

  assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below");

  // convert from field index to ConstantPoolCacheEntry

  // aarch64 already has the cache in rcpool so there is no need to

  // install it in cache. instead we pre-add the indexed offset to

  // rcpool and return it in cache. All clients of this method need to

  // be modified accordingly.

  add(cache, rcpool, index, Assembler::LSL, 5);

}

void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register cache,

                                                                        Register index,

                                                                        Register bytecode,

                                                                        int byte_no,

                                                                        int bcp_offset,

                                                                        size_t index_size) {

  get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size);

  // We use a 32-bit load here since the layout of 64-bit words on

  // little-endian machines allow us that.

  // n.b. unlike x86 cache already includes the index offset

  lea(bytecode, Address(cache,

                         ConstantPoolCache::base_offset()

                         + ConstantPoolCacheEntry::indices_offset()));

  ldarw(bytecode, bytecode);

  const int shift_count = (1 + byte_no) * BitsPerByte;

  ubfx(bytecode, bytecode, shift_count, BitsPerByte);

}

void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,

                                                               Register tmp,

                                                               int bcp_offset,

                                                               size_t index_size) {

  assert(cache != tmp, "must use different register");

  get_cache_index_at_bcp(tmp, bcp_offset, index_size);

  assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below");

  // convert from field index to ConstantPoolCacheEntry index

  // and from word offset to byte offset

  assert(exact_log2(in_bytes(ConstantPoolCacheEntry::size_in_bytes())) == 2 + LogBytesPerWord, "else change next line");

  ldr(cache, Address(rfp, frame::interpreter_frame_cache_offset * wordSize));

  // skip past the header

  add(cache, cache, in_bytes(ConstantPoolCache::base_offset()));

  add(cache, cache, tmp, Assembler::LSL, 2 + LogBytesPerWord);  // construct pointer to cache entry

}

void InterpreterMacroAssembler::get_method_counters(Register method,

                                                    Register mcs, Label& skip) {

  Label has_counters;

  ldr(mcs, Address(method, Method::method_counters_offset()));

  cbnz(mcs, has_counters);

  call_VM(noreg, CAST_FROM_FN_PTR(address,

          InterpreterRuntime::build_method_counters), method);

  ldr(mcs, Address(method, Method::method_counters_offset()));

  cbz(mcs, skip); // No MethodCounters allocated, OutOfMemory

  bind(has_counters);

}

// Load object from cpool->resolved_references(index)

void InterpreterMacroAssembler::load_resolved_reference_at_index(

                                           Register result, Register index) {

  assert_different_registers(result, index);

  // convert from field index to resolved_references() index and from

  // word index to byte offset. Since this is a java object, it can be compressed

  Register tmp = index;  // reuse

  lslw(tmp, tmp, LogBytesPerHeapOop);

  get_constant_pool(result);

  // load pointer for resolved_references[] objArray

  ldr(result, Address(result, ConstantPool::resolved_references_offset_in_bytes()));

  // JNIHandles::resolve(obj);

  ldr(result, Address(result, 0));

  // Add in the index

  add(result, result, tmp);

  load_heap_oop(result, Address(result, arrayOopDesc::base_offset_in_bytes(T_OBJECT)));

}

// Generate a subtype check: branch to ok_is_subtype if sub_klass is a

// subtype of super_klass.

//

// Args:

//      r0: superklass

//      Rsub_klass: subklass

//

// Kills:

//      r2, r5

void InterpreterMacroAssembler::gen_subtype_check(Register Rsub_klass,

                                                  Label& ok_is_subtype) {

  assert(Rsub_klass != r0, "r0 holds superklass");

  assert(Rsub_klass != r2, "r2 holds 2ndary super array length");

  assert(Rsub_klass != r5, "r5 holds 2ndary super array scan ptr");

  // Profile the not-null value's klass.

  profile_typecheck(r2, Rsub_klass, r5); // blows r2, reloads r5

  // Do the check.

  check_klass_subtype(Rsub_klass, r0, r2, ok_is_subtype); // blows r2

  // Profile the failure of the check.

  profile_typecheck_failed(r2); // blows r2

}

// Java Expression Stack

void InterpreterMacroAssembler::pop_ptr(Register r) {

  ldr(r, post(esp, wordSize));

}

void InterpreterMacroAssembler::pop_i(Register r) {

  ldrw(r, post(esp, wordSize));

}

void InterpreterMacroAssembler::pop_l(Register r) {

  ldr(r, post(esp, 2 * Interpreter::stackElementSize));

}

void InterpreterMacroAssembler::push_ptr(Register r) {

  str(r, pre(esp, -wordSize));

 }

void InterpreterMacroAssembler::push_i(Register r) {

  str(r, pre(esp, -wordSize));

}

void InterpreterMacroAssembler::push_l(Register r) {

  str(r, pre(esp, 2 * -wordSize));

}

void InterpreterMacroAssembler::pop_f(FloatRegister r) {

  ldrs(r, post(esp, wordSize));

}

void InterpreterMacroAssembler::pop_d(FloatRegister r) {

  ldrd(r, post(esp, 2 * Interpreter::stackElementSize));

}

void InterpreterMacroAssembler::push_f(FloatRegister r) {

  strs(r, pre(esp, -wordSize));

}

void InterpreterMacroAssembler::push_d(FloatRegister r) {

  strd(r, pre(esp, 2* -wordSize));

}

void InterpreterMacroAssembler::pop(TosState state) {

  switch (state) {

  case atos: pop_ptr();                 break;

  case btos:

  case ztos:

  case ctos:

  case stos:

  case itos: pop_i();                   break;

  case ltos: pop_l();                   break;

  case ftos: pop_f();                   break;

  case dtos: pop_d();                   break;

  case vtos: /* nothing to do */        break;

  default:   ShouldNotReachHere();

  }

  verify_oop(r0, state);

}

void InterpreterMacroAssembler::push(TosState state) {

  verify_oop(r0, state);

  switch (state) {

  case atos: push_ptr();                break;

  case btos:

  case ztos:

  case ctos:

  case stos:

  case itos: push_i();                  break;

  case ltos: push_l();                  break;

  case ftos: push_f();                  break;

  case dtos: push_d();                  break;

  case vtos: /* nothing to do */        break;

  default  : ShouldNotReachHere();

  }

}

// Helpers for swap and dup

void InterpreterMacroAssembler::load_ptr(int n, Register val) {

  ldr(val, Address(esp, Interpreter::expr_offset_in_bytes(n)));

}

void InterpreterMacroAssembler::store_ptr(int n, Register val) {

  str(val, Address(esp, Interpreter::expr_offset_in_bytes(n)));

}

void InterpreterMacroAssembler::prepare_to_jump_from_interpreted() {

  // set sender sp

  mov(r13, sp);

  // record last_sp

  str(esp, Address(rfp, frame::interpreter_frame_last_sp_offset * wordSize));

}

// Jump to from_interpreted entry of a call unless single stepping is possible

// in this thread in which case we must call the i2i entry

void InterpreterMacroAssembler::jump_from_interpreted(Register method, Register temp) {

  prepare_to_jump_from_interpreted();

  if (JvmtiExport::can_post_interpreter_events()) {

    Label run_compiled_code;

    // JVMTI events, such as single-stepping, are implemented partly by avoiding running

    // compiled code in threads for which the event is enabled.  Check here for

    // interp_only_mode if these events CAN be enabled.

    // interp_only is an int, on little endian it is sufficient to test the byte only

    // Is a cmpl faster?

    ldr(rscratch1, Address(rthread, JavaThread::interp_only_mode_offset()));

    cbz(rscratch1, run_compiled_code);

    ldr(rscratch1, Address(method, Method::interpreter_entry_offset()));

    br(rscratch1);

    bind(run_compiled_code);

  }

  ldr(rscratch1, Address(method, Method::from_interpreted_offset()));

  br(rscratch1);

}

// The following two routines provide a hook so that an implementation

// can schedule the dispatch in two parts.  amd64 does not do this.

void InterpreterMacroAssembler::dispatch_prolog(TosState state, int step) {

}

void InterpreterMacroAssembler::dispatch_epilog(TosState state, int step) {

    dispatch_next(state, step);

}

void InterpreterMacroAssembler::dispatch_base(TosState state,

                                              address* table,

                                              bool verifyoop) {

  if (VerifyActivationFrameSize) {

    Unimplemented();

  }

  if (verifyoop) {

    verify_oop(r0, state);

  }

  if (table == Interpreter::dispatch_table(state)) {

    addw(rscratch2, rscratch1, Interpreter::distance_from_dispatch_table(state));

    ldr(rscratch2, Address(rdispatch, rscratch2, Address::uxtw(3)));

  } else {

    mov(rscratch2, (address)table);

    ldr(rscratch2, Address(rscratch2, rscratch1, Address::uxtw(3)));

  }

  br(rscratch2);

}

void InterpreterMacroAssembler::dispatch_only(TosState state) {

  dispatch_base(state, Interpreter::dispatch_table(state));

}

void InterpreterMacroAssembler::dispatch_only_normal(TosState state) {

  dispatch_base(state, Interpreter::normal_table(state));

}

void InterpreterMacroAssembler::dispatch_only_noverify(TosState state) {

  dispatch_base(state, Interpreter::normal_table(state), false);

}

void InterpreterMacroAssembler::dispatch_next(TosState state, int step) {

  // load next bytecode

  ldrb(rscratch1, Address(pre(rbcp, step)));

  dispatch_base(state, Interpreter::dispatch_table(state));

}

void InterpreterMacroAssembler::dispatch_via(TosState state, address* table) {

  // load current bytecode

  ldrb(rscratch1, Address(rbcp, 0));

  dispatch_base(state, table);

}

// remove activation

//

// Unlock the receiver if this is a synchronized method.

// Unlock any Java monitors from syncronized blocks.

// Remove the activation from the stack.

//

// If there are locked Java monitors

//    If throw_monitor_exception

//       throws IllegalMonitorStateException

//    Else if install_monitor_exception

//       installs IllegalMonitorStateException

//    Else

//       no error processing

void InterpreterMacroAssembler::remove_activation(

        TosState state,

        bool throw_monitor_exception,

        bool install_monitor_exception,

        bool notify_jvmdi) {

  // Note: Registers r3 xmm0 may be in use for the

  // result check if synchronized method

  Label unlocked, unlock, no_unlock;

  // get the value of _do_not_unlock_if_synchronized into r3

  const Address do_not_unlock_if_synchronized(rthread,

    in_bytes(JavaThread::do_not_unlock_if_synchronized_offset()));

  ldrb(r3, do_not_unlock_if_synchronized);

  strb(zr, do_not_unlock_if_synchronized); // reset the flag

 // get method access flags

  ldr(r1, Address(rfp, frame::interpreter_frame_method_offset * wordSize));

  ldr(r2, Address(r1, Method::access_flags_offset()));

  tst(r2, JVM_ACC_SYNCHRONIZED);

  br(Assembler::EQ, unlocked);

  // Don't unlock anything if the _do_not_unlock_if_synchronized flag

  // is set.

  cbnz(r3, no_unlock);

  // unlock monitor

  push(state); // save result

  // BasicObjectLock will be first in list, since this is a

  // synchronized method. However, need to check that the object has

  // not been unlocked by an explicit monitorexit bytecode.

  const Address monitor(rfp, frame::interpreter_frame_initial_sp_offset *

                        wordSize - (int) sizeof(BasicObjectLock));

  // We use c_rarg1 so that if we go slow path it will be the correct