test/hotspot/jtreg/compiler/c2/aarch64/TestVolatiles.java
author rkennke
Mon, 10 Dec 2018 15:47:44 +0100
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child 55587 4644b3155fce
permissions -rw-r--r--
8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental) Reviewed-by: kvn, roland, shade, coleenp, lmesnik, pliden, jgeorge, ihse, erikj Contributed-by: Christine Flood <chf@redhat.com>, Aleksey Shipilev <shade@redhat.com>, Roland Westrelin <rwestrel@redhat.com>, Zhenygu Gu <zgu@redhat.com>, Andrew Haley <aph@redhat.com>, Andrew Dinn <adinn@redhat.com>, Mario Torre <mtorre@redhat.com>, Roman Kennke <rkennke@redhat.com>
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/*
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 * Copyright (c) 2018, Red Hat, Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 */
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/*
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 * common code to run and validate tests of code generation for
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 * volatile ops on AArch64
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 *
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 * incoming args are <testclass> <testtype>
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 *
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 * where <testclass> in {TestVolatileLoad,
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 *                       TestVolatileStore,
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 *                       TestUnsafeVolatileLoad,
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 *                       TestUnsafeVolatileStore,
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 *                       TestUnsafeVolatileCAS,
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 *                       TestUnsafeVolatileWeakCAS,
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 *                       TestUnsafeVolatileCAE,
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 *                       TestUnsafeVolatileGAS}
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 * and <testtype> in {G1,
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 *                    CMS,
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 *                    CMSCondMark,
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 *                    Serial,
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 *                    Parallel,
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 *                    Shenandoah,
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 *                    ShenandoahTraversal}
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 */
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package compiler.c2.aarch64;
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import java.util.List;
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import java.util.ListIterator;
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import java.util.Iterator;
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import java.util.regex.Pattern;
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import java.io.*;
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import jdk.test.lib.Asserts;
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import jdk.test.lib.compiler.InMemoryJavaCompiler;
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import jdk.test.lib.process.OutputAnalyzer;
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import jdk.test.lib.process.ProcessTools;
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import sun.hotspot.WhiteBox;
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// runner class that spawns a new JVM to exercises a combination of
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// volatile MemOp and GC. The ops are compiled with the dmb -->
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// ldar/stlr transforms either enabled or disabled. this runner parses
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// the PrintOptoAssembly output checking that the generated code is
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// correct.
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public class TestVolatiles {
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    public void runtest(String classname, String testType) throws Throwable {
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        // n.b. clients omit the package name for the class
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        String fullclassname = "compiler.c2.aarch64." + classname;
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        // build up a command line for the spawned JVM
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        String[] procArgs;
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        int argcount;
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        // add one or two extra arguments according to test type
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        // i.e. GC type plus GC conifg
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        switch(testType) {
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        case "G1":
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            argcount = 9;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseG1GC";
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            break;
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        case "Parallel":
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            argcount = 9;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseParallelGC";
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            break;
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        case "Serial":
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            argcount = 9;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseSerialGC";
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            break;
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        case "CMS":
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            argcount = 10;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UseConcMarkSweepGC";
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            procArgs[argcount - 2] = "-XX:-UseCondCardMark";
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            break;
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        case "CMSCondMark":
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            argcount = 10;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UseConcMarkSweepGC";
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            procArgs[argcount - 2] = "-XX:+UseCondCardMark";
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            break;
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        case "Shenandoah":
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            argcount = 10;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UnlockExperimentalVMOptions";
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            procArgs[argcount - 2] = "-XX:+UseShenandoahGC";
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            break;
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        case "ShenandoahTraversal":
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            argcount = 11;
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            procArgs = new String[argcount];
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            procArgs[argcount - 4] = "-XX:+UnlockExperimentalVMOptions";
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            procArgs[argcount - 3] = "-XX:+UseShenandoahGC";
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            procArgs[argcount - 2] = "-XX:ShenandoahGCHeuristics=traversal";
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            break;
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        default:
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            throw new RuntimeException("unexpected test type " + testType);
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        }
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        // fill in arguments common to all cases
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        // the first round of test enables transform of barriers to
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        // use acquiring loads and releasing stores by setting arg
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        // zero appropriately. this arg is reset in the second run to
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        // disable the transform.
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        procArgs[0] = "-XX:-UseBarriersForVolatile";
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        procArgs[1] = "-XX:+UseCompressedOops";
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        procArgs[2] = "-XX:-TieredCompilation";
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        procArgs[3] = "-XX:+PrintOptoAssembly";
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        procArgs[4] = "-XX:CompileCommand=compileonly," + fullclassname + "::" + "test*";
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        procArgs[5] = "--add-exports";
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        procArgs[6] = "java.base/jdk.internal.misc=ALL-UNNAMED";
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        procArgs[argcount - 1] = fullclassname;
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        runtest(classname, testType, false, true, procArgs);
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        // rerun the test class without the transform applied and
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        // check the alternative generation is as expected
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        procArgs[0] = "-XX:+UseBarriersForVolatile";
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        runtest(classname, testType, true, true, procArgs);
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        if (!classname.equals("TestUnsafeVolatileGAA")) {
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            procArgs[0] = "-XX:-UseBarriersForVolatile";
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            procArgs[1] = "-XX:-UseCompressedOops";
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            runtest(classname, testType, false, false, procArgs);
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            procArgs[0] = "-XX:+UseBarriersForVolatile";
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            runtest(classname, testType, true, false, procArgs);
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        }
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    }
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    public void runtest(String classname, String testType, boolean useBarriersForVolatile, boolean useCompressedOops, String[] procArgs) throws Throwable {
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        ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(procArgs);
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        OutputAnalyzer output = new OutputAnalyzer(pb.start());
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        output.stderrShouldBeEmptyIgnoreVMWarnings();
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        output.stdoutShouldNotBeEmpty();
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        output.shouldHaveExitValue(0);
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        // check the output for the correct asm sequence as
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        // appropriate to test class, test type and whether transform
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        // was applied
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        checkoutput(output, classname, testType, useBarriersForVolatile, useCompressedOops);
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    }
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    // skip through output returning a line containing the desireed
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    // substring or null
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    private String skipTo(Iterator<String> iter, String substring)
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    {
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        while (iter.hasNext()) {
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            String nextLine = iter.next();
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            if (nextLine.matches(".*" + substring + ".*")) {
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                return nextLine;
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            }
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        }
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        return null;
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    }
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    // locate the start of compiler output for the desired method and
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    // then check that each expected instruction occurs in the output
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    // in the order supplied. throw an excpetion if not found.
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    // n.b. the spawned JVM's output is included in the exception
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    // message to make it easeir to identify what is missing.
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    private boolean checkCompile(Iterator<String> iter, String methodname, String[] expected, OutputAnalyzer output, boolean do_throw)
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    {
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        // trace call to allow eyeball check of what we are checking against
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        System.out.println("checkCompile(" + methodname + ",");
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        String sepr = "  { ";
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        for (String s : expected) {
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            System.out.print(sepr);
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            System.out.print(s);
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            sepr = ",\n    ";
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        }
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        System.out.println(" })");
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        // look for the start of an opto assembly print block
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        String match = skipTo(iter, Pattern.quote("{method}"));
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        if (match == null) {
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            if (do_throw) {
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                throw new RuntimeException("Missing compiler output for " + methodname + "!\n\n" + output.getOutput());
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            }
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            return false;
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        }
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        // check the compiled method name is right
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        match = skipTo(iter, Pattern.quote("- name:"));
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        if (match == null) {
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            if (do_throw) {
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                throw new RuntimeException("Missing compiled method name!\n\n" + output.getOutput());
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            }
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            return false;
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        }
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        if (!match.contains(methodname)) {
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            if (do_throw) {
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                throw new RuntimeException("Wrong method " + match + "!\n  -- expecting " + methodname + "\n\n" + output.getOutput());
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            }
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            return false;
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        }
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        // make sure we can match each expected term in order
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        for (String s : expected) {
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            match = skipTo(iter, s);
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            if (match == null) {
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                if (do_throw) {
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                    throw new RuntimeException("Missing expected output " + s + "!\n\n" + output.getOutput());
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                }
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                return false;
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            }
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        }
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        return true;
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    }
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    // check for expected asm output from a volatile load
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    private void checkload(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
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    {
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        Iterator<String> iter = output.asLines().listIterator();
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        // we shoud see this same sequence for normal or unsafe volatile load
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        // for both int and Object fields
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        String[] matches;
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        if (!useBarriersForVolatile) {
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            matches = new String[] {
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                "ldarw",
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                "membar_acquire \\(elided\\)",
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                "ret"
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            };
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        } else {
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            matches = new String[] {
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                "ldrw",
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                "membar_acquire",
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                "dmb ish",
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                "ret"
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            };
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        }
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        checkCompile(iter, "testInt", matches, output, true);
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        if (!useBarriersForVolatile) {
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            matches = new String[] {
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                useCompressedOops ? "ldarw?" : "ldar",
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                "membar_acquire \\(elided\\)",
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                "ret"
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            };
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        } else {
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            matches = new String[] {
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                useCompressedOops ? "ldrw?" : "ldr",
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                "membar_acquire",
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                "dmb ish",
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                "ret"
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            };
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        }
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        checkCompile(iter, "testObj", matches, output, true);
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    }
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   285
    // check for expected asm output from a volatile store
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   286
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   287
    private void checkstore(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   288
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   289
        Iterator<String> iter = output.asLines().listIterator();
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   290
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   291
        String[] matches;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   292
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   293
        // non object stores are straightforward
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   294
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   295
            // this is the sequence of instructions for all cases
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   296
            matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   297
                "membar_release \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   298
                "stlrw",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   299
                "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   300
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   301
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   302
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   303
            // this is the alternative sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   304
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   305
                "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   306
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   307
                "strw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   308
                "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   309
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   310
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   311
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   312
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   313
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   314
        checkCompile(iter, "testInt", matches, output, true);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   315
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   316
        // object stores will be as above except for when the GC
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   317
        // introduces barriers for card marking
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   318
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   319
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   320
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   321
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   322
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   323
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   324
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   325
                    useCompressedOops ? "stlrw?" : "stlr",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   326
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   327
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   328
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   329
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   330
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   331
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   332
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   333
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   334
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   335
                    useCompressedOops ? "stlrw?" : "stlr",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   336
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   337
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   338
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   339
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   340
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   341
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   342
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   343
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   344
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   345
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   346
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   347
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   348
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   349
                    useCompressedOops ? "stlrw?" : "stlr",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   350
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   351
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   352
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   353
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   354
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   355
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   356
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   357
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   358
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   359
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   360
                // before the card mark strb from the StoreCM and the
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   361
                // storestore barrier from the StoreCM should be
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   362
                // generated as "dmb ishst"
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   363
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   364
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   365
                    useCompressedOops ? "stlrw?" : "stlr",
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   366
                    "storestore",
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   367
                    "dmb ishst",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   368
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   369
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   370
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   371
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   372
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   373
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   374
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   375
                 // Shenandoah generates normal object graphs for
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   376
                 // volatile stores
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   377
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   378
                    "membar_release \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   379
                    useCompressedOops ? "stlrw?" : "stlr",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   380
                    "membar_volatile \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   381
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   382
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   383
                break;
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   384
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   385
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   386
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   387
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   388
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   389
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   390
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   391
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   392
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   393
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   394
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   395
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   396
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   397
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   398
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   399
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   400
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   401
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   402
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   403
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   404
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   405
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   406
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   407
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   408
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   409
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   410
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   411
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   412
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   413
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   414
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   415
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   416
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   417
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   418
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   419
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   420
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   421
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   422
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   423
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   424
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   425
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   426
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   427
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   428
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   429
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   430
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   431
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   432
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   433
                // storestore barrier from the StoreCM should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   434
                // as "dmb ishst"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   435
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   436
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   437
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   438
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   439
                    "storestore",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   440
                    "dmb ishst",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   441
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   442
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   443
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   444
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   445
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   446
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   447
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   448
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   449
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   450
                 // Shenandoah generates normal object graphs for
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   451
                 // volatile stores
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   452
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   453
                    "membar_release",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   454
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   455
                    useCompressedOops ? "strw?" : "str",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   456
                    "membar_volatile",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   457
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   458
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   459
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   460
                break;
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   461
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   462
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   463
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   464
        checkCompile(iter, "testObj", matches, output, true);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   465
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   466
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   467
    // check for expected asm output from a volatile cas
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   468
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   469
    private void checkcas(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   470
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   471
        Iterator<String> iter = output.asLines().listIterator();
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   472
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   473
        String[] matches;
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   474
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   475
            { "testInt", "cmpxchgw" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   476
            { "testLong", "cmpxchg" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   477
            { "testByte", "cmpxchgb" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   478
            { "testShort", "cmpxchgs" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   479
        };
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   480
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   481
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   482
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   483
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   484
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   485
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   486
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   487
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   488
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   489
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   490
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   491
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   492
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   493
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   494
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   495
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   496
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   497
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   498
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   499
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   500
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   501
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   502
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   503
            checkCompile(iter, test[0], matches, output, true);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   504
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   505
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   506
        // object stores will be as above except for when the GC
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   507
        // introduces barriers for card marking
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   508
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   509
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   510
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   511
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   512
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   513
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   514
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   515
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   516
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   517
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   518
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   519
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   520
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   521
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   522
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   523
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   524
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   525
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   526
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   527
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   528
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   529
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   530
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   531
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   532
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   533
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   534
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   535
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   536
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   537
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   538
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   539
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   540
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   541
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   542
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   543
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   544
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   545
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   546
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   547
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   548
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   549
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   550
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   551
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   552
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   553
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   554
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   555
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   556
                    "storestore",
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   557
                    "dmb ishst",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   558
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   559
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   560
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   561
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   562
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   563
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   564
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   565
                // For volatile CAS, Shenanodoah generates normal
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   566
                // graphs with a shenandoah-specific cmpxchg
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   567
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   568
                    "membar_release \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   569
                    useCompressedOops ? "cmpxchgw?_acq_shenandoah" : "cmpxchg_acq_shenandoah",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   570
                    "membar_acquire \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   571
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   572
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   573
                break;
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   574
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   575
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   576
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   577
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   578
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   579
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   580
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   581
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   582
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   583
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   584
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   585
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   586
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   587
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   588
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   589
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   590
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   591
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   592
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   593
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   594
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   595
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   596
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   597
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   598
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   599
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   600
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   601
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   602
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   603
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   604
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   605
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   606
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   607
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   608
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   609
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   610
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   611
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   612
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   613
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   614
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   615
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   616
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   617
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   618
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   619
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   620
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   621
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   622
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   623
                // storestore barrier from the StoreCM should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   624
                // as "dmb ishst"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   625
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   626
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   627
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   628
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   629
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   630
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   631
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   632
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   633
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   634
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   635
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   636
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   637
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   638
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   639
                // For volatile CAS, Shenanodoah generates normal
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   640
                // graphs with a shenandoah-specific cmpxchg
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   641
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   642
                    "membar_release",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   643
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   644
                    useCompressedOops ? "cmpxchgw?_shenandoah" : "cmpxchg_shenandoah",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   645
                    "membar_acquire",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   646
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   647
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   648
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   649
                break;
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   650
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   651
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   652
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   653
        checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   654
    }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   655
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   656
    private void checkcae(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   657
    {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   658
        ListIterator<String> iter = output.asLines().listIterator();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   659
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   660
        String[] matches;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   661
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   662
            { "testInt", "cmpxchgw" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   663
            { "testLong", "cmpxchg" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   664
            { "testByte", "cmpxchgb" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   665
            { "testShort", "cmpxchgs" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   666
        };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   667
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   668
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   669
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   670
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   671
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   672
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   673
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   674
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   675
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   676
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   677
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   678
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   679
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   680
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   681
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   682
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   683
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   684
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   685
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   686
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   687
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   688
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   689
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   690
            checkCompile(iter, test[0], matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   691
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   692
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   693
        // object stores will be as above except for when the GC
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   694
        // introduces barriers for card marking
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   695
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   696
        if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   697
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   698
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   699
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   700
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   701
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   702
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   703
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   704
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   705
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   706
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   707
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   708
                // card marking store may be scheduled before or after
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   709
                // the cmpxchg so try both sequences.
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   710
                int idx = iter.nextIndex();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   711
                if (!checkCompile(iter, "testObj", matches, output, false)) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   712
                    iter = output.asLines().listIterator(idx);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   713
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   714
                    matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   715
                        "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   716
                        useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   717
                        "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   718
                        "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   719
                        "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   720
                    };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   721
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   722
                    checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   723
                }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   724
                return;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   725
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   726
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   727
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   728
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   729
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   730
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   731
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   732
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   733
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   734
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   735
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   736
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   737
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   738
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   739
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   740
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   741
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   742
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   743
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   744
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   745
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   746
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   747
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   748
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   749
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   750
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   751
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   752
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   753
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   754
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   755
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   756
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   757
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   758
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   759
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   760
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   761
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   762
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   763
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   764
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   765
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   766
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   767
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   768
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   769
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   770
                // For volatile CAS, Shenanodoah generates normal
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   771
                // graphs with a shenandoah-specific cmpxchg
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   772
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   773
                    "membar_release \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   774
                    useCompressedOops ? "cmpxchgw?_acq_shenandoah" : "cmpxchg_acq_shenandoah",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   775
                    "membar_acquire \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   776
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   777
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   778
                break;
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   779
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   780
        } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   781
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   782
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   783
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   784
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   785
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   786
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   787
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   788
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   789
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   790
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   791
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   792
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   793
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   794
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   795
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   796
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   797
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   798
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   799
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   800
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   801
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   802
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   803
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   804
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   805
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   806
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   807
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   808
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   809
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   810
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   811
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   812
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   813
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   814
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   815
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   816
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   817
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   818
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   819
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   820
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   821
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   822
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   823
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   824
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   825
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   826
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   827
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   828
                // storestore barrier from the StoreCM should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   829
                // as "dmb ishst"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   830
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   831
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   832
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   833
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   834
                    "storestore",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   835
                    "dmb ishst",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   836
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   837
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   838
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   839
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   840
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   841
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   842
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   843
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   844
                // For volatile CAS, Shenanodoah generates normal
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   845
                // graphs with a shenandoah-specific cmpxchg
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   846
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   847
                    "membar_release",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   848
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   849
                    useCompressedOops ? "cmpxchgw?_shenandoah" : "cmpxchg_shenandoah",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   850
                    "membar_acquire",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   851
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   852
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   853
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   854
                break;
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   855
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   856
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   857
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   858
        checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   859
    }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   860
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   861
    private void checkgas(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   862
    {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   863
        Iterator<String> iter = output.asLines().listIterator();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   864
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   865
        String[] matches;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   866
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   867
            { "testInt", "atomic_xchgw" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   868
            { "testLong", "atomic_xchg" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   869
        };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   870
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   871
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   872
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   873
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   874
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   875
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   876
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   877
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   878
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   879
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   880
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   881
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   882
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   883
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   884
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   885
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   886
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   887
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   888
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   889
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   890
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   891
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   892
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   893
            checkCompile(iter, test[0], matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   894
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   895
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   896
        // object stores will be as above except for when the GC
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   897
        // introduces barriers for card marking
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   898
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   899
        if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   900
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   901
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   902
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   903
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   904
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   905
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   906
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   907
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   908
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   909
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   910
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   911
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   912
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   913
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   914
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   915
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   916
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   917
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   918
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   919
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   920
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   921
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   922
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   923
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   924
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   925
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   926
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   927
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   928
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   929
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   930
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   931
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   932
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   933
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   934
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   935
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   936
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   937
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   938
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   939
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   940
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   941
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   942
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   943
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   944
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   945
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   946
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   947
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   948
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   949
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   950
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   951
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   952
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   953
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   954
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   955
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   956
                    "membar_release \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   957
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   958
                    "membar_acquire \\(elided\\)",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   959
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   960
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
   961
                break;
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   962
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   963
        } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   964
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   965
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   966
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   967
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   968
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   969
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   970
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   971
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   972
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   973
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   974
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   975
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   976
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   977
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   978
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   979
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   980
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   981
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   982
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   983
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   984
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   985
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   986
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   987
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   988
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   989
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   990
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   991
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   992
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   993
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   994
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   995
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   996
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   997
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   998
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   999
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1000
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1001
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1002
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1003
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1004
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1005
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1006
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1007
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1008
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1009
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1010
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1011
                // storestore barrier from the StoreCM should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1012
                // as "dmb ishst"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1013
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1014
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1015
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1016
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1017
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1018
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1019
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1020
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1021
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1022
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1023
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1024
                break;
52925
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1025
            case "Shenandoah":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1026
            case "ShenandoahTraversal":
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1027
                matches = new String[] {
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1028
                    "membar_release",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1029
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1030
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1031
                    "membar_acquire",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1032
                    "dmb ish",
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1033
                    "ret"
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1034
                };
9c18c9d839d3 8214259: Implementation: JEP 189: Shenandoah: A Low-Pause-Time Garbage Collector (Experimental)
rkennke
parents: 52409
diff changeset
  1035
                break;
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1036
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1037
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1038
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1039
        checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1040
    }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1041
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1042
    private void checkgaa(OutputAnalyzer output, String testType, boolean useBarriersForVolatile) throws Throwable
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1043
    {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1044
        Iterator<String> iter = output.asLines().listIterator();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1045
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1046
        String[] matches;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1047
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1048
            { "testInt", "get_and_addI" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1049
            { "testLong", "get_and_addL" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1050
        };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1051
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1052
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1053
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1054
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1055
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1056
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1057
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1058
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1059
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1060
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1061
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1062
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1063
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1064
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1065
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1066
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1067
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1068
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1069
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1070
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1071
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1072
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1073
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1074
            checkCompile(iter, test[0], matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1075
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1076
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1077
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1078
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1079
    // perform a check appropriate to the classname
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1080
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1081
    private void checkoutput(OutputAnalyzer output, String classname, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1082
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1083
        // trace call to allow eyeball check of what is being checked
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1084
        System.out.println("checkoutput(" +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1085
                           classname + ", " +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1086
                           testType + ", " +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1087
                           useBarriersForVolatile + ")\n" +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1088
                           output.getOutput());
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1089
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1090
        switch (classname) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1091
        case "TestVolatileLoad":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1092
            checkload(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1093
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1094
        case "TestVolatileStore":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1095
            checkstore(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1096
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1097
        case "TestUnsafeVolatileLoad":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1098
            checkload(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1099
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1100
        case "TestUnsafeVolatileStore":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1101
            checkstore(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1102
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1103
        case "TestUnsafeVolatileCAS":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1104
        case "TestUnsafeVolatileWeakCAS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1105
            checkcas(output, testType, useBarriersForVolatile, useCompressedOops);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1106
            break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1107
        case "TestUnsafeVolatileCAE":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1108
            checkcae(output, testType, useBarriersForVolatile, useCompressedOops);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1109
            break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1110
        case "TestUnsafeVolatileGAS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1111
            checkgas(output, testType, useBarriersForVolatile, useCompressedOops);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1112
            break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1113
        case "TestUnsafeVolatileGAA":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1114
            checkgaa(output, testType, useBarriersForVolatile);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1115
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1116
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1117
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1118
}