test/hotspot/jtreg/compiler/c2/aarch64/TestVolatiles.java
author adinn
Mon, 09 Jul 2018 09:38:11 +0100
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child 52409 87bc444ca642
permissions -rw-r--r--
8206163: AArch64: incorrect code generation for StoreCM Summary: StoreCM may require planting a StoreStore barrier Reviewed-by: aph, zyao, roland
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/*
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 * Copyright (c) 2018, Red Hat, Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 */
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/*
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 * common code to run and validate tests of code generation for
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 * volatile ops on AArch64
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 *
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 * incoming args are <testclass> <testtype>
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 *
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 * where <testclass> in {TestVolatileLoad,
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 *                       TestVolatileStore,
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 *                       TestUnsafeVolatileLoad,
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 *                       TestUnsafeVolatileStore,
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 *                       TestUnsafeVolatileCAS}
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 * and <testtype> in {G1,
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 *                    CMS,
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 *                    CMSCondMark,
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 *                    Serial,
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 *                    Parallel}
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 */
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package compiler.c2.aarch64;
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import java.util.List;
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import java.util.Iterator;
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import java.io.*;
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import jdk.test.lib.Asserts;
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import jdk.test.lib.compiler.InMemoryJavaCompiler;
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import jdk.test.lib.process.OutputAnalyzer;
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import jdk.test.lib.process.ProcessTools;
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// runner class that spawns a new JVM to exercises a combination of
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// volatile MemOp and GC. The ops are compiled with the dmb -->
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// ldar/stlr transforms either enabled or disabled. this runner parses
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// the PrintOptoAssembly output checking that the generated code is
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// correct.
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public class TestVolatiles {
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    public void runtest(String classname, String testType) throws Throwable {
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        // n.b. clients omit the package name for the class
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        String fullclassname = "compiler.c2.aarch64." + classname;
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        // build up a command line for the spawned JVM
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        String[] procArgs;
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        int argcount;
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        // add one or two extra arguments according to test type
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        // i.e. GC type plus GC conifg
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        switch(testType) {
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        case "G1":
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            argcount = 8;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseG1GC";
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            break;
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        case "Parallel":
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            argcount = 8;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseParallelGC";
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            break;
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        case "Serial":
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            argcount = 8;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseSerialGC";
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            break;
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        case "CMS":
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            argcount = 9 ;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UseConcMarkSweepGC";
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            procArgs[argcount - 2] = "-XX:-UseCondCardMark";
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            break;
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        case "CMSCondMark":
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            argcount = 9 ;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UseConcMarkSweepGC";
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            procArgs[argcount - 2] = "-XX:+UseCondCardMark";
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            break;
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        default:
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            throw new RuntimeException("unexpected test type " + testType);
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        }
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        // fill in arguments common to all cases
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        // the first round of test enables transform of barriers to
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        // use acquiring loads and releasing stores by setting arg
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        // zero appropriately. this arg is reset in the second run to
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        // disable the transform.
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        procArgs[0] = "-XX:-UseBarriersForVolatile";
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        procArgs[1] = "-XX:-TieredCompilation";
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        procArgs[2] = "-XX:+PrintOptoAssembly";
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        procArgs[3] = "-XX:CompileCommand=compileonly," + fullclassname + "::" + "test*";
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        procArgs[4] = "--add-exports";
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        procArgs[5] = "java.base/jdk.internal.misc=ALL-UNNAMED";
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        procArgs[argcount - 1] = fullclassname;
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        ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(procArgs);
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        OutputAnalyzer output = new OutputAnalyzer(pb.start());
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        output.stderrShouldBeEmptyIgnoreVMWarnings();
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        output.stdoutShouldNotBeEmpty();
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        output.shouldHaveExitValue(0);
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        // check the output for the correct asm sequence as
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        // appropriate to test class, test type and whether transform
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        // was applied
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        checkoutput(output, classname, testType, false);
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        // rerun the test class without the transform applied and
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        // check the alternative generation is as expected
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        procArgs[0] = "-XX:+UseBarriersForVolatile";
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        pb = ProcessTools.createJavaProcessBuilder(procArgs);
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        output = new OutputAnalyzer(pb.start());
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        output.stderrShouldBeEmptyIgnoreVMWarnings();
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        output.stdoutShouldNotBeEmpty();
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        output.shouldHaveExitValue(0);
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        // again check the output for the correct asm sequence
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        checkoutput(output, classname, testType, true);
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   145
    }
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diff changeset
   146
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   147
    // skip through output returning a line containing the desireed
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   148
    // substring or null
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   149
    private String skipTo(Iterator<String> iter, String substring)
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   150
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   151
        while (iter.hasNext()) {
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   152
            String nextLine = iter.next();
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diff changeset
   153
            if (nextLine.contains(substring)) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   154
                return nextLine;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   155
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   156
        }
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   157
        return null;
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diff changeset
   158
    }
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   159
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   160
    // locate the start of compiler output for the desired method and
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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parents:
diff changeset
   161
    // then check that each expected instruction occurs in the output
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   162
    // in the order supplied. throw an excpetion if not found.
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   163
    // n.b. the spawned JVM's output is included in the exception
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   164
    // message to make it easeir to identify what is missing.
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diff changeset
   165
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   166
    private void checkCompile(Iterator<String> iter, String methodname, String[] expected, OutputAnalyzer output)
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   167
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   168
        // trace call to allow eyeball check of what we are checking against
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   169
        System.out.println("checkCompile(" + methodname + ",");
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   170
        String sepr = "  { ";
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   171
        for (String s : expected) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   172
            System.out.print(sepr);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   173
            System.out.print(s);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   174
            sepr = ",\n    ";
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   175
        }
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   176
        System.out.println(" })");
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   177
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   178
        // look for the start of an opto assembly print block
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   179
        String match = skipTo(iter, "{method}");
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   180
        if (match == null) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   181
            throw new RuntimeException("Missing compiler output for " + methodname + "!\n\n" + output.getOutput());
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   182
        }
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   183
        // check the compiled method name is right
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   184
        match = skipTo(iter, "- name:");
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   185
        if (match == null) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   186
            throw new RuntimeException("Missing compiled method name!\n\n" + output.getOutput());
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   187
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   188
        if (!match.contains(methodname)) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   189
            throw new RuntimeException("Wrong method " + match + "!\n  -- expecting " + methodname + "\n\n" + output.getOutput());
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   190
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   191
        // make sure we can match each expected term in order
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   192
        for (String s : expected) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   193
            match = skipTo(iter, s);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   194
            if (match == null) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   195
                throw new RuntimeException("Missing expected output " + s + "!\n\n" + output.getOutput());
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   196
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   197
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   198
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   199
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   200
    // check for expected asm output from a volatile load
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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parents:
diff changeset
   201
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   202
    private void checkload(OutputAnalyzer output, String testType, boolean useBarriersForVolatile) throws Throwable
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   203
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   204
        Iterator<String> iter = output.asLines().listIterator();
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   205
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   206
        // we shoud see this same sequence for normal or unsafe volatile load
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   207
        // for both int and Object fields
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   208
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   209
        String[] matches;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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parents:
diff changeset
   210
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   211
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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diff changeset
   212
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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   213
                "ldarw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
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   214
                "membar_acquire (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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parents:
diff changeset
   215
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   216
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   217
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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parents:
diff changeset
   218
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
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parents:
diff changeset
   219
                "ldrw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   220
                "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   221
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   222
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   223
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   224
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   225
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
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   226
        checkCompile(iter, "testInt", matches, output);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   227
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   228
        checkCompile(iter, "testObj", matches, output) ;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   229
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   230
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   231
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   232
    // check for expected asm output from a volatile store
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   233
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
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diff changeset
   234
    private void checkstore(OutputAnalyzer output, String testType, boolean useBarriersForVolatile) throws Throwable
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   235
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   236
        Iterator<String> iter = output.asLines().listIterator();
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   237
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   238
        String[] matches;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   239
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   240
        // non object stores are straightforward
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   241
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   242
            // this is the sequence of instructions for all cases
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   243
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   244
                "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   245
                "stlrw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   246
                "membar_volatile (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   247
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   248
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   249
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   250
            // this is the alternative sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   251
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   252
                "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   253
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   254
                "strw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   255
                "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   256
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   257
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   258
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   259
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   260
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   261
        checkCompile(iter, "testInt", matches, output);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   262
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   263
        // object stores will be as above except for when the GC
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   264
        // introduces barriers for card marking
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   265
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   266
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   267
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   268
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   269
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   270
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   271
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   272
                    "stlrw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   273
                    "membar_volatile (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   274
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   275
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   276
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   277
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   278
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   279
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   280
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   281
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   282
                    "stlrw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   283
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   284
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   285
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   286
                    "membar_volatile (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   287
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   288
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   289
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   290
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   291
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   292
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   293
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   294
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   295
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   296
                    "stlrw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   297
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   298
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   299
                    "storestore (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   300
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   301
                    "membar_volatile (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   302
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   303
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   304
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   305
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   306
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   307
                // before the card mark strb from the StoreCM and the
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   308
                // storestore barrier from the StoreCM should be
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   309
                // generated as "dmb ishst"
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   310
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   311
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   312
                    "stlrw",
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   313
                    "storestore",
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   314
                    "dmb ishst",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   315
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   316
                    "membar_volatile (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   317
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   318
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   319
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   320
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   321
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   322
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   323
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   324
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   325
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   326
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   327
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   328
                    "strw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   329
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   330
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   331
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   332
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   333
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   334
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   335
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   336
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   337
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   338
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   339
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   340
                    "strw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   341
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   342
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   343
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   344
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   345
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   346
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   347
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   348
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   349
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   350
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   351
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   352
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   353
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   354
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   355
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   356
                    "strw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   357
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   358
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   359
                    "storestore (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   360
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   361
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   362
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   363
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   364
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   365
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   366
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   367
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   368
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   369
                // storestore barrier from the StoreCM should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   370
                // as "dmb ishst"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   371
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   372
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   373
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   374
                    "strw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   375
                    "storestore",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   376
                    "dmb ishst",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   377
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   378
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   379
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   380
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   381
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   382
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   383
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   384
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   385
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   386
        checkCompile(iter, "testObj", matches, output);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   387
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   388
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   389
    // check for expected asm output from a volatile cas
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   390
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   391
    private void checkcas(OutputAnalyzer output, String testType, boolean useBarriersForVolatile) throws Throwable
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   392
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   393
        Iterator<String> iter = output.asLines().listIterator();
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   394
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   395
        String[] matches;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   396
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   397
        // non object stores are straightforward
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   398
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   399
            // this is the sequence of instructions for all cases
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   400
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   401
                "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   402
                "cmpxchgw_acq",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   403
                "membar_acquire (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   404
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   405
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   406
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   407
            // this is the alternative sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   408
            matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   409
                "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   410
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   411
                "cmpxchgw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   412
                "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   413
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   414
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   415
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   416
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   417
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   418
        checkCompile(iter, "testInt", matches, output);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   419
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   420
        // object stores will be as above except for when the GC
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   421
        // introduces barriers for card marking
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   422
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   423
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   424
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   425
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   426
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   427
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   428
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   429
                    "cmpxchgw_acq",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   430
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   431
                    "membar_acquire (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   432
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   433
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   434
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   435
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   436
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   437
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   438
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   439
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   440
                    "cmpxchgw_acq",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   441
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   442
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   443
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   444
                    "membar_acquire (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   445
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   446
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   447
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   448
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   449
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   450
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   451
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   452
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   453
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   454
                    "cmpxchgw_acq",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   455
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   456
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   457
                    "storestore (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   458
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   459
                    "membar_acquire (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   460
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   461
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   462
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   463
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   464
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   465
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   466
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   467
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   468
                    "membar_release (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   469
                    "cmpxchgw_acq",
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   470
                    "storestore",
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   471
                    "dmb ishst",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   472
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   473
                    "membar_acquire (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   474
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   475
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   476
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   477
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   478
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   479
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   480
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   481
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   482
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   483
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   484
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   485
                    "cmpxchgw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   486
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   487
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   488
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   489
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   490
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   491
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   492
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   493
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   494
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   495
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   496
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   497
                    "cmpxchgw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   498
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   499
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   500
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   501
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   502
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   503
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   504
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   505
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   506
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   507
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   508
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   509
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   510
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   511
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   512
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   513
                    "cmpxchgw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   514
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   515
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   516
                    "storestore (elided)",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   517
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   518
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   519
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   520
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   521
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   522
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   523
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   524
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   525
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   526
                // storestore barrier from the StoreCM should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   527
                // as "dmb ishst"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   528
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   529
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   530
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   531
                    "cmpxchgw",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   532
                    "storestore",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   533
                    "dmb ishst",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   534
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   535
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   536
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   537
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   538
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   539
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   540
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   541
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   542
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   543
        checkCompile(iter, "testObj", matches, output);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   544
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   545
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   546
    // perform a check appropriate to the classname
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   547
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   548
    private void checkoutput(OutputAnalyzer output, String classname, String testType, boolean useBarriersForVolatile) throws Throwable
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   549
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   550
        // trace call to allow eyeball check of what is being checked
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   551
        System.out.println("checkoutput(" +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   552
                           classname + ", " +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   553
                           testType + ", " +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   554
                           useBarriersForVolatile + ")\n" +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   555
                           output.getOutput());
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   556
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   557
        switch (classname) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   558
        case "TestVolatileLoad":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   559
            checkload(output, testType, useBarriersForVolatile);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   560
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   561
        case "TestVolatileStore":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   562
            checkstore(output, testType, useBarriersForVolatile);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   563
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   564
        case "TestUnsafeVolatileLoad":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   565
            checkload(output, testType, useBarriersForVolatile);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   566
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   567
        case "TestUnsafeVolatileStore":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   568
            checkstore(output, testType, useBarriersForVolatile);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   569
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   570
        case "TestUnsafeVolatileCAS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   571
            checkcas(output, testType, useBarriersForVolatile);
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   572
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   573
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   574
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   575
}