test/hotspot/jtreg/compiler/c2/aarch64/TestVolatiles.java
author roland
Mon, 05 Nov 2018 12:53:55 +0100
changeset 52409 87bc444ca642
parent 51008 8df91a1b549b
child 52925 9c18c9d839d3
permissions -rw-r--r--
8209835: Aarch64: elide barriers on all volatile operations Reviewed-by: aph, adinn
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/*
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 * Copyright (c) 2018, Red Hat, Inc. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 */
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/*
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 * common code to run and validate tests of code generation for
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 * volatile ops on AArch64
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 *
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 * incoming args are <testclass> <testtype>
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 *
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 * where <testclass> in {TestVolatileLoad,
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 *                       TestVolatileStore,
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 *                       TestUnsafeVolatileLoad,
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 *                       TestUnsafeVolatileStore,
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 *                       TestUnsafeVolatileCAS,
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 *                       TestUnsafeVolatileWeakCAS,
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 *                       TestUnsafeVolatileCAE,
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 *                       TestUnsafeVolatileGAS}
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 * and <testtype> in {G1,
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 *                    CMS,
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 *                    CMSCondMark,
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 *                    Serial,
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 *                    Parallel}
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 */
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package compiler.c2.aarch64;
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import java.util.List;
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import java.util.ListIterator;
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import java.util.Iterator;
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import java.util.regex.Pattern;
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import java.io.*;
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import jdk.test.lib.Asserts;
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import jdk.test.lib.compiler.InMemoryJavaCompiler;
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import jdk.test.lib.process.OutputAnalyzer;
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import jdk.test.lib.process.ProcessTools;
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import sun.hotspot.WhiteBox;
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// runner class that spawns a new JVM to exercises a combination of
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// volatile MemOp and GC. The ops are compiled with the dmb -->
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// ldar/stlr transforms either enabled or disabled. this runner parses
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// the PrintOptoAssembly output checking that the generated code is
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// correct.
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public class TestVolatiles {
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    public void runtest(String classname, String testType) throws Throwable {
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        // n.b. clients omit the package name for the class
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        String fullclassname = "compiler.c2.aarch64." + classname;
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        // build up a command line for the spawned JVM
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        String[] procArgs;
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        int argcount;
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        // add one or two extra arguments according to test type
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        // i.e. GC type plus GC conifg
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        switch(testType) {
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        case "G1":
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            argcount = 9;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseG1GC";
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            break;
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        case "Parallel":
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            argcount = 9;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseParallelGC";
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            break;
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        case "Serial":
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            argcount = 9;
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            procArgs = new String[argcount];
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            procArgs[argcount - 2] = "-XX:+UseSerialGC";
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            break;
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        case "CMS":
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            argcount = 10;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UseConcMarkSweepGC";
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            procArgs[argcount - 2] = "-XX:-UseCondCardMark";
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            break;
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        case "CMSCondMark":
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            argcount = 10;
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            procArgs = new String[argcount];
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            procArgs[argcount - 3] = "-XX:+UseConcMarkSweepGC";
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            procArgs[argcount - 2] = "-XX:+UseCondCardMark";
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            break;
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        default:
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            throw new RuntimeException("unexpected test type " + testType);
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        }
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        // fill in arguments common to all cases
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        // the first round of test enables transform of barriers to
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        // use acquiring loads and releasing stores by setting arg
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        // zero appropriately. this arg is reset in the second run to
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        // disable the transform.
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        procArgs[0] = "-XX:-UseBarriersForVolatile";
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        procArgs[1] = "-XX:+UseCompressedOops";
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        procArgs[2] = "-XX:-TieredCompilation";
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        procArgs[3] = "-XX:+PrintOptoAssembly";
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        procArgs[4] = "-XX:CompileCommand=compileonly," + fullclassname + "::" + "test*";
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        procArgs[5] = "--add-exports";
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        procArgs[6] = "java.base/jdk.internal.misc=ALL-UNNAMED";
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        procArgs[argcount - 1] = fullclassname;
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        runtest(classname, testType, false, true, procArgs);
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        // rerun the test class without the transform applied and
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        // check the alternative generation is as expected
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        procArgs[0] = "-XX:+UseBarriersForVolatile";
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        runtest(classname, testType, true, true, procArgs);
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        if (!classname.equals("TestUnsafeVolatileGAA")) {
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            procArgs[0] = "-XX:-UseBarriersForVolatile";
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            procArgs[1] = "-XX:-UseCompressedOops";
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            runtest(classname, testType, false, false, procArgs);
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            procArgs[0] = "-XX:+UseBarriersForVolatile";
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            runtest(classname, testType, true, false, procArgs);
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        }
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    }
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    public void runtest(String classname, String testType, boolean useBarriersForVolatile, boolean useCompressedOops, String[] procArgs) throws Throwable {
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        ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(procArgs);
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        OutputAnalyzer output = new OutputAnalyzer(pb.start());
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        output.stderrShouldBeEmptyIgnoreVMWarnings();
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        output.stdoutShouldNotBeEmpty();
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        output.shouldHaveExitValue(0);
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        // check the output for the correct asm sequence as
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        // appropriate to test class, test type and whether transform
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        // was applied
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        checkoutput(output, classname, testType, useBarriersForVolatile, useCompressedOops);
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    }
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    // skip through output returning a line containing the desireed
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    // substring or null
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    private String skipTo(Iterator<String> iter, String substring)
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    {
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        while (iter.hasNext()) {
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            String nextLine = iter.next();
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            if (nextLine.matches(".*" + substring + ".*")) {
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                return nextLine;
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            }
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        }
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        return null;
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    }
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    // locate the start of compiler output for the desired method and
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    // then check that each expected instruction occurs in the output
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    // in the order supplied. throw an excpetion if not found.
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    // n.b. the spawned JVM's output is included in the exception
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    // message to make it easeir to identify what is missing.
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    private boolean checkCompile(Iterator<String> iter, String methodname, String[] expected, OutputAnalyzer output, boolean do_throw)
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    {
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        // trace call to allow eyeball check of what we are checking against
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        System.out.println("checkCompile(" + methodname + ",");
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        String sepr = "  { ";
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        for (String s : expected) {
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            System.out.print(sepr);
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            System.out.print(s);
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            sepr = ",\n    ";
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        }
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        System.out.println(" })");
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        // look for the start of an opto assembly print block
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        String match = skipTo(iter, Pattern.quote("{method}"));
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        if (match == null) {
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            if (do_throw) {
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                throw new RuntimeException("Missing compiler output for " + methodname + "!\n\n" + output.getOutput());
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            }
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            return false;
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        }
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        // check the compiled method name is right
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        match = skipTo(iter, Pattern.quote("- name:"));
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        if (match == null) {
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            if (do_throw) {
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                throw new RuntimeException("Missing compiled method name!\n\n" + output.getOutput());
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            }
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            return false;
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        }
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        if (!match.contains(methodname)) {
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            if (do_throw) {
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                throw new RuntimeException("Wrong method " + match + "!\n  -- expecting " + methodname + "\n\n" + output.getOutput());
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            }
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            return false;
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        }
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        // make sure we can match each expected term in order
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        for (String s : expected) {
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            match = skipTo(iter, s);
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            if (match == null) {
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                if (do_throw) {
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                    throw new RuntimeException("Missing expected output " + s + "!\n\n" + output.getOutput());
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                }
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                return false;
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            }
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        }
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        return true;
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    }
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    // check for expected asm output from a volatile load
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    private void checkload(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
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    {
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        Iterator<String> iter = output.asLines().listIterator();
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        // we shoud see this same sequence for normal or unsafe volatile load
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        // for both int and Object fields
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        String[] matches;
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        if (!useBarriersForVolatile) {
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            matches = new String[] {
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                "ldarw",
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                "membar_acquire \\(elided\\)",
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                "ret"
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            };
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        } else {
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            matches = new String[] {
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                "ldrw",
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                "membar_acquire",
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                "dmb ish",
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                "ret"
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            };
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        }
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        checkCompile(iter, "testInt", matches, output, true);
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        if (!useBarriersForVolatile) {
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            matches = new String[] {
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                useCompressedOops ? "ldarw?" : "ldar",
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                "membar_acquire \\(elided\\)",
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                "ret"
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            };
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        } else {
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            matches = new String[] {
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                useCompressedOops ? "ldrw?" : "ldr",
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                "membar_acquire",
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                "dmb ish",
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                "ret"
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            };
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        }
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        checkCompile(iter, "testObj", matches, output, true);
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    }
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    // check for expected asm output from a volatile store
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    private void checkstore(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
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    {
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        Iterator<String> iter = output.asLines().listIterator();
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        String[] matches;
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        // non object stores are straightforward
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        if (!useBarriersForVolatile) {
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            // this is the sequence of instructions for all cases
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            matches = new String[] {
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                "membar_release \\(elided\\)",
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                "stlrw",
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                "membar_volatile \\(elided\\)",
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                "ret"
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            };
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        } else {
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            // this is the alternative sequence of instructions
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            matches = new String[] {
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                "membar_release",
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                "dmb ish",
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                "strw",
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   293
                "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   294
                "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   295
                "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   296
            };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   297
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   298
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
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parents: 51008
diff changeset
   299
        checkCompile(iter, "testInt", matches, output, true);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   300
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   301
        // object stores will be as above except for when the GC
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   302
        // introduces barriers for card marking
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   303
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   304
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   305
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   306
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   307
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   308
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   309
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   310
                    useCompressedOops ? "stlrw?" : "stlr",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   311
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   312
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   313
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   314
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   315
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   316
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   317
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   318
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   319
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   320
                    useCompressedOops ? "stlrw?" : "stlr",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   321
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   322
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   323
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   324
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   325
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   326
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   327
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   328
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   329
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   330
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   331
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   332
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   333
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   334
                    useCompressedOops ? "stlrw?" : "stlr",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   335
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   336
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   337
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   338
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   339
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   340
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   341
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   342
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   343
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   344
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   345
                // before the card mark strb from the StoreCM and the
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   346
                // storestore barrier from the StoreCM should be
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   347
                // generated as "dmb ishst"
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   348
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   349
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   350
                    useCompressedOops ? "stlrw?" : "stlr",
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   351
                    "storestore",
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   352
                    "dmb ishst",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   353
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   354
                    "membar_volatile \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   355
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   356
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   357
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   358
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   359
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   360
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   361
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   362
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   363
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   364
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   365
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   366
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   367
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   368
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   369
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   370
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   371
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   372
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   373
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   374
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   375
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   376
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   377
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   378
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   379
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   380
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   381
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   382
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   383
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   384
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   385
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   386
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   387
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   388
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   389
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   390
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   391
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   392
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   393
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   394
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   395
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   396
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   397
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   398
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   399
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   400
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   401
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   402
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   403
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   404
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   405
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   406
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   407
                // storestore barrier from the StoreCM should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   408
                // as "dmb ishst"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   409
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   410
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   411
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   412
                    useCompressedOops ? "strw?" : "str",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   413
                    "storestore",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   414
                    "dmb ishst",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   415
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   416
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   417
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   418
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   419
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   420
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   421
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   422
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   423
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   424
        checkCompile(iter, "testObj", matches, output, true);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   425
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   426
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   427
    // check for expected asm output from a volatile cas
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   428
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   429
    private void checkcas(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   430
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   431
        Iterator<String> iter = output.asLines().listIterator();
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   432
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   433
        String[] matches;
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   434
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   435
            { "testInt", "cmpxchgw" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   436
            { "testLong", "cmpxchg" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   437
            { "testByte", "cmpxchgb" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   438
            { "testShort", "cmpxchgs" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   439
        };
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   440
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   441
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   442
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   443
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   444
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   445
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   446
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   447
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   448
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   449
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   450
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   451
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   452
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   453
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   454
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   455
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   456
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   457
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   458
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   459
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   460
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   461
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   462
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   463
            checkCompile(iter, test[0], matches, output, true);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   464
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   465
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   466
        // object stores will be as above except for when the GC
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   467
        // introduces barriers for card marking
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   468
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   469
        if (!useBarriersForVolatile) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   470
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   471
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   472
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   473
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   474
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   475
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   476
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   477
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   478
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   479
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   480
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   481
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   482
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   483
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   484
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   485
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   486
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   487
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   488
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   489
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   490
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   491
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   492
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   493
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   494
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   495
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   496
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   497
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   498
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   499
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   500
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   501
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   502
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   503
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   504
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   505
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   506
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   507
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   508
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   509
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   510
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   511
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   512
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   513
                matches = new String[] {
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   514
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   515
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   516
                    "storestore",
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   517
                    "dmb ishst",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   518
                    "strb",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   519
                    "membar_acquire \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   520
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   521
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   522
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   523
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   524
        } else {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   525
            switch (testType) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   526
            default:
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   527
                // this is the basic sequence of instructions
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   528
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   529
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   530
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   531
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   532
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   533
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   534
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   535
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   536
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   537
            case "G1":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   538
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   539
                // before the card mark strb
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   540
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   541
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   542
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   543
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   544
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   545
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   546
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   547
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   548
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   549
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   550
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   551
                break;
51008
8df91a1b549b 8206163: AArch64: incorrect code generation for StoreCM
adinn
parents: 50874
diff changeset
   552
            case "CMSCondMark":
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   553
                // a card mark volatile barrier should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   554
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   555
                // storestore barrier from the StoreCM should be elided
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   556
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   557
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   558
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   559
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   560
                    "membar_volatile",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   561
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   562
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   563
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   564
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   565
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   566
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   567
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   568
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   569
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   570
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   571
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   572
                // storestore barrier from the StoreCM should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   573
                // as "dmb ishst"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   574
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   575
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   576
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   577
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   578
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   579
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   580
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   581
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   582
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   583
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   584
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   585
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   586
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   587
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   588
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   589
        checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   590
    }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   591
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   592
    private void checkcae(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   593
    {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   594
        ListIterator<String> iter = output.asLines().listIterator();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   595
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   596
        String[] matches;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   597
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   598
            { "testInt", "cmpxchgw" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   599
            { "testLong", "cmpxchg" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   600
            { "testByte", "cmpxchgb" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   601
            { "testShort", "cmpxchgs" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   602
        };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   603
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   604
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   605
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   606
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   607
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   608
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   609
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   610
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   611
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   612
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   613
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   614
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   615
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   616
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   617
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   618
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   619
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   620
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   621
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   622
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   623
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   624
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   625
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   626
            checkCompile(iter, test[0], matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   627
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   628
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   629
        // object stores will be as above except for when the GC
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   630
        // introduces barriers for card marking
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   631
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   632
        if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   633
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   634
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   635
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   636
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   637
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   638
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   639
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   640
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   641
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   642
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   643
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   644
                // card marking store may be scheduled before or after
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   645
                // the cmpxchg so try both sequences.
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   646
                int idx = iter.nextIndex();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   647
                if (!checkCompile(iter, "testObj", matches, output, false)) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   648
                    iter = output.asLines().listIterator(idx);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   649
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   650
                    matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   651
                        "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   652
                        useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   653
                        "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   654
                        "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   655
                        "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   656
                    };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   657
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   658
                    checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   659
                }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   660
                return;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   661
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   662
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   663
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   664
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   665
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   666
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   667
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   668
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   669
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   670
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   671
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   672
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   673
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   674
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   675
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   676
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   677
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   678
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   679
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   680
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   681
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   682
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   683
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   684
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   685
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   686
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   687
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   688
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   689
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   690
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   691
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   692
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   693
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   694
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   695
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   696
                    useCompressedOops ? "cmpxchgw?_acq" : "cmpxchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   697
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   698
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   699
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   700
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   701
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   702
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   703
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   704
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   705
        } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   706
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   707
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   708
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   709
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   710
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   711
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   712
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   713
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   714
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   715
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   716
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   717
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   718
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   719
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   720
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   721
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   722
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   723
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   724
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   725
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   726
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   727
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   728
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   729
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   730
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   731
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   732
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   733
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   734
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   735
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   736
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   737
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   738
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   739
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   740
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   741
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   742
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   743
                    "storestore \\(elided\\)",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   744
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   745
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   746
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   747
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   748
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   749
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   750
            case "CMS":
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   751
                // a volatile card mark membar should not be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   752
                // before the card mark strb from the StoreCM and the
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   753
                // storestore barrier from the StoreCM should be generated
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   754
                // as "dmb ishst"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   755
                matches = new String[] {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   756
                    "membar_release",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   757
                    "dmb ish",
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   758
                    useCompressedOops ? "cmpxchgw? " : "cmpxchg ",
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   759
                    "storestore",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   760
                    "dmb ishst",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   761
                    "strb",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   762
                    "membar_acquire",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   763
                    "dmb ish",
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   764
                    "ret"
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   765
                };
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   766
                break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   767
            }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   768
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   769
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   770
        checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   771
    }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   772
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   773
    private void checkgas(OutputAnalyzer output, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   774
    {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   775
        Iterator<String> iter = output.asLines().listIterator();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   776
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   777
        String[] matches;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   778
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   779
            { "testInt", "atomic_xchgw" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   780
            { "testLong", "atomic_xchg" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   781
        };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   782
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   783
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   784
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   785
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   786
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   787
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   788
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   789
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   790
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   791
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   792
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   793
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   794
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   795
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   796
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   797
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   798
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   799
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   800
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   801
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   802
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   803
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   804
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   805
            checkCompile(iter, test[0], matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   806
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   807
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   808
        // object stores will be as above except for when the GC
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   809
        // introduces barriers for card marking
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   810
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   811
        if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   812
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   813
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   814
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   815
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   816
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   817
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   818
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   819
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   820
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   821
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   822
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   823
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   824
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   825
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   826
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   827
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   828
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   829
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   830
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   831
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   832
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   833
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   834
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   835
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   836
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   837
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   838
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   839
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   840
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   841
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   842
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   843
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   844
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   845
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   846
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   847
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   848
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   849
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   850
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   851
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   852
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   853
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   854
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   855
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   856
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   857
                    useCompressedOops ? "atomic_xchgw?_acq" : "atomic_xchg_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   858
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   859
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   860
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   861
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   862
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   863
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   864
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   865
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   866
        } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   867
            switch (testType) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   868
            default:
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   869
                // this is the basic sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   870
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   871
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   872
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   873
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   874
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   875
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   876
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   877
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   878
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   879
            case "G1":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   880
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   881
                // before the card mark strb
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   882
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   883
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   884
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   885
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   886
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   887
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   888
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   889
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   890
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   891
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   892
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   893
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   894
            case "CMSCondMark":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   895
                // a card mark volatile barrier should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   896
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   897
                // storestore barrier from the StoreCM should be elided
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   898
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   899
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   900
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   901
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   902
                    "membar_volatile",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   903
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   904
                    "storestore \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   905
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   906
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   907
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   908
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   909
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   910
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   911
            case "CMS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   912
                // a volatile card mark membar should not be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   913
                // before the card mark strb from the StoreCM and the
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   914
                // storestore barrier from the StoreCM should be generated
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   915
                // as "dmb ishst"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   916
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   917
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   918
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   919
                    useCompressedOops ? "atomic_xchgw? " : "atomic_xchg ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   920
                    "storestore",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   921
                    "dmb ishst",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   922
                    "strb",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   923
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   924
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   925
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   926
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   927
                break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   928
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   929
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   930
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   931
        checkCompile(iter, "testObj", matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   932
    }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   933
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   934
    private void checkgaa(OutputAnalyzer output, String testType, boolean useBarriersForVolatile) throws Throwable
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   935
    {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   936
        Iterator<String> iter = output.asLines().listIterator();
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   937
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   938
        String[] matches;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   939
        String[][] tests = {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   940
            { "testInt", "get_and_addI" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   941
            { "testLong", "get_and_addL" },
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   942
        };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   943
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   944
        for (String[] test : tests) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   945
            // non object stores are straightforward
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   946
            if (!useBarriersForVolatile) {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   947
                // this is the sequence of instructions for all cases
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   948
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   949
                    "membar_release \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   950
                    test[1] + "_acq",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   951
                    "membar_acquire \\(elided\\)",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   952
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   953
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   954
            } else {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   955
                // this is the alternative sequence of instructions
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   956
                matches = new String[] {
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   957
                    "membar_release",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   958
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   959
                    test[1] + " ",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   960
                    "membar_acquire",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   961
                    "dmb ish",
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   962
                    "ret"
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   963
                };
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   964
            }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   965
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   966
            checkCompile(iter, test[0], matches, output, true);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   967
        }
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   968
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   969
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   970
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   971
    // perform a check appropriate to the classname
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   972
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   973
    private void checkoutput(OutputAnalyzer output, String classname, String testType, boolean useBarriersForVolatile, boolean useCompressedOops) throws Throwable
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   974
    {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   975
        // trace call to allow eyeball check of what is being checked
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   976
        System.out.println("checkoutput(" +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   977
                           classname + ", " +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   978
                           testType + ", " +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   979
                           useBarriersForVolatile + ")\n" +
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   980
                           output.getOutput());
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   981
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   982
        switch (classname) {
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   983
        case "TestVolatileLoad":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   984
            checkload(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   985
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   986
        case "TestVolatileStore":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   987
            checkstore(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   988
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   989
        case "TestUnsafeVolatileLoad":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   990
            checkload(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   991
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   992
        case "TestUnsafeVolatileStore":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   993
            checkstore(output, testType, useBarriersForVolatile, useCompressedOops);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   994
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
   995
        case "TestUnsafeVolatileCAS":
52409
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   996
        case "TestUnsafeVolatileWeakCAS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   997
            checkcas(output, testType, useBarriersForVolatile, useCompressedOops);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   998
            break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
   999
        case "TestUnsafeVolatileCAE":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1000
            checkcae(output, testType, useBarriersForVolatile, useCompressedOops);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1001
            break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1002
        case "TestUnsafeVolatileGAS":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1003
            checkgas(output, testType, useBarriersForVolatile, useCompressedOops);
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1004
            break;
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1005
        case "TestUnsafeVolatileGAA":
87bc444ca642 8209835: Aarch64: elide barriers on all volatile operations
roland
parents: 51008
diff changeset
  1006
            checkgaa(output, testType, useBarriersForVolatile);
50874
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1007
            break;
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1008
        }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1009
    }
551c340ca01a 8205694: AArch64: Add test to validate volatile load, store and CAS code generation
adinn
parents:
diff changeset
  1010
}