/*

 * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2016, 2017 SAP SE. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

// Major contributions by AHa, AS, JL, ML.

#include "precompiled.hpp"

#include "asm/macroAssembler.inline.hpp"

#include "interp_masm_s390.hpp"

#include "interpreter/interpreter.hpp"

#include "interpreter/interpreterRuntime.hpp"

#include "oops/arrayOop.hpp"

#include "oops/markOop.hpp"

#include "prims/jvmtiExport.hpp"

#include "prims/jvmtiThreadState.hpp"

#include "runtime/basicLock.hpp"

#include "runtime/biasedLocking.hpp"

#include "runtime/sharedRuntime.hpp"

#include "runtime/thread.inline.hpp"

// Implementation of InterpreterMacroAssembler.

// This file specializes the assember with interpreter-specific macros.

#ifdef PRODUCT

#define BLOCK_COMMENT(str)

#define BIND(label)        bind(label);

#else

#define BLOCK_COMMENT(str) block_comment(str)

#define BIND(label)        bind(label); BLOCK_COMMENT(#label ":")

#endif

void InterpreterMacroAssembler::jump_to_entry(address entry, Register Rscratch) {

  assert(entry != NULL, "Entry must have been generated by now");

  assert(Rscratch != Z_R0, "Can't use R0 for addressing");

  branch_optimized(Assembler::bcondAlways, entry);

}

void InterpreterMacroAssembler::empty_expression_stack(void) {

  get_monitors(Z_R1_scratch);

  add2reg(Z_esp, -Interpreter::stackElementSize, Z_R1_scratch);

}

// Dispatch code executed in the prolog of a bytecode which does not do it's

// own dispatch.

void InterpreterMacroAssembler::dispatch_prolog(TosState state, int bcp_incr) {

  // On z/Architecture we are short on registers, therefore we do not preload the

  // dispatch address of the next bytecode.

}

// Dispatch code executed in the epilog of a bytecode which does not do it's

// own dispatch.

void InterpreterMacroAssembler::dispatch_epilog(TosState state, int step) {

  dispatch_next(state, step);

}

  z_llgc(Z_bytecode, bcp_incr, Z_R0, Z_bcp);  // Load next bytecode.

  add2reg(Z_bcp, bcp_incr);                   // Advance bcp. Add2reg produces optimal code.

}

// Common code to dispatch and dispatch_only.

// Dispatch value in Lbyte_code and increment Lbcp.

  verify_FPU(1, state);

#ifdef ASSERT

  address reentry = NULL;

  { Label OK;

    // Check if the frame pointer in Z_fp is correct.

    z_cg(Z_fp, 0, Z_SP);

    z_bre(OK);

    reentry = stop_chain_static(reentry, "invalid frame pointer Z_fp: " FILE_AND_LINE);

    bind(OK);

  }

  { Label OK;

    // check if the locals pointer in Z_locals is correct

    z_cg(Z_locals, _z_ijava_state_neg(locals), Z_fp);

    z_bre(OK);

    reentry = stop_chain_static(reentry, "invalid locals pointer Z_locals: " FILE_AND_LINE);

    bind(OK);

  }

#endif

  // TODO: Maybe implement +VerifyActivationFrameSize here.

  // verify_thread(); // Too slow. We will just verify on method entry & exit.

  verify_oop(Z_tos, state);

  // Dispatch table to use.

  // 0 <= Z_bytecode < 256 => Use a 32 bit shift, because it is shorter than sllg.

  // Z_bytecode must have been loaded zero-extended for this approach to be correct.

  z_sll(Z_bytecode, LogBytesPerWord, Z_R0);   // Multiply by wordSize.

  z_lg(Z_tmp_1, 0, Z_bytecode, Z_tmp_1);      // Get entry addr.

  z_br(Z_tmp_1);

}

}

void InterpreterMacroAssembler::dispatch_only_normal(TosState state) {

  dispatch_base(state, Interpreter::normal_table(state));

}

void InterpreterMacroAssembler::dispatch_via(TosState state, address *table) {

  // Load current bytecode.

  z_llgc(Z_bytecode, Address(Z_bcp, (intptr_t)0));

  dispatch_base(state, table);

}

// The following call_VM*_base() methods overload and mask the respective

// declarations/definitions in class MacroAssembler. They are meant as a "detour"

// to perform additional, template interpreter specific tasks before actually

// calling their MacroAssembler counterparts.

void InterpreterMacroAssembler::call_VM_leaf_base(address entry_point) {

  bool allow_relocation = true; // Fenerally valid variant. Assume code is relocated.

  // interpreter specific

  // Note: No need to save/restore bcp (Z_R13) pointer since these are callee

  // saved registers and no blocking/ GC can happen in leaf calls.

  // super call

  MacroAssembler::call_VM_leaf_base(entry_point, allow_relocation);

}

void InterpreterMacroAssembler::call_VM_leaf_base(address entry_point, bool allow_relocation) {

  // interpreter specific

  // Note: No need to save/restore bcp (Z_R13) pointer since these are callee

  // saved registers and no blocking/ GC can happen in leaf calls.

  // super call

  MacroAssembler::call_VM_leaf_base(entry_point, allow_relocation);

}

void InterpreterMacroAssembler::call_VM_base(Register oop_result, Register last_java_sp,

                                             address entry_point, bool check_exceptions) {

  bool allow_relocation = true; // Fenerally valid variant. Assume code is relocated.

  // interpreter specific

  save_bcp();

  save_esp();

  // super call

  MacroAssembler::call_VM_base(oop_result, last_java_sp,

                               entry_point, allow_relocation, check_exceptions);

  restore_bcp();

}

void InterpreterMacroAssembler::call_VM_base(Register oop_result, Register last_java_sp,

                                             address entry_point, bool allow_relocation,

                                             bool check_exceptions) {

  // interpreter specific

  save_bcp();

  save_esp();

  // super call

  MacroAssembler::call_VM_base(oop_result, last_java_sp,

                               entry_point, allow_relocation, check_exceptions);

  restore_bcp();

}

void InterpreterMacroAssembler::check_and_handle_popframe(Register scratch_reg) {

  if (JvmtiExport::can_pop_frame()) {

    BLOCK_COMMENT("check_and_handle_popframe {");

    Label L;

    // Initiate popframe handling only if it is not already being

    // processed. If the flag has the popframe_processing bit set, it

    // means that this code is called *during* popframe handling - we

    // don't want to reenter.

    // TODO: Check if all four state combinations could be visible.

    // If (processing and !pending) is an invisible/impossible state,

    // there is optimization potential by testing both bits at once.

    // Then, All_Zeroes and All_Ones means skip, Mixed means doit.

    testbit(Address(Z_thread, JavaThread::popframe_condition_offset()),

            exact_log2(JavaThread::popframe_pending_bit));

    z_bfalse(L);

    testbit(Address(Z_thread, JavaThread::popframe_condition_offset()),

            exact_log2(JavaThread::popframe_processing_bit));

    z_btrue(L);

    // Call Interpreter::remove_activation_preserving_args_entry() to get the

    // address of the same-named entrypoint in the generated interpreter code.

    call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry));

    // The above call should (as its only effect) return the contents of the field

    // _remove_activation_preserving_args_entry in Z_RET.

    // We just jump there to have the work done.

    z_br(Z_RET);

    // There is no way for control to fall thru here.

    bind(L);

    BLOCK_COMMENT("} check_and_handle_popframe");

  }

}

void InterpreterMacroAssembler::load_earlyret_value(TosState state) {

  Register RjvmtiState = Z_R1_scratch;

  int      tos_off     = in_bytes(JvmtiThreadState::earlyret_tos_offset());

  int      oop_off     = in_bytes(JvmtiThreadState::earlyret_oop_offset());

  int      val_off     = in_bytes(JvmtiThreadState::earlyret_value_offset());

  int      state_off   = in_bytes(JavaThread::jvmti_thread_state_offset());

  z_lg(RjvmtiState, state_off, Z_thread);

  switch (state) {

    case atos: z_lg(Z_tos, oop_off, RjvmtiState);

      store_const(Address(RjvmtiState, oop_off), 0L, 8, 8, Z_R0_scratch);

                                                    break;

    case ltos: z_lg(Z_tos, val_off, RjvmtiState);   break;

    case btos: // fall through

    case ztos: // fall through

    case ctos: // fall through

    case stos: // fall through

    case itos: z_llgf(Z_tos, val_off, RjvmtiState); break;

    case ftos: z_le(Z_ftos, val_off, RjvmtiState);  break;

    case dtos: z_ld(Z_ftos, val_off, RjvmtiState);  break;

    case vtos:   /* nothing to do */                break;

    default  : ShouldNotReachHere();

  }

  // Clean up tos value in the jvmti thread state.

  store_const(Address(RjvmtiState, val_off),   0L, 8, 8, Z_R0_scratch);

  // Set tos state field to illegal value.

  store_const(Address(RjvmtiState, tos_off), ilgl, 4, 1, Z_R0_scratch);

}

void InterpreterMacroAssembler::check_and_handle_earlyret(Register scratch_reg) {

  if (JvmtiExport::can_force_early_return()) {

    BLOCK_COMMENT("check_and_handle_earlyret {");

    Label L;

    // arg regs are save, because we are just behind the call in call_VM_base

    Register jvmti_thread_state = Z_ARG2;

    Register tmp                = Z_ARG3;

    load_and_test_long(jvmti_thread_state, Address(Z_thread, JavaThread::jvmti_thread_state_offset()));

    z_bre(L); // if (thread->jvmti_thread_state() == NULL) exit;

    // Initiate earlyret handling only if it is not already being processed.

    // If the flag has the earlyret_processing bit set, it means that this code

    // is called *during* earlyret handling - we don't want to reenter.

    assert((JvmtiThreadState::earlyret_pending != 0) && (JvmtiThreadState::earlyret_inactive == 0),

          "must fix this check, when changing the values of the earlyret enum");

    assert(JvmtiThreadState::earlyret_pending == 1, "must fix this check, when changing the values of the earlyret enum");

    load_and_test_int(tmp, Address(jvmti_thread_state, JvmtiThreadState::earlyret_state_offset()));

    z_brz(L); // if (thread->jvmti_thread_state()->_earlyret_state != JvmtiThreadState::earlyret_pending) exit;

    // Call Interpreter::remove_activation_early_entry() to get the address of the

    // same-named entrypoint in the generated interpreter code.

    assert(sizeof(TosState) == 4, "unexpected size");

    z_l(Z_ARG1, Address(jvmti_thread_state, JvmtiThreadState::earlyret_tos_offset()));

    call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_early_entry), Z_ARG1);

    // The above call should (as its only effect) return the contents of the field

    // _remove_activation_preserving_args_entry in Z_RET.

    // We just jump there to have the work done.

    z_br(Z_RET);

    // There is no way for control to fall thru here.

    bind(L);

    BLOCK_COMMENT("} check_and_handle_earlyret");

  }

}

void InterpreterMacroAssembler::super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {

  lgr_if_needed(Z_ARG1, arg_1);

  assert(arg_2 != Z_ARG1, "smashed argument");

  lgr_if_needed(Z_ARG2, arg_2);

  MacroAssembler::call_VM_leaf_base(entry_point, true);

}

void InterpreterMacroAssembler::get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size) {

  Address param(Z_bcp, bcp_offset);

  BLOCK_COMMENT("get_cache_index_at_bcp {");

  assert(bcp_offset > 0, "bcp is still pointing to start of bytecode");

  if (index_size == sizeof(u2)) {

    load_sized_value(index, param, 2, false /*signed*/);

  } else if (index_size == sizeof(u4)) {

    load_sized_value(index, param, 4, false);

    // Check if the secondary index definition is still ~x, otherwise

    // we have to change the following assembler code to calculate the

    // plain index.

    assert(ConstantPool::decode_invokedynamic_index(~123) == 123, "else change next line");

    not_(index);  // Convert to plain index.

  } else if (index_size == sizeof(u1)) {

    z_llgc(index, param);

  } else {

    ShouldNotReachHere();

  }

  BLOCK_COMMENT("}");

}

void InterpreterMacroAssembler::get_cache_and_index_at_bcp(Register cache, Register cpe_offset,

                                                           int bcp_offset, size_t index_size) {

  BLOCK_COMMENT("get_cache_and_index_at_bcp {");

  assert_different_registers(cache, cpe_offset);

  get_cache_index_at_bcp(cpe_offset, bcp_offset, index_size);

  z_lg(cache, Address(Z_fp, _z_ijava_state_neg(cpoolCache)));

  // Convert from field index to ConstantPoolCache offset in bytes.

  z_sllg(cpe_offset, cpe_offset, exact_log2(in_words(ConstantPoolCacheEntry::size()) * BytesPerWord));

  BLOCK_COMMENT("}");

}

// Kills Z_R0_scratch.

void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register cache,

                                                                        Register cpe_offset,

                                                                        Register bytecode,

                                                                        int byte_no,

                                                                        int bcp_offset,

                                                                        size_t index_size) {

  BLOCK_COMMENT("get_cache_and_index_and_bytecode_at_bcp {");

  get_cache_and_index_at_bcp(cache, cpe_offset, bcp_offset, index_size);

  // We want to load (from CP cache) the bytecode that corresponds to the passed-in byte_no.

  // It is located at (cache + cpe_offset + base_offset + indices_offset + (8-1) (last byte in DW) - (byte_no+1).

  // Instead of loading, shifting and masking a DW, we just load that one byte of interest with z_llgc (unsigned).

  const int base_ix_off = in_bytes(ConstantPoolCache::base_offset() + ConstantPoolCacheEntry::indices_offset());

  const int off_in_DW   = (8-1) - (1+byte_no);

  assert(ConstantPoolCacheEntry::bytecode_1_mask == ConstantPoolCacheEntry::bytecode_2_mask, "common mask");

  assert(ConstantPoolCacheEntry::bytecode_1_mask == 0xff, "");

  load_sized_value(bytecode, Address(cache, cpe_offset, base_ix_off+off_in_DW), 1, false /*signed*/);

  BLOCK_COMMENT("}");

}

// Load object from cpool->resolved_references(index).

void InterpreterMacroAssembler::load_resolved_reference_at_index(Register result, Register index) {

  assert_different_registers(result, index);

  get_constant_pool(result);

  // Convert

  //  - from field index to resolved_references() index and

  //  - from word index to byte offset.

  // Since this is a java object, it is potentially compressed.

  Register tmp = index;  // reuse

  z_sllg(index, index, LogBytesPerHeapOop); // Offset into resolved references array.

  // Load pointer for resolved_references[] objArray.

  z_lg(result, ConstantPool::cache_offset_in_bytes(), result);

  z_lg(result, ConstantPoolCache::resolved_references_offset_in_bytes(), result);

  resolve_oop_handle(result); // Load resolved references array itself.

#ifdef ASSERT

  NearLabel index_ok;

  z_lgf(Z_R0, Address(result, arrayOopDesc::length_offset_in_bytes()));

  z_sllg(Z_R0, Z_R0, LogBytesPerHeapOop);

  compare64_and_branch(tmp, Z_R0, Assembler::bcondLow, index_ok);

  stop("resolved reference index out of bounds", 0x09256);

  bind(index_ok);

#endif

  z_agr(result, index);    // Address of indexed array element.

  load_heap_oop(result, arrayOopDesc::base_offset_in_bytes(T_OBJECT), result);

}

// load cpool->resolved_klass_at(index)

void InterpreterMacroAssembler::load_resolved_klass_at_offset(Register cpool, Register offset, Register iklass) {

  // int value = *(Rcpool->int_at_addr(which));

  // int resolved_klass_index = extract_low_short_from_int(value);

  z_llgh(offset, Address(cpool, offset, sizeof(ConstantPool) + 2)); // offset = resolved_klass_index (s390 is big-endian)

  z_sllg(offset, offset, LogBytesPerWord);                          // Convert 'index' to 'offset'

  z_lg(iklass, Address(cpool, ConstantPool::resolved_klasses_offset_in_bytes())); // iklass = cpool->_resolved_klasses

  z_lg(iklass, Address(iklass, offset, Array<Klass*>::base_offset_in_bytes()));

}

void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache,

                                                               Register tmp,

                                                               int bcp_offset,

                                                               size_t index_size) {

  BLOCK_COMMENT("get_cache_entry_pointer_at_bcp {");

    get_cache_and_index_at_bcp(cache, tmp, bcp_offset, index_size);

    add2reg_with_index(cache, in_bytes(ConstantPoolCache::base_offset()), tmp, cache);

  BLOCK_COMMENT("}");

}

// Generate a subtype check: branch to ok_is_subtype if sub_klass is

// a subtype of super_klass. Blows registers Rsuper_klass, Rsub_klass, tmp1, tmp2.

void InterpreterMacroAssembler::gen_subtype_check(Register Rsub_klass,

                                                  Register Rsuper_klass,

                                                  Register Rtmp1,

                                                  Register Rtmp2,

                                                  Label &ok_is_subtype) {

  // Profile the not-null value's klass.

  profile_typecheck(Rtmp1, Rsub_klass, Rtmp2);

  // Do the check.

  check_klass_subtype(Rsub_klass, Rsuper_klass, Rtmp1, Rtmp2, ok_is_subtype);

  // Profile the failure of the check.

  profile_typecheck_failed(Rtmp1, Rtmp2);

}

// Pop topmost element from stack. It just disappears.

// Useful if consumed previously by access via stackTop().

void InterpreterMacroAssembler::popx(int len) {

  add2reg(Z_esp, len*Interpreter::stackElementSize);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

}

// Get Address object of stack top. No checks. No pop.

// Purpose: - Provide address of stack operand to exploit reg-mem operations.

//          - Avoid RISC-like mem2reg - reg-reg-op sequence.

Address InterpreterMacroAssembler::stackTop() {

  return Address(Z_esp, Interpreter::expr_offset_in_bytes(0));

}

void InterpreterMacroAssembler::pop_i(Register r) {

  z_l(r, Interpreter::expr_offset_in_bytes(0), Z_esp);

  add2reg(Z_esp, Interpreter::stackElementSize);

  assert_different_registers(r, Z_R1_scratch);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

}

void InterpreterMacroAssembler::pop_ptr(Register r) {

  z_lg(r, Interpreter::expr_offset_in_bytes(0), Z_esp);

  add2reg(Z_esp, Interpreter::stackElementSize);

  assert_different_registers(r, Z_R1_scratch);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

}

void InterpreterMacroAssembler::pop_l(Register r) {

  z_lg(r, Interpreter::expr_offset_in_bytes(0), Z_esp);

  add2reg(Z_esp, 2*Interpreter::stackElementSize);

  assert_different_registers(r, Z_R1_scratch);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

}

void InterpreterMacroAssembler::pop_f(FloatRegister f) {

  mem2freg_opt(f, Address(Z_esp, Interpreter::expr_offset_in_bytes(0)), false);

  add2reg(Z_esp, Interpreter::stackElementSize);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

}

void InterpreterMacroAssembler::pop_d(FloatRegister f) {

  mem2freg_opt(f, Address(Z_esp, Interpreter::expr_offset_in_bytes(0)), true);

  add2reg(Z_esp, 2*Interpreter::stackElementSize);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

}

void InterpreterMacroAssembler::push_i(Register r) {

  assert_different_registers(r, Z_R1_scratch);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

  z_st(r, Address(Z_esp));

  add2reg(Z_esp, -Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push_ptr(Register r) {

  z_stg(r, Address(Z_esp));

  add2reg(Z_esp, -Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push_l(Register r) {

  assert_different_registers(r, Z_R1_scratch);

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

  int offset = -Interpreter::stackElementSize;

  z_stg(r, Address(Z_esp, offset));

  clear_mem(Address(Z_esp), Interpreter::stackElementSize);

  add2reg(Z_esp, 2 * offset);

}

void InterpreterMacroAssembler::push_f(FloatRegister f) {

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

  freg2mem_opt(f, Address(Z_esp), false);

  add2reg(Z_esp, -Interpreter::stackElementSize);

}

void InterpreterMacroAssembler::push_d(FloatRegister d) {

  debug_only(verify_esp(Z_esp, Z_R1_scratch));

  int offset = -Interpreter::stackElementSize;

  freg2mem_opt(d, Address(Z_esp, offset));

  add2reg(Z_esp, 2 * offset);

}

void InterpreterMacroAssembler::push(TosState state) {

  verify_oop(Z_tos, state);

  switch (state) {

    case atos: push_ptr();           break;

    case btos: push_i();             break;

    case ztos:

    case ctos:

    case stos: push_i();             break;

    case itos: push_i();             break;

    case ltos: push_l();             break;

    case ftos: push_f();             break;

    case dtos: push_d();             break;

    case vtos: /* nothing to do */   break;