author | stefank |
Mon, 25 Nov 2019 12:32:40 +0100 | |
changeset 59251 | 4cbfa5077d68 |
parent 59249 | 29b0d0b61615 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include "precompiled.hpp" |
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#include "asm/macroAssembler.hpp" |
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#include "asm/macroAssembler.inline.hpp" |
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#include "ci/ciUtilities.hpp" |
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#include "gc/shared/barrierSet.hpp" |
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#include "gc/shared/barrierSetAssembler.hpp" |
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#include "gc/shared/barrierSetNMethod.hpp" |
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#include "interpreter/interpreter.hpp" |
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#include "memory/universe.hpp" |
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#include "nativeInst_x86.hpp" |
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#include "oops/instanceOop.hpp" |
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#include "oops/method.hpp" |
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#include "oops/objArrayKlass.hpp" |
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#include "oops/oop.inline.hpp" |
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#include "prims/methodHandles.hpp" |
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#include "runtime/frame.inline.hpp" |
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#include "runtime/handles.inline.hpp" |
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#include "runtime/sharedRuntime.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
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#include "runtime/stubRoutines.hpp" |
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#include "runtime/thread.inline.hpp" |
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#ifdef COMPILER2 |
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#include "opto/runtime.hpp" |
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#endif |
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#if INCLUDE_ZGC |
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#include "gc/z/zThreadLocalData.hpp" |
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#endif |
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// Declaration and definition of StubGenerator (no .hpp file). |
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// For a more detailed description of the stub routine structure |
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// see the comment in stubRoutines.hpp |
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#define __ _masm-> |
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#define TIMES_OOP (UseCompressedOops ? Address::times_4 : Address::times_8) |
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#define a__ ((Assembler*)_masm)-> |
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#ifdef PRODUCT |
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#define BLOCK_COMMENT(str) /* nothing */ |
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#else |
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#define BLOCK_COMMENT(str) __ block_comment(str) |
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#endif |
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
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const int MXCSR_MASK = 0xFFC0; // Mask out any pending exceptions |
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// Stub Code definitions |
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class StubGenerator: public StubCodeGenerator { |
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private: |
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#ifdef PRODUCT |
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#define inc_counter_np(counter) ((void)0) |
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#else |
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void inc_counter_np_(int& counter) { |
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// This can destroy rscratch1 if counter is far from the code cache |
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__ incrementl(ExternalAddress((address)&counter)); |
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} |
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#define inc_counter_np(counter) \ |
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BLOCK_COMMENT("inc_counter " #counter); \ |
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inc_counter_np_(counter); |
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#endif |
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// Call stubs are used to call Java from C |
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// |
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// Linux Arguments: |
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// c_rarg0: call wrapper address address |
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// c_rarg1: result address |
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// c_rarg2: result type BasicType |
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// c_rarg3: method Method* |
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// c_rarg4: (interpreter) entry point address |
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// c_rarg5: parameters intptr_t* |
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// 16(rbp): parameter size (in words) int |
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// 24(rbp): thread Thread* |
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// |
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// [ return_from_Java ] <--- rsp |
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// [ argument word n ] |
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// ... |
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// -12 [ argument word 1 ] |
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// -11 [ saved r15 ] <--- rsp_after_call |
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// -10 [ saved r14 ] |
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// -9 [ saved r13 ] |
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// -8 [ saved r12 ] |
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// -7 [ saved rbx ] |
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// -6 [ call wrapper ] |
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// -5 [ result ] |
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// -4 [ result type ] |
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// -3 [ method ] |
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// -2 [ entry point ] |
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// -1 [ parameters ] |
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// 0 [ saved rbp ] <--- rbp |
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// 1 [ return address ] |
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// 2 [ parameter size ] |
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// 3 [ thread ] |
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// |
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// Windows Arguments: |
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// c_rarg0: call wrapper address address |
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// c_rarg1: result address |
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// c_rarg2: result type BasicType |
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// c_rarg3: method Method* |
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// 48(rbp): (interpreter) entry point address |
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// 56(rbp): parameters intptr_t* |
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// 64(rbp): parameter size (in words) int |
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// 72(rbp): thread Thread* |
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// |
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// [ return_from_Java ] <--- rsp |
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// [ argument word n ] |
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// ... |
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30624 | 132 |
// -60 [ argument word 1 ] |
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// -59 [ saved xmm31 ] <--- rsp after_call |
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// [ saved xmm16-xmm30 ] (EVEX enabled, else the space is blank) |
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// -27 [ saved xmm15 ] |
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// [ saved xmm7-xmm14 ] |
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// -9 [ saved xmm6 ] (each xmm register takes 2 slots) |
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// -7 [ saved r15 ] |
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// -6 [ saved r14 ] |
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// -5 [ saved r13 ] |
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// -4 [ saved r12 ] |
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// -3 [ saved rdi ] |
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// -2 [ saved rsi ] |
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// -1 [ saved rbx ] |
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// 0 [ saved rbp ] <--- rbp |
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// 1 [ return address ] |
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// 2 [ call wrapper ] |
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// 3 [ result ] |
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// 4 [ result type ] |
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// 5 [ method ] |
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// 6 [ entry point ] |
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// 7 [ parameters ] |
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// 8 [ parameter size ] |
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// 9 [ thread ] |
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// |
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// Windows reserves the callers stack space for arguments 1-4. |
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// We spill c_rarg0-c_rarg3 to this space. |
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// Call stub stack layout word offsets from rbp |
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enum call_stub_layout { |
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#ifdef _WIN64 |
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xmm_save_first = 6, // save from xmm6 |
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xmm_save_last = 31, // to xmm31 |
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xmm_save_base = -9, |
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rsp_after_call_off = xmm_save_base - 2 * (xmm_save_last - xmm_save_first), // -27 |
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r15_off = -7, |
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r14_off = -6, |
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r13_off = -5, |
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r12_off = -4, |
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rdi_off = -3, |
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rsi_off = -2, |
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rbx_off = -1, |
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rbp_off = 0, |
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retaddr_off = 1, |
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call_wrapper_off = 2, |
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result_off = 3, |
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result_type_off = 4, |
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method_off = 5, |
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entry_point_off = 6, |
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parameters_off = 7, |
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parameter_size_off = 8, |
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thread_off = 9 |
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#else |
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rsp_after_call_off = -12, |
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mxcsr_off = rsp_after_call_off, |
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r15_off = -11, |
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r14_off = -10, |
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r13_off = -9, |
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r12_off = -8, |
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rbx_off = -7, |
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call_wrapper_off = -6, |
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result_off = -5, |
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result_type_off = -4, |
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method_off = -3, |
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entry_point_off = -2, |
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parameters_off = -1, |
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rbp_off = 0, |
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retaddr_off = 1, |
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parameter_size_off = 2, |
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thread_off = 3 |
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#endif |
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}; |
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#ifdef _WIN64 |
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Address xmm_save(int reg) { |
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assert(reg >= xmm_save_first && reg <= xmm_save_last, "XMM register number out of range"); |
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return Address(rbp, (xmm_save_base - (reg - xmm_save_first) * 2) * wordSize); |
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} |
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#endif |
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1 | 211 |
address generate_call_stub(address& return_address) { |
212 |
assert((int)frame::entry_frame_after_call_words == -(int)rsp_after_call_off + 1 && |
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(int)frame::entry_frame_call_wrapper_offset == (int)call_wrapper_off, |
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"adjust this code"); |
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215 |
StubCodeMark mark(this, "StubRoutines", "call_stub"); |
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address start = __ pc(); |
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217 |
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// same as in generate_catch_exception()! |
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219 |
const Address rsp_after_call(rbp, rsp_after_call_off * wordSize); |
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220 |
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const Address call_wrapper (rbp, call_wrapper_off * wordSize); |
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222 |
const Address result (rbp, result_off * wordSize); |
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223 |
const Address result_type (rbp, result_type_off * wordSize); |
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const Address method (rbp, method_off * wordSize); |
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225 |
const Address entry_point (rbp, entry_point_off * wordSize); |
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226 |
const Address parameters (rbp, parameters_off * wordSize); |
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const Address parameter_size(rbp, parameter_size_off * wordSize); |
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228 |
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229 |
// same as in generate_catch_exception()! |
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230 |
const Address thread (rbp, thread_off * wordSize); |
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231 |
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232 |
const Address r15_save(rbp, r15_off * wordSize); |
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233 |
const Address r14_save(rbp, r14_off * wordSize); |
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234 |
const Address r13_save(rbp, r13_off * wordSize); |
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235 |
const Address r12_save(rbp, r12_off * wordSize); |
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236 |
const Address rbx_save(rbp, rbx_off * wordSize); |
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237 |
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238 |
// stub code |
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239 |
__ enter(); |
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1066 | 240 |
__ subptr(rsp, -rsp_after_call_off * wordSize); |
1 | 241 |
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242 |
// save register parameters |
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243 |
#ifndef _WIN64 |
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1066 | 244 |
__ movptr(parameters, c_rarg5); // parameters |
245 |
__ movptr(entry_point, c_rarg4); // entry_point |
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1 | 246 |
#endif |
247 |
||
1066 | 248 |
__ movptr(method, c_rarg3); // method |
249 |
__ movl(result_type, c_rarg2); // result type |
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250 |
__ movptr(result, c_rarg1); // result |
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251 |
__ movptr(call_wrapper, c_rarg0); // call wrapper |
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1 | 252 |
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253 |
// save regs belonging to calling function |
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1066 | 254 |
__ movptr(rbx_save, rbx); |
255 |
__ movptr(r12_save, r12); |
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256 |
__ movptr(r13_save, r13); |
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257 |
__ movptr(r14_save, r14); |
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258 |
__ movptr(r15_save, r15); |
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1 | 260 |
#ifdef _WIN64 |
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int last_reg = 15; |
30624 | 262 |
if (UseAVX > 2) { |
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last_reg = 31; |
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} |
34162 | 265 |
if (VM_Version::supports_evex()) { |
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for (int i = xmm_save_first; i <= last_reg; i++) { |
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__ vextractf32x4(xmm_save(i), as_XMMRegister(i), 0); |
30624 | 268 |
} |
269 |
} else { |
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for (int i = xmm_save_first; i <= last_reg; i++) { |
30624 | 271 |
__ movdqu(xmm_save(i), as_XMMRegister(i)); |
272 |
} |
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} |
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1 | 275 |
const Address rdi_save(rbp, rdi_off * wordSize); |
276 |
const Address rsi_save(rbp, rsi_off * wordSize); |
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277 |
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1066 | 278 |
__ movptr(rsi_save, rsi); |
279 |
__ movptr(rdi_save, rdi); |
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1 | 280 |
#else |
281 |
const Address mxcsr_save(rbp, mxcsr_off * wordSize); |
|
282 |
{ |
|
283 |
Label skip_ldmx; |
|
284 |
__ stmxcsr(mxcsr_save); |
|
285 |
__ movl(rax, mxcsr_save); |
|
286 |
__ andl(rax, MXCSR_MASK); // Only check control and mask bits |
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ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std()); |
1 | 288 |
__ cmp32(rax, mxcsr_std); |
289 |
__ jcc(Assembler::equal, skip_ldmx); |
|
290 |
__ ldmxcsr(mxcsr_std); |
|
291 |
__ bind(skip_ldmx); |
|
292 |
} |
|
293 |
#endif |
|
294 |
||
295 |
// Load up thread register |
|
1066 | 296 |
__ movptr(r15_thread, thread); |
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297 |
__ reinit_heapbase(); |
1 | 298 |
|
299 |
#ifdef ASSERT |
|
300 |
// make sure we have no pending exceptions |
|
301 |
{ |
|
302 |
Label L; |
|
1066 | 303 |
__ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); |
1 | 304 |
__ jcc(Assembler::equal, L); |
305 |
__ stop("StubRoutines::call_stub: entered with pending exception"); |
|
306 |
__ bind(L); |
|
307 |
} |
|
308 |
#endif |
|
309 |
||
310 |
// pass parameters if any |
|
311 |
BLOCK_COMMENT("pass parameters if any"); |
|
312 |
Label parameters_done; |
|
313 |
__ movl(c_rarg3, parameter_size); |
|
314 |
__ testl(c_rarg3, c_rarg3); |
|
315 |
__ jcc(Assembler::zero, parameters_done); |
|
316 |
||
317 |
Label loop; |
|
1066 | 318 |
__ movptr(c_rarg2, parameters); // parameter pointer |
319 |
__ movl(c_rarg1, c_rarg3); // parameter counter is in c_rarg1 |
|
1 | 320 |
__ BIND(loop); |
1066 | 321 |
__ movptr(rax, Address(c_rarg2, 0));// get parameter |
322 |
__ addptr(c_rarg2, wordSize); // advance to next parameter |
|
323 |
__ decrementl(c_rarg1); // decrement counter |
|
324 |
__ push(rax); // pass parameter |
|
1 | 325 |
__ jcc(Assembler::notZero, loop); |
326 |
||
327 |
// call Java function |
|
328 |
__ BIND(parameters_done); |
|
13728
882756847a04
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changeset
|
329 |
__ movptr(rbx, method); // get Method* |
1066 | 330 |
__ movptr(c_rarg1, entry_point); // get entry_point |
331 |
__ mov(r13, rsp); // set sender sp |
|
1 | 332 |
BLOCK_COMMENT("call Java function"); |
333 |
__ call(c_rarg1); |
|
334 |
||
335 |
BLOCK_COMMENT("call_stub_return_address:"); |
|
336 |
return_address = __ pc(); |
|
337 |
||
338 |
// store result depending on type (everything that is not |
|
339 |
// T_OBJECT, T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT) |
|
1066 | 340 |
__ movptr(c_rarg0, result); |
1 | 341 |
Label is_long, is_float, is_double, exit; |
342 |
__ movl(c_rarg1, result_type); |
|
343 |
__ cmpl(c_rarg1, T_OBJECT); |
|
344 |
__ jcc(Assembler::equal, is_long); |
|
345 |
__ cmpl(c_rarg1, T_LONG); |
|
346 |
__ jcc(Assembler::equal, is_long); |
|
347 |
__ cmpl(c_rarg1, T_FLOAT); |
|
348 |
__ jcc(Assembler::equal, is_float); |
|
349 |
__ cmpl(c_rarg1, T_DOUBLE); |
|
350 |
__ jcc(Assembler::equal, is_double); |
|
351 |
||
352 |
// handle T_INT case |
|
353 |
__ movl(Address(c_rarg0, 0), rax); |
|
354 |
||
355 |
__ BIND(exit); |
|
356 |
||
357 |
// pop parameters |
|
1066 | 358 |
__ lea(rsp, rsp_after_call); |
1 | 359 |
|
360 |
#ifdef ASSERT |
|
361 |
// verify that threads correspond |
|
362 |
{ |
|
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
363 |
Label L1, L2, L3; |
1066 | 364 |
__ cmpptr(r15_thread, thread); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
365 |
__ jcc(Assembler::equal, L1); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
366 |
__ stop("StubRoutines::call_stub: r15_thread is corrupted"); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
367 |
__ bind(L1); |
1 | 368 |
__ get_thread(rbx); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
369 |
__ cmpptr(r15_thread, thread); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
370 |
__ jcc(Assembler::equal, L2); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
371 |
__ stop("StubRoutines::call_stub: r15_thread is modified by call"); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
372 |
__ bind(L2); |
1066 | 373 |
__ cmpptr(r15_thread, rbx); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
374 |
__ jcc(Assembler::equal, L3); |
1 | 375 |
__ stop("StubRoutines::call_stub: threads must correspond"); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
376 |
__ bind(L3); |
1 | 377 |
} |
378 |
#endif |
|
379 |
||
380 |
// restore regs belonging to calling function |
|
8874
b2030880129c
6741940: Nonvolatile XMM registers not preserved across JNI calls
iveresov
parents:
8498
diff
changeset
|
381 |
#ifdef _WIN64 |
31410 | 382 |
// emit the restores for xmm regs |
34162 | 383 |
if (VM_Version::supports_evex()) { |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
384 |
for (int i = xmm_save_first; i <= last_reg; i++) { |
36561
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
385 |
__ vinsertf32x4(as_XMMRegister(i), as_XMMRegister(i), xmm_save(i), 0); |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
386 |
} |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
387 |
} else { |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
388 |
for (int i = xmm_save_first; i <= last_reg; i++) { |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
389 |
__ movdqu(as_XMMRegister(i), xmm_save(i)); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
390 |
} |
8874
b2030880129c
6741940: Nonvolatile XMM registers not preserved across JNI calls
iveresov
parents:
8498
diff
changeset
|
391 |
} |
b2030880129c
6741940: Nonvolatile XMM registers not preserved across JNI calls
iveresov
parents:
8498
diff
changeset
|
392 |
#endif |
1066 | 393 |
__ movptr(r15, r15_save); |
394 |
__ movptr(r14, r14_save); |
|
395 |
__ movptr(r13, r13_save); |
|
396 |
__ movptr(r12, r12_save); |
|
397 |
__ movptr(rbx, rbx_save); |
|
1 | 398 |
|
399 |
#ifdef _WIN64 |
|
1066 | 400 |
__ movptr(rdi, rdi_save); |
401 |
__ movptr(rsi, rsi_save); |
|
1 | 402 |
#else |
403 |
__ ldmxcsr(mxcsr_save); |
|
404 |
#endif |
|
405 |
||
406 |
// restore rsp |
|
1066 | 407 |
__ addptr(rsp, -rsp_after_call_off * wordSize); |
1 | 408 |
|
409 |
// return |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
410 |
__ vzeroupper(); |
1066 | 411 |
__ pop(rbp); |
1 | 412 |
__ ret(0); |
413 |
||
414 |
// handle return types different from T_INT |
|
415 |
__ BIND(is_long); |
|
416 |
__ movq(Address(c_rarg0, 0), rax); |
|
417 |
__ jmp(exit); |
|
418 |
||
419 |
__ BIND(is_float); |
|
420 |
__ movflt(Address(c_rarg0, 0), xmm0); |
|
421 |
__ jmp(exit); |
|
422 |
||
423 |
__ BIND(is_double); |
|
424 |
__ movdbl(Address(c_rarg0, 0), xmm0); |
|
425 |
__ jmp(exit); |
|
426 |
||
427 |
return start; |
|
428 |
} |
|
429 |
||
430 |
// Return point for a Java call if there's an exception thrown in |
|
431 |
// Java code. The exception is caught and transformed into a |
|
432 |
// pending exception stored in JavaThread that can be tested from |
|
433 |
// within the VM. |
|
434 |
// |
|
435 |
// Note: Usually the parameters are removed by the callee. In case |
|
436 |
// of an exception crossing an activation frame boundary, that is |
|
437 |
// not the case if the callee is compiled code => need to setup the |
|
438 |
// rsp. |
|
439 |
// |
|
440 |
// rax: exception oop |
|
441 |
||
442 |
address generate_catch_exception() { |
|
443 |
StubCodeMark mark(this, "StubRoutines", "catch_exception"); |
|
444 |
address start = __ pc(); |
|
445 |
||
446 |
// same as in generate_call_stub(): |
|
447 |
const Address rsp_after_call(rbp, rsp_after_call_off * wordSize); |
|
448 |
const Address thread (rbp, thread_off * wordSize); |
|
449 |
||
450 |
#ifdef ASSERT |
|
451 |
// verify that threads correspond |
|
452 |
{ |
|
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
453 |
Label L1, L2, L3; |
1066 | 454 |
__ cmpptr(r15_thread, thread); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
455 |
__ jcc(Assembler::equal, L1); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
456 |
__ stop("StubRoutines::catch_exception: r15_thread is corrupted"); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
457 |
__ bind(L1); |
1 | 458 |
__ get_thread(rbx); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
459 |
__ cmpptr(r15_thread, thread); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
460 |
__ jcc(Assembler::equal, L2); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
461 |
__ stop("StubRoutines::catch_exception: r15_thread is modified by call"); |
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
462 |
__ bind(L2); |
1066 | 463 |
__ cmpptr(r15_thread, rbx); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
464 |
__ jcc(Assembler::equal, L3); |
1 | 465 |
__ stop("StubRoutines::catch_exception: threads must correspond"); |
32590
66edb61f17d4
8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents:
31584
diff
changeset
|
466 |
__ bind(L3); |
1 | 467 |
} |
468 |
#endif |
|
469 |
||
470 |
// set pending exception |
|
471 |
__ verify_oop(rax); |
|
472 |
||
1066 | 473 |
__ movptr(Address(r15_thread, Thread::pending_exception_offset()), rax); |
1 | 474 |
__ lea(rscratch1, ExternalAddress((address)__FILE__)); |
1066 | 475 |
__ movptr(Address(r15_thread, Thread::exception_file_offset()), rscratch1); |
1 | 476 |
__ movl(Address(r15_thread, Thread::exception_line_offset()), (int) __LINE__); |
477 |
||
478 |
// complete return to VM |
|
479 |
assert(StubRoutines::_call_stub_return_address != NULL, |
|
480 |
"_call_stub_return_address must have been generated before"); |
|
481 |
__ jump(RuntimeAddress(StubRoutines::_call_stub_return_address)); |
|
482 |
||
483 |
return start; |
|
484 |
} |
|
485 |
||
486 |
// Continuation point for runtime calls returning with a pending |
|
487 |
// exception. The pending exception check happened in the runtime |
|
488 |
// or native call stub. The pending exception in Thread is |
|
489 |
// converted into a Java-level exception. |
|
490 |
// |
|
491 |
// Contract with Java-level exception handlers: |
|
492 |
// rax: exception |
|
493 |
// rdx: throwing pc |
|
494 |
// |
|
495 |
// NOTE: At entry of this stub, exception-pc must be on stack !! |
|
496 |
||
497 |
address generate_forward_exception() { |
|
498 |
StubCodeMark mark(this, "StubRoutines", "forward exception"); |
|
499 |
address start = __ pc(); |
|
500 |
||
501 |
// Upon entry, the sp points to the return address returning into |
|
502 |
// Java (interpreted or compiled) code; i.e., the return address |
|
503 |
// becomes the throwing pc. |
|
504 |
// |
|
505 |
// Arguments pushed before the runtime call are still on the stack |
|
506 |
// but the exception handler will reset the stack pointer -> |
|
507 |
// ignore them. A potential result in registers can be ignored as |
|
508 |
// well. |
|
509 |
||
510 |
#ifdef ASSERT |
|
511 |
// make sure this code is only executed if there is a pending exception |
|
512 |
{ |
|
513 |
Label L; |
|
1066 | 514 |
__ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t) NULL); |
1 | 515 |
__ jcc(Assembler::notEqual, L); |
516 |
__ stop("StubRoutines::forward exception: no pending exception (1)"); |
|
517 |
__ bind(L); |
|
518 |
} |
|
519 |
#endif |
|
520 |
||
521 |
// compute exception handler into rbx |
|
1066 | 522 |
__ movptr(c_rarg0, Address(rsp, 0)); |
1 | 523 |
BLOCK_COMMENT("call exception_handler_for_return_address"); |
524 |
__ call_VM_leaf(CAST_FROM_FN_PTR(address, |
|
525 |
SharedRuntime::exception_handler_for_return_address), |
|
5046 | 526 |
r15_thread, c_rarg0); |
1066 | 527 |
__ mov(rbx, rax); |
1 | 528 |
|
529 |
// setup rax & rdx, remove return address & clear pending exception |
|
1066 | 530 |
__ pop(rdx); |
531 |
__ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); |
|
1888
bbf498fb4354
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
1437
diff
changeset
|
532 |
__ movptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); |
1 | 533 |
|
534 |
#ifdef ASSERT |
|
535 |
// make sure exception is set |
|
536 |
{ |
|
537 |
Label L; |
|
1066 | 538 |
__ testptr(rax, rax); |
1 | 539 |
__ jcc(Assembler::notEqual, L); |
540 |
__ stop("StubRoutines::forward exception: no pending exception (2)"); |
|
541 |
__ bind(L); |
|
542 |
} |
|
543 |
#endif |
|
544 |
||
545 |
// continue at exception handler (return address removed) |
|
546 |
// rax: exception |
|
547 |
// rbx: exception handler |
|
548 |
// rdx: throwing pc |
|
549 |
__ verify_oop(rax); |
|
550 |
__ jmp(rbx); |
|
551 |
||
552 |
return start; |
|
553 |
} |
|
554 |
||
59251
4cbfa5077d68
8234739: Harmonize parameter order in Atomic - xchg
stefank
parents:
59249
diff
changeset
|
555 |
// Implementation of jint atomic_xchg(jint add_value, volatile jint* dest) |
4cbfa5077d68
8234739: Harmonize parameter order in Atomic - xchg
stefank
parents:
59249
diff
changeset
|
556 |
// used by Atomic::xchg(volatile jint* dest, jint exchange_value) |
1 | 557 |
// |
558 |
// Arguments : |
|
559 |
// c_rarg0: exchange_value |
|
560 |
// c_rarg0: dest |
|
561 |
// |
|
562 |
// Result: |
|
563 |
// *dest <- ex, return (orig *dest) |
|
564 |
address generate_atomic_xchg() { |
|
565 |
StubCodeMark mark(this, "StubRoutines", "atomic_xchg"); |
|
566 |
address start = __ pc(); |
|
567 |
||
568 |
__ movl(rax, c_rarg0); // Copy to eax we need a return value anyhow |
|
569 |
__ xchgl(rax, Address(c_rarg1, 0)); // automatic LOCK |
|
570 |
__ ret(0); |
|
571 |
||
572 |
return start; |
|
573 |
} |
|
574 |
||
59251
4cbfa5077d68
8234739: Harmonize parameter order in Atomic - xchg
stefank
parents:
59249
diff
changeset
|
575 |
// Implementation of intptr_t atomic_xchg(jlong add_value, volatile jlong* dest) |
4cbfa5077d68
8234739: Harmonize parameter order in Atomic - xchg
stefank
parents:
59249
diff
changeset
|
576 |
// used by Atomic::xchg(volatile jlong* dest, jlong exchange_value) |
1 | 577 |
// |
578 |
// Arguments : |
|
579 |
// c_rarg0: exchange_value |
|
580 |
// c_rarg1: dest |
|
581 |
// |
|
582 |
// Result: |
|
583 |
// *dest <- ex, return (orig *dest) |
|
47634
6a0c42c40cd1
8188220: Remove Atomic::*_ptr() uses and overloads from hotspot
coleenp
parents:
47216
diff
changeset
|
584 |
address generate_atomic_xchg_long() { |
6a0c42c40cd1
8188220: Remove Atomic::*_ptr() uses and overloads from hotspot
coleenp
parents:
47216
diff
changeset
|
585 |
StubCodeMark mark(this, "StubRoutines", "atomic_xchg_long"); |
1 | 586 |
address start = __ pc(); |
587 |
||
1066 | 588 |
__ movptr(rax, c_rarg0); // Copy to eax we need a return value anyhow |
589 |
__ xchgptr(rax, Address(c_rarg1, 0)); // automatic LOCK |
|
1 | 590 |
__ ret(0); |
591 |
||
592 |
return start; |
|
593 |
} |
|
594 |
||
595 |
// Support for jint atomic::atomic_cmpxchg(jint exchange_value, volatile jint* dest, |
|
596 |
// jint compare_value) |
|
597 |
// |
|
598 |
// Arguments : |
|
599 |
// c_rarg0: exchange_value |
|
600 |
// c_rarg1: dest |
|
601 |
// c_rarg2: compare_value |
|
602 |
// |
|
603 |
// Result: |
|
604 |
// if ( compare_value == *dest ) { |
|
605 |
// *dest = exchange_value |
|
606 |
// return compare_value; |
|
607 |
// else |
|
608 |
// return *dest; |
|
609 |
address generate_atomic_cmpxchg() { |
|
610 |
StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg"); |
|
611 |
address start = __ pc(); |
|
612 |
||
613 |
__ movl(rax, c_rarg2); |
|
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
614 |
__ lock(); |
1 | 615 |
__ cmpxchgl(c_rarg0, Address(c_rarg1, 0)); |
616 |
__ ret(0); |
|
617 |
||
618 |
return start; |
|
619 |
} |
|
620 |
||
48468 | 621 |
// Support for int8_t atomic::atomic_cmpxchg(int8_t exchange_value, volatile int8_t* dest, |
622 |
// int8_t compare_value) |
|
27691
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
623 |
// |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
624 |
// Arguments : |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
625 |
// c_rarg0: exchange_value |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
626 |
// c_rarg1: dest |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
627 |
// c_rarg2: compare_value |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
628 |
// |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
629 |
// Result: |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
630 |
// if ( compare_value == *dest ) { |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
631 |
// *dest = exchange_value |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
632 |
// return compare_value; |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
633 |
// else |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
634 |
// return *dest; |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
635 |
address generate_atomic_cmpxchg_byte() { |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
636 |
StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg_byte"); |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
637 |
address start = __ pc(); |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
638 |
|
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
639 |
__ movsbq(rax, c_rarg2); |
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
640 |
__ lock(); |
27691
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
641 |
__ cmpxchgb(c_rarg0, Address(c_rarg1, 0)); |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
642 |
__ ret(0); |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
643 |
|
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
644 |
return start; |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
645 |
} |
733f189ad1f7
8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents:
26434
diff
changeset
|
646 |
|
48468 | 647 |
// Support for int64_t atomic::atomic_cmpxchg(int64_t exchange_value, |
648 |
// volatile int64_t* dest, |
|
649 |
// int64_t compare_value) |
|
1 | 650 |
// Arguments : |
651 |
// c_rarg0: exchange_value |
|
652 |
// c_rarg1: dest |
|
653 |
// c_rarg2: compare_value |
|
654 |
// |
|
655 |
// Result: |
|
656 |
// if ( compare_value == *dest ) { |
|
657 |
// *dest = exchange_value |
|
658 |
// return compare_value; |
|
659 |
// else |
|
660 |
// return *dest; |
|
661 |
address generate_atomic_cmpxchg_long() { |
|
662 |
StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg_long"); |
|
663 |
address start = __ pc(); |
|
664 |
||
665 |
__ movq(rax, c_rarg2); |
|
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
666 |
__ lock(); |
1 | 667 |
__ cmpxchgq(c_rarg0, Address(c_rarg1, 0)); |
668 |
__ ret(0); |
|
669 |
||
670 |
return start; |
|
671 |
} |
|
672 |
||
59249
29b0d0b61615
8234737: Harmonize parameter order in Atomic - add
stefank
parents:
58977
diff
changeset
|
673 |
// Implementation of jint atomic_add(jint add_value, volatile jint* dest) |
29b0d0b61615
8234737: Harmonize parameter order in Atomic - add
stefank
parents:
58977
diff
changeset
|
674 |
// used by Atomic::add(volatile jint* dest, jint add_value) |
1 | 675 |
// |
676 |
// Arguments : |
|
677 |
// c_rarg0: add_value |
|
678 |
// c_rarg1: dest |
|
679 |
// |
|
680 |
// Result: |
|
681 |
// *dest += add_value |
|
682 |
// return *dest; |
|
683 |
address generate_atomic_add() { |
|
684 |
StubCodeMark mark(this, "StubRoutines", "atomic_add"); |
|
685 |
address start = __ pc(); |
|
686 |
||
687 |
__ movl(rax, c_rarg0); |
|
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
688 |
__ lock(); |
1 | 689 |
__ xaddl(Address(c_rarg1, 0), c_rarg0); |
690 |
__ addl(rax, c_rarg0); |
|
691 |
__ ret(0); |
|
692 |
||
693 |
return start; |
|
694 |
} |
|
695 |
||
59249
29b0d0b61615
8234737: Harmonize parameter order in Atomic - add
stefank
parents:
58977
diff
changeset
|
696 |
// Implementation of intptr_t atomic_add(intptr_t add_value, volatile intptr_t* dest) |
29b0d0b61615
8234737: Harmonize parameter order in Atomic - add
stefank
parents:
58977
diff
changeset
|
697 |
// used by Atomic::add(volatile intptr_t* dest, intptr_t add_value) |
1 | 698 |
// |
699 |
// Arguments : |
|
700 |
// c_rarg0: add_value |
|
701 |
// c_rarg1: dest |
|
702 |
// |
|
703 |
// Result: |
|
704 |
// *dest += add_value |
|
705 |
// return *dest; |
|
48468 | 706 |
address generate_atomic_add_long() { |
707 |
StubCodeMark mark(this, "StubRoutines", "atomic_add_long"); |
|
1 | 708 |
address start = __ pc(); |
709 |
||
1066 | 710 |
__ movptr(rax, c_rarg0); // Copy to eax we need a return value anyhow |
51996
84743156e780
8188764: Obsolete AssumeMP and then remove all support for non-MP builds
dholmes
parents:
51976
diff
changeset
|
711 |
__ lock(); |
1066 | 712 |
__ xaddptr(Address(c_rarg1, 0), c_rarg0); |
713 |
__ addptr(rax, c_rarg0); |
|
1 | 714 |
__ ret(0); |
715 |
||
716 |
return start; |
|
717 |
} |
|
718 |
||
719 |
// Support for intptr_t OrderAccess::fence() |
|
720 |
// |
|
721 |
// Arguments : |
|
722 |
// |
|
723 |
// Result: |
|
724 |
address generate_orderaccess_fence() { |
|
725 |
StubCodeMark mark(this, "StubRoutines", "orderaccess_fence"); |
|
726 |
address start = __ pc(); |
|
2338
a8660a1b709b
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
2259
diff
changeset
|
727 |
__ membar(Assembler::StoreLoad); |
1 | 728 |
__ ret(0); |
729 |
||
730 |
return start; |
|
731 |
} |
|
732 |
||
733 |
// Support for intptr_t get_previous_fp() |
|
734 |
// |
|
735 |
// This routine is used to find the previous frame pointer for the |
|
736 |
// caller (current_frame_guess). This is used as part of debugging |
|
737 |
// ps() is seemingly lost trying to find frames. |
|
738 |
// This code assumes that caller current_frame_guess) has a frame. |
|
739 |
address generate_get_previous_fp() { |
|
740 |
StubCodeMark mark(this, "StubRoutines", "get_previous_fp"); |
|
741 |
const Address old_fp(rbp, 0); |
|
742 |
const Address older_fp(rax, 0); |
|
743 |
address start = __ pc(); |
|
744 |
||
745 |
__ enter(); |
|
1066 | 746 |
__ movptr(rax, old_fp); // callers fp |
747 |
__ movptr(rax, older_fp); // the frame for ps() |
|
748 |
__ pop(rbp); |
|
1 | 749 |
__ ret(0); |
750 |
||
751 |
return start; |
|
752 |
} |
|
753 |
||
11961
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
754 |
// Support for intptr_t get_previous_sp() |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
755 |
// |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
756 |
// This routine is used to find the previous stack pointer for the |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
757 |
// caller. |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
758 |
address generate_get_previous_sp() { |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
759 |
StubCodeMark mark(this, "StubRoutines", "get_previous_sp"); |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
760 |
address start = __ pc(); |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
761 |
|
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
762 |
__ movptr(rax, rsp); |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
763 |
__ addptr(rax, 8); // return address is at the top of the stack. |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
764 |
__ ret(0); |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
765 |
|
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
766 |
return start; |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
767 |
} |
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
768 |
|
1 | 769 |
//---------------------------------------------------------------------------------------------------- |
770 |
// Support for void verify_mxcsr() |
|
771 |
// |
|
772 |
// This routine is used with -Xcheck:jni to verify that native |
|
773 |
// JNI code does not return to Java code without restoring the |
|
774 |
// MXCSR register to our expected state. |
|
775 |
||
776 |
address generate_verify_mxcsr() { |
|
777 |
StubCodeMark mark(this, "StubRoutines", "verify_mxcsr"); |
|
778 |
address start = __ pc(); |
|
779 |
||
780 |
const Address mxcsr_save(rsp, 0); |
|
781 |
||
782 |
if (CheckJNICalls) { |
|
783 |
Label ok_ret; |
|
18958
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
784 |
ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std()); |
1066 | 785 |
__ push(rax); |
786 |
__ subptr(rsp, wordSize); // allocate a temp location |
|
1 | 787 |
__ stmxcsr(mxcsr_save); |
788 |
__ movl(rax, mxcsr_save); |
|
789 |
__ andl(rax, MXCSR_MASK); // Only check control and mask bits |
|
18958
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
790 |
__ cmp32(rax, mxcsr_std); |
1 | 791 |
__ jcc(Assembler::equal, ok_ret); |
792 |
||
793 |
__ warn("MXCSR changed by native JNI code, use -XX:+RestoreMXCSROnJNICall"); |
|
794 |
||
18958
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
795 |
__ ldmxcsr(mxcsr_std); |
1 | 796 |
|
797 |
__ bind(ok_ret); |
|
1066 | 798 |
__ addptr(rsp, wordSize); |
799 |
__ pop(rax); |
|
1 | 800 |
} |
801 |
||
802 |
__ ret(0); |
|
803 |
||
804 |
return start; |
|
805 |
} |
|
806 |
||
807 |
address generate_f2i_fixup() { |
|
808 |
StubCodeMark mark(this, "StubRoutines", "f2i_fixup"); |
|
809 |
Address inout(rsp, 5 * wordSize); // return address + 4 saves |
|
810 |
||
811 |
address start = __ pc(); |
|
812 |
||
813 |
Label L; |
|
814 |
||
1066 | 815 |
__ push(rax); |
816 |
__ push(c_rarg3); |
|
817 |
__ push(c_rarg2); |
|
818 |
__ push(c_rarg1); |
|
1 | 819 |
|
820 |
__ movl(rax, 0x7f800000); |
|
821 |
__ xorl(c_rarg3, c_rarg3); |
|
822 |
__ movl(c_rarg2, inout); |
|
823 |
__ movl(c_rarg1, c_rarg2); |
|
824 |
__ andl(c_rarg1, 0x7fffffff); |
|
825 |
__ cmpl(rax, c_rarg1); // NaN? -> 0 |
|
826 |
__ jcc(Assembler::negative, L); |
|
827 |
__ testl(c_rarg2, c_rarg2); // signed ? min_jint : max_jint |
|
828 |
__ movl(c_rarg3, 0x80000000); |
|
829 |
__ movl(rax, 0x7fffffff); |
|
830 |
__ cmovl(Assembler::positive, c_rarg3, rax); |
|
831 |
||
832 |
__ bind(L); |
|
1066 | 833 |
__ movptr(inout, c_rarg3); |
834 |
||
835 |
__ pop(c_rarg1); |
|
836 |
__ pop(c_rarg2); |
|
837 |
__ pop(c_rarg3); |
|
838 |
__ pop(rax); |
|
1 | 839 |
|
840 |
__ ret(0); |
|
841 |
||
842 |
return start; |
|
843 |
} |
|
844 |
||
845 |
address generate_f2l_fixup() { |
|
846 |
StubCodeMark mark(this, "StubRoutines", "f2l_fixup"); |
|
847 |
Address inout(rsp, 5 * wordSize); // return address + 4 saves |
|
848 |
address start = __ pc(); |
|
849 |
||
850 |
Label L; |
|
851 |
||
1066 | 852 |
__ push(rax); |
853 |
__ push(c_rarg3); |
|
854 |
__ push(c_rarg2); |
|
855 |
__ push(c_rarg1); |
|
1 | 856 |
|
857 |
__ movl(rax, 0x7f800000); |
|
858 |
__ xorl(c_rarg3, c_rarg3); |
|
859 |
__ movl(c_rarg2, inout); |
|
860 |
__ movl(c_rarg1, c_rarg2); |
|
861 |
__ andl(c_rarg1, 0x7fffffff); |
|
862 |
__ cmpl(rax, c_rarg1); // NaN? -> 0 |
|
863 |
__ jcc(Assembler::negative, L); |
|
864 |
__ testl(c_rarg2, c_rarg2); // signed ? min_jlong : max_jlong |
|
865 |
__ mov64(c_rarg3, 0x8000000000000000); |
|
866 |
__ mov64(rax, 0x7fffffffffffffff); |
|
1066 | 867 |
__ cmov(Assembler::positive, c_rarg3, rax); |
1 | 868 |
|
869 |
__ bind(L); |
|
1066 | 870 |
__ movptr(inout, c_rarg3); |
871 |
||
872 |
__ pop(c_rarg1); |
|
873 |
__ pop(c_rarg2); |
|
874 |
__ pop(c_rarg3); |
|
875 |
__ pop(rax); |
|
1 | 876 |
|
877 |
__ ret(0); |
|
878 |
||
879 |
return start; |
|
880 |
} |
|
881 |
||
882 |
address generate_d2i_fixup() { |
|
883 |
StubCodeMark mark(this, "StubRoutines", "d2i_fixup"); |
|
884 |
Address inout(rsp, 6 * wordSize); // return address + 5 saves |
|
885 |
||
886 |
address start = __ pc(); |
|
887 |
||
888 |
Label L; |
|
889 |
||
1066 | 890 |
__ push(rax); |
891 |
__ push(c_rarg3); |
|
892 |
__ push(c_rarg2); |
|
893 |
__ push(c_rarg1); |
|
894 |
__ push(c_rarg0); |
|
1 | 895 |
|
896 |
__ movl(rax, 0x7ff00000); |
|
897 |
__ movq(c_rarg2, inout); |
|
898 |
__ movl(c_rarg3, c_rarg2); |
|
1066 | 899 |
__ mov(c_rarg1, c_rarg2); |
900 |
__ mov(c_rarg0, c_rarg2); |
|
1 | 901 |
__ negl(c_rarg3); |
1066 | 902 |
__ shrptr(c_rarg1, 0x20); |
1 | 903 |
__ orl(c_rarg3, c_rarg2); |
904 |
__ andl(c_rarg1, 0x7fffffff); |
|
905 |
__ xorl(c_rarg2, c_rarg2); |
|
906 |
__ shrl(c_rarg3, 0x1f); |
|
907 |
__ orl(c_rarg1, c_rarg3); |
|
908 |
__ cmpl(rax, c_rarg1); |
|
909 |
__ jcc(Assembler::negative, L); // NaN -> 0 |
|
1066 | 910 |
__ testptr(c_rarg0, c_rarg0); // signed ? min_jint : max_jint |
1 | 911 |
__ movl(c_rarg2, 0x80000000); |
912 |
__ movl(rax, 0x7fffffff); |
|
1066 | 913 |
__ cmov(Assembler::positive, c_rarg2, rax); |
1 | 914 |
|
915 |
__ bind(L); |
|
1066 | 916 |
__ movptr(inout, c_rarg2); |
917 |
||
918 |
__ pop(c_rarg0); |
|
919 |
__ pop(c_rarg1); |
|
920 |
__ pop(c_rarg2); |
|
921 |
__ pop(c_rarg3); |
|
922 |
__ pop(rax); |
|
1 | 923 |
|
924 |
__ ret(0); |
|
925 |
||
926 |
return start; |
|
927 |
} |
|
928 |
||
929 |
address generate_d2l_fixup() { |
|
930 |
StubCodeMark mark(this, "StubRoutines", "d2l_fixup"); |
|
931 |
Address inout(rsp, 6 * wordSize); // return address + 5 saves |
|
932 |
||
933 |
address start = __ pc(); |
|
934 |
||
935 |
Label L; |
|
936 |
||
1066 | 937 |
__ push(rax); |
938 |
__ push(c_rarg3); |
|
939 |
__ push(c_rarg2); |
|
940 |
__ push(c_rarg1); |
|
941 |
__ push(c_rarg0); |
|
1 | 942 |
|
943 |
__ movl(rax, 0x7ff00000); |
|
944 |
__ movq(c_rarg2, inout); |
|
945 |
__ movl(c_rarg3, c_rarg2); |
|
1066 | 946 |
__ mov(c_rarg1, c_rarg2); |
947 |
__ mov(c_rarg0, c_rarg2); |
|
1 | 948 |
__ negl(c_rarg3); |
1066 | 949 |
__ shrptr(c_rarg1, 0x20); |
1 | 950 |
__ orl(c_rarg3, c_rarg2); |
951 |
__ andl(c_rarg1, 0x7fffffff); |
|
952 |
__ xorl(c_rarg2, c_rarg2); |
|
953 |
__ shrl(c_rarg3, 0x1f); |
|
954 |
__ orl(c_rarg1, c_rarg3); |
|
955 |
__ cmpl(rax, c_rarg1); |
|
956 |
__ jcc(Assembler::negative, L); // NaN -> 0 |
|
957 |
__ testq(c_rarg0, c_rarg0); // signed ? min_jlong : max_jlong |
|
958 |
__ mov64(c_rarg2, 0x8000000000000000); |
|
959 |
__ mov64(rax, 0x7fffffffffffffff); |
|
960 |
__ cmovq(Assembler::positive, c_rarg2, rax); |
|
961 |
||
962 |
__ bind(L); |
|
963 |
__ movq(inout, c_rarg2); |
|
964 |
||
1066 | 965 |
__ pop(c_rarg0); |
966 |
__ pop(c_rarg1); |
|
967 |
__ pop(c_rarg2); |
|
968 |
__ pop(c_rarg3); |
|
969 |
__ pop(rax); |
|
1 | 970 |
|
971 |
__ ret(0); |
|
972 |
||
973 |
return start; |
|
974 |
} |
|
975 |
||
976 |
address generate_fp_mask(const char *stub_name, int64_t mask) { |
|
5249 | 977 |
__ align(CodeEntryAlignment); |
1 | 978 |
StubCodeMark mark(this, "StubRoutines", stub_name); |
979 |
address start = __ pc(); |
|
980 |
||
981 |
__ emit_data64( mask, relocInfo::none ); |
|
982 |
__ emit_data64( mask, relocInfo::none ); |
|
983 |
||
984 |
return start; |
|
985 |
} |
|
986 |
||
54750 | 987 |
address generate_vector_mask(const char *stub_name, int64_t mask) { |
988 |
__ align(CodeEntryAlignment); |
|
989 |
StubCodeMark mark(this, "StubRoutines", stub_name); |
|
990 |
address start = __ pc(); |
|
991 |
||
992 |
__ emit_data64(mask, relocInfo::none); |
|
993 |
__ emit_data64(mask, relocInfo::none); |
|
994 |
__ emit_data64(mask, relocInfo::none); |
|
995 |
__ emit_data64(mask, relocInfo::none); |
|
996 |
__ emit_data64(mask, relocInfo::none); |
|
997 |
__ emit_data64(mask, relocInfo::none); |
|
998 |
__ emit_data64(mask, relocInfo::none); |
|
999 |
__ emit_data64(mask, relocInfo::none); |
|
1000 |
||
1001 |
return start; |
|
1002 |
} |
|
1003 |
||
1004 |
address generate_vector_byte_perm_mask(const char *stub_name) { |
|
1005 |
__ align(CodeEntryAlignment); |
|
1006 |
StubCodeMark mark(this, "StubRoutines", stub_name); |
|
1007 |
address start = __ pc(); |
|
1008 |
||
1009 |
__ emit_data64(0x0000000000000001, relocInfo::none); |
|
1010 |
__ emit_data64(0x0000000000000003, relocInfo::none); |
|
1011 |
__ emit_data64(0x0000000000000005, relocInfo::none); |
|
1012 |
__ emit_data64(0x0000000000000007, relocInfo::none); |
|
1013 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
|
1014 |
__ emit_data64(0x0000000000000002, relocInfo::none); |
|
1015 |
__ emit_data64(0x0000000000000004, relocInfo::none); |
|
1016 |
__ emit_data64(0x0000000000000006, relocInfo::none); |
|
1017 |
||
1018 |
return start; |
|
1019 |
} |
|
1020 |
||
1 | 1021 |
// Non-destructive plausibility checks for oops |
1022 |
// |
|
1023 |
// Arguments: |
|
1024 |
// all args on stack! |
|
1025 |
// |
|
1026 |
// Stack after saving c_rarg3: |
|
1027 |
// [tos + 0]: saved c_rarg3 |
|
1028 |
// [tos + 1]: saved c_rarg2 |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1029 |
// [tos + 2]: saved r12 (several TemplateTable methods use it) |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1030 |
// [tos + 3]: saved flags |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1031 |
// [tos + 4]: return address |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1032 |
// * [tos + 5]: error message (char*) |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1033 |
// * [tos + 6]: object to verify (oop) |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1034 |
// * [tos + 7]: saved rax - saved by caller and bashed |
5706 | 1035 |
// * [tos + 8]: saved r10 (rscratch1) - saved by caller |
1 | 1036 |
// * = popped on exit |
1037 |
address generate_verify_oop() { |
|
1038 |
StubCodeMark mark(this, "StubRoutines", "verify_oop"); |
|
1039 |
address start = __ pc(); |
|
1040 |
||
1041 |
Label exit, error; |
|
1042 |
||
1066 | 1043 |
__ pushf(); |
1 | 1044 |
__ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr())); |
1045 |
||
1066 | 1046 |
__ push(r12); |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1047 |
|
1 | 1048 |
// save c_rarg2 and c_rarg3 |
1066 | 1049 |
__ push(c_rarg2); |
1050 |
__ push(c_rarg3); |
|
1 | 1051 |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1052 |
enum { |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1053 |
// After previous pushes. |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1054 |
oop_to_verify = 6 * wordSize, |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1055 |
saved_rax = 7 * wordSize, |
5706 | 1056 |
saved_r10 = 8 * wordSize, |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1057 |
|
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1058 |
// Before the call to MacroAssembler::debug(), see below. |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1059 |
return_addr = 16 * wordSize, |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1060 |
error_msg = 17 * wordSize |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1061 |
}; |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1062 |
|
1 | 1063 |
// get object |
1066 | 1064 |
__ movptr(rax, Address(rsp, oop_to_verify)); |
1 | 1065 |
|
1066 |
// make sure object is 'reasonable' |
|
1066 | 1067 |
__ testptr(rax, rax); |
1 | 1068 |
__ jcc(Assembler::zero, exit); // if obj is NULL it is OK |
50525
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1069 |
|
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1070 |
#if INCLUDE_ZGC |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1071 |
if (UseZGC) { |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1072 |
// Check if metadata bits indicate a bad oop |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1073 |
__ testptr(rax, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1074 |
__ jcc(Assembler::notZero, error); |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1075 |
} |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1076 |
#endif |
767cdb97f103
8204210: Implementation: JEP 333: ZGC: A Scalable Low-Latency Garbage Collector (Experimental)
pliden
parents:
50179
diff
changeset
|
1077 |
|
1 | 1078 |
// Check if the oop is in the right area of memory |
1066 | 1079 |
__ movptr(c_rarg2, rax); |
1888
bbf498fb4354
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
1437
diff
changeset
|
1080 |
__ movptr(c_rarg3, (intptr_t) Universe::verify_oop_mask()); |
1066 | 1081 |
__ andptr(c_rarg2, c_rarg3); |
1888
bbf498fb4354
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
1437
diff
changeset
|
1082 |
__ movptr(c_rarg3, (intptr_t) Universe::verify_oop_bits()); |
1066 | 1083 |
__ cmpptr(c_rarg2, c_rarg3); |
1 | 1084 |
__ jcc(Assembler::notZero, error); |
1085 |
||
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1086 |
// set r12 to heapbase for load_klass() |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1087 |
__ reinit_heapbase(); |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1088 |
|
13728
882756847a04
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
13391
diff
changeset
|
1089 |
// make sure klass is 'reasonable', which is not zero. |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
1090 |
__ load_klass(rax, rax); // get klass |
1066 | 1091 |
__ testptr(rax, rax); |
1 | 1092 |
__ jcc(Assembler::zero, error); // if klass is NULL it is broken |
1093 |
||
1094 |
// return if everything seems ok |
|
1095 |
__ bind(exit); |
|
1066 | 1096 |
__ movptr(rax, Address(rsp, saved_rax)); // get saved rax back |
5706 | 1097 |
__ movptr(rscratch1, Address(rsp, saved_r10)); // get saved r10 back |
1066 | 1098 |
__ pop(c_rarg3); // restore c_rarg3 |
1099 |
__ pop(c_rarg2); // restore c_rarg2 |
|
1100 |
__ pop(r12); // restore r12 |
|
1101 |
__ popf(); // restore flags |
|
5706 | 1102 |
__ ret(4 * wordSize); // pop caller saved stuff |
1 | 1103 |
|
1104 |
// handle errors |
|
1105 |
__ bind(error); |
|
1066 | 1106 |
__ movptr(rax, Address(rsp, saved_rax)); // get saved rax back |
5706 | 1107 |
__ movptr(rscratch1, Address(rsp, saved_r10)); // get saved r10 back |
1066 | 1108 |
__ pop(c_rarg3); // get saved c_rarg3 back |
1109 |
__ pop(c_rarg2); // get saved c_rarg2 back |
|
1110 |
__ pop(r12); // get saved r12 back |
|
1111 |
__ popf(); // get saved flags off stack -- |
|
1 | 1112 |
// will be ignored |
1113 |
||
1066 | 1114 |
__ pusha(); // push registers |
1 | 1115 |
// (rip is already |
1116 |
// already pushed) |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1117 |
// debug(char* msg, int64_t pc, int64_t regs[]) |
1 | 1118 |
// We've popped the registers we'd saved (c_rarg3, c_rarg2 and flags), and |
1119 |
// pushed all the registers, so now the stack looks like: |
|
1120 |
// [tos + 0] 16 saved registers |
|
1121 |
// [tos + 16] return address |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1122 |
// * [tos + 17] error message (char*) |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1123 |
// * [tos + 18] object to verify (oop) |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1124 |
// * [tos + 19] saved rax - saved by caller and bashed |
5706 | 1125 |
// * [tos + 20] saved r10 (rscratch1) - saved by caller |
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1126 |
// * = popped on exit |
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1127 |
|
1066 | 1128 |
__ movptr(c_rarg0, Address(rsp, error_msg)); // pass address of error message |
1129 |
__ movptr(c_rarg1, Address(rsp, return_addr)); // pass return address |
|
1130 |
__ movq(c_rarg2, rsp); // pass address of regs on stack |
|
1131 |
__ mov(r12, rsp); // remember rsp |
|
1132 |
__ subptr(rsp, frame::arg_reg_save_area_bytes); // windows |
|
1133 |
__ andptr(rsp, -16); // align stack as required by ABI |
|
1 | 1134 |
BLOCK_COMMENT("call MacroAssembler::debug"); |
1066 | 1135 |
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); |
58103
689a80d20550
8230762: Change MacroAssembler::debug32/64 to use fatal instead of assert
chagedorn
parents:
57804
diff
changeset
|
1136 |
__ hlt(); |
1 | 1137 |
return start; |
1138 |
} |
|
1139 |
||
1140 |
// |
|
1141 |
// Verify that a register contains clean 32-bits positive value |
|
1142 |
// (high 32-bits are 0) so it could be used in 64-bits shifts. |
|
1143 |
// |
|
1144 |
// Input: |
|
1145 |
// Rint - 32-bits value |
|
1146 |
// Rtmp - scratch |
|
1147 |
// |
|
1148 |
void assert_clean_int(Register Rint, Register Rtmp) { |
|
1149 |
#ifdef ASSERT |
|
1150 |
Label L; |
|
1151 |
assert_different_registers(Rtmp, Rint); |
|
1152 |
__ movslq(Rtmp, Rint); |
|
1153 |
__ cmpq(Rtmp, Rint); |
|
371
1aacedc9db7c
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
360
diff
changeset
|
1154 |
__ jcc(Assembler::equal, L); |
1 | 1155 |
__ stop("high 32-bits of int value are not 0"); |
1156 |
__ bind(L); |
|
1157 |
#endif |
|
1158 |
} |
|
1159 |
||
1160 |
// Generate overlap test for array copy stubs |
|
1161 |
// |
|
1162 |
// Input: |
|
1163 |
// c_rarg0 - from |
|
1164 |
// c_rarg1 - to |
|
1165 |
// c_rarg2 - element count |
|
1166 |
// |
|
1167 |
// Output: |
|
1168 |
// rax - &from[element count - 1] |
|
1169 |
// |
|
1170 |
void array_overlap_test(address no_overlap_target, Address::ScaleFactor sf) { |
|
1171 |
assert(no_overlap_target != NULL, "must be generated"); |
|
1172 |
array_overlap_test(no_overlap_target, NULL, sf); |
|
1173 |
} |
|
1174 |
void array_overlap_test(Label& L_no_overlap, Address::ScaleFactor sf) { |
|
1175 |
array_overlap_test(NULL, &L_no_overlap, sf); |
|
1176 |
} |
|
1177 |
void array_overlap_test(address no_overlap_target, Label* NOLp, Address::ScaleFactor sf) { |
|
1178 |
const Register from = c_rarg0; |
|
1179 |
const Register to = c_rarg1; |
|
1180 |
const Register count = c_rarg2; |
|
1181 |
const Register end_from = rax; |
|
1182 |
||
1066 | 1183 |
__ cmpptr(to, from); |
1184 |
__ lea(end_from, Address(from, count, sf, 0)); |
|
1 | 1185 |
if (NOLp == NULL) { |
1186 |
ExternalAddress no_overlap(no_overlap_target); |
|
1187 |
__ jump_cc(Assembler::belowEqual, no_overlap); |
|
1066 | 1188 |
__ cmpptr(to, end_from); |
1 | 1189 |
__ jump_cc(Assembler::aboveEqual, no_overlap); |
1190 |
} else { |
|
1191 |
__ jcc(Assembler::belowEqual, (*NOLp)); |
|
1066 | 1192 |
__ cmpptr(to, end_from); |
1 | 1193 |
__ jcc(Assembler::aboveEqual, (*NOLp)); |
1194 |
} |
|
1195 |
} |
|
1196 |
||
1197 |
// Shuffle first three arg regs on Windows into Linux/Solaris locations. |
|
1198 |
// |
|
1199 |
// Outputs: |
|
1200 |
// rdi - rcx |
|
1201 |
// rsi - rdx |
|
1202 |
// rdx - r8 |
|
1203 |
// rcx - r9 |
|
1204 |
// |
|
1205 |
// Registers r9 and r10 are used to save rdi and rsi on Windows, which latter |
|
1206 |
// are non-volatile. r9 and r10 should not be used by the caller. |
|
1207 |
// |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1208 |
DEBUG_ONLY(bool regs_in_thread;) |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1209 |
|
1 | 1210 |
void setup_arg_regs(int nargs = 3) { |
1211 |
const Register saved_rdi = r9; |
|
1212 |
const Register saved_rsi = r10; |
|
1213 |
assert(nargs == 3 || nargs == 4, "else fix"); |
|
1214 |
#ifdef _WIN64 |
|
1215 |
assert(c_rarg0 == rcx && c_rarg1 == rdx && c_rarg2 == r8 && c_rarg3 == r9, |
|
1216 |
"unexpected argument registers"); |
|
1217 |
if (nargs >= 4) |
|
1066 | 1218 |
__ mov(rax, r9); // r9 is also saved_rdi |
1219 |
__ movptr(saved_rdi, rdi); |
|
1220 |
__ movptr(saved_rsi, rsi); |
|
1221 |
__ mov(rdi, rcx); // c_rarg0 |
|
1222 |
__ mov(rsi, rdx); // c_rarg1 |
|
1223 |
__ mov(rdx, r8); // c_rarg2 |
|
1 | 1224 |
if (nargs >= 4) |
1066 | 1225 |
__ mov(rcx, rax); // c_rarg3 (via rax) |
1 | 1226 |
#else |
1227 |
assert(c_rarg0 == rdi && c_rarg1 == rsi && c_rarg2 == rdx && c_rarg3 == rcx, |
|
1228 |
"unexpected argument registers"); |
|
1229 |
#endif |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1230 |
DEBUG_ONLY(regs_in_thread = false;) |
1 | 1231 |
} |
1232 |
||
1233 |
void restore_arg_regs() { |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1234 |
assert(!regs_in_thread, "wrong call to restore_arg_regs"); |
1 | 1235 |
const Register saved_rdi = r9; |
1236 |
const Register saved_rsi = r10; |
|
1237 |
#ifdef _WIN64 |
|
1066 | 1238 |
__ movptr(rdi, saved_rdi); |
1239 |
__ movptr(rsi, saved_rsi); |
|
1 | 1240 |
#endif |
1241 |
} |
|
1242 |
||
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1243 |
// This is used in places where r10 is a scratch register, and can |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1244 |
// be adapted if r9 is needed also. |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1245 |
void setup_arg_regs_using_thread() { |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1246 |
const Register saved_r15 = r9; |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1247 |
#ifdef _WIN64 |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1248 |
__ mov(saved_r15, r15); // r15 is callee saved and needs to be restored |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1249 |
__ get_thread(r15_thread); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1250 |
assert(c_rarg0 == rcx && c_rarg1 == rdx && c_rarg2 == r8 && c_rarg3 == r9, |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1251 |
"unexpected argument registers"); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1252 |
__ movptr(Address(r15_thread, in_bytes(JavaThread::windows_saved_rdi_offset())), rdi); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1253 |
__ movptr(Address(r15_thread, in_bytes(JavaThread::windows_saved_rsi_offset())), rsi); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1254 |
|
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1255 |
__ mov(rdi, rcx); // c_rarg0 |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1256 |
__ mov(rsi, rdx); // c_rarg1 |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1257 |
__ mov(rdx, r8); // c_rarg2 |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1258 |
#else |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1259 |
assert(c_rarg0 == rdi && c_rarg1 == rsi && c_rarg2 == rdx && c_rarg3 == rcx, |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1260 |
"unexpected argument registers"); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1261 |
#endif |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1262 |
DEBUG_ONLY(regs_in_thread = true;) |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1263 |
} |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1264 |
|
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1265 |
void restore_arg_regs_using_thread() { |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1266 |
assert(regs_in_thread, "wrong call to restore_arg_regs"); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1267 |
const Register saved_r15 = r9; |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1268 |
#ifdef _WIN64 |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1269 |
__ get_thread(r15_thread); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1270 |
__ movptr(rsi, Address(r15_thread, in_bytes(JavaThread::windows_saved_rsi_offset()))); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1271 |
__ movptr(rdi, Address(r15_thread, in_bytes(JavaThread::windows_saved_rdi_offset()))); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1272 |
__ mov(r15, saved_r15); // r15 is callee saved and needs to be restored |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1273 |
#endif |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1274 |
} |
1437 | 1275 |
|
1 | 1276 |
// Copy big chunks forward |
1277 |
// |
|
1278 |
// Inputs: |
|
1279 |
// end_from - source arrays end address |
|
1280 |
// end_to - destination array end address |
|
1281 |
// qword_count - 64-bits element count, negative |
|
1282 |
// to - scratch |
|
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1283 |
// L_copy_bytes - entry label |
1 | 1284 |
// L_copy_8_bytes - exit label |
1285 |
// |
|
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1286 |
void copy_bytes_forward(Register end_from, Register end_to, |
1 | 1287 |
Register qword_count, Register to, |
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1288 |
Label& L_copy_bytes, Label& L_copy_8_bytes) { |
1 | 1289 |
DEBUG_ONLY(__ stop("enter at entry label, not here")); |
1290 |
Label L_loop; |
|
5249 | 1291 |
__ align(OptoLoopAlignment); |
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1292 |
if (UseUnalignedLoadStores) { |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1293 |
Label L_end; |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1294 |
// Copy 64-bytes per iteration |
30624 | 1295 |
if (UseAVX > 2) { |
58462
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1296 |
Label L_loop_avx512, L_loop_avx2, L_32_byte_head, L_above_threshold, L_below_threshold; |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1297 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1298 |
__ BIND(L_copy_bytes); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1299 |
__ cmpptr(qword_count, (-1 * AVX3Threshold / 8)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1300 |
__ jccb(Assembler::less, L_above_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1301 |
__ jmpb(L_below_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1302 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1303 |
__ bind(L_loop_avx512); |
32727
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
1304 |
__ evmovdqul(xmm0, Address(end_from, qword_count, Address::times_8, -56), Assembler::AVX_512bit); |
320855c2baef
8132160: support for AVX 512 call frames and stack management
mcberg
parents:
32596
diff
changeset
|
1305 |
__ evmovdqul(Address(end_to, qword_count, Address::times_8, -56), xmm0, Assembler::AVX_512bit); |
58462
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1306 |
__ bind(L_above_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1307 |
__ addptr(qword_count, 8); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1308 |
__ jcc(Assembler::lessEqual, L_loop_avx512); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1309 |
__ jmpb(L_32_byte_head); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1310 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1311 |
__ bind(L_loop_avx2); |
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1312 |
__ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1313 |
__ vmovdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1314 |
__ vmovdqu(xmm1, Address(end_from, qword_count, Address::times_8, -24)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1315 |
__ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm1); |
58462
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1316 |
__ bind(L_below_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1317 |
__ addptr(qword_count, 8); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1318 |
__ jcc(Assembler::lessEqual, L_loop_avx2); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1319 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1320 |
__ bind(L_32_byte_head); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1321 |
__ subptr(qword_count, 4); // sub(8) and add(4) |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1322 |
__ jccb(Assembler::greater, L_end); |
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1323 |
} else { |
58462
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1324 |
__ BIND(L_loop); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1325 |
if (UseAVX == 2) { |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1326 |
__ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1327 |
__ vmovdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1328 |
__ vmovdqu(xmm1, Address(end_from, qword_count, Address::times_8, -24)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1329 |
__ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm1); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1330 |
} else { |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1331 |
__ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1332 |
__ movdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1333 |
__ movdqu(xmm1, Address(end_from, qword_count, Address::times_8, -40)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1334 |
__ movdqu(Address(end_to, qword_count, Address::times_8, -40), xmm1); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1335 |
__ movdqu(xmm2, Address(end_from, qword_count, Address::times_8, -24)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1336 |
__ movdqu(Address(end_to, qword_count, Address::times_8, -24), xmm2); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1337 |
__ movdqu(xmm3, Address(end_from, qword_count, Address::times_8, - 8)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1338 |
__ movdqu(Address(end_to, qword_count, Address::times_8, - 8), xmm3); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1339 |
} |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1340 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1341 |
__ BIND(L_copy_bytes); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1342 |
__ addptr(qword_count, 8); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1343 |
__ jcc(Assembler::lessEqual, L_loop); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1344 |
__ subptr(qword_count, 4); // sub(8) and add(4) |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1345 |
__ jccb(Assembler::greater, L_end); |
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1346 |
} |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1347 |
// Copy trailing 32 bytes |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1348 |
if (UseAVX >= 2) { |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1349 |
__ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -24)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1350 |
__ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm0); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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|
1351 |
} else { |
f8ef87f6f07f
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changeset
|
1352 |
__ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -24)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1353 |
__ movdqu(Address(end_to, qword_count, Address::times_8, -24), xmm0); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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changeset
|
1354 |
__ movdqu(xmm1, Address(end_from, qword_count, Address::times_8, - 8)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1355 |
__ movdqu(Address(end_to, qword_count, Address::times_8, - 8), xmm1); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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changeset
|
1356 |
} |
f8ef87f6f07f
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diff
changeset
|
1357 |
__ addptr(qword_count, 4); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1358 |
__ BIND(L_end); |
16624
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8011102: Clear AVX registers after return from JNI call
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diff
changeset
|
1359 |
if (UseAVX >= 2) { |
9dbd4b210bf9
8011102: Clear AVX registers after return from JNI call
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parents:
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diff
changeset
|
1360 |
// clean upper bits of YMM registers |
30299 | 1361 |
__ vpxor(xmm0, xmm0); |
1362 |
__ vpxor(xmm1, xmm1); |
|
16624
9dbd4b210bf9
8011102: Clear AVX registers after return from JNI call
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diff
changeset
|
1363 |
} |
1437 | 1364 |
} else { |
15115
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diff
changeset
|
1365 |
// Copy 32-bytes per iteration |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1366 |
__ BIND(L_loop); |
1437 | 1367 |
__ movq(to, Address(end_from, qword_count, Address::times_8, -24)); |
1368 |
__ movq(Address(end_to, qword_count, Address::times_8, -24), to); |
|
1369 |
__ movq(to, Address(end_from, qword_count, Address::times_8, -16)); |
|
1370 |
__ movq(Address(end_to, qword_count, Address::times_8, -16), to); |
|
1371 |
__ movq(to, Address(end_from, qword_count, Address::times_8, - 8)); |
|
1372 |
__ movq(Address(end_to, qword_count, Address::times_8, - 8), to); |
|
1373 |
__ movq(to, Address(end_from, qword_count, Address::times_8, - 0)); |
|
1374 |
__ movq(Address(end_to, qword_count, Address::times_8, - 0), to); |
|
15115
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changeset
|
1375 |
|
f8ef87f6f07f
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changeset
|
1376 |
__ BIND(L_copy_bytes); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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changeset
|
1377 |
__ addptr(qword_count, 4); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1378 |
__ jcc(Assembler::lessEqual, L_loop); |
1437 | 1379 |
} |
1066 | 1380 |
__ subptr(qword_count, 4); |
1 | 1381 |
__ jcc(Assembler::less, L_copy_8_bytes); // Copy trailing qwords |
1382 |
} |
|
1383 |
||
1384 |
// Copy big chunks backward |
|
1385 |
// |
|
1386 |
// Inputs: |
|
1387 |
// from - source arrays address |
|
1388 |
// dest - destination array address |
|
1389 |
// qword_count - 64-bits element count |
|
1390 |
// to - scratch |
|
15115
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|
1391 |
// L_copy_bytes - entry label |
1 | 1392 |
// L_copy_8_bytes - exit label |
1393 |
// |
|
15115
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changeset
|
1394 |
void copy_bytes_backward(Register from, Register dest, |
1 | 1395 |
Register qword_count, Register to, |
15115
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changeset
|
1396 |
Label& L_copy_bytes, Label& L_copy_8_bytes) { |
1 | 1397 |
DEBUG_ONLY(__ stop("enter at entry label, not here")); |
1398 |
Label L_loop; |
|
5249 | 1399 |
__ align(OptoLoopAlignment); |
15115
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changeset
|
1400 |
if (UseUnalignedLoadStores) { |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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parents:
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diff
changeset
|
1401 |
Label L_end; |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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diff
changeset
|
1402 |
// Copy 64-bytes per iteration |
30624 | 1403 |
if (UseAVX > 2) { |
58462
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changeset
|
1404 |
Label L_loop_avx512, L_loop_avx2, L_32_byte_head, L_above_threshold, L_below_threshold; |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1405 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1406 |
__ BIND(L_copy_bytes); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1407 |
__ cmpptr(qword_count, (AVX3Threshold / 8)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1408 |
__ jccb(Assembler::greater, L_above_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1409 |
__ jmpb(L_below_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1410 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1411 |
__ BIND(L_loop_avx512); |
34203 | 1412 |
__ evmovdqul(xmm0, Address(from, qword_count, Address::times_8, 0), Assembler::AVX_512bit); |
1413 |
__ evmovdqul(Address(dest, qword_count, Address::times_8, 0), xmm0, Assembler::AVX_512bit); |
|
58462
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changeset
|
1414 |
__ bind(L_above_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1415 |
__ subptr(qword_count, 8); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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parents:
58103
diff
changeset
|
1416 |
__ jcc(Assembler::greaterEqual, L_loop_avx512); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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changeset
|
1417 |
__ jmpb(L_32_byte_head); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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changeset
|
1418 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1419 |
__ bind(L_loop_avx2); |
15115
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changeset
|
1420 |
__ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 32)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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changeset
|
1421 |
__ vmovdqu(Address(dest, qword_count, Address::times_8, 32), xmm0); |
58462
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1422 |
__ vmovdqu(xmm1, Address(from, qword_count, Address::times_8, 0)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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diff
changeset
|
1423 |
__ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm1); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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changeset
|
1424 |
__ bind(L_below_threshold); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
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diff
changeset
|
1425 |
__ subptr(qword_count, 8); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1426 |
__ jcc(Assembler::greaterEqual, L_loop_avx2); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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changeset
|
1427 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1428 |
__ bind(L_32_byte_head); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1429 |
__ addptr(qword_count, 4); // add(8) and sub(4) |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1430 |
__ jccb(Assembler::less, L_end); |
15115
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parents:
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changeset
|
1431 |
} else { |
58462
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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changeset
|
1432 |
__ BIND(L_loop); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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changeset
|
1433 |
if (UseAVX == 2) { |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1434 |
__ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 32)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1435 |
__ vmovdqu(Address(dest, qword_count, Address::times_8, 32), xmm0); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1436 |
__ vmovdqu(xmm1, Address(from, qword_count, Address::times_8, 0)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1437 |
__ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm1); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1438 |
} else { |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1439 |
__ movdqu(xmm0, Address(from, qword_count, Address::times_8, 48)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1440 |
__ movdqu(Address(dest, qword_count, Address::times_8, 48), xmm0); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1441 |
__ movdqu(xmm1, Address(from, qword_count, Address::times_8, 32)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1442 |
__ movdqu(Address(dest, qword_count, Address::times_8, 32), xmm1); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1443 |
__ movdqu(xmm2, Address(from, qword_count, Address::times_8, 16)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1444 |
__ movdqu(Address(dest, qword_count, Address::times_8, 16), xmm2); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1445 |
__ movdqu(xmm3, Address(from, qword_count, Address::times_8, 0)); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1446 |
__ movdqu(Address(dest, qword_count, Address::times_8, 0), xmm3); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
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diff
changeset
|
1447 |
} |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1448 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1449 |
__ BIND(L_copy_bytes); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1450 |
__ subptr(qword_count, 8); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1451 |
__ jcc(Assembler::greaterEqual, L_loop); |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
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diff
changeset
|
1452 |
|
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1453 |
__ addptr(qword_count, 4); // add(8) and sub(4) |
c6f1226cfb72
8221092: UseAVX=3 has performance degredation on Skylake (X7) processors
vdeshpande
parents:
58103
diff
changeset
|
1454 |
__ jccb(Assembler::less, L_end); |
15115
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parents:
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changeset
|
1455 |
} |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
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parents:
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diff
changeset
|
1456 |
// Copy trailing 32 bytes |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1457 |
if (UseAVX >= 2) { |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1458 |
__ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 0)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1459 |
__ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm0); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1460 |
} else { |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1461 |
__ movdqu(xmm0, Address(from, qword_count, Address::times_8, 16)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1462 |
__ movdqu(Address(dest, qword_count, Address::times_8, 16), xmm0); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1463 |
__ movdqu(xmm1, Address(from, qword_count, Address::times_8, 0)); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1464 |
__ movdqu(Address(dest, qword_count, Address::times_8, 0), xmm1); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1465 |
} |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1466 |
__ subptr(qword_count, 4); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1467 |
__ BIND(L_end); |
16624
9dbd4b210bf9
8011102: Clear AVX registers after return from JNI call
kvn
parents:
15115
diff
changeset
|
1468 |
if (UseAVX >= 2) { |
9dbd4b210bf9
8011102: Clear AVX registers after return from JNI call
kvn
parents:
15115
diff
changeset
|
1469 |
// clean upper bits of YMM registers |
30299 | 1470 |
__ vpxor(xmm0, xmm0); |
1471 |
__ vpxor(xmm1, xmm1); |
|
16624
9dbd4b210bf9
8011102: Clear AVX registers after return from JNI call
kvn
parents:
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diff
changeset
|
1472 |
} |
1437 | 1473 |
} else { |
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
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diff
changeset
|
1474 |
// Copy 32-bytes per iteration |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1475 |
__ BIND(L_loop); |
1437 | 1476 |
__ movq(to, Address(from, qword_count, Address::times_8, 24)); |
1477 |
__ movq(Address(dest, qword_count, Address::times_8, 24), to); |
|
1478 |
__ movq(to, Address(from, qword_count, Address::times_8, 16)); |
|
1479 |
__ movq(Address(dest, qword_count, Address::times_8, 16), to); |
|
1480 |
__ movq(to, Address(from, qword_count, Address::times_8, 8)); |
|
1481 |
__ movq(Address(dest, qword_count, Address::times_8, 8), to); |
|
1482 |
__ movq(to, Address(from, qword_count, Address::times_8, 0)); |
|
1483 |
__ movq(Address(dest, qword_count, Address::times_8, 0), to); |
|
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1484 |
|
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1485 |
__ BIND(L_copy_bytes); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1486 |
__ subptr(qword_count, 4); |
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1487 |
__ jcc(Assembler::greaterEqual, L_loop); |
1437 | 1488 |
} |
1066 | 1489 |
__ addptr(qword_count, 4); |
1 | 1490 |
__ jcc(Assembler::greater, L_copy_8_bytes); // Copy trailing qwords |
1491 |
} |
|
1492 |
||
1493 |
// Arguments: |
|
1494 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1495 |
// ignored |
|
1496 |
// name - stub name string |
|
1497 |
// |
|
1498 |
// Inputs: |
|
1499 |
// c_rarg0 - source array address |
|
1500 |
// c_rarg1 - destination array address |
|
1501 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1502 |
// |
|
1503 |
// If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, |
|
1504 |
// we let the hardware handle it. The one to eight bytes within words, |
|
1505 |
// dwords or qwords that span cache line boundaries will still be loaded |
|
1506 |
// and stored atomically. |
|
1507 |
// |
|
1508 |
// Side Effects: |
|
1509 |
// disjoint_byte_copy_entry is set to the no-overlap entry point |
|
1510 |
// used by generate_conjoint_byte_copy(). |
|
1511 |
// |
|
8487
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7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1512 |
address generate_disjoint_byte_copy(bool aligned, address* entry, const char *name) { |
1 | 1513 |
__ align(CodeEntryAlignment); |
1514 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1515 |
address start = __ pc(); |
|
1516 |
||
15115
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8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1517 |
Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes, L_copy_2_bytes; |
1 | 1518 |
Label L_copy_byte, L_exit; |
1519 |
const Register from = rdi; // source array address |
|
1520 |
const Register to = rsi; // destination array address |
|
1521 |
const Register count = rdx; // elements count |
|
1522 |
const Register byte_count = rcx; |
|
1523 |
const Register qword_count = count; |
|
1524 |
const Register end_from = from; // source array end address |
|
1525 |
const Register end_to = to; // destination array end address |
|
1526 |
// End pointers are inclusive, and if count is not zero they point |
|
1527 |
// to the last unit copied: end_to[0] := end_from[0] |
|
1528 |
||
1529 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1530 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
1531 |
||
8487
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7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1532 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1533 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1534 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1535 |
BLOCK_COMMENT("Entry:"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
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diff
changeset
|
1536 |
} |
1 | 1537 |
|
1538 |
setup_arg_regs(); // from => rdi, to => rsi, count => rdx |
|
1539 |
// r9 and r10 may be used to save non-volatile registers |
|
1540 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1541 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1542 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1543 |
UnsafeCopyMemoryMark ucmm(this, !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1544 |
// 'from', 'to' and 'count' are now valid |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1545 |
__ movptr(byte_count, count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1546 |
__ shrptr(count, 3); // count => qword_count |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1547 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1548 |
// Copy from low to high addresses. Use 'to' as scratch. |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1549 |
__ lea(end_from, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1550 |
__ lea(end_to, Address(to, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1551 |
__ negptr(qword_count); // make the count negative |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1552 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1553 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1554 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1555 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1556 |
__ movq(rax, Address(end_from, qword_count, Address::times_8, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1557 |
__ movq(Address(end_to, qword_count, Address::times_8, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1558 |
__ increment(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1559 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1560 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1561 |
// Check for and copy trailing dword |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1562 |
__ BIND(L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1563 |
__ testl(byte_count, 4); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1564 |
__ jccb(Assembler::zero, L_copy_2_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1565 |
__ movl(rax, Address(end_from, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1566 |
__ movl(Address(end_to, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1567 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1568 |
__ addptr(end_from, 4); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1569 |
__ addptr(end_to, 4); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1570 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1571 |
// Check for and copy trailing word |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1572 |
__ BIND(L_copy_2_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1573 |
__ testl(byte_count, 2); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1574 |
__ jccb(Assembler::zero, L_copy_byte); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1575 |
__ movw(rax, Address(end_from, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1576 |
__ movw(Address(end_to, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1577 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1578 |
__ addptr(end_from, 2); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1579 |
__ addptr(end_to, 2); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1580 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1581 |
// Check for and copy trailing byte |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1582 |
__ BIND(L_copy_byte); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1583 |
__ testl(byte_count, 1); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1584 |
__ jccb(Assembler::zero, L_exit); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1585 |
__ movb(rax, Address(end_from, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1586 |
__ movb(Address(end_to, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1587 |
} |
1 | 1588 |
__ BIND(L_exit); |
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1589 |
address ucme_exit_pc = __ pc(); |
1 | 1590 |
restore_arg_regs(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
1591 |
inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 1592 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
1593 |
__ vzeroupper(); |
1 | 1594 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1595 |
__ ret(0); |
|
1596 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1597 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1598 |
UnsafeCopyMemoryMark ucmm(this, !aligned, false, ucme_exit_pc); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1599 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1600 |
copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1601 |
__ jmp(L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1602 |
} |
1 | 1603 |
return start; |
1604 |
} |
|
1605 |
||
1606 |
// Arguments: |
|
1607 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1608 |
// ignored |
|
1609 |
// name - stub name string |
|
1610 |
// |
|
1611 |
// Inputs: |
|
1612 |
// c_rarg0 - source array address |
|
1613 |
// c_rarg1 - destination array address |
|
1614 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1615 |
// |
|
1616 |
// If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries, |
|
1617 |
// we let the hardware handle it. The one to eight bytes within words, |
|
1618 |
// dwords or qwords that span cache line boundaries will still be loaded |
|
1619 |
// and stored atomically. |
|
1620 |
// |
|
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1621 |
address generate_conjoint_byte_copy(bool aligned, address nooverlap_target, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1622 |
address* entry, const char *name) { |
1 | 1623 |
__ align(CodeEntryAlignment); |
1624 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1625 |
address start = __ pc(); |
|
1626 |
||
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1627 |
Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes, L_copy_2_bytes; |
1 | 1628 |
const Register from = rdi; // source array address |
1629 |
const Register to = rsi; // destination array address |
|
1630 |
const Register count = rdx; // elements count |
|
1631 |
const Register byte_count = rcx; |
|
1632 |
const Register qword_count = count; |
|
1633 |
||
1634 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1635 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
1636 |
||
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1637 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1638 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1639 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1640 |
BLOCK_COMMENT("Entry:"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1641 |
} |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1642 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1643 |
array_overlap_test(nooverlap_target, Address::times_1); |
1 | 1644 |
setup_arg_regs(); // from => rdi, to => rsi, count => rdx |
1645 |
// r9 and r10 may be used to save non-volatile registers |
|
1646 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1647 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1648 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1649 |
UnsafeCopyMemoryMark ucmm(this, !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1650 |
// 'from', 'to' and 'count' are now valid |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1651 |
__ movptr(byte_count, count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1652 |
__ shrptr(count, 3); // count => qword_count |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1653 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1654 |
// Copy from high to low addresses. |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1655 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1656 |
// Check for and copy trailing byte |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1657 |
__ testl(byte_count, 1); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1658 |
__ jcc(Assembler::zero, L_copy_2_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1659 |
__ movb(rax, Address(from, byte_count, Address::times_1, -1)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1660 |
__ movb(Address(to, byte_count, Address::times_1, -1), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1661 |
__ decrement(byte_count); // Adjust for possible trailing word |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1662 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1663 |
// Check for and copy trailing word |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1664 |
__ BIND(L_copy_2_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1665 |
__ testl(byte_count, 2); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1666 |
__ jcc(Assembler::zero, L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1667 |
__ movw(rax, Address(from, byte_count, Address::times_1, -2)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1668 |
__ movw(Address(to, byte_count, Address::times_1, -2), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1669 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1670 |
// Check for and copy trailing dword |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1671 |
__ BIND(L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1672 |
__ testl(byte_count, 4); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1673 |
__ jcc(Assembler::zero, L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1674 |
__ movl(rax, Address(from, qword_count, Address::times_8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1675 |
__ movl(Address(to, qword_count, Address::times_8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1676 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1677 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1678 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1679 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1680 |
__ movq(rax, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1681 |
__ movq(Address(to, qword_count, Address::times_8, -8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1682 |
__ decrement(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1683 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1684 |
} |
1 | 1685 |
restore_arg_regs(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
1686 |
inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 1687 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
1688 |
__ vzeroupper(); |
1 | 1689 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1690 |
__ ret(0); |
|
1691 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1692 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1693 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1694 |
UnsafeCopyMemoryMark ucmm(this, !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1695 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1696 |
copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1697 |
} |
1 | 1698 |
restore_arg_regs(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
1699 |
inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 1700 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
1701 |
__ vzeroupper(); |
1 | 1702 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1703 |
__ ret(0); |
|
1704 |
||
1705 |
return start; |
|
1706 |
} |
|
1707 |
||
1708 |
// Arguments: |
|
1709 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1710 |
// ignored |
|
1711 |
// name - stub name string |
|
1712 |
// |
|
1713 |
// Inputs: |
|
1714 |
// c_rarg0 - source array address |
|
1715 |
// c_rarg1 - destination array address |
|
1716 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1717 |
// |
|
1718 |
// If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we |
|
1719 |
// let the hardware handle it. The two or four words within dwords |
|
1720 |
// or qwords that span cache line boundaries will still be loaded |
|
1721 |
// and stored atomically. |
|
1722 |
// |
|
1723 |
// Side Effects: |
|
1724 |
// disjoint_short_copy_entry is set to the no-overlap entry point |
|
1725 |
// used by generate_conjoint_short_copy(). |
|
1726 |
// |
|
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1727 |
address generate_disjoint_short_copy(bool aligned, address *entry, const char *name) { |
1 | 1728 |
__ align(CodeEntryAlignment); |
1729 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1730 |
address start = __ pc(); |
|
1731 |
||
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1732 |
Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes,L_copy_2_bytes,L_exit; |
1 | 1733 |
const Register from = rdi; // source array address |
1734 |
const Register to = rsi; // destination array address |
|
1735 |
const Register count = rdx; // elements count |
|
1736 |
const Register word_count = rcx; |
|
1737 |
const Register qword_count = count; |
|
1738 |
const Register end_from = from; // source array end address |
|
1739 |
const Register end_to = to; // destination array end address |
|
1740 |
// End pointers are inclusive, and if count is not zero they point |
|
1741 |
// to the last unit copied: end_to[0] := end_from[0] |
|
1742 |
||
1743 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1744 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
1745 |
||
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1746 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1747 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1748 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1749 |
BLOCK_COMMENT("Entry:"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
1750 |
} |
1 | 1751 |
|
1752 |
setup_arg_regs(); // from => rdi, to => rsi, count => rdx |
|
1753 |
// r9 and r10 may be used to save non-volatile registers |
|
1754 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1755 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1756 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1757 |
UnsafeCopyMemoryMark ucmm(this, !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1758 |
// 'from', 'to' and 'count' are now valid |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1759 |
__ movptr(word_count, count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1760 |
__ shrptr(count, 2); // count => qword_count |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1761 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1762 |
// Copy from low to high addresses. Use 'to' as scratch. |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1763 |
__ lea(end_from, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1764 |
__ lea(end_to, Address(to, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1765 |
__ negptr(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1766 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1767 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1768 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1769 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1770 |
__ movq(rax, Address(end_from, qword_count, Address::times_8, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1771 |
__ movq(Address(end_to, qword_count, Address::times_8, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1772 |
__ increment(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1773 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1774 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1775 |
// Original 'dest' is trashed, so we can't use it as a |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1776 |
// base register for a possible trailing word copy |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1777 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1778 |
// Check for and copy trailing dword |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1779 |
__ BIND(L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1780 |
__ testl(word_count, 2); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1781 |
__ jccb(Assembler::zero, L_copy_2_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1782 |
__ movl(rax, Address(end_from, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1783 |
__ movl(Address(end_to, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1784 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1785 |
__ addptr(end_from, 4); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1786 |
__ addptr(end_to, 4); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1787 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1788 |
// Check for and copy trailing word |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1789 |
__ BIND(L_copy_2_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1790 |
__ testl(word_count, 1); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1791 |
__ jccb(Assembler::zero, L_exit); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1792 |
__ movw(rax, Address(end_from, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1793 |
__ movw(Address(end_to, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1794 |
} |
1 | 1795 |
__ BIND(L_exit); |
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1796 |
address ucme_exit_pc = __ pc(); |
1 | 1797 |
restore_arg_regs(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
1798 |
inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 1799 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
1800 |
__ vzeroupper(); |
1 | 1801 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1802 |
__ ret(0); |
|
1803 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1804 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1805 |
UnsafeCopyMemoryMark ucmm(this, !aligned, false, ucme_exit_pc); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1806 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1807 |
copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1808 |
__ jmp(L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1809 |
} |
1 | 1810 |
|
1811 |
return start; |
|
1812 |
} |
|
1813 |
||
6433 | 1814 |
address generate_fill(BasicType t, bool aligned, const char *name) { |
1815 |
__ align(CodeEntryAlignment); |
|
1816 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1817 |
address start = __ pc(); |
|
1818 |
||
1819 |
BLOCK_COMMENT("Entry:"); |
|
1820 |
||
1821 |
const Register to = c_rarg0; // source array address |
|
1822 |
const Register value = c_rarg1; // value |
|
1823 |
const Register count = c_rarg2; // elements count |
|
1824 |
||
1825 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1826 |
||
1827 |
__ generate_fill(t, aligned, to, value, count, rax, xmm0); |
|
1828 |
||
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|
1829 |
__ vzeroupper(); |
6433 | 1830 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1831 |
__ ret(0); |
|
1832 |
return start; |
|
1833 |
} |
|
1834 |
||
1 | 1835 |
// Arguments: |
1836 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1837 |
// ignored |
|
1838 |
// name - stub name string |
|
1839 |
// |
|
1840 |
// Inputs: |
|
1841 |
// c_rarg0 - source array address |
|
1842 |
// c_rarg1 - destination array address |
|
1843 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1844 |
// |
|
1845 |
// If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we |
|
1846 |
// let the hardware handle it. The two or four words within dwords |
|
1847 |
// or qwords that span cache line boundaries will still be loaded |
|
1848 |
// and stored atomically. |
|
1849 |
// |
|
8487
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|
1850 |
address generate_conjoint_short_copy(bool aligned, address nooverlap_target, |
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|
1851 |
address *entry, const char *name) { |
1 | 1852 |
__ align(CodeEntryAlignment); |
1853 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1854 |
address start = __ pc(); |
|
1855 |
||
15115
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|
1856 |
Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes; |
1 | 1857 |
const Register from = rdi; // source array address |
1858 |
const Register to = rsi; // destination array address |
|
1859 |
const Register count = rdx; // elements count |
|
1860 |
const Register word_count = rcx; |
|
1861 |
const Register qword_count = count; |
|
1862 |
||
1863 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1864 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
1865 |
||
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|
1866 |
if (entry != NULL) { |
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changeset
|
1867 |
*entry = __ pc(); |
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changeset
|
1868 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
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changeset
|
1869 |
BLOCK_COMMENT("Entry:"); |
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|
1870 |
} |
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changeset
|
1871 |
|
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changeset
|
1872 |
array_overlap_test(nooverlap_target, Address::times_2); |
1 | 1873 |
setup_arg_regs(); // from => rdi, to => rsi, count => rdx |
1874 |
// r9 and r10 may be used to save non-volatile registers |
|
1875 |
||
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|
1876 |
{ |
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changeset
|
1877 |
// UnsafeCopyMemory page error: continue after ucm |
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|
1878 |
UnsafeCopyMemoryMark ucmm(this, !aligned, true); |
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changeset
|
1879 |
// 'from', 'to' and 'count' are now valid |
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|
1880 |
__ movptr(word_count, count); |
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|
1881 |
__ shrptr(count, 2); // count => qword_count |
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changeset
|
1882 |
|
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|
1883 |
// Copy from high to low addresses. Use 'to' as scratch. |
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|
1884 |
|
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|
1885 |
// Check for and copy trailing word |
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|
1886 |
__ testl(word_count, 1); |
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|
1887 |
__ jccb(Assembler::zero, L_copy_4_bytes); |
3f3dc00a69a5
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changeset
|
1888 |
__ movw(rax, Address(from, word_count, Address::times_2, -2)); |
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changeset
|
1889 |
__ movw(Address(to, word_count, Address::times_2, -2), rax); |
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changeset
|
1890 |
|
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|
1891 |
// Check for and copy trailing dword |
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|
1892 |
__ BIND(L_copy_4_bytes); |
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|
1893 |
__ testl(word_count, 2); |
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|
1894 |
__ jcc(Assembler::zero, L_copy_bytes); |
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changeset
|
1895 |
__ movl(rax, Address(from, qword_count, Address::times_8)); |
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|
1896 |
__ movl(Address(to, qword_count, Address::times_8), rax); |
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changeset
|
1897 |
__ jmp(L_copy_bytes); |
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changeset
|
1898 |
|
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changeset
|
1899 |
// Copy trailing qwords |
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changeset
|
1900 |
__ BIND(L_copy_8_bytes); |
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changeset
|
1901 |
__ movq(rax, Address(from, qword_count, Address::times_8, -8)); |
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changeset
|
1902 |
__ movq(Address(to, qword_count, Address::times_8, -8), rax); |
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|
1903 |
__ decrement(qword_count); |
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changeset
|
1904 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
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8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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changeset
|
1905 |
} |
1 | 1906 |
restore_arg_regs(); |
11194
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7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
1907 |
inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 1908 |
__ xorptr(rax, rax); // return 0 |
46440
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vdeshpande
parents:
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diff
changeset
|
1909 |
__ vzeroupper(); |
1 | 1910 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1911 |
__ ret(0); |
|
1912 |
||
55490
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8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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changeset
|
1913 |
{ |
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changeset
|
1914 |
// UnsafeCopyMemory page error: continue after ucm |
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changeset
|
1915 |
UnsafeCopyMemoryMark ucmm(this, !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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parents:
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changeset
|
1916 |
// Copy in multi-bytes chunks |
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8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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changeset
|
1917 |
copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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changeset
|
1918 |
} |
1 | 1919 |
restore_arg_regs(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
1920 |
inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 1921 |
__ xorptr(rax, rax); // return 0 |
46440
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8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
1922 |
__ vzeroupper(); |
1 | 1923 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1924 |
__ ret(0); |
|
1925 |
||
1926 |
return start; |
|
1927 |
} |
|
1928 |
||
1929 |
// Arguments: |
|
1930 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
1931 |
// ignored |
|
360
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189
diff
changeset
|
1932 |
// is_oop - true => oop array, so generate store check code |
1 | 1933 |
// name - stub name string |
1934 |
// |
|
1935 |
// Inputs: |
|
1936 |
// c_rarg0 - source array address |
|
1937 |
// c_rarg1 - destination array address |
|
1938 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
1939 |
// |
|
1940 |
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let |
|
1941 |
// the hardware handle it. The two dwords within qwords that span |
|
1942 |
// cache line boundaries will still be loaded and stored atomicly. |
|
1943 |
// |
|
1944 |
// Side Effects: |
|
1945 |
// disjoint_int_copy_entry is set to the no-overlap entry point |
|
360
21d113ecbf6a
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changeset
|
1946 |
// used by generate_conjoint_int_oop_copy(). |
1 | 1947 |
// |
8498 | 1948 |
address generate_disjoint_int_oop_copy(bool aligned, bool is_oop, address* entry, |
1949 |
const char *name, bool dest_uninitialized = false) { |
|
1 | 1950 |
__ align(CodeEntryAlignment); |
1951 |
StubCodeMark mark(this, "StubRoutines", name); |
|
1952 |
address start = __ pc(); |
|
1953 |
||
15115
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8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
1954 |
Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes, L_exit; |
1 | 1955 |
const Register from = rdi; // source array address |
1956 |
const Register to = rsi; // destination array address |
|
1957 |
const Register count = rdx; // elements count |
|
1958 |
const Register dword_count = rcx; |
|
1959 |
const Register qword_count = count; |
|
1960 |
const Register end_from = from; // source array end address |
|
1961 |
const Register end_to = to; // destination array end address |
|
1962 |
// End pointers are inclusive, and if count is not zero they point |
|
1963 |
// to the last unit copied: end_to[0] := end_from[0] |
|
1964 |
||
1965 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
1966 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
1967 |
||
8487
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7020521: arraycopy stubs place prebarriers incorrectly
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diff
changeset
|
1968 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
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7431
diff
changeset
|
1969 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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7431
diff
changeset
|
1970 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
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diff
changeset
|
1971 |
BLOCK_COMMENT("Entry:"); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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189
diff
changeset
|
1972 |
} |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
1973 |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1974 |
setup_arg_regs_using_thread(); // from => rdi, to => rsi, count => rdx |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
1975 |
// r9 is used to save r15_thread |
49484
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eosterlund
parents:
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diff
changeset
|
1976 |
|
50728 | 1977 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_DISJOINT; |
49484
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eosterlund
parents:
49455
diff
changeset
|
1978 |
if (dest_uninitialized) { |
50728 | 1979 |
decorators |= IS_DEST_UNINITIALIZED; |
360
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diff
changeset
|
1980 |
} |
49484
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8198949: Modularize arraycopy stub routine GC barriers
eosterlund
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49455
diff
changeset
|
1981 |
if (aligned) { |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1982 |
decorators |= ARRAYCOPY_ALIGNED; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1983 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1984 |
|
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1985 |
BasicType type = is_oop ? T_OBJECT : T_INT; |
49754 | 1986 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
49484
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8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
1987 |
bs->arraycopy_prologue(_masm, decorators, type, from, to, count); |
360
21d113ecbf6a
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changeset
|
1988 |
|
55490
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8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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changeset
|
1989 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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changeset
|
1990 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
1991 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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parents:
54786
diff
changeset
|
1992 |
// 'from', 'to' and 'count' are now valid |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
1993 |
__ movptr(dword_count, count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
1994 |
__ shrptr(count, 1); // count => qword_count |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
1995 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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parents:
54786
diff
changeset
|
1996 |
// Copy from low to high addresses. Use 'to' as scratch. |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
1997 |
__ lea(end_from, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
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jcm
parents:
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changeset
|
1998 |
__ lea(end_to, Address(to, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
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parents:
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changeset
|
1999 |
__ negptr(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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parents:
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diff
changeset
|
2000 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2001 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2002 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2003 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2004 |
__ movq(rax, Address(end_from, qword_count, Address::times_8, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2005 |
__ movq(Address(end_to, qword_count, Address::times_8, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
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parents:
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changeset
|
2006 |
__ increment(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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changeset
|
2007 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2008 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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changeset
|
2009 |
// Check for and copy trailing dword |
3f3dc00a69a5
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changeset
|
2010 |
__ BIND(L_copy_4_bytes); |
3f3dc00a69a5
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parents:
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changeset
|
2011 |
__ testl(dword_count, 1); // Only byte test since the value is 0 or 1 |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2012 |
__ jccb(Assembler::zero, L_exit); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2013 |
__ movl(rax, Address(end_from, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2014 |
__ movl(Address(end_to, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2015 |
} |
1 | 2016 |
__ BIND(L_exit); |
55490
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8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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changeset
|
2017 |
address ucme_exit_pc = __ pc(); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2018 |
bs->arraycopy_epilogue(_masm, decorators, type, from, to, dword_count); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2019 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2020 |
inc_counter_np(SharedRuntime::_jint_array_copy_ctr); // Update counter after rscratch1 is free |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2021 |
__ vzeroupper(); |
1066 | 2022 |
__ xorptr(rax, rax); // return 0 |
1 | 2023 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2024 |
__ ret(0); |
|
2025 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2026 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2027 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, false, ucme_exit_pc); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2028 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2029 |
copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2030 |
__ jmp(L_copy_4_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
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diff
changeset
|
2031 |
} |
1 | 2032 |
|
2033 |
return start; |
|
2034 |
} |
|
2035 |
||
2036 |
// Arguments: |
|
2037 |
// aligned - true => Input and output aligned on a HeapWord == 8-byte boundary |
|
2038 |
// ignored |
|
360
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|
2039 |
// is_oop - true => oop array, so generate store check code |
1 | 2040 |
// name - stub name string |
2041 |
// |
|
2042 |
// Inputs: |
|
2043 |
// c_rarg0 - source array address |
|
2044 |
// c_rarg1 - destination array address |
|
2045 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
2046 |
// |
|
2047 |
// If 'from' and/or 'to' are aligned on 4-byte boundaries, we let |
|
2048 |
// the hardware handle it. The two dwords within qwords that span |
|
2049 |
// cache line boundaries will still be loaded and stored atomicly. |
|
2050 |
// |
|
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2051 |
address generate_conjoint_int_oop_copy(bool aligned, bool is_oop, address nooverlap_target, |
8498 | 2052 |
address *entry, const char *name, |
2053 |
bool dest_uninitialized = false) { |
|
1 | 2054 |
__ align(CodeEntryAlignment); |
2055 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2056 |
address start = __ pc(); |
|
2057 |
||
51756 | 2058 |
Label L_copy_bytes, L_copy_8_bytes, L_exit; |
1 | 2059 |
const Register from = rdi; // source array address |
2060 |
const Register to = rsi; // destination array address |
|
2061 |
const Register count = rdx; // elements count |
|
2062 |
const Register dword_count = rcx; |
|
2063 |
const Register qword_count = count; |
|
2064 |
||
2065 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2066 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
2067 |
||
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2068 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2069 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2070 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2071 |
BLOCK_COMMENT("Entry:"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2072 |
} |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2073 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2074 |
array_overlap_test(nooverlap_target, Address::times_4); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2075 |
setup_arg_regs_using_thread(); // from => rdi, to => rsi, count => rdx |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2076 |
// r9 is used to save r15_thread |
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2077 |
|
50728 | 2078 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY; |
49484
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8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2079 |
if (dest_uninitialized) { |
50728 | 2080 |
decorators |= IS_DEST_UNINITIALIZED; |
360
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parents:
189
diff
changeset
|
2081 |
} |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2082 |
if (aligned) { |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2083 |
decorators |= ARRAYCOPY_ALIGNED; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2084 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2085 |
|
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2086 |
BasicType type = is_oop ? T_OBJECT : T_INT; |
49754 | 2087 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2088 |
// no registers are destroyed by this call |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2089 |
bs->arraycopy_prologue(_masm, decorators, type, from, to, count); |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2090 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2091 |
assert_clean_int(count, rax); // Make sure 'count' is clean int. |
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2092 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2093 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2094 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2095 |
// 'from', 'to' and 'count' are now valid |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2096 |
__ movptr(dword_count, count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2097 |
__ shrptr(count, 1); // count => qword_count |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2098 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2099 |
// Copy from high to low addresses. Use 'to' as scratch. |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2100 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2101 |
// Check for and copy trailing dword |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2102 |
__ testl(dword_count, 1); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2103 |
__ jcc(Assembler::zero, L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2104 |
__ movl(rax, Address(from, dword_count, Address::times_4, -4)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2105 |
__ movl(Address(to, dword_count, Address::times_4, -4), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2106 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2107 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2108 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2109 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2110 |
__ movq(rax, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2111 |
__ movq(Address(to, qword_count, Address::times_8, -8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2112 |
__ decrement(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2113 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2114 |
} |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2115 |
if (is_oop) { |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2116 |
__ jmp(L_exit); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2117 |
} |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2118 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2119 |
inc_counter_np(SharedRuntime::_jint_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 2120 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2121 |
__ vzeroupper(); |
1 | 2122 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2123 |
__ ret(0); |
|
2124 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2125 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2126 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2127 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2128 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2129 |
copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2130 |
} |
1 | 2131 |
|
17622
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2132 |
__ BIND(L_exit); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2133 |
bs->arraycopy_epilogue(_masm, decorators, type, from, to, dword_count); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2134 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2135 |
inc_counter_np(SharedRuntime::_jint_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 2136 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2137 |
__ vzeroupper(); |
1 | 2138 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2139 |
__ ret(0); |
|
2140 |
||
2141 |
return start; |
|
2142 |
} |
|
2143 |
||
2144 |
// Arguments: |
|
2145 |
// aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes |
|
2146 |
// ignored |
|
2147 |
// is_oop - true => oop array, so generate store check code |
|
2148 |
// name - stub name string |
|
2149 |
// |
|
2150 |
// Inputs: |
|
2151 |
// c_rarg0 - source array address |
|
2152 |
// c_rarg1 - destination array address |
|
2153 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
2154 |
// |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2155 |
// Side Effects: |
1 | 2156 |
// disjoint_oop_copy_entry or disjoint_long_copy_entry is set to the |
2157 |
// no-overlap entry point used by generate_conjoint_long_oop_copy(). |
|
2158 |
// |
|
8498 | 2159 |
address generate_disjoint_long_oop_copy(bool aligned, bool is_oop, address *entry, |
2160 |
const char *name, bool dest_uninitialized = false) { |
|
1 | 2161 |
__ align(CodeEntryAlignment); |
2162 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2163 |
address start = __ pc(); |
|
2164 |
||
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
2165 |
Label L_copy_bytes, L_copy_8_bytes, L_exit; |
1 | 2166 |
const Register from = rdi; // source array address |
2167 |
const Register to = rsi; // destination array address |
|
2168 |
const Register qword_count = rdx; // elements count |
|
2169 |
const Register end_from = from; // source array end address |
|
2170 |
const Register end_to = rcx; // destination array end address |
|
17622
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2171 |
const Register saved_count = r11; |
1 | 2172 |
// End pointers are inclusive, and if count is not zero they point |
2173 |
// to the last unit copied: end_to[0] := end_from[0] |
|
2174 |
||
2175 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2176 |
// Save no-overlap entry point for generate_conjoint_long_oop_copy() |
|
2177 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
2178 |
||
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2179 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2180 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2181 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2182 |
BLOCK_COMMENT("Entry:"); |
1 | 2183 |
} |
2184 |
||
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2185 |
setup_arg_regs_using_thread(); // from => rdi, to => rsi, count => rdx |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2186 |
// r9 is used to save r15_thread |
1 | 2187 |
// 'from', 'to' and 'qword_count' are now valid |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2188 |
|
50728 | 2189 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_DISJOINT; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2190 |
if (dest_uninitialized) { |
50728 | 2191 |
decorators |= IS_DEST_UNINITIALIZED; |
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2192 |
} |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2193 |
if (aligned) { |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2194 |
decorators |= ARRAYCOPY_ALIGNED; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2195 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2196 |
|
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2197 |
BasicType type = is_oop ? T_OBJECT : T_LONG; |
49754 | 2198 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2199 |
bs->arraycopy_prologue(_masm, decorators, type, from, to, qword_count); |
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2200 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2201 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2202 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2203 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2204 |
// Copy from low to high addresses. Use 'to' as scratch. |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2205 |
__ lea(end_from, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2206 |
__ lea(end_to, Address(to, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2207 |
__ negptr(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2208 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2209 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2210 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2211 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2212 |
__ movq(rax, Address(end_from, qword_count, Address::times_8, 8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2213 |
__ movq(Address(end_to, qword_count, Address::times_8, 8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2214 |
__ increment(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2215 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2216 |
} |
1 | 2217 |
if (is_oop) { |
2218 |
__ jmp(L_exit); |
|
2219 |
} else { |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2220 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2221 |
inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 2222 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2223 |
__ vzeroupper(); |
1 | 2224 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2225 |
__ ret(0); |
|
2226 |
} |
|
2227 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2228 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2229 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2230 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2231 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2232 |
copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2233 |
} |
1 | 2234 |
|
2235 |
__ BIND(L_exit); |
|
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2236 |
bs->arraycopy_epilogue(_masm, decorators, type, from, to, qword_count); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2237 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2238 |
if (is_oop) { |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2239 |
inc_counter_np(SharedRuntime::_oop_array_copy_ctr); // Update counter after rscratch1 is free |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2240 |
} else { |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2241 |
inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2242 |
} |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2243 |
__ vzeroupper(); |
1066 | 2244 |
__ xorptr(rax, rax); // return 0 |
1 | 2245 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2246 |
__ ret(0); |
|
2247 |
||
2248 |
return start; |
|
2249 |
} |
|
2250 |
||
2251 |
// Arguments: |
|
2252 |
// aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes |
|
2253 |
// ignored |
|
2254 |
// is_oop - true => oop array, so generate store check code |
|
2255 |
// name - stub name string |
|
2256 |
// |
|
2257 |
// Inputs: |
|
2258 |
// c_rarg0 - source array address |
|
2259 |
// c_rarg1 - destination array address |
|
2260 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
2261 |
// |
|
8498 | 2262 |
address generate_conjoint_long_oop_copy(bool aligned, bool is_oop, |
2263 |
address nooverlap_target, address *entry, |
|
2264 |
const char *name, bool dest_uninitialized = false) { |
|
1 | 2265 |
__ align(CodeEntryAlignment); |
2266 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2267 |
address start = __ pc(); |
|
2268 |
||
15115
f8ef87f6f07f
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
14834
diff
changeset
|
2269 |
Label L_copy_bytes, L_copy_8_bytes, L_exit; |
1 | 2270 |
const Register from = rdi; // source array address |
2271 |
const Register to = rsi; // destination array address |
|
2272 |
const Register qword_count = rdx; // elements count |
|
2273 |
const Register saved_count = rcx; |
|
2274 |
||
2275 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2276 |
assert_clean_int(c_rarg2, rax); // Make sure 'count' is clean int. |
|
2277 |
||
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2278 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2279 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2280 |
// caller can pass a 64-bit byte count here (from Unsafe.copyMemory) |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2281 |
BLOCK_COMMENT("Entry:"); |
1 | 2282 |
} |
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2283 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2284 |
array_overlap_test(nooverlap_target, Address::times_8); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2285 |
setup_arg_regs_using_thread(); // from => rdi, to => rsi, count => rdx |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2286 |
// r9 is used to save r15_thread |
1 | 2287 |
// 'from', 'to' and 'qword_count' are now valid |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2288 |
|
54755
de34f4b370b0
8223244: Fix usage of ARRAYCOPY_DISJOINT decorator
rkennke
parents:
54750
diff
changeset
|
2289 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2290 |
if (dest_uninitialized) { |
50728 | 2291 |
decorators |= IS_DEST_UNINITIALIZED; |
1 | 2292 |
} |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2293 |
if (aligned) { |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2294 |
decorators |= ARRAYCOPY_ALIGNED; |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2295 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2296 |
|
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2297 |
BasicType type = is_oop ? T_OBJECT : T_LONG; |
49754 | 2298 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2299 |
bs->arraycopy_prologue(_masm, decorators, type, from, to, qword_count); |
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2300 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2301 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2302 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2303 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2304 |
__ jmp(L_copy_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2305 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2306 |
// Copy trailing qwords |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2307 |
__ BIND(L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2308 |
__ movq(rax, Address(from, qword_count, Address::times_8, -8)); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2309 |
__ movq(Address(to, qword_count, Address::times_8, -8), rax); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2310 |
__ decrement(qword_count); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2311 |
__ jcc(Assembler::notZero, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2312 |
} |
1 | 2313 |
if (is_oop) { |
2314 |
__ jmp(L_exit); |
|
2315 |
} else { |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2316 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2317 |
inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free |
1066 | 2318 |
__ xorptr(rax, rax); // return 0 |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2319 |
__ vzeroupper(); |
1 | 2320 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2321 |
__ ret(0); |
|
2322 |
} |
|
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2323 |
{ |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2324 |
// UnsafeCopyMemory page error: continue after ucm |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2325 |
UnsafeCopyMemoryMark ucmm(this, !is_oop && !aligned, true); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2326 |
|
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2327 |
// Copy in multi-bytes chunks |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2328 |
copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
2329 |
} |
1 | 2330 |
__ BIND(L_exit); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2331 |
bs->arraycopy_epilogue(_masm, decorators, type, from, to, qword_count); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2332 |
restore_arg_regs_using_thread(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2333 |
if (is_oop) { |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2334 |
inc_counter_np(SharedRuntime::_oop_array_copy_ctr); // Update counter after rscratch1 is free |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2335 |
} else { |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2336 |
inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free |
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2337 |
} |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
2338 |
__ vzeroupper(); |
1066 | 2339 |
__ xorptr(rax, rax); // return 0 |
1 | 2340 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2341 |
__ ret(0); |
|
2342 |
||
2343 |
return start; |
|
2344 |
} |
|
2345 |
||
2346 |
||
2347 |
// Helper for generating a dynamic type check. |
|
2348 |
// Smashes no registers. |
|
2349 |
void generate_type_check(Register sub_klass, |
|
2350 |
Register super_check_offset, |
|
2351 |
Register super_klass, |
|
2352 |
Label& L_success) { |
|
2353 |
assert_different_registers(sub_klass, super_check_offset, super_klass); |
|
2354 |
||
2355 |
BLOCK_COMMENT("type_check:"); |
|
2356 |
||
2357 |
Label L_miss; |
|
2358 |
||
2256
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
1888
diff
changeset
|
2359 |
__ check_klass_subtype_fast_path(sub_klass, super_klass, noreg, &L_success, &L_miss, NULL, |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
1888
diff
changeset
|
2360 |
super_check_offset); |
82d4e10b7c6b
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
1888
diff
changeset
|
2361 |
__ check_klass_subtype_slow_path(sub_klass, super_klass, noreg, noreg, &L_success, NULL); |
1 | 2362 |
|
2363 |
// Fall through on failure! |
|
2364 |
__ BIND(L_miss); |
|
2365 |
} |
|
2366 |
||
2367 |
// |
|
2368 |
// Generate checkcasting array copy stub |
|
2369 |
// |
|
2370 |
// Input: |
|
2371 |
// c_rarg0 - source array address |
|
2372 |
// c_rarg1 - destination array address |
|
2373 |
// c_rarg2 - element count, treated as ssize_t, can be zero |
|
2374 |
// c_rarg3 - size_t ckoff (super_check_offset) |
|
2375 |
// not Win64 |
|
2376 |
// c_rarg4 - oop ckval (super_klass) |
|
2377 |
// Win64 |
|
2378 |
// rsp+40 - oop ckval (super_klass) |
|
2379 |
// |
|
2380 |
// Output: |
|
2381 |
// rax == 0 - success |
|
2382 |
// rax == -1^K - failure, where K is partial transfer count |
|
2383 |
// |
|
8498 | 2384 |
address generate_checkcast_copy(const char *name, address *entry, |
2385 |
bool dest_uninitialized = false) { |
|
1 | 2386 |
|
2387 |
Label L_load_element, L_store_element, L_do_card_marks, L_done; |
|
2388 |
||
2389 |
// Input registers (after setup_arg_regs) |
|
2390 |
const Register from = rdi; // source array address |
|
2391 |
const Register to = rsi; // destination array address |
|
2392 |
const Register length = rdx; // elements count |
|
2393 |
const Register ckoff = rcx; // super_check_offset |
|
2394 |
const Register ckval = r8; // super_klass |
|
2395 |
||
2396 |
// Registers used as temps (r13, r14 are save-on-entry) |
|
2397 |
const Register end_from = from; // source array end address |
|
2398 |
const Register end_to = r13; // destination array end address |
|
2399 |
const Register count = rdx; // -(count_remaining) |
|
2400 |
const Register r14_length = r14; // saved copy of length |
|
2401 |
// End pointers are inclusive, and if length is not zero they point |
|
2402 |
// to the last unit copied: end_to[0] := end_from[0] |
|
2403 |
||
2404 |
const Register rax_oop = rax; // actual oop copied |
|
2405 |
const Register r11_klass = r11; // oop._klass |
|
2406 |
||
2407 |
//--------------------------------------------------------------- |
|
2408 |
// Assembler stub will be used for this call to arraycopy |
|
2409 |
// if the two arrays are subtypes of Object[] but the |
|
2410 |
// destination array type is not equal to or a supertype |
|
2411 |
// of the source type. Each element must be separately |
|
2412 |
// checked. |
|
2413 |
||
2414 |
__ align(CodeEntryAlignment); |
|
2415 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2416 |
address start = __ pc(); |
|
2417 |
||
2418 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2419 |
||
2420 |
#ifdef ASSERT |
|
2421 |
// caller guarantees that the arrays really are different |
|
2422 |
// otherwise, we would have to make conjoint checks |
|
2423 |
{ Label L; |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2424 |
array_overlap_test(L, TIMES_OOP); |
1 | 2425 |
__ stop("checkcast_copy within a single array"); |
2426 |
__ bind(L); |
|
2427 |
} |
|
2428 |
#endif //ASSERT |
|
2429 |
||
2430 |
setup_arg_regs(4); // from => rdi, to => rsi, length => rdx |
|
2431 |
// ckoff => rcx, ckval => r8 |
|
2432 |
// r9 and r10 may be used to save non-volatile registers |
|
2433 |
#ifdef _WIN64 |
|
2434 |
// last argument (#4) is on stack on Win64 |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2435 |
__ movptr(ckval, Address(rsp, 6 * wordSize)); |
1 | 2436 |
#endif |
2437 |
||
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2438 |
// Caller of this entry point must set up the argument registers. |
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2439 |
if (entry != NULL) { |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2440 |
*entry = __ pc(); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2441 |
BLOCK_COMMENT("Entry:"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2442 |
} |
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2443 |
|
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2444 |
// allocate spill slots for r13, r14 |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2445 |
enum { |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2446 |
saved_r13_offset, |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2447 |
saved_r14_offset, |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2448 |
saved_r10_offset, |
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2449 |
saved_rbp_offset |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2450 |
}; |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2451 |
__ subptr(rsp, saved_rbp_offset * wordSize); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2452 |
__ movptr(Address(rsp, saved_r13_offset * wordSize), r13); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2453 |
__ movptr(Address(rsp, saved_r14_offset * wordSize), r14); |
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2454 |
__ movptr(Address(rsp, saved_r10_offset * wordSize), r10); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2455 |
|
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2456 |
#ifdef ASSERT |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2457 |
Label L2; |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2458 |
__ get_thread(r14); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2459 |
__ cmpptr(r15_thread, r14); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2460 |
__ jcc(Assembler::equal, L2); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2461 |
__ stop("StubRoutines::call_stub: r15_thread is modified by call"); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2462 |
__ bind(L2); |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2463 |
#endif // ASSERT |
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2464 |
|
1 | 2465 |
// check that int operands are properly extended to size_t |
2466 |
assert_clean_int(length, rax); |
|
2467 |
assert_clean_int(ckoff, rax); |
|
2468 |
||
2469 |
#ifdef ASSERT |
|
2470 |
BLOCK_COMMENT("assert consistent ckoff/ckval"); |
|
2471 |
// The ckoff and ckval must be mutually consistent, |
|
2472 |
// even though caller generates both. |
|
2473 |
{ Label L; |
|
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11194
diff
changeset
|
2474 |
int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
1 | 2475 |
__ cmpl(ckoff, Address(ckval, sco_offset)); |
2476 |
__ jcc(Assembler::equal, L); |
|
2477 |
__ stop("super_check_offset inconsistent"); |
|
2478 |
__ bind(L); |
|
2479 |
} |
|
2480 |
#endif //ASSERT |
|
2481 |
||
2482 |
// Loop-invariant addresses. They are exclusive end pointers. |
|
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2483 |
Address end_from_addr(from, length, TIMES_OOP, 0); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2484 |
Address end_to_addr(to, length, TIMES_OOP, 0); |
1 | 2485 |
// Loop-variant addresses. They assume post-incremented count < 0. |
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2486 |
Address from_element_addr(end_from, count, TIMES_OOP, 0); |
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2487 |
Address to_element_addr(end_to, count, TIMES_OOP, 0); |
1 | 2488 |
|
54755
de34f4b370b0
8223244: Fix usage of ARRAYCOPY_DISJOINT decorator
rkennke
parents:
54750
diff
changeset
|
2489 |
DecoratorSet decorators = IN_HEAP | IS_ARRAY | ARRAYCOPY_CHECKCAST | ARRAYCOPY_DISJOINT; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2490 |
if (dest_uninitialized) { |
50728 | 2491 |
decorators |= IS_DEST_UNINITIALIZED; |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2492 |
} |
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2493 |
|
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2494 |
BasicType type = T_OBJECT; |
49754 | 2495 |
BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler(); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2496 |
bs->arraycopy_prologue(_masm, decorators, type, from, to, count); |
1 | 2497 |
|
2498 |
// Copy from low to high addresses, indexed from the end of each array. |
|
1066 | 2499 |
__ lea(end_from, end_from_addr); |
2500 |
__ lea(end_to, end_to_addr); |
|
2501 |
__ movptr(r14_length, length); // save a copy of the length |
|
2502 |
assert(length == count, ""); // else fix next line: |
|
2503 |
__ negptr(count); // negate and test the length |
|
1 | 2504 |
__ jcc(Assembler::notZero, L_load_element); |
2505 |
||
2506 |
// Empty array: Nothing to do. |
|
1066 | 2507 |
__ xorptr(rax, rax); // return 0 on (trivial) success |
1 | 2508 |
__ jmp(L_done); |
2509 |
||
2510 |
// ======== begin loop ======== |
|
2511 |
// (Loop is rotated; its entry is L_load_element.) |
|
2512 |
// Loop control: |
|
2513 |
// for (count = -count; count != 0; count++) |
|
2514 |
// Base pointers src, dst are biased by 8*(count-1),to last element. |
|
5249 | 2515 |
__ align(OptoLoopAlignment); |
1 | 2516 |
|
2517 |
__ BIND(L_store_element); |
|
49748 | 2518 |
__ store_heap_oop(to_element_addr, rax_oop, noreg, noreg, AS_RAW); // store the oop |
1066 | 2519 |
__ increment(count); // increment the count toward zero |
1 | 2520 |
__ jcc(Assembler::zero, L_do_card_marks); |
2521 |
||
2522 |
// ======== loop entry is here ======== |
|
2523 |
__ BIND(L_load_element); |
|
49748 | 2524 |
__ load_heap_oop(rax_oop, from_element_addr, noreg, noreg, AS_RAW); // load the oop |
1066 | 2525 |
__ testptr(rax_oop, rax_oop); |
1 | 2526 |
__ jcc(Assembler::zero, L_store_element); |
2527 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2528 |
__ load_klass(r11_klass, rax_oop);// query the object klass |
1 | 2529 |
generate_type_check(r11_klass, ckoff, ckval, L_store_element); |
2530 |
// ======== end loop ======== |
|
2531 |
||
2532 |
// It was a real error; we must depend on the caller to finish the job. |
|
2533 |
// Register rdx = -1 * number of *remaining* oops, r14 = *total* oops. |
|
2534 |
// Emit GC store barriers for the oops we have copied (r14 + rdx), |
|
2535 |
// and report their number to the caller. |
|
17622
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2536 |
assert_different_registers(rax, r14_length, count, to, end_to, rcx, rscratch1); |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2537 |
Label L_post_barrier; |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2538 |
__ addptr(r14_length, count); // K = (original - remaining) oops |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2539 |
__ movptr(rax, r14_length); // save the value |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2540 |
__ notptr(rax); // report (-1^K) to caller (does not affect flags) |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2541 |
__ jccb(Assembler::notZero, L_post_barrier); |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2542 |
__ jmp(L_done); // K == 0, nothing was copied, skip post barrier |
1 | 2543 |
|
2544 |
// Come here on success only. |
|
2545 |
__ BIND(L_do_card_marks); |
|
17622
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2546 |
__ xorptr(rax, rax); // return 0 on success |
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2547 |
|
4037daf22a17
8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents:
16624
diff
changeset
|
2548 |
__ BIND(L_post_barrier); |
49484
ee8fa73b90f9
8198949: Modularize arraycopy stub routine GC barriers
eosterlund
parents:
49455
diff
changeset
|
2549 |
bs->arraycopy_epilogue(_masm, decorators, type, from, to, r14_length); |
1 | 2550 |
|
2551 |
// Common exit point (success or failure). |
|
2552 |
__ BIND(L_done); |
|
1066 | 2553 |
__ movptr(r13, Address(rsp, saved_r13_offset * wordSize)); |
2554 |
__ movptr(r14, Address(rsp, saved_r14_offset * wordSize)); |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
2555 |
__ movptr(r10, Address(rsp, saved_r10_offset * wordSize)); |
1 | 2556 |
restore_arg_regs(); |
11194
ee1235a09fc3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents:
11190
diff
changeset
|
2557 |
inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr); // Update counter after rscratch1 is free |
1 | 2558 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2559 |
__ ret(0); |
|
2560 |
||
2561 |
return start; |
|
2562 |
} |
|
2563 |
||
2564 |
// |
|
2565 |
// Generate 'unsafe' array copy stub |
|
2566 |
// Though just as safe as the other stubs, it takes an unscaled |
|
2567 |
// size_t argument instead of an element count. |
|
2568 |
// |
|
2569 |
// Input: |
|
2570 |
// c_rarg0 - source array address |
|
2571 |
// c_rarg1 - destination array address |
|
2572 |
// c_rarg2 - byte count, treated as ssize_t, can be zero |
|
2573 |
// |
|
2574 |
// Examines the alignment of the operands and dispatches |
|
2575 |
// to a long, int, short, or byte copy loop. |
|
2576 |
// |
|
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2577 |
address generate_unsafe_copy(const char *name, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2578 |
address byte_copy_entry, address short_copy_entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2579 |
address int_copy_entry, address long_copy_entry) { |
1 | 2580 |
|
2581 |
Label L_long_aligned, L_int_aligned, L_short_aligned; |
|
2582 |
||
2583 |
// Input registers (before setup_arg_regs) |
|
2584 |
const Register from = c_rarg0; // source array address |
|
2585 |
const Register to = c_rarg1; // destination array address |
|
2586 |
const Register size = c_rarg2; // byte count (size_t) |
|
2587 |
||
2588 |
// Register used as a temp |
|
2589 |
const Register bits = rax; // test copy of low bits |
|
2590 |
||
2591 |
__ align(CodeEntryAlignment); |
|
2592 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2593 |
address start = __ pc(); |
|
2594 |
||
2595 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2596 |
||
2597 |
// bump this on entry, not on exit: |
|
2598 |
inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr); |
|
2599 |
||
1066 | 2600 |
__ mov(bits, from); |
2601 |
__ orptr(bits, to); |
|
2602 |
__ orptr(bits, size); |
|
1 | 2603 |
|
2604 |
__ testb(bits, BytesPerLong-1); |
|
2605 |
__ jccb(Assembler::zero, L_long_aligned); |
|
2606 |
||
2607 |
__ testb(bits, BytesPerInt-1); |
|
2608 |
__ jccb(Assembler::zero, L_int_aligned); |
|
2609 |
||
2610 |
__ testb(bits, BytesPerShort-1); |
|
2611 |
__ jump_cc(Assembler::notZero, RuntimeAddress(byte_copy_entry)); |
|
2612 |
||
2613 |
__ BIND(L_short_aligned); |
|
1066 | 2614 |
__ shrptr(size, LogBytesPerShort); // size => short_count |
1 | 2615 |
__ jump(RuntimeAddress(short_copy_entry)); |
2616 |
||
2617 |
__ BIND(L_int_aligned); |
|
1066 | 2618 |
__ shrptr(size, LogBytesPerInt); // size => int_count |
1 | 2619 |
__ jump(RuntimeAddress(int_copy_entry)); |
2620 |
||
2621 |
__ BIND(L_long_aligned); |
|
1066 | 2622 |
__ shrptr(size, LogBytesPerLong); // size => qword_count |
1 | 2623 |
__ jump(RuntimeAddress(long_copy_entry)); |
2624 |
||
2625 |
return start; |
|
2626 |
} |
|
2627 |
||
2628 |
// Perform range checks on the proposed arraycopy. |
|
2629 |
// Kills temp, but nothing else. |
|
2630 |
// Also, clean the sign bits of src_pos and dst_pos. |
|
2631 |
void arraycopy_range_checks(Register src, // source array oop (c_rarg0) |
|
2632 |
Register src_pos, // source position (c_rarg1) |
|
2633 |
Register dst, // destination array oo (c_rarg2) |
|
2634 |
Register dst_pos, // destination position (c_rarg3) |
|
2635 |
Register length, |
|
2636 |
Register temp, |
|
2637 |
Label& L_failed) { |
|
2638 |
BLOCK_COMMENT("arraycopy_range_checks:"); |
|
2639 |
||
2640 |
// if (src_pos + length > arrayOop(src)->length()) FAIL; |
|
2641 |
__ movl(temp, length); |
|
2642 |
__ addl(temp, src_pos); // src_pos + length |
|
2643 |
__ cmpl(temp, Address(src, arrayOopDesc::length_offset_in_bytes())); |
|
2644 |
__ jcc(Assembler::above, L_failed); |
|
2645 |
||
2646 |
// if (dst_pos + length > arrayOop(dst)->length()) FAIL; |
|
2647 |
__ movl(temp, length); |
|
2648 |
__ addl(temp, dst_pos); // dst_pos + length |
|
2649 |
__ cmpl(temp, Address(dst, arrayOopDesc::length_offset_in_bytes())); |
|
2650 |
__ jcc(Assembler::above, L_failed); |
|
2651 |
||
2652 |
// Have to clean up high 32-bits of 'src_pos' and 'dst_pos'. |
|
2653 |
// Move with sign extension can be used since they are positive. |
|
2654 |
__ movslq(src_pos, src_pos); |
|
2655 |
__ movslq(dst_pos, dst_pos); |
|
2656 |
||
2657 |
BLOCK_COMMENT("arraycopy_range_checks done"); |
|
2658 |
} |
|
2659 |
||
2660 |
// |
|
2661 |
// Generate generic array copy stubs |
|
2662 |
// |
|
2663 |
// Input: |
|
2664 |
// c_rarg0 - src oop |
|
2665 |
// c_rarg1 - src_pos (32-bits) |
|
2666 |
// c_rarg2 - dst oop |
|
2667 |
// c_rarg3 - dst_pos (32-bits) |
|
2668 |
// not Win64 |
|
2669 |
// c_rarg4 - element count (32-bits) |
|
2670 |
// Win64 |
|
2671 |
// rsp+40 - element count (32-bits) |
|
2672 |
// |
|
2673 |
// Output: |
|
2674 |
// rax == 0 - success |
|
2675 |
// rax == -1^K - failure, where K is partial transfer count |
|
2676 |
// |
|
8487
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2677 |
address generate_generic_copy(const char *name, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
2678 |
address byte_copy_entry, address short_copy_entry, |
8876
f82367de21f5
7026307: DEBUG MESSAGE: broken null klass on amd64
iveresov
parents:
8874
diff
changeset
|
2679 |
address int_copy_entry, address oop_copy_entry, |
f82367de21f5
7026307: DEBUG MESSAGE: broken null klass on amd64
iveresov
parents:
8874
diff
changeset
|
2680 |
address long_copy_entry, address checkcast_copy_entry) { |
1 | 2681 |
|
2682 |
Label L_failed, L_failed_0, L_objArray; |
|
2683 |
Label L_copy_bytes, L_copy_shorts, L_copy_ints, L_copy_longs; |
|
2684 |
||
2685 |
// Input registers |
|
2686 |
const Register src = c_rarg0; // source array oop |
|
2687 |
const Register src_pos = c_rarg1; // source position |
|
2688 |
const Register dst = c_rarg2; // destination array oop |
|
2689 |
const Register dst_pos = c_rarg3; // destination position |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2690 |
#ifndef _WIN64 |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2691 |
const Register length = c_rarg4; |
1 | 2692 |
#else |
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2693 |
const Address length(rsp, 6 * wordSize); // elements count is on stack on Win64 |
1 | 2694 |
#endif |
2695 |
||
2696 |
{ int modulus = CodeEntryAlignment; |
|
2697 |
int target = modulus - 5; // 5 = sizeof jmp(L_failed) |
|
2698 |
int advance = target - (__ offset() % modulus); |
|
2699 |
if (advance < 0) advance += modulus; |
|
2700 |
if (advance > 0) __ nop(advance); |
|
2701 |
} |
|
2702 |
StubCodeMark mark(this, "StubRoutines", name); |
|
2703 |
||
2704 |
// Short-hop target to L_failed. Makes for denser prologue code. |
|
2705 |
__ BIND(L_failed_0); |
|
2706 |
__ jmp(L_failed); |
|
2707 |
assert(__ offset() % CodeEntryAlignment == 0, "no further alignment needed"); |
|
2708 |
||
2709 |
__ align(CodeEntryAlignment); |
|
2710 |
address start = __ pc(); |
|
2711 |
||
2712 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
2713 |
||
2714 |
// bump this on entry, not on exit: |
|
2715 |
inc_counter_np(SharedRuntime::_generic_array_copy_ctr); |
|
2716 |
||
2717 |
//----------------------------------------------------------------------- |
|
2718 |
// Assembler stub will be used for this call to arraycopy |
|
2719 |
// if the following conditions are met: |
|
2720 |
// |
|
2721 |
// (1) src and dst must not be null. |
|
2722 |
// (2) src_pos must not be negative. |
|
2723 |
// (3) dst_pos must not be negative. |
|
2724 |
// (4) length must not be negative. |
|
2725 |
// (5) src klass and dst klass should be the same and not NULL. |
|
2726 |
// (6) src and dst should be arrays. |
|
2727 |
// (7) src_pos + length must not exceed length of src. |
|
2728 |
// (8) dst_pos + length must not exceed length of dst. |
|
2729 |
// |
|
2730 |
||
2731 |
// if (src == NULL) return -1; |
|
1066 | 2732 |
__ testptr(src, src); // src oop |
1 | 2733 |
size_t j1off = __ offset(); |
2734 |
__ jccb(Assembler::zero, L_failed_0); |
|
2735 |
||
2736 |
// if (src_pos < 0) return -1; |
|
2737 |
__ testl(src_pos, src_pos); // src_pos (32-bits) |
|
2738 |
__ jccb(Assembler::negative, L_failed_0); |
|
2739 |
||
2740 |
// if (dst == NULL) return -1; |
|
1066 | 2741 |
__ testptr(dst, dst); // dst oop |
1 | 2742 |
__ jccb(Assembler::zero, L_failed_0); |
2743 |
||
2744 |
// if (dst_pos < 0) return -1; |
|
2745 |
__ testl(dst_pos, dst_pos); // dst_pos (32-bits) |
|
2746 |
size_t j4off = __ offset(); |
|
2747 |
__ jccb(Assembler::negative, L_failed_0); |
|
2748 |
||
2749 |
// The first four tests are very dense code, |
|
2750 |
// but not quite dense enough to put four |
|
2751 |
// jumps in a 16-byte instruction fetch buffer. |
|
2752 |
// That's good, because some branch predicters |
|
2753 |
// do not like jumps so close together. |
|
2754 |
// Make sure of this. |
|
2755 |
guarantee(((j1off ^ j4off) & ~15) != 0, "I$ line of 1st & 4th jumps"); |
|
2756 |
||
2757 |
// registers used as temp |
|
2758 |
const Register r11_length = r11; // elements count to copy |
|
2759 |
const Register r10_src_klass = r10; // array klass |
|
2760 |
||
2761 |
// if (length < 0) return -1; |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2762 |
__ movl(r11_length, length); // length (elements count, 32-bits value) |
1 | 2763 |
__ testl(r11_length, r11_length); |
2764 |
__ jccb(Assembler::negative, L_failed_0); |
|
2765 |
||
360
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
189
diff
changeset
|
2766 |
__ load_klass(r10_src_klass, src); |
1 | 2767 |
#ifdef ASSERT |
2768 |
// assert(src->klass() != NULL); |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2769 |
{ |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2770 |
BLOCK_COMMENT("assert klasses not null {"); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2771 |
Label L1, L2; |
1066 | 2772 |
__ testptr(r10_src_klass, r10_src_klass); |
1 | 2773 |
__ jcc(Assembler::notZero, L2); // it is broken if klass is NULL |
2774 |
__ bind(L1); |
|
2775 |
__ stop("broken null klass"); |
|
2776 |
__ bind(L2); |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2777 |
__ load_klass(rax, dst); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2778 |
__ cmpq(rax, 0); |
1 | 2779 |
__ jcc(Assembler::equal, L1); // this would be broken also |
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2780 |
BLOCK_COMMENT("} assert klasses not null done"); |
1 | 2781 |
} |
2782 |
#endif |
|
2783 |
||
2784 |
// Load layout helper (32-bits) |
|
2785 |
// |
|
2786 |
// |array_tag| | header_size | element_type | |log2_element_size| |
|
2787 |
// 32 30 24 16 8 2 0 |
|
2788 |
// |
|
2789 |
// array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0 |
|
2790 |
// |
|
2791 |
||
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11194
diff
changeset
|
2792 |
const int lh_offset = in_bytes(Klass::layout_helper_offset()); |
1 | 2793 |
|
2794 |
// Handle objArrays completely differently... |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2795 |
const jint objArray_lh = Klass::array_layout_helper(T_OBJECT); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2796 |
__ cmpl(Address(r10_src_klass, lh_offset), objArray_lh); |
1 | 2797 |
__ jcc(Assembler::equal, L_objArray); |
2798 |
||
2799 |
// if (src->klass() != dst->klass()) return -1; |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2800 |
__ load_klass(rax, dst); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2801 |
__ cmpq(r10_src_klass, rax); |
1 | 2802 |
__ jcc(Assembler::notEqual, L_failed); |
2803 |
||
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2804 |
const Register rax_lh = rax; // layout helper |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2805 |
__ movl(rax_lh, Address(r10_src_klass, lh_offset)); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2806 |
|
1 | 2807 |
// if (!src->is_Array()) return -1; |
2808 |
__ cmpl(rax_lh, Klass::_lh_neutral_value); |
|
2809 |
__ jcc(Assembler::greaterEqual, L_failed); |
|
2810 |
||
2811 |
// At this point, it is known to be a typeArray (array_tag 0x3). |
|
2812 |
#ifdef ASSERT |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2813 |
{ |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2814 |
BLOCK_COMMENT("assert primitive array {"); |
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2815 |
Label L; |
1 | 2816 |
__ cmpl(rax_lh, (Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift)); |
2817 |
__ jcc(Assembler::greaterEqual, L); |
|
2818 |
__ stop("must be a primitive array"); |
|
2819 |
__ bind(L); |
|
7431
e9f07f8aef47
6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents:
7397
diff
changeset
|
2820 |
BLOCK_COMMENT("} assert primitive array done"); |
1 | 2821 |
} |
2822 |
#endif |
|
2823 |
||
2824 |
arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length, |
|
2825 |
r10, L_failed); |
|
2826 |
||
13952
e3cf184080bc
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
13728
diff
changeset
|
2827 |
// TypeArrayKlass |
1 | 2828 |
// |
2829 |
// src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize); |
|
2830 |
// dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize); |
|
2831 |
// |
|
2832 |
||
2833 |
const Register r10_offset = r10; // array offset |
|
2834 |
const Register rax_elsize = rax_lh; // element size |
|
2835 |
||
2836 |
__ movl(r10_offset, rax_lh); |
|
2837 |
__ shrl(r10_offset, Klass::_lh_header_size_shift); |
|
1066 | 2838 |
__ andptr(r10_offset, Klass::_lh_header_size_mask); // array_offset |
2839 |
__ addptr(src, r10_offset); // src array offset |
|
2840 |
__ addptr(dst, r10_offset); // dst array offset |
|
1 | 2841 |
BLOCK_COMMENT("choose copy loop based on element size"); |
2842 |
__ andl(rax_lh, Klass::_lh_log2_element_size_mask); // rax_lh -> rax_elsize |
|
2843 |
||
2844 |
// next registers should be set before the jump to corresponding stub |
|
2845 |
const Register from = c_rarg0; // source array address |
|
2846 |
const Register to = c_rarg1; // destination array address |
|
2847 |
const Register count = c_rarg2; // elements count |
|
2848 |
||
2849 |
// 'from', 'to', 'count' registers should be set in such order |
|
2850 |
// since they are the same as 'src', 'src_pos', 'dst'. |
|
2851 |
||
2852 |
__ BIND(L_copy_bytes); |
|
2853 |
__ cmpl(rax_elsize, 0); |
|
2854 |
__ jccb(Assembler::notEqual, L_copy_shorts); |
|
1066 | 2855 |
__ lea(from, Address(src, src_pos, Address::times_1, 0));// src_addr |
2856 |
__ lea(to, Address(dst, dst_pos, Address::times_1, 0));// dst_addr |
|
2857 |
__ movl2ptr(count, r11_length); // length |
|
1 | 2858 |
__ jump(RuntimeAddress(byte_copy_entry)); |
2859 |
||
2860 |
__ BIND(L_copy_shorts); |
|
2861 |
__ cmpl(rax_elsize, LogBytesPerShort); |
|
2862 |
__ jccb(Assembler::notEqual, L_copy_ints); |
|
1066 | 2863 |
__ lea(from, Address(src, src_pos, Address::times_2, 0));// src_addr |
2864 |
__ lea(to, Address(dst, dst_pos, Address::times_2, 0));// dst_addr |
|
2865 |
__ movl2ptr(count, r11_length); // length |
|
1 | 2866 |
__ jump(RuntimeAddress(short_copy_entry)); |
2867 |
||
2868 |
__ BIND(L_copy_ints); |
|
2869 |
__ cmpl(rax_elsize, LogBytesPerInt); |
|
2870 |
__ jccb(Assembler::notEqual, L_copy_longs); |
|
1066 | 2871 |
__ lea(from, Address(src, src_pos, Address::times_4, 0));// src_addr |
2872 |
__ lea(to, Address(dst, dst_pos, Address::times_4, 0));// dst_addr |
|
2873 |
__ movl2ptr(count, r11_length); // length |
|
1 | 2874 |
__ jump(RuntimeAddress(int_copy_entry)); |
2875 |
||
2876 |
__ BIND(L_copy_longs); |
|
2877 |
#ifdef ASSERT |
|
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diff
changeset
|
2878 |
{ |
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7397
diff
changeset
|
2879 |
BLOCK_COMMENT("assert long copy {"); |
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7397
diff
changeset
|
2880 |
Label L; |
1 | 2881 |
__ cmpl(rax_elsize, LogBytesPerLong); |
2882 |
__ jcc(Assembler::equal, L); |
|
2883 |
__ stop("must be long copy, but elsize is wrong"); |
|
2884 |
__ bind(L); |
|
7431
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diff
changeset
|
2885 |
BLOCK_COMMENT("} assert long copy done"); |
1 | 2886 |
} |
2887 |
#endif |
|
1066 | 2888 |
__ lea(from, Address(src, src_pos, Address::times_8, 0));// src_addr |
2889 |
__ lea(to, Address(dst, dst_pos, Address::times_8, 0));// dst_addr |
|
2890 |
__ movl2ptr(count, r11_length); // length |
|
1 | 2891 |
__ jump(RuntimeAddress(long_copy_entry)); |
2892 |
||
13952
e3cf184080bc
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
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13728
diff
changeset
|
2893 |
// ObjArrayKlass |
1 | 2894 |
__ BIND(L_objArray); |
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diff
changeset
|
2895 |
// live at this point: r10_src_klass, r11_length, src[_pos], dst[_pos] |
1 | 2896 |
|
2897 |
Label L_plain_copy, L_checkcast_copy; |
|
2898 |
// test array classes for subtyping |
|
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diff
changeset
|
2899 |
__ load_klass(rax, dst); |
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diff
changeset
|
2900 |
__ cmpq(r10_src_klass, rax); // usual case is exact equality |
1 | 2901 |
__ jcc(Assembler::notEqual, L_checkcast_copy); |
2902 |
||
2903 |
// Identically typed arrays can be copied without element-wise checks. |
|
2904 |
arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length, |
|
2905 |
r10, L_failed); |
|
2906 |
||
1066 | 2907 |
__ lea(from, Address(src, src_pos, TIMES_OOP, |
1 | 2908 |
arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr |
1066 | 2909 |
__ lea(to, Address(dst, dst_pos, TIMES_OOP, |
2910 |
arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr |
|
2911 |
__ movl2ptr(count, r11_length); // length |
|
1 | 2912 |
__ BIND(L_plain_copy); |
2913 |
__ jump(RuntimeAddress(oop_copy_entry)); |
|
2914 |
||
2915 |
__ BIND(L_checkcast_copy); |
|
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diff
changeset
|
2916 |
// live at this point: r10_src_klass, r11_length, rax (dst_klass) |
1 | 2917 |
{ |
2918 |
// Before looking at dst.length, make sure dst is also an objArray. |
|
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diff
changeset
|
2919 |
__ cmpl(Address(rax, lh_offset), objArray_lh); |
1 | 2920 |
__ jcc(Assembler::notEqual, L_failed); |
2921 |
||
2922 |
// It is safe to examine both src.length and dst.length. |
|
2923 |
arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length, |
|
2924 |
rax, L_failed); |
|
7431
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diff
changeset
|
2925 |
|
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diff
changeset
|
2926 |
const Register r11_dst_klass = r11; |
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|
2927 |
__ load_klass(r11_dst_klass, dst); // reload |
1 | 2928 |
|
2929 |
// Marshal the base address arguments now, freeing registers. |
|
1066 | 2930 |
__ lea(from, Address(src, src_pos, TIMES_OOP, |
1 | 2931 |
arrayOopDesc::base_offset_in_bytes(T_OBJECT))); |
1066 | 2932 |
__ lea(to, Address(dst, dst_pos, TIMES_OOP, |
1 | 2933 |
arrayOopDesc::base_offset_in_bytes(T_OBJECT))); |
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changeset
|
2934 |
__ movl(count, length); // length (reloaded) |
1 | 2935 |
Register sco_temp = c_rarg3; // this register is free now |
2936 |
assert_different_registers(from, to, count, sco_temp, |
|
2937 |
r11_dst_klass, r10_src_klass); |
|
2938 |
assert_clean_int(count, sco_temp); |
|
2939 |
||
2940 |
// Generate the type check. |
|
11430
718fc06da49a
7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents:
11194
diff
changeset
|
2941 |
const int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
1 | 2942 |
__ movl(sco_temp, Address(r11_dst_klass, sco_offset)); |
2943 |
assert_clean_int(sco_temp, rax); |
|
2944 |
generate_type_check(r10_src_klass, sco_temp, r11_dst_klass, L_plain_copy); |
|
2945 |
||
13952
e3cf184080bc
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diff
changeset
|
2946 |
// Fetch destination element klass from the ObjArrayKlass header. |
e3cf184080bc
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
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diff
changeset
|
2947 |
int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); |
1066 | 2948 |
__ movptr(r11_dst_klass, Address(r11_dst_klass, ek_offset)); |
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changeset
|
2949 |
__ movl( sco_temp, Address(r11_dst_klass, sco_offset)); |
1 | 2950 |
assert_clean_int(sco_temp, rax); |
2951 |
||
2952 |
// the checkcast_copy loop needs two extra arguments: |
|
2953 |
assert(c_rarg3 == sco_temp, "#3 already in place"); |
|
7431
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diff
changeset
|
2954 |
// Set up arguments for checkcast_copy_entry. |
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diff
changeset
|
2955 |
setup_arg_regs(4); |
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diff
changeset
|
2956 |
__ movptr(r8, r11_dst_klass); // dst.klass.element_klass, r8 is c_rarg4 on Linux/Solaris |
1 | 2957 |
__ jump(RuntimeAddress(checkcast_copy_entry)); |
2958 |
} |
|
2959 |
||
2960 |
__ BIND(L_failed); |
|
1066 | 2961 |
__ xorptr(rax, rax); |
2962 |
__ notptr(rax); // return -1 |
|
1 | 2963 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
2964 |
__ ret(0); |
|
2965 |
||
2966 |
return start; |
|
2967 |
} |
|
2968 |
||
57804 | 2969 |
address generate_data_cache_writeback() { |
2970 |
const Register src = c_rarg0; // source address |
|
2971 |
||
2972 |
__ align(CodeEntryAlignment); |
|
2973 |
||
2974 |
StubCodeMark mark(this, "StubRoutines", "_data_cache_writeback"); |
|
2975 |
||
2976 |
address start = __ pc(); |
|
2977 |
__ enter(); |
|
2978 |
__ cache_wb(Address(src, 0)); |
|
2979 |
__ leave(); |
|
2980 |
__ ret(0); |
|
2981 |
||
2982 |
return start; |
|
2983 |
} |
|
2984 |
||
2985 |
address generate_data_cache_writeback_sync() { |
|
2986 |
const Register is_pre = c_rarg0; // pre or post sync |
|
2987 |
||
2988 |
__ align(CodeEntryAlignment); |
|
2989 |
||
2990 |
StubCodeMark mark(this, "StubRoutines", "_data_cache_writeback_sync"); |
|
2991 |
||
2992 |
// pre wbsync is a no-op |
|
2993 |
// post wbsync translates to an sfence |
|
2994 |
||
2995 |
Label skip; |
|
2996 |
address start = __ pc(); |
|
2997 |
__ enter(); |
|
2998 |
__ cmpl(is_pre, 0); |
|
2999 |
__ jcc(Assembler::notEqual, skip); |
|
3000 |
__ cache_wbsync(false); |
|
3001 |
__ bind(skip); |
|
3002 |
__ leave(); |
|
3003 |
__ ret(0); |
|
3004 |
||
3005 |
return start; |
|
3006 |
} |
|
3007 |
||
1 | 3008 |
void generate_arraycopy_stubs() { |
8487
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diff
changeset
|
3009 |
address entry; |
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7020521: arraycopy stubs place prebarriers incorrectly
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diff
changeset
|
3010 |
address entry_jbyte_arraycopy; |
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7020521: arraycopy stubs place prebarriers incorrectly
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diff
changeset
|
3011 |
address entry_jshort_arraycopy; |
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diff
changeset
|
3012 |
address entry_jint_arraycopy; |
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7020521: arraycopy stubs place prebarriers incorrectly
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diff
changeset
|
3013 |
address entry_oop_arraycopy; |
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7020521: arraycopy stubs place prebarriers incorrectly
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diff
changeset
|
3014 |
address entry_jlong_arraycopy; |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
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diff
changeset
|
3015 |
address entry_checkcast_arraycopy; |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
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diff
changeset
|
3016 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
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diff
changeset
|
3017 |
StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, &entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
7431
diff
changeset
|
3018 |
"jbyte_disjoint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
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diff
changeset
|
3019 |
StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, entry, &entry_jbyte_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3020 |
"jbyte_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3021 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
7431
diff
changeset
|
3022 |
StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, &entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3023 |
"jshort_disjoint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3024 |
StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, entry, &entry_jshort_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3025 |
"jshort_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3026 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3027 |
StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, false, &entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3028 |
"jint_disjoint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3029 |
StubRoutines::_jint_arraycopy = generate_conjoint_int_oop_copy(false, false, entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
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diff
changeset
|
3030 |
&entry_jint_arraycopy, "jint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3031 |
|
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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7431
diff
changeset
|
3032 |
StubRoutines::_jlong_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, false, &entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3033 |
"jlong_disjoint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3034 |
StubRoutines::_jlong_arraycopy = generate_conjoint_long_oop_copy(false, false, entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
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diff
changeset
|
3035 |
&entry_jlong_arraycopy, "jlong_arraycopy"); |
1 | 3036 |
|
360
21d113ecbf6a
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parents:
189
diff
changeset
|
3037 |
|
21d113ecbf6a
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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189
diff
changeset
|
3038 |
if (UseCompressedOops) { |
8487
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7431
diff
changeset
|
3039 |
StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, true, &entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
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diff
changeset
|
3040 |
"oop_disjoint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
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diff
changeset
|
3041 |
StubRoutines::_oop_arraycopy = generate_conjoint_int_oop_copy(false, true, entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3042 |
&entry_oop_arraycopy, "oop_arraycopy"); |
8498 | 3043 |
StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_int_oop_copy(false, true, &entry, |
3044 |
"oop_disjoint_arraycopy_uninit", |
|
3045 |
/*dest_uninitialized*/true); |
|
3046 |
StubRoutines::_oop_arraycopy_uninit = generate_conjoint_int_oop_copy(false, true, entry, |
|
3047 |
NULL, "oop_arraycopy_uninit", |
|
3048 |
/*dest_uninitialized*/true); |
|
360
21d113ecbf6a
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parents:
189
diff
changeset
|
3049 |
} else { |
8487
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parents:
7431
diff
changeset
|
3050 |
StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, true, &entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3051 |
"oop_disjoint_arraycopy"); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3052 |
StubRoutines::_oop_arraycopy = generate_conjoint_long_oop_copy(false, true, entry, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3053 |
&entry_oop_arraycopy, "oop_arraycopy"); |
8498 | 3054 |
StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_long_oop_copy(false, true, &entry, |
3055 |
"oop_disjoint_arraycopy_uninit", |
|
3056 |
/*dest_uninitialized*/true); |
|
3057 |
StubRoutines::_oop_arraycopy_uninit = generate_conjoint_long_oop_copy(false, true, entry, |
|
3058 |
NULL, "oop_arraycopy_uninit", |
|
3059 |
/*dest_uninitialized*/true); |
|
360
21d113ecbf6a
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coleenp
parents:
189
diff
changeset
|
3060 |
} |
1 | 3061 |
|
8498 | 3062 |
StubRoutines::_checkcast_arraycopy = generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy); |
3063 |
StubRoutines::_checkcast_arraycopy_uninit = generate_checkcast_copy("checkcast_arraycopy_uninit", NULL, |
|
3064 |
/*dest_uninitialized*/true); |
|
3065 |
||
8487
bf96596f06d2
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parents:
7431
diff
changeset
|
3066 |
StubRoutines::_unsafe_arraycopy = generate_unsafe_copy("unsafe_arraycopy", |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3067 |
entry_jbyte_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3068 |
entry_jshort_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3069 |
entry_jint_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3070 |
entry_jlong_arraycopy); |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3071 |
StubRoutines::_generic_arraycopy = generate_generic_copy("generic_arraycopy", |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3072 |
entry_jbyte_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
7431
diff
changeset
|
3073 |
entry_jshort_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
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parents:
7431
diff
changeset
|
3074 |
entry_jint_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3075 |
entry_oop_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3076 |
entry_jlong_arraycopy, |
bf96596f06d2
7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents:
7431
diff
changeset
|
3077 |
entry_checkcast_arraycopy); |
1 | 3078 |
|
6433 | 3079 |
StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill"); |
3080 |
StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill"); |
|
3081 |
StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill"); |
|
3082 |
StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill"); |
|
3083 |
StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill"); |
|
3084 |
StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill"); |
|
3085 |
||
1 | 3086 |
// We don't generate specialized code for HeapWord-aligned source |
3087 |
// arrays, so just use the code we've already generated |
|
3088 |
StubRoutines::_arrayof_jbyte_disjoint_arraycopy = StubRoutines::_jbyte_disjoint_arraycopy; |
|
3089 |
StubRoutines::_arrayof_jbyte_arraycopy = StubRoutines::_jbyte_arraycopy; |
|
3090 |
||
3091 |
StubRoutines::_arrayof_jshort_disjoint_arraycopy = StubRoutines::_jshort_disjoint_arraycopy; |
|
3092 |
StubRoutines::_arrayof_jshort_arraycopy = StubRoutines::_jshort_arraycopy; |
|
3093 |
||
3094 |
StubRoutines::_arrayof_jint_disjoint_arraycopy = StubRoutines::_jint_disjoint_arraycopy; |
|
3095 |
StubRoutines::_arrayof_jint_arraycopy = StubRoutines::_jint_arraycopy; |
|
3096 |
||
3097 |
StubRoutines::_arrayof_jlong_disjoint_arraycopy = StubRoutines::_jlong_disjoint_arraycopy; |
|
3098 |
StubRoutines::_arrayof_jlong_arraycopy = StubRoutines::_jlong_arraycopy; |
|
3099 |
||
3100 |
StubRoutines::_arrayof_oop_disjoint_arraycopy = StubRoutines::_oop_disjoint_arraycopy; |
|
3101 |
StubRoutines::_arrayof_oop_arraycopy = StubRoutines::_oop_arraycopy; |
|
8498 | 3102 |
|
3103 |
StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit = StubRoutines::_oop_disjoint_arraycopy_uninit; |
|
3104 |
StubRoutines::_arrayof_oop_arraycopy_uninit = StubRoutines::_oop_arraycopy_uninit; |
|
1 | 3105 |
} |
3106 |
||
14132 | 3107 |
// AES intrinsic stubs |
3108 |
enum {AESBlockSize = 16}; |
|
3109 |
||
3110 |
address generate_key_shuffle_mask() { |
|
3111 |
__ align(16); |
|
3112 |
StubCodeMark mark(this, "StubRoutines", "key_shuffle_mask"); |
|
3113 |
address start = __ pc(); |
|
3114 |
__ emit_data64( 0x0405060700010203, relocInfo::none ); |
|
3115 |
__ emit_data64( 0x0c0d0e0f08090a0b, relocInfo::none ); |
|
3116 |
return start; |
|
3117 |
} |
|
3118 |
||
35154 | 3119 |
address generate_counter_shuffle_mask() { |
3120 |
__ align(16); |
|
3121 |
StubCodeMark mark(this, "StubRoutines", "counter_shuffle_mask"); |
|
3122 |
address start = __ pc(); |
|
3123 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); |
|
3124 |
__ emit_data64(0x0001020304050607, relocInfo::none); |
|
3125 |
return start; |
|
3126 |
} |
|
3127 |
||
14132 | 3128 |
// Utility routine for loading a 128-bit key word in little endian format |
3129 |
// can optionally specify that the shuffle mask is already in an xmmregister |
|
3130 |
void load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) { |
|
3131 |
__ movdqu(xmmdst, Address(key, offset)); |
|
3132 |
if (xmm_shuf_mask != NULL) { |
|
3133 |
__ pshufb(xmmdst, xmm_shuf_mask); |
|
3134 |
} else { |
|
3135 |
__ pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
|
3136 |
} |
|
3137 |
} |
|
3138 |
||
35154 | 3139 |
// Utility routine for increase 128bit counter (iv in CTR mode) |
3140 |
void inc_counter(Register reg, XMMRegister xmmdst, int inc_delta, Label& next_block) { |
|
3141 |
__ pextrq(reg, xmmdst, 0x0); |
|
3142 |
__ addq(reg, inc_delta); |
|
3143 |
__ pinsrq(xmmdst, reg, 0x0); |
|
3144 |
__ jcc(Assembler::carryClear, next_block); // jump if no carry |
|
3145 |
__ pextrq(reg, xmmdst, 0x01); // Carry |
|
3146 |
__ addq(reg, 0x01); |
|
3147 |
__ pinsrq(xmmdst, reg, 0x01); //Carry end |
|
3148 |
__ BIND(next_block); // next instruction |
|
3149 |
} |
|
3150 |
||
14132 | 3151 |
// Arguments: |
3152 |
// |
|
3153 |
// Inputs: |
|
3154 |
// c_rarg0 - source byte array address |
|
3155 |
// c_rarg1 - destination byte array address |
|
3156 |
// c_rarg2 - K (key) in little endian int array |
|
3157 |
// |
|
3158 |
address generate_aescrypt_encryptBlock() { |
|
14834 | 3159 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
14132 | 3160 |
__ align(CodeEntryAlignment); |
3161 |
StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock"); |
|
3162 |
Label L_doLast; |
|
3163 |
address start = __ pc(); |
|
3164 |
||
3165 |
const Register from = c_rarg0; // source array address |
|
3166 |
const Register to = c_rarg1; // destination array address |
|
3167 |
const Register key = c_rarg2; // key array address |
|
3168 |
const Register keylen = rax; |
|
3169 |
||
3170 |
const XMMRegister xmm_result = xmm0; |
|
14834 | 3171 |
const XMMRegister xmm_key_shuf_mask = xmm1; |
3172 |
// On win64 xmm6-xmm15 must be preserved so don't use them. |
|
3173 |
const XMMRegister xmm_temp1 = xmm2; |
|
3174 |
const XMMRegister xmm_temp2 = xmm3; |
|
3175 |
const XMMRegister xmm_temp3 = xmm4; |
|
3176 |
const XMMRegister xmm_temp4 = xmm5; |
|
14132 | 3177 |
|
3178 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
3179 |
||
14834 | 3180 |
// keylen could be only {11, 13, 15} * 4 = {44, 52, 60} |
14132 | 3181 |
__ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
3182 |
||
3183 |
__ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
|
3184 |
__ movdqu(xmm_result, Address(from, 0)); // get 16 bytes of input |
|
3185 |
||
3186 |
// For encryption, the java expanded key ordering is just what we need |
|
3187 |
// we don't know if the key is aligned, hence not using load-execute form |
|
3188 |
||
14834 | 3189 |
load_key(xmm_temp1, key, 0x00, xmm_key_shuf_mask); |
3190 |
__ pxor(xmm_result, xmm_temp1); |
|
3191 |
||
3192 |
load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask); |
|
3193 |
load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask); |
|
3194 |
load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask); |
|
3195 |
load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask); |
|
3196 |
||
3197 |
__ aesenc(xmm_result, xmm_temp1); |
|
3198 |
__ aesenc(xmm_result, xmm_temp2); |
|
3199 |
__ aesenc(xmm_result, xmm_temp3); |
|
3200 |
__ aesenc(xmm_result, xmm_temp4); |
|
3201 |
||
3202 |
load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask); |
|
3203 |
load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask); |
|
3204 |
load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask); |
|
3205 |
load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask); |
|
3206 |
||
3207 |
__ aesenc(xmm_result, xmm_temp1); |
|
3208 |
__ aesenc(xmm_result, xmm_temp2); |
|
3209 |
__ aesenc(xmm_result, xmm_temp3); |
|
3210 |
__ aesenc(xmm_result, xmm_temp4); |
|
3211 |
||
3212 |
load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask); |
|
3213 |
load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask); |
|
3214 |
||
3215 |
__ cmpl(keylen, 44); |
|
3216 |
__ jccb(Assembler::equal, L_doLast); |
|
3217 |
||
3218 |
__ aesenc(xmm_result, xmm_temp1); |
|
3219 |
__ aesenc(xmm_result, xmm_temp2); |
|
3220 |
||
3221 |
load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask); |
|
3222 |
load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask); |
|
3223 |
||
3224 |
__ cmpl(keylen, 52); |
|
3225 |
__ jccb(Assembler::equal, L_doLast); |
|
3226 |
||
3227 |
__ aesenc(xmm_result, xmm_temp1); |
|
3228 |
__ aesenc(xmm_result, xmm_temp2); |
|
3229 |
||
3230 |
load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask); |
|
3231 |
load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask); |
|
14132 | 3232 |
|
3233 |
__ BIND(L_doLast); |
|
14834 | 3234 |
__ aesenc(xmm_result, xmm_temp1); |
3235 |
__ aesenclast(xmm_result, xmm_temp2); |
|
14132 | 3236 |
__ movdqu(Address(to, 0), xmm_result); // store the result |
3237 |
__ xorptr(rax, rax); // return 0 |
|
3238 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
3239 |
__ ret(0); |
|
3240 |
||
3241 |
return start; |
|
3242 |
} |
|
3243 |
||
3244 |
||
3245 |
// Arguments: |
|
3246 |
// |
|
3247 |
// Inputs: |
|
3248 |
// c_rarg0 - source byte array address |
|
3249 |
// c_rarg1 - destination byte array address |
|
3250 |
// c_rarg2 - K (key) in little endian int array |
|
3251 |
// |
|
3252 |
address generate_aescrypt_decryptBlock() { |
|
14834 | 3253 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
14132 | 3254 |
__ align(CodeEntryAlignment); |
3255 |
StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock"); |
|
3256 |
Label L_doLast; |
|
3257 |
address start = __ pc(); |
|
3258 |
||
3259 |
const Register from = c_rarg0; // source array address |
|
3260 |
const Register to = c_rarg1; // destination array address |
|
3261 |
const Register key = c_rarg2; // key array address |
|
3262 |
const Register keylen = rax; |
|
3263 |
||
3264 |
const XMMRegister xmm_result = xmm0; |
|
14834 | 3265 |
const XMMRegister xmm_key_shuf_mask = xmm1; |
3266 |
// On win64 xmm6-xmm15 must be preserved so don't use them. |
|
3267 |
const XMMRegister xmm_temp1 = xmm2; |
|
3268 |
const XMMRegister xmm_temp2 = xmm3; |
|
3269 |
const XMMRegister xmm_temp3 = xmm4; |
|
3270 |
const XMMRegister xmm_temp4 = xmm5; |
|
14132 | 3271 |
|
3272 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
3273 |
||
14834 | 3274 |
// keylen could be only {11, 13, 15} * 4 = {44, 52, 60} |
14132 | 3275 |
__ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
3276 |
||
3277 |
__ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
|
3278 |
__ movdqu(xmm_result, Address(from, 0)); |
|
3279 |
||
3280 |
// for decryption java expanded key ordering is rotated one position from what we want |
|
3281 |
// so we start from 0x10 here and hit 0x00 last |
|
3282 |
// we don't know if the key is aligned, hence not using load-execute form |
|
14834 | 3283 |
load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask); |
3284 |
load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask); |
|
3285 |
load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask); |
|
3286 |
load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask); |
|
3287 |
||
3288 |
__ pxor (xmm_result, xmm_temp1); |
|
3289 |
__ aesdec(xmm_result, xmm_temp2); |
|
3290 |
__ aesdec(xmm_result, xmm_temp3); |
|
3291 |
__ aesdec(xmm_result, xmm_temp4); |
|
3292 |
||
3293 |
load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask); |
|
3294 |
load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask); |
|
3295 |
load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask); |
|
3296 |
load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask); |
|
3297 |
||
3298 |
__ aesdec(xmm_result, xmm_temp1); |
|
3299 |
__ aesdec(xmm_result, xmm_temp2); |
|
3300 |
__ aesdec(xmm_result, xmm_temp3); |
|
3301 |
__ aesdec(xmm_result, xmm_temp4); |
|
3302 |
||
3303 |
load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask); |
|
3304 |
load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask); |
|
3305 |
load_key(xmm_temp3, key, 0x00, xmm_key_shuf_mask); |
|
3306 |
||
3307 |
__ cmpl(keylen, 44); |
|
3308 |
__ jccb(Assembler::equal, L_doLast); |
|
3309 |
||
3310 |
__ aesdec(xmm_result, xmm_temp1); |
|
3311 |
__ aesdec(xmm_result, xmm_temp2); |
|
3312 |
||
3313 |
load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask); |
|
3314 |
load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask); |
|
3315 |
||
3316 |
__ cmpl(keylen, 52); |
|
3317 |
__ jccb(Assembler::equal, L_doLast); |
|
3318 |
||
3319 |
__ aesdec(xmm_result, xmm_temp1); |
|
3320 |
__ aesdec(xmm_result, xmm_temp2); |
|
3321 |
||
3322 |
load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask); |
|
3323 |
load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask); |
|
14132 | 3324 |
|
3325 |
__ BIND(L_doLast); |
|
14834 | 3326 |
__ aesdec(xmm_result, xmm_temp1); |
3327 |
__ aesdec(xmm_result, xmm_temp2); |
|
3328 |
||
14132 | 3329 |
// for decryption the aesdeclast operation is always on key+0x00 |
14834 | 3330 |
__ aesdeclast(xmm_result, xmm_temp3); |
14132 | 3331 |
__ movdqu(Address(to, 0), xmm_result); // store the result |
3332 |
__ xorptr(rax, rax); // return 0 |
|
3333 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
3334 |
__ ret(0); |
|
3335 |
||
3336 |
return start; |
|
3337 |
} |
|
3338 |
||
3339 |
||
3340 |
// Arguments: |
|
3341 |
// |
|
3342 |
// Inputs: |
|
3343 |
// c_rarg0 - source byte array address |
|
3344 |
// c_rarg1 - destination byte array address |
|
3345 |
// c_rarg2 - K (key) in little endian int array |
|
3346 |
// c_rarg3 - r vector byte array address |
|
3347 |
// c_rarg4 - input length |
|
3348 |
// |
|
22505 | 3349 |
// Output: |
3350 |
// rax - input length |
|
3351 |
// |
|
14132 | 3352 |
address generate_cipherBlockChaining_encryptAESCrypt() { |
14834 | 3353 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
14132 | 3354 |
__ align(CodeEntryAlignment); |
3355 |
StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt"); |
|
3356 |
address start = __ pc(); |
|
3357 |
||
3358 |
Label L_exit, L_key_192_256, L_key_256, L_loopTop_128, L_loopTop_192, L_loopTop_256; |
|
3359 |
const Register from = c_rarg0; // source array address |
|
3360 |
const Register to = c_rarg1; // destination array address |
|
3361 |
const Register key = c_rarg2; // key array address |
|
3362 |
const Register rvec = c_rarg3; // r byte array initialized from initvector array address |
|
3363 |
// and left with the results of the last encryption block |
|
3364 |
#ifndef _WIN64 |
|
3365 |
const Register len_reg = c_rarg4; // src len (must be multiple of blocksize 16) |
|
3366 |
#else |
|
22505 | 3367 |
const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64 |
43423
bcaab17f72a5
8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents:
42618
diff
changeset
|
3368 |
const Register len_reg = r11; // pick the volatile windows register |
14132 | 3369 |
#endif |
3370 |
const Register pos = rax; |
|
3371 |
||
3372 |
// xmm register assignments for the loops below |
|
3373 |
const XMMRegister xmm_result = xmm0; |
|
3374 |
const XMMRegister xmm_temp = xmm1; |
|
3375 |
// keys 0-10 preloaded into xmm2-xmm12 |
|
3376 |
const int XMM_REG_NUM_KEY_FIRST = 2; |
|
14834 | 3377 |
const int XMM_REG_NUM_KEY_LAST = 15; |
14132 | 3378 |
const XMMRegister xmm_key0 = as_XMMRegister(XMM_REG_NUM_KEY_FIRST); |
14834 | 3379 |
const XMMRegister xmm_key10 = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+10); |
3380 |
const XMMRegister xmm_key11 = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+11); |
|
3381 |
const XMMRegister xmm_key12 = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+12); |
|
3382 |
const XMMRegister xmm_key13 = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+13); |
|
14132 | 3383 |
|
3384 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
3385 |
||
3386 |
#ifdef _WIN64 |
|
3387 |
// on win64, fill len_reg from stack position |
|
3388 |
__ movl(len_reg, len_mem); |
|
22505 | 3389 |
#else |
3390 |
__ push(len_reg); // Save |
|
14132 | 3391 |
#endif |
3392 |
||
3393 |
const XMMRegister xmm_key_shuf_mask = xmm_temp; // used temporarily to swap key bytes up front |
|
3394 |
__ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
|
14834 | 3395 |
// load up xmm regs xmm2 thru xmm12 with key 0x00 - 0xa0 |
3396 |
for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x00; rnum <= XMM_REG_NUM_KEY_FIRST+10; rnum++) { |
|
14132 | 3397 |
load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask); |
3398 |
offset += 0x10; |
|
3399 |
} |
|
3400 |
__ movdqu(xmm_result, Address(rvec, 0x00)); // initialize xmm_result with r vec |
|
3401 |
||
3402 |
// now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256)) |
|
3403 |
__ movl(rax, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
|
3404 |
__ cmpl(rax, 44); |
|
3405 |
__ jcc(Assembler::notEqual, L_key_192_256); |
|
3406 |
||
3407 |
// 128 bit code follows here |
|
3408 |
__ movptr(pos, 0); |
|
3409 |
__ align(OptoLoopAlignment); |
|
14834 | 3410 |
|
14132 | 3411 |
__ BIND(L_loopTop_128); |
3412 |
__ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of input |
|
3413 |
__ pxor (xmm_result, xmm_temp); // xor with the current r vector |
|
3414 |
__ pxor (xmm_result, xmm_key0); // do the aes rounds |
|
14834 | 3415 |
for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_FIRST + 9; rnum++) { |
14132 | 3416 |
__ aesenc(xmm_result, as_XMMRegister(rnum)); |
3417 |
} |
|
3418 |
__ aesenclast(xmm_result, xmm_key10); |
|
3419 |
__ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output |
|
3420 |
// no need to store r to memory until we exit |
|
3421 |
__ addptr(pos, AESBlockSize); |
|
3422 |
__ subptr(len_reg, AESBlockSize); |
|
3423 |
__ jcc(Assembler::notEqual, L_loopTop_128); |
|
3424 |
||
3425 |
__ BIND(L_exit); |
|
3426 |
__ movdqu(Address(rvec, 0), xmm_result); // final value of r stored in rvec of CipherBlockChaining object |
|
3427 |
||
3428 |
#ifdef _WIN64 |
|
22505 | 3429 |
__ movl(rax, len_mem); |
3430 |
#else |
|
3431 |
__ pop(rax); // return length |
|
14132 | 3432 |
#endif |
3433 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
3434 |
__ ret(0); |
|
3435 |
||
3436 |
__ BIND(L_key_192_256); |
|
3437 |
// here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256) |
|
14834 | 3438 |
load_key(xmm_key11, key, 0xb0, xmm_key_shuf_mask); |
3439 |
load_key(xmm_key12, key, 0xc0, xmm_key_shuf_mask); |
|
14132 | 3440 |
__ cmpl(rax, 52); |
3441 |
__ jcc(Assembler::notEqual, L_key_256); |
|
3442 |
||
3443 |
// 192-bit code follows here (could be changed to use more xmm registers) |
|
3444 |
__ movptr(pos, 0); |
|
3445 |
__ align(OptoLoopAlignment); |
|
14834 | 3446 |
|
14132 | 3447 |
__ BIND(L_loopTop_192); |
3448 |
__ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of input |
|
3449 |
__ pxor (xmm_result, xmm_temp); // xor with the current r vector |
|
3450 |
__ pxor (xmm_result, xmm_key0); // do the aes rounds |
|
14834 | 3451 |
for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_FIRST + 11; rnum++) { |
14132 | 3452 |
__ aesenc(xmm_result, as_XMMRegister(rnum)); |
3453 |
} |
|
14834 | 3454 |
__ aesenclast(xmm_result, xmm_key12); |
14132 | 3455 |
__ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output |
3456 |
// no need to store r to memory until we exit |
|
3457 |
__ addptr(pos, AESBlockSize); |
|
3458 |
__ subptr(len_reg, AESBlockSize); |
|
3459 |
__ jcc(Assembler::notEqual, L_loopTop_192); |
|
3460 |
__ jmp(L_exit); |
|
3461 |
||
3462 |
__ BIND(L_key_256); |
|
3463 |
// 256-bit code follows here (could be changed to use more xmm registers) |
|
14834 | 3464 |
load_key(xmm_key13, key, 0xd0, xmm_key_shuf_mask); |
14132 | 3465 |
__ movptr(pos, 0); |
3466 |
__ align(OptoLoopAlignment); |
|
14834 | 3467 |
|
14132 | 3468 |
__ BIND(L_loopTop_256); |
3469 |
__ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of input |
|
3470 |
__ pxor (xmm_result, xmm_temp); // xor with the current r vector |
|
3471 |
__ pxor (xmm_result, xmm_key0); // do the aes rounds |
|
14834 | 3472 |
for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_FIRST + 13; rnum++) { |
14132 | 3473 |
__ aesenc(xmm_result, as_XMMRegister(rnum)); |
3474 |
} |
|
3475 |
load_key(xmm_temp, key, 0xe0); |
|
3476 |
__ aesenclast(xmm_result, xmm_temp); |
|
3477 |
__ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output |
|
3478 |
// no need to store r to memory until we exit |
|
3479 |
__ addptr(pos, AESBlockSize); |
|
3480 |
__ subptr(len_reg, AESBlockSize); |
|
3481 |
__ jcc(Assembler::notEqual, L_loopTop_256); |
|
3482 |
__ jmp(L_exit); |
|
3483 |
||
3484 |
return start; |
|
3485 |
} |
|
3486 |
||
18740 | 3487 |
// Safefetch stubs. |
3488 |
void generate_safefetch(const char* name, int size, address* entry, |
|
3489 |
address* fault_pc, address* continuation_pc) { |
|
3490 |
// safefetch signatures: |
|
3491 |
// int SafeFetch32(int* adr, int errValue); |
|
3492 |
// intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue); |
|
3493 |
// |
|
3494 |
// arguments: |
|
3495 |
// c_rarg0 = adr |
|
3496 |
// c_rarg1 = errValue |
|
3497 |
// |
|
3498 |
// result: |
|
3499 |
// PPC_RET = *adr or errValue |
|
3500 |
||
3501 |
StubCodeMark mark(this, "StubRoutines", name); |
|
3502 |
||
3503 |
// Entry point, pc or function descriptor. |
|
3504 |
*entry = __ pc(); |
|
3505 |
||
3506 |
// Load *adr into c_rarg1, may fault. |
|
3507 |
*fault_pc = __ pc(); |
|
3508 |
switch (size) { |
|
3509 |
case 4: |
|
3510 |
// int32_t |
|
3511 |
__ movl(c_rarg1, Address(c_rarg0, 0)); |
|
3512 |
break; |
|
3513 |
case 8: |
|
3514 |
// int64_t |
|
3515 |
__ movq(c_rarg1, Address(c_rarg0, 0)); |
|
3516 |
break; |
|
3517 |
default: |
|
3518 |
ShouldNotReachHere(); |
|
3519 |
} |
|
3520 |
||
3521 |
// return errValue or *adr |
|
3522 |
*continuation_pc = __ pc(); |
|
3523 |
__ movq(rax, c_rarg1); |
|
3524 |
__ ret(0); |
|
3525 |
} |
|
14132 | 3526 |
|
3527 |
// This is a version of CBC/AES Decrypt which does 4 blocks in a loop at a time |
|
3528 |
// to hide instruction latency |
|
3529 |
// |
|
3530 |
// Arguments: |
|
3531 |
// |
|
3532 |
// Inputs: |
|
3533 |
// c_rarg0 - source byte array address |
|
3534 |
// c_rarg1 - destination byte array address |
|
3535 |
// c_rarg2 - K (key) in little endian int array |
|
3536 |
// c_rarg3 - r vector byte array address |
|
3537 |
// c_rarg4 - input length |
|
3538 |
// |
|
22505 | 3539 |
// Output: |
3540 |
// rax - input length |
|
3541 |
// |
|
14132 | 3542 |
address generate_cipherBlockChaining_decryptAESCrypt_Parallel() { |
14834 | 3543 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
14132 | 3544 |
__ align(CodeEntryAlignment); |
3545 |
StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt"); |
|
3546 |
address start = __ pc(); |
|
3547 |
||
3548 |
const Register from = c_rarg0; // source array address |
|
3549 |
const Register to = c_rarg1; // destination array address |
|
3550 |
const Register key = c_rarg2; // key array address |
|
3551 |
const Register rvec = c_rarg3; // r byte array initialized from initvector array address |
|
3552 |
// and left with the results of the last encryption block |
|
3553 |
#ifndef _WIN64 |
|
3554 |
const Register len_reg = c_rarg4; // src len (must be multiple of blocksize 16) |
|
3555 |
#else |
|
22505 | 3556 |
const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64 |
43423
bcaab17f72a5
8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents:
42618
diff
changeset
|
3557 |
const Register len_reg = r11; // pick the volatile windows register |
14132 | 3558 |
#endif |
3559 |
const Register pos = rax; |
|
3560 |
||
36825 | 3561 |
const int PARALLEL_FACTOR = 4; |
3562 |
const int ROUNDS[3] = { 10, 12, 14 }; // aes rounds for key128, key192, key256 |
|
3563 |
||
3564 |
Label L_exit; |
|
3565 |
Label L_singleBlock_loopTopHead[3]; // 128, 192, 256 |
|
3566 |
Label L_singleBlock_loopTopHead2[3]; // 128, 192, 256 |
|
3567 |
Label L_singleBlock_loopTop[3]; // 128, 192, 256 |
|
3568 |
Label L_multiBlock_loopTopHead[3]; // 128, 192, 256 |
|
3569 |
Label L_multiBlock_loopTop[3]; // 128, 192, 256 |
|
3570 |
||
3571 |
// keys 0-10 preloaded into xmm5-xmm15 |
|
14132 | 3572 |
const int XMM_REG_NUM_KEY_FIRST = 5; |
3573 |
const int XMM_REG_NUM_KEY_LAST = 15; |
|
14834 | 3574 |
const XMMRegister xmm_key_first = as_XMMRegister(XMM_REG_NUM_KEY_FIRST); |
14132 | 3575 |
const XMMRegister xmm_key_last = as_XMMRegister(XMM_REG_NUM_KEY_LAST); |
3576 |
||
3577 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
3578 |
||
3579 |
#ifdef _WIN64 |
|
3580 |
// on win64, fill len_reg from stack position |
|
3581 |
__ movl(len_reg, len_mem); |
|
22505 | 3582 |
#else |
3583 |
__ push(len_reg); // Save |
|
14132 | 3584 |
#endif |
36825 | 3585 |
__ push(rbx); |
14132 | 3586 |
// the java expanded key ordering is rotated one position from what we want |
3587 |
// so we start from 0x10 here and hit 0x00 last |
|
3588 |
const XMMRegister xmm_key_shuf_mask = xmm1; // used temporarily to swap key bytes up front |
|
3589 |
__ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
|
3590 |
// load up xmm regs 5 thru 15 with key 0x10 - 0xa0 - 0x00 |
|
14834 | 3591 |
for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x10; rnum < XMM_REG_NUM_KEY_LAST; rnum++) { |
14132 | 3592 |
load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask); |
3593 |
offset += 0x10; |
|
3594 |
} |
|
14834 | 3595 |
load_key(xmm_key_last, key, 0x00, xmm_key_shuf_mask); |
14132 | 3596 |
|
3597 |
const XMMRegister xmm_prev_block_cipher = xmm1; // holds cipher of previous block |
|
14834 | 3598 |
|
14132 | 3599 |
// registers holding the four results in the parallelized loop |
3600 |
const XMMRegister xmm_result0 = xmm0; |
|
3601 |
const XMMRegister xmm_result1 = xmm2; |
|
3602 |
const XMMRegister xmm_result2 = xmm3; |
|
3603 |
const XMMRegister xmm_result3 = xmm4; |
|
3604 |
||
3605 |
__ movdqu(xmm_prev_block_cipher, Address(rvec, 0x00)); // initialize with initial rvec |
|
3606 |
||
36825 | 3607 |
__ xorptr(pos, pos); |
3608 |
||
14132 | 3609 |
// now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256)) |
36825 | 3610 |
__ movl(rbx, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
3611 |
__ cmpl(rbx, 52); |
|
3612 |
__ jcc(Assembler::equal, L_multiBlock_loopTopHead[1]); |
|
3613 |
__ cmpl(rbx, 60); |
|
3614 |
__ jcc(Assembler::equal, L_multiBlock_loopTopHead[2]); |
|
3615 |
||
3616 |
#define DoFour(opc, src_reg) \ |
|
3617 |
__ opc(xmm_result0, src_reg); \ |
|
3618 |
__ opc(xmm_result1, src_reg); \ |
|
3619 |
__ opc(xmm_result2, src_reg); \ |
|
3620 |
__ opc(xmm_result3, src_reg); \ |
|
3621 |
||
3622 |
for (int k = 0; k < 3; ++k) { |
|
3623 |
__ BIND(L_multiBlock_loopTopHead[k]); |
|
3624 |
if (k != 0) { |
|
3625 |
__ cmpptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // see if at least 4 blocks left |
|
3626 |
__ jcc(Assembler::less, L_singleBlock_loopTopHead2[k]); |
|
3627 |
} |
|
3628 |
if (k == 1) { |
|
3629 |
__ subptr(rsp, 6 * wordSize); |
|
3630 |
__ movdqu(Address(rsp, 0), xmm15); //save last_key from xmm15 |
|
3631 |
load_key(xmm15, key, 0xb0); // 0xb0; 192-bit key goes up to 0xc0 |
|
3632 |
__ movdqu(Address(rsp, 2 * wordSize), xmm15); |
|
3633 |
load_key(xmm1, key, 0xc0); // 0xc0; |
|
3634 |
__ movdqu(Address(rsp, 4 * wordSize), xmm1); |
|
3635 |
} else if (k == 2) { |
|
3636 |
__ subptr(rsp, 10 * wordSize); |
|
3637 |
__ movdqu(Address(rsp, 0), xmm15); //save last_key from xmm15 |
|
3638 |
load_key(xmm15, key, 0xd0); // 0xd0; 256-bit key goes upto 0xe0 |
|
3639 |
__ movdqu(Address(rsp, 6 * wordSize), xmm15); |
|
3640 |
load_key(xmm1, key, 0xe0); // 0xe0; |
|
3641 |
__ movdqu(Address(rsp, 8 * wordSize), xmm1); |
|
3642 |
load_key(xmm15, key, 0xb0); // 0xb0; |
|
3643 |
__ movdqu(Address(rsp, 2 * wordSize), xmm15); |
|
3644 |
load_key(xmm1, key, 0xc0); // 0xc0; |
|
3645 |
__ movdqu(Address(rsp, 4 * wordSize), xmm1); |
|
3646 |
} |
|
3647 |
__ align(OptoLoopAlignment); |
|
3648 |
__ BIND(L_multiBlock_loopTop[k]); |
|
3649 |
__ cmpptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // see if at least 4 blocks left |
|
3650 |
__ jcc(Assembler::less, L_singleBlock_loopTopHead[k]); |
|
3651 |
||
3652 |
if (k != 0) { |
|
3653 |
__ movdqu(xmm15, Address(rsp, 2 * wordSize)); |
|
3654 |
__ movdqu(xmm1, Address(rsp, 4 * wordSize)); |
|
3655 |
} |
|
3656 |
||
3657 |
__ movdqu(xmm_result0, Address(from, pos, Address::times_1, 0 * AESBlockSize)); // get next 4 blocks into xmmresult registers |
|
3658 |
__ movdqu(xmm_result1, Address(from, pos, Address::times_1, 1 * AESBlockSize)); |
|
3659 |
__ movdqu(xmm_result2, Address(from, pos, Address::times_1, 2 * AESBlockSize)); |
|
3660 |
__ movdqu(xmm_result3, Address(from, pos, Address::times_1, 3 * AESBlockSize)); |
|
3661 |
||
3662 |
DoFour(pxor, xmm_key_first); |
|
3663 |
if (k == 0) { |
|
3664 |
for (int rnum = 1; rnum < ROUNDS[k]; rnum++) { |
|
3665 |
DoFour(aesdec, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST)); |
|
3666 |
} |
|
3667 |
DoFour(aesdeclast, xmm_key_last); |
|
3668 |
} else if (k == 1) { |
|
3669 |
for (int rnum = 1; rnum <= ROUNDS[k]-2; rnum++) { |
|
3670 |
DoFour(aesdec, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST)); |
|
3671 |
} |
|
3672 |
__ movdqu(xmm_key_last, Address(rsp, 0)); // xmm15 needs to be loaded again. |
|
3673 |
DoFour(aesdec, xmm1); // key : 0xc0 |
|
3674 |
__ movdqu(xmm_prev_block_cipher, Address(rvec, 0x00)); // xmm1 needs to be loaded again |
|
3675 |
DoFour(aesdeclast, xmm_key_last); |
|
3676 |
} else if (k == 2) { |
|
3677 |
for (int rnum = 1; rnum <= ROUNDS[k] - 4; rnum++) { |
|
3678 |
DoFour(aesdec, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST)); |
|
3679 |
} |
|
3680 |
DoFour(aesdec, xmm1); // key : 0xc0 |
|
3681 |
__ movdqu(xmm15, Address(rsp, 6 * wordSize)); |
|
3682 |
__ movdqu(xmm1, Address(rsp, 8 * wordSize)); |
|
3683 |
DoFour(aesdec, xmm15); // key : 0xd0 |
|
3684 |
__ movdqu(xmm_key_last, Address(rsp, 0)); // xmm15 needs to be loaded again. |
|
3685 |
DoFour(aesdec, xmm1); // key : 0xe0 |
|
3686 |
__ movdqu(xmm_prev_block_cipher, Address(rvec, 0x00)); // xmm1 needs to be loaded again |
|
3687 |
DoFour(aesdeclast, xmm_key_last); |
|
3688 |
} |
|
3689 |
||
3690 |
// for each result, xor with the r vector of previous cipher block |
|
3691 |
__ pxor(xmm_result0, xmm_prev_block_cipher); |
|
3692 |
__ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 0 * AESBlockSize)); |
|
3693 |
__ pxor(xmm_result1, xmm_prev_block_cipher); |
|
3694 |
__ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 1 * AESBlockSize)); |
|
3695 |
__ pxor(xmm_result2, xmm_prev_block_cipher); |
|
3696 |
__ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 2 * AESBlockSize)); |
|
3697 |
__ pxor(xmm_result3, xmm_prev_block_cipher); |
|
3698 |
__ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 3 * AESBlockSize)); // this will carry over to next set of blocks |
|
3699 |
if (k != 0) { |
|
3700 |
__ movdqu(Address(rvec, 0x00), xmm_prev_block_cipher); |
|
3701 |
} |
|
3702 |
||
3703 |
__ movdqu(Address(to, pos, Address::times_1, 0 * AESBlockSize), xmm_result0); // store 4 results into the next 64 bytes of output |
|
3704 |
__ movdqu(Address(to, pos, Address::times_1, 1 * AESBlockSize), xmm_result1); |
|
3705 |
__ movdqu(Address(to, pos, Address::times_1, 2 * AESBlockSize), xmm_result2); |
|
3706 |
__ movdqu(Address(to, pos, Address::times_1, 3 * AESBlockSize), xmm_result3); |
|
3707 |
||
3708 |
__ addptr(pos, PARALLEL_FACTOR * AESBlockSize); |
|
3709 |
__ subptr(len_reg, PARALLEL_FACTOR * AESBlockSize); |
|
3710 |
__ jmp(L_multiBlock_loopTop[k]); |
|
3711 |
||
3712 |
// registers used in the non-parallelized loops |
|
3713 |
// xmm register assignments for the loops below |
|
3714 |
const XMMRegister xmm_result = xmm0; |
|
3715 |
const XMMRegister xmm_prev_block_cipher_save = xmm2; |
|
3716 |
const XMMRegister xmm_key11 = xmm3; |
|
3717 |
const XMMRegister xmm_key12 = xmm4; |
|
3718 |
const XMMRegister key_tmp = xmm4; |
|
3719 |
||
3720 |
__ BIND(L_singleBlock_loopTopHead[k]); |
|
3721 |
if (k == 1) { |
|
3722 |
__ addptr(rsp, 6 * wordSize); |
|
3723 |
} else if (k == 2) { |
|
3724 |
__ addptr(rsp, 10 * wordSize); |
|
3725 |
} |
|
3726 |
__ cmpptr(len_reg, 0); // any blocks left?? |
|
3727 |
__ jcc(Assembler::equal, L_exit); |
|
3728 |
__ BIND(L_singleBlock_loopTopHead2[k]); |
|
3729 |
if (k == 1) { |
|
3730 |
load_key(xmm_key11, key, 0xb0); // 0xb0; 192-bit key goes upto 0xc0 |
|
3731 |
load_key(xmm_key12, key, 0xc0); // 0xc0; 192-bit key goes upto 0xc0 |
|
3732 |
} |
|
3733 |
if (k == 2) { |
|
3734 |
load_key(xmm_key11, key, 0xb0); // 0xb0; 256-bit key goes upto 0xe0 |
|
3735 |
} |
|
3736 |
__ align(OptoLoopAlignment); |
|
3737 |
__ BIND(L_singleBlock_loopTop[k]); |
|
3738 |
__ movdqu(xmm_result, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of cipher input |
|
3739 |
__ movdqa(xmm_prev_block_cipher_save, xmm_result); // save for next r vector |
|
3740 |
__ pxor(xmm_result, xmm_key_first); // do the aes dec rounds |
|
3741 |
for (int rnum = 1; rnum <= 9 ; rnum++) { |
|
3742 |
__ aesdec(xmm_result, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST)); |
|
3743 |
} |
|
3744 |
if (k == 1) { |
|
3745 |
__ aesdec(xmm_result, xmm_key11); |
|
3746 |
__ aesdec(xmm_result, xmm_key12); |
|
3747 |
} |
|
3748 |
if (k == 2) { |
|
3749 |
__ aesdec(xmm_result, xmm_key11); |
|
3750 |
load_key(key_tmp, key, 0xc0); |
|
3751 |
__ aesdec(xmm_result, key_tmp); |
|
3752 |
load_key(key_tmp, key, 0xd0); |
|
3753 |
__ aesdec(xmm_result, key_tmp); |
|
3754 |
load_key(key_tmp, key, 0xe0); |
|
3755 |
__ aesdec(xmm_result, key_tmp); |
|
3756 |
} |
|
3757 |
||
3758 |
__ aesdeclast(xmm_result, xmm_key_last); // xmm15 always came from key+0 |
|
3759 |
__ pxor(xmm_result, xmm_prev_block_cipher); // xor with the current r vector |
|
3760 |
__ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output |
|
3761 |
// no need to store r to memory until we exit |
|
3762 |
__ movdqa(xmm_prev_block_cipher, xmm_prev_block_cipher_save); // set up next r vector with cipher input from this block |
|
3763 |
__ addptr(pos, AESBlockSize); |
|
3764 |
__ subptr(len_reg, AESBlockSize); |
|
3765 |
__ jcc(Assembler::notEqual, L_singleBlock_loopTop[k]); |
|
3766 |
if (k != 2) { |
|
3767 |
__ jmp(L_exit); |
|
3768 |
} |
|
3769 |
} //for 128/192/256 |
|
14132 | 3770 |
|
3771 |
__ BIND(L_exit); |
|
3772 |
__ movdqu(Address(rvec, 0), xmm_prev_block_cipher); // final value of r stored in rvec of CipherBlockChaining object |
|
36825 | 3773 |
__ pop(rbx); |
14132 | 3774 |
#ifdef _WIN64 |
22505 | 3775 |
__ movl(rax, len_mem); |
3776 |
#else |
|
3777 |
__ pop(rax); // return length |
|
14132 | 3778 |
#endif |
3779 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
3780 |
__ ret(0); |
|
3781 |
return start; |
|
36825 | 3782 |
} |
14132 | 3783 |
|
57786
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3784 |
address generate_electronicCodeBook_encryptAESCrypt() { |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3785 |
__ align(CodeEntryAlignment); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3786 |
StubCodeMark mark(this, "StubRoutines", "electronicCodeBook_encryptAESCrypt"); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3787 |
address start = __ pc(); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3788 |
const Register from = c_rarg0; // source array address |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3789 |
const Register to = c_rarg1; // destination array address |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3790 |
const Register key = c_rarg2; // key array address |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3791 |
const Register len = c_rarg3; // src len (must be multiple of blocksize 16) |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3792 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3793 |
__ aesecb_encrypt(from, to, key, len); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3794 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3795 |
__ ret(0); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3796 |
return start; |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3797 |
} |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3798 |
|
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3799 |
address generate_electronicCodeBook_decryptAESCrypt() { |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3800 |
__ align(CodeEntryAlignment); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3801 |
StubCodeMark mark(this, "StubRoutines", "electronicCodeBook_decryptAESCrypt"); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3802 |
address start = __ pc(); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3803 |
const Register from = c_rarg0; // source array address |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3804 |
const Register to = c_rarg1; // destination array address |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3805 |
const Register key = c_rarg2; // key array address |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3806 |
const Register len = c_rarg3; // src len (must be multiple of blocksize 16) |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3807 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3808 |
__ aesecb_decrypt(from, to, key, len); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3809 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3810 |
__ ret(0); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3811 |
return start; |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3812 |
} |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
3813 |
|
36555 | 3814 |
address generate_upper_word_mask() { |
3815 |
__ align(64); |
|
3816 |
StubCodeMark mark(this, "StubRoutines", "upper_word_mask"); |
|
3817 |
address start = __ pc(); |
|
3818 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
|
3819 |
__ emit_data64(0xFFFFFFFF00000000, relocInfo::none); |
|
3820 |
return start; |
|
3821 |
} |
|
3822 |
||
3823 |
address generate_shuffle_byte_flip_mask() { |
|
3824 |
__ align(64); |
|
3825 |
StubCodeMark mark(this, "StubRoutines", "shuffle_byte_flip_mask"); |
|
3826 |
address start = __ pc(); |
|
3827 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); |
|
3828 |
__ emit_data64(0x0001020304050607, relocInfo::none); |
|
3829 |
return start; |
|
3830 |
} |
|
3831 |
||
3832 |
// ofs and limit are use for multi-block byte array. |
|
3833 |
// int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit) |
|
3834 |
address generate_sha1_implCompress(bool multi_block, const char *name) { |
|
3835 |
__ align(CodeEntryAlignment); |
|
3836 |
StubCodeMark mark(this, "StubRoutines", name); |
|
3837 |
address start = __ pc(); |
|
3838 |
||
3839 |
Register buf = c_rarg0; |
|
3840 |
Register state = c_rarg1; |
|
3841 |
Register ofs = c_rarg2; |
|
3842 |
Register limit = c_rarg3; |
|
3843 |
||
3844 |
const XMMRegister abcd = xmm0; |
|
3845 |
const XMMRegister e0 = xmm1; |
|
3846 |
const XMMRegister e1 = xmm2; |
|
3847 |
const XMMRegister msg0 = xmm3; |
|
3848 |
||
3849 |
const XMMRegister msg1 = xmm4; |
|
3850 |
const XMMRegister msg2 = xmm5; |
|
3851 |
const XMMRegister msg3 = xmm6; |
|
3852 |
const XMMRegister shuf_mask = xmm7; |
|
3853 |
||
3854 |
__ enter(); |
|
3855 |
||
3856 |
__ subptr(rsp, 4 * wordSize); |
|
3857 |
||
3858 |
__ fast_sha1(abcd, e0, e1, msg0, msg1, msg2, msg3, shuf_mask, |
|
3859 |
buf, state, ofs, limit, rsp, multi_block); |
|
3860 |
||
3861 |
__ addptr(rsp, 4 * wordSize); |
|
3862 |
||
3863 |
__ leave(); |
|
3864 |
__ ret(0); |
|
3865 |
return start; |
|
3866 |
} |
|
3867 |
||
3868 |
address generate_pshuffle_byte_flip_mask() { |
|
3869 |
__ align(64); |
|
3870 |
StubCodeMark mark(this, "StubRoutines", "pshuffle_byte_flip_mask"); |
|
3871 |
address start = __ pc(); |
|
3872 |
__ emit_data64(0x0405060700010203, relocInfo::none); |
|
3873 |
__ emit_data64(0x0c0d0e0f08090a0b, relocInfo::none); |
|
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3874 |
|
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3875 |
if (VM_Version::supports_avx2()) { |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3876 |
__ emit_data64(0x0405060700010203, relocInfo::none); // second copy |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3877 |
__ emit_data64(0x0c0d0e0f08090a0b, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3878 |
// _SHUF_00BA |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3879 |
__ emit_data64(0x0b0a090803020100, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3880 |
__ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3881 |
__ emit_data64(0x0b0a090803020100, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3882 |
__ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3883 |
// _SHUF_DC00 |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3884 |
__ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3885 |
__ emit_data64(0x0b0a090803020100, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3886 |
__ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3887 |
__ emit_data64(0x0b0a090803020100, relocInfo::none); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3888 |
} |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3889 |
|
36555 | 3890 |
return start; |
3891 |
} |
|
3892 |
||
42039 | 3893 |
//Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb. |
3894 |
address generate_pshuffle_byte_flip_mask_sha512() { |
|
3895 |
__ align(32); |
|
3896 |
StubCodeMark mark(this, "StubRoutines", "pshuffle_byte_flip_mask_sha512"); |
|
3897 |
address start = __ pc(); |
|
3898 |
if (VM_Version::supports_avx2()) { |
|
3899 |
__ emit_data64(0x0001020304050607, relocInfo::none); // PSHUFFLE_BYTE_FLIP_MASK |
|
3900 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); |
|
3901 |
__ emit_data64(0x1011121314151617, relocInfo::none); |
|
3902 |
__ emit_data64(0x18191a1b1c1d1e1f, relocInfo::none); |
|
3903 |
__ emit_data64(0x0000000000000000, relocInfo::none); //MASK_YMM_LO |
|
3904 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
|
3905 |
__ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none); |
|
3906 |
__ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none); |
|
3907 |
} |
|
3908 |
||
3909 |
return start; |
|
3910 |
} |
|
3911 |
||
36555 | 3912 |
// ofs and limit are use for multi-block byte array. |
3913 |
// int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit) |
|
3914 |
address generate_sha256_implCompress(bool multi_block, const char *name) { |
|
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3915 |
assert(VM_Version::supports_sha() || VM_Version::supports_avx2(), ""); |
36555 | 3916 |
__ align(CodeEntryAlignment); |
3917 |
StubCodeMark mark(this, "StubRoutines", name); |
|
3918 |
address start = __ pc(); |
|
3919 |
||
3920 |
Register buf = c_rarg0; |
|
3921 |
Register state = c_rarg1; |
|
3922 |
Register ofs = c_rarg2; |
|
3923 |
Register limit = c_rarg3; |
|
3924 |
||
3925 |
const XMMRegister msg = xmm0; |
|
3926 |
const XMMRegister state0 = xmm1; |
|
3927 |
const XMMRegister state1 = xmm2; |
|
3928 |
const XMMRegister msgtmp0 = xmm3; |
|
3929 |
||
3930 |
const XMMRegister msgtmp1 = xmm4; |
|
3931 |
const XMMRegister msgtmp2 = xmm5; |
|
3932 |
const XMMRegister msgtmp3 = xmm6; |
|
3933 |
const XMMRegister msgtmp4 = xmm7; |
|
3934 |
||
3935 |
const XMMRegister shuf_mask = xmm8; |
|
3936 |
||
3937 |
__ enter(); |
|
3938 |
||
3939 |
__ subptr(rsp, 4 * wordSize); |
|
3940 |
||
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3941 |
if (VM_Version::supports_sha()) { |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3942 |
__ fast_sha256(msg, state0, state1, msgtmp0, msgtmp1, msgtmp2, msgtmp3, msgtmp4, |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3943 |
buf, state, ofs, limit, rsp, multi_block, shuf_mask); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3944 |
} else if (VM_Version::supports_avx2()) { |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3945 |
__ sha256_AVX2(msg, state0, state1, msgtmp0, msgtmp1, msgtmp2, msgtmp3, msgtmp4, |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3946 |
buf, state, ofs, limit, rsp, multi_block, shuf_mask); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
3947 |
} |
36555 | 3948 |
__ addptr(rsp, 4 * wordSize); |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
3949 |
__ vzeroupper(); |
36555 | 3950 |
__ leave(); |
3951 |
__ ret(0); |
|
3952 |
return start; |
|
3953 |
} |
|
3954 |
||
42039 | 3955 |
address generate_sha512_implCompress(bool multi_block, const char *name) { |
3956 |
assert(VM_Version::supports_avx2(), ""); |
|
3957 |
assert(VM_Version::supports_bmi2(), ""); |
|
3958 |
__ align(CodeEntryAlignment); |
|
3959 |
StubCodeMark mark(this, "StubRoutines", name); |
|
3960 |
address start = __ pc(); |
|
3961 |
||
3962 |
Register buf = c_rarg0; |
|
3963 |
Register state = c_rarg1; |
|
3964 |
Register ofs = c_rarg2; |
|
3965 |
Register limit = c_rarg3; |
|
3966 |
||
3967 |
const XMMRegister msg = xmm0; |
|
3968 |
const XMMRegister state0 = xmm1; |
|
3969 |
const XMMRegister state1 = xmm2; |
|
3970 |
const XMMRegister msgtmp0 = xmm3; |
|
3971 |
const XMMRegister msgtmp1 = xmm4; |
|
3972 |
const XMMRegister msgtmp2 = xmm5; |
|
3973 |
const XMMRegister msgtmp3 = xmm6; |
|
3974 |
const XMMRegister msgtmp4 = xmm7; |
|
3975 |
||
3976 |
const XMMRegister shuf_mask = xmm8; |
|
3977 |
||
3978 |
__ enter(); |
|
3979 |
||
3980 |
__ sha512_AVX2(msg, state0, state1, msgtmp0, msgtmp1, msgtmp2, msgtmp3, msgtmp4, |
|
3981 |
buf, state, ofs, limit, rsp, multi_block, shuf_mask); |
|
3982 |
||
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
3983 |
__ vzeroupper(); |
42039 | 3984 |
__ leave(); |
3985 |
__ ret(0); |
|
3986 |
return start; |
|
3987 |
} |
|
3988 |
||
58977
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3989 |
// This mask is used for incrementing counter value(linc0, linc4, etc.) |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3990 |
address counter_mask_addr() { |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3991 |
__ align(64); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3992 |
StubCodeMark mark(this, "StubRoutines", "counter_mask_addr"); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3993 |
address start = __ pc(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3994 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none);//lbswapmask |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3995 |
__ emit_data64(0x0001020304050607, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3996 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3997 |
__ emit_data64(0x0001020304050607, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3998 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
3999 |
__ emit_data64(0x0001020304050607, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4000 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4001 |
__ emit_data64(0x0001020304050607, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4002 |
__ emit_data64(0x0000000000000000, relocInfo::none);//linc0 = counter_mask_addr+64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4003 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4004 |
__ emit_data64(0x0000000000000001, relocInfo::none);//counter_mask_addr() + 80 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4005 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4006 |
__ emit_data64(0x0000000000000002, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4007 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4008 |
__ emit_data64(0x0000000000000003, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4009 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4010 |
__ emit_data64(0x0000000000000004, relocInfo::none);//linc4 = counter_mask_addr() + 128 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4011 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4012 |
__ emit_data64(0x0000000000000004, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4013 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4014 |
__ emit_data64(0x0000000000000004, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4015 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4016 |
__ emit_data64(0x0000000000000004, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4017 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4018 |
__ emit_data64(0x0000000000000008, relocInfo::none);//linc8 = counter_mask_addr() + 192 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4019 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4020 |
__ emit_data64(0x0000000000000008, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4021 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4022 |
__ emit_data64(0x0000000000000008, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4023 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4024 |
__ emit_data64(0x0000000000000008, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4025 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4026 |
__ emit_data64(0x0000000000000020, relocInfo::none);//linc32 = counter_mask_addr() + 256 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4027 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4028 |
__ emit_data64(0x0000000000000020, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4029 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4030 |
__ emit_data64(0x0000000000000020, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4031 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4032 |
__ emit_data64(0x0000000000000020, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4033 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4034 |
__ emit_data64(0x0000000000000010, relocInfo::none);//linc16 = counter_mask_addr() + 320 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4035 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4036 |
__ emit_data64(0x0000000000000010, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4037 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4038 |
__ emit_data64(0x0000000000000010, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4039 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4040 |
__ emit_data64(0x0000000000000010, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4041 |
__ emit_data64(0x0000000000000000, relocInfo::none); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4042 |
return start; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4043 |
} |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4044 |
|
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4045 |
// Vector AES Counter implementation |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4046 |
address generate_counterMode_VectorAESCrypt() { |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4047 |
__ align(CodeEntryAlignment); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4048 |
StubCodeMark mark(this, "StubRoutines", "counterMode_AESCrypt"); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4049 |
address start = __ pc(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4050 |
const Register from = c_rarg0; // source array address |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4051 |
const Register to = c_rarg1; // destination array address |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4052 |
const Register key = c_rarg2; // key array address r8 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4053 |
const Register counter = c_rarg3; // counter byte array initialized from counter array address |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4054 |
// and updated with the incremented counter in the end |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4055 |
#ifndef _WIN64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4056 |
const Register len_reg = c_rarg4; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4057 |
const Register saved_encCounter_start = c_rarg5; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4058 |
const Register used_addr = r10; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4059 |
const Address used_mem(rbp, 2 * wordSize); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4060 |
const Register used = r11; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4061 |
#else |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4062 |
const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4063 |
const Address saved_encCounter_mem(rbp, 7 * wordSize); // saved encrypted counter is on stack on Win64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4064 |
const Address used_mem(rbp, 8 * wordSize); // used length is on stack on Win64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4065 |
const Register len_reg = r10; // pick the first volatile windows register |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4066 |
const Register saved_encCounter_start = r11; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4067 |
const Register used_addr = r13; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4068 |
const Register used = r14; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4069 |
#endif |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4070 |
__ enter(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4071 |
// Save state before entering routine |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4072 |
__ push(r12); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4073 |
__ push(r13); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4074 |
__ push(r14); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4075 |
__ push(r15); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4076 |
#ifdef _WIN64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4077 |
// on win64, fill len_reg from stack position |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4078 |
__ movl(len_reg, len_mem); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4079 |
__ movptr(saved_encCounter_start, saved_encCounter_mem); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4080 |
__ movptr(used_addr, used_mem); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4081 |
__ movl(used, Address(used_addr, 0)); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4082 |
#else |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4083 |
__ push(len_reg); // Save |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4084 |
__ movptr(used_addr, used_mem); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4085 |
__ movl(used, Address(used_addr, 0)); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4086 |
#endif |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4087 |
__ push(rbx); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4088 |
__ aesctr_encrypt(from, to, key, counter, len_reg, used, used_addr, saved_encCounter_start); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4089 |
// Restore state before leaving routine |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4090 |
__ pop(rbx); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4091 |
#ifdef _WIN64 |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4092 |
__ movl(rax, len_mem); // return length |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4093 |
#else |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4094 |
__ pop(rax); // return length |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4095 |
#endif |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4096 |
__ pop(r15); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4097 |
__ pop(r14); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4098 |
__ pop(r13); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4099 |
__ pop(r12); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4100 |
|
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4101 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4102 |
__ ret(0); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4103 |
return start; |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4104 |
} |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
4105 |
|
35154 | 4106 |
// This is a version of CTR/AES crypt which does 6 blocks in a loop at a time |
4107 |
// to hide instruction latency |
|
4108 |
// |
|
4109 |
// Arguments: |
|
4110 |
// |
|
4111 |
// Inputs: |
|
4112 |
// c_rarg0 - source byte array address |
|
4113 |
// c_rarg1 - destination byte array address |
|
4114 |
// c_rarg2 - K (key) in little endian int array |
|
4115 |
// c_rarg3 - counter vector byte array address |
|
4116 |
// Linux |
|
4117 |
// c_rarg4 - input length |
|
4118 |
// c_rarg5 - saved encryptedCounter start |
|
4119 |
// rbp + 6 * wordSize - saved used length |
|
4120 |
// Windows |
|
4121 |
// rbp + 6 * wordSize - input length |
|
4122 |
// rbp + 7 * wordSize - saved encryptedCounter start |
|
4123 |
// rbp + 8 * wordSize - saved used length |
|
4124 |
// |
|
4125 |
// Output: |
|
4126 |
// rax - input length |
|
4127 |
// |
|
4128 |
address generate_counterMode_AESCrypt_Parallel() { |
|
4129 |
assert(UseAES, "need AES instructions and misaligned SSE support"); |
|
4130 |
__ align(CodeEntryAlignment); |
|
4131 |
StubCodeMark mark(this, "StubRoutines", "counterMode_AESCrypt"); |
|
4132 |
address start = __ pc(); |
|
4133 |
const Register from = c_rarg0; // source array address |
|
4134 |
const Register to = c_rarg1; // destination array address |
|
4135 |
const Register key = c_rarg2; // key array address |
|
4136 |
const Register counter = c_rarg3; // counter byte array initialized from counter array address |
|
35537
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
4137 |
// and updated with the incremented counter in the end |
35154 | 4138 |
#ifndef _WIN64 |
4139 |
const Register len_reg = c_rarg4; |
|
4140 |
const Register saved_encCounter_start = c_rarg5; |
|
4141 |
const Register used_addr = r10; |
|
4142 |
const Address used_mem(rbp, 2 * wordSize); |
|
4143 |
const Register used = r11; |
|
4144 |
#else |
|
4145 |
const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64 |
|
4146 |
const Address saved_encCounter_mem(rbp, 7 * wordSize); // length is on stack on Win64 |
|
4147 |
const Address used_mem(rbp, 8 * wordSize); // length is on stack on Win64 |
|
4148 |
const Register len_reg = r10; // pick the first volatile windows register |
|
4149 |
const Register saved_encCounter_start = r11; |
|
4150 |
const Register used_addr = r13; |
|
4151 |
const Register used = r14; |
|
4152 |
#endif |
|
4153 |
const Register pos = rax; |
|
4154 |
||
4155 |
const int PARALLEL_FACTOR = 6; |
|
4156 |
const XMMRegister xmm_counter_shuf_mask = xmm0; |
|
4157 |
const XMMRegister xmm_key_shuf_mask = xmm1; // used temporarily to swap key bytes up front |
|
4158 |
const XMMRegister xmm_curr_counter = xmm2; |
|
4159 |
||
4160 |
const XMMRegister xmm_key_tmp0 = xmm3; |
|
4161 |
const XMMRegister xmm_key_tmp1 = xmm4; |
|
4162 |
||
4163 |
// registers holding the four results in the parallelized loop |
|
4164 |
const XMMRegister xmm_result0 = xmm5; |
|
4165 |
const XMMRegister xmm_result1 = xmm6; |
|
4166 |
const XMMRegister xmm_result2 = xmm7; |
|
4167 |
const XMMRegister xmm_result3 = xmm8; |
|
4168 |
const XMMRegister xmm_result4 = xmm9; |
|
4169 |
const XMMRegister xmm_result5 = xmm10; |
|
4170 |
||
4171 |
const XMMRegister xmm_from0 = xmm11; |
|
4172 |
const XMMRegister xmm_from1 = xmm12; |
|
4173 |
const XMMRegister xmm_from2 = xmm13; |
|
4174 |
const XMMRegister xmm_from3 = xmm14; //the last one is xmm14. we have to preserve it on WIN64. |
|
4175 |
const XMMRegister xmm_from4 = xmm3; //reuse xmm3~4. Because xmm_key_tmp0~1 are useless when loading input text |
|
4176 |
const XMMRegister xmm_from5 = xmm4; |
|
4177 |
||
4178 |
//for key_128, key_192, key_256 |
|
4179 |
const int rounds[3] = {10, 12, 14}; |
|
4180 |
Label L_exit_preLoop, L_preLoop_start; |
|
4181 |
Label L_multiBlock_loopTop[3]; |
|
4182 |
Label L_singleBlockLoopTop[3]; |
|
4183 |
Label L__incCounter[3][6]; //for 6 blocks |
|
4184 |
Label L__incCounter_single[3]; //for single block, key128, key192, key256 |
|
4185 |
Label L_processTail_insr[3], L_processTail_4_insr[3], L_processTail_2_insr[3], L_processTail_1_insr[3], L_processTail_exit_insr[3]; |
|
51756 | 4186 |
Label L_processTail_4_extr[3], L_processTail_2_extr[3], L_processTail_1_extr[3], L_processTail_exit_extr[3]; |
35154 | 4187 |
|
4188 |
Label L_exit; |
|
4189 |
||
4190 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
4191 |
||
4192 |
#ifdef _WIN64 |
|
41333
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4193 |
// allocate spill slots for r13, r14 |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4194 |
enum { |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4195 |
saved_r13_offset, |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4196 |
saved_r14_offset |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4197 |
}; |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4198 |
__ subptr(rsp, 2 * wordSize); |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4199 |
__ movptr(Address(rsp, saved_r13_offset * wordSize), r13); |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4200 |
__ movptr(Address(rsp, saved_r14_offset * wordSize), r14); |
35154 | 4201 |
|
4202 |
// on win64, fill len_reg from stack position |
|
4203 |
__ movl(len_reg, len_mem); |
|
4204 |
__ movptr(saved_encCounter_start, saved_encCounter_mem); |
|
4205 |
__ movptr(used_addr, used_mem); |
|
4206 |
__ movl(used, Address(used_addr, 0)); |
|
4207 |
#else |
|
4208 |
__ push(len_reg); // Save |
|
4209 |
__ movptr(used_addr, used_mem); |
|
4210 |
__ movl(used, Address(used_addr, 0)); |
|
4211 |
#endif |
|
4212 |
||
4213 |
__ push(rbx); // Save RBX |
|
4214 |
__ movdqu(xmm_curr_counter, Address(counter, 0x00)); // initialize counter with initial counter |
|
43423
bcaab17f72a5
8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents:
42618
diff
changeset
|
4215 |
__ movdqu(xmm_counter_shuf_mask, ExternalAddress(StubRoutines::x86::counter_shuffle_mask_addr()), pos); // pos as scratch |
35154 | 4216 |
__ pshufb(xmm_curr_counter, xmm_counter_shuf_mask); //counter is shuffled |
4217 |
__ movptr(pos, 0); |
|
4218 |
||
4219 |
// Use the partially used encrpyted counter from last invocation |
|
4220 |
__ BIND(L_preLoop_start); |
|
4221 |
__ cmpptr(used, 16); |
|
4222 |
__ jcc(Assembler::aboveEqual, L_exit_preLoop); |
|
4223 |
__ cmpptr(len_reg, 0); |
|
4224 |
__ jcc(Assembler::lessEqual, L_exit_preLoop); |
|
4225 |
__ movb(rbx, Address(saved_encCounter_start, used)); |
|
4226 |
__ xorb(rbx, Address(from, pos)); |
|
4227 |
__ movb(Address(to, pos), rbx); |
|
4228 |
__ addptr(pos, 1); |
|
4229 |
__ addptr(used, 1); |
|
4230 |
__ subptr(len_reg, 1); |
|
4231 |
||
4232 |
__ jmp(L_preLoop_start); |
|
4233 |
||
4234 |
__ BIND(L_exit_preLoop); |
|
4235 |
__ movl(Address(used_addr, 0), used); |
|
4236 |
||
4237 |
// key length could be only {11, 13, 15} * 4 = {44, 52, 60} |
|
43423
bcaab17f72a5
8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents:
42618
diff
changeset
|
4238 |
__ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()), rbx); // rbx as scratch |
35154 | 4239 |
__ movl(rbx, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
4240 |
__ cmpl(rbx, 52); |
|
4241 |
__ jcc(Assembler::equal, L_multiBlock_loopTop[1]); |
|
4242 |
__ cmpl(rbx, 60); |
|
4243 |
__ jcc(Assembler::equal, L_multiBlock_loopTop[2]); |
|
4244 |
||
4245 |
#define CTR_DoSix(opc, src_reg) \ |
|
4246 |
__ opc(xmm_result0, src_reg); \ |
|
4247 |
__ opc(xmm_result1, src_reg); \ |
|
4248 |
__ opc(xmm_result2, src_reg); \ |
|
4249 |
__ opc(xmm_result3, src_reg); \ |
|
4250 |
__ opc(xmm_result4, src_reg); \ |
|
4251 |
__ opc(xmm_result5, src_reg); |
|
4252 |
||
4253 |
// k == 0 : generate code for key_128 |
|
4254 |
// k == 1 : generate code for key_192 |
|
4255 |
// k == 2 : generate code for key_256 |
|
4256 |
for (int k = 0; k < 3; ++k) { |
|
4257 |
//multi blocks starts here |
|
4258 |
__ align(OptoLoopAlignment); |
|
4259 |
__ BIND(L_multiBlock_loopTop[k]); |
|
4260 |
__ cmpptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // see if at least PARALLEL_FACTOR blocks left |
|
4261 |
__ jcc(Assembler::less, L_singleBlockLoopTop[k]); |
|
4262 |
load_key(xmm_key_tmp0, key, 0x00, xmm_key_shuf_mask); |
|
4263 |
||
4264 |
//load, then increase counters |
|
4265 |
CTR_DoSix(movdqa, xmm_curr_counter); |
|
4266 |
inc_counter(rbx, xmm_result1, 0x01, L__incCounter[k][0]); |
|
4267 |
inc_counter(rbx, xmm_result2, 0x02, L__incCounter[k][1]); |
|
4268 |
inc_counter(rbx, xmm_result3, 0x03, L__incCounter[k][2]); |
|
4269 |
inc_counter(rbx, xmm_result4, 0x04, L__incCounter[k][3]); |
|
4270 |
inc_counter(rbx, xmm_result5, 0x05, L__incCounter[k][4]); |
|
4271 |
inc_counter(rbx, xmm_curr_counter, 0x06, L__incCounter[k][5]); |
|
4272 |
CTR_DoSix(pshufb, xmm_counter_shuf_mask); // after increased, shuffled counters back for PXOR |
|
4273 |
CTR_DoSix(pxor, xmm_key_tmp0); //PXOR with Round 0 key |
|
4274 |
||
4275 |
//load two ROUND_KEYs at a time |
|
4276 |
for (int i = 1; i < rounds[k]; ) { |
|
4277 |
load_key(xmm_key_tmp1, key, (0x10 * i), xmm_key_shuf_mask); |
|
4278 |
load_key(xmm_key_tmp0, key, (0x10 * (i+1)), xmm_key_shuf_mask); |
|
4279 |
CTR_DoSix(aesenc, xmm_key_tmp1); |
|
4280 |
i++; |
|
4281 |
if (i != rounds[k]) { |
|
4282 |
CTR_DoSix(aesenc, xmm_key_tmp0); |
|
4283 |
} else { |
|
4284 |
CTR_DoSix(aesenclast, xmm_key_tmp0); |
|
4285 |
} |
|
4286 |
i++; |
|
4287 |
} |
|
4288 |
||
4289 |
// get next PARALLEL_FACTOR blocks into xmm_result registers |
|
4290 |
__ movdqu(xmm_from0, Address(from, pos, Address::times_1, 0 * AESBlockSize)); |
|
4291 |
__ movdqu(xmm_from1, Address(from, pos, Address::times_1, 1 * AESBlockSize)); |
|
4292 |
__ movdqu(xmm_from2, Address(from, pos, Address::times_1, 2 * AESBlockSize)); |
|
4293 |
__ movdqu(xmm_from3, Address(from, pos, Address::times_1, 3 * AESBlockSize)); |
|
4294 |
__ movdqu(xmm_from4, Address(from, pos, Address::times_1, 4 * AESBlockSize)); |
|
4295 |
__ movdqu(xmm_from5, Address(from, pos, Address::times_1, 5 * AESBlockSize)); |
|
4296 |
||
4297 |
__ pxor(xmm_result0, xmm_from0); |
|
4298 |
__ pxor(xmm_result1, xmm_from1); |
|
4299 |
__ pxor(xmm_result2, xmm_from2); |
|
4300 |
__ pxor(xmm_result3, xmm_from3); |
|
4301 |
__ pxor(xmm_result4, xmm_from4); |
|
4302 |
__ pxor(xmm_result5, xmm_from5); |
|
4303 |
||
4304 |
// store 6 results into the next 64 bytes of output |
|
4305 |
__ movdqu(Address(to, pos, Address::times_1, 0 * AESBlockSize), xmm_result0); |
|
4306 |
__ movdqu(Address(to, pos, Address::times_1, 1 * AESBlockSize), xmm_result1); |
|
4307 |
__ movdqu(Address(to, pos, Address::times_1, 2 * AESBlockSize), xmm_result2); |
|
4308 |
__ movdqu(Address(to, pos, Address::times_1, 3 * AESBlockSize), xmm_result3); |
|
4309 |
__ movdqu(Address(to, pos, Address::times_1, 4 * AESBlockSize), xmm_result4); |
|
4310 |
__ movdqu(Address(to, pos, Address::times_1, 5 * AESBlockSize), xmm_result5); |
|
4311 |
||
4312 |
__ addptr(pos, PARALLEL_FACTOR * AESBlockSize); // increase the length of crypt text |
|
4313 |
__ subptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // decrease the remaining length |
|
4314 |
__ jmp(L_multiBlock_loopTop[k]); |
|
4315 |
||
4316 |
// singleBlock starts here |
|
4317 |
__ align(OptoLoopAlignment); |
|
4318 |
__ BIND(L_singleBlockLoopTop[k]); |
|
4319 |
__ cmpptr(len_reg, 0); |
|
4320 |
__ jcc(Assembler::lessEqual, L_exit); |
|
4321 |
load_key(xmm_key_tmp0, key, 0x00, xmm_key_shuf_mask); |
|
4322 |
__ movdqa(xmm_result0, xmm_curr_counter); |
|
4323 |
inc_counter(rbx, xmm_curr_counter, 0x01, L__incCounter_single[k]); |
|
4324 |
__ pshufb(xmm_result0, xmm_counter_shuf_mask); |
|
4325 |
__ pxor(xmm_result0, xmm_key_tmp0); |
|
4326 |
for (int i = 1; i < rounds[k]; i++) { |
|
4327 |
load_key(xmm_key_tmp0, key, (0x10 * i), xmm_key_shuf_mask); |
|
4328 |
__ aesenc(xmm_result0, xmm_key_tmp0); |
|
4329 |
} |
|
4330 |
load_key(xmm_key_tmp0, key, (rounds[k] * 0x10), xmm_key_shuf_mask); |
|
4331 |
__ aesenclast(xmm_result0, xmm_key_tmp0); |
|
4332 |
__ cmpptr(len_reg, AESBlockSize); |
|
4333 |
__ jcc(Assembler::less, L_processTail_insr[k]); |
|
4334 |
__ movdqu(xmm_from0, Address(from, pos, Address::times_1, 0 * AESBlockSize)); |
|
4335 |
__ pxor(xmm_result0, xmm_from0); |
|
4336 |
__ movdqu(Address(to, pos, Address::times_1, 0 * AESBlockSize), xmm_result0); |
|
4337 |
__ addptr(pos, AESBlockSize); |
|
4338 |
__ subptr(len_reg, AESBlockSize); |
|
4339 |
__ jmp(L_singleBlockLoopTop[k]); |
|
35537
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
4340 |
__ BIND(L_processTail_insr[k]); // Process the tail part of the input array |
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
4341 |
__ addptr(pos, len_reg); // 1. Insert bytes from src array into xmm_from0 register |
35154 | 4342 |
__ testptr(len_reg, 8); |
4343 |
__ jcc(Assembler::zero, L_processTail_4_insr[k]); |
|
4344 |
__ subptr(pos,8); |
|
4345 |
__ pinsrq(xmm_from0, Address(from, pos), 0); |
|
4346 |
__ BIND(L_processTail_4_insr[k]); |
|
4347 |
__ testptr(len_reg, 4); |
|
4348 |
__ jcc(Assembler::zero, L_processTail_2_insr[k]); |
|
4349 |
__ subptr(pos,4); |
|
4350 |
__ pslldq(xmm_from0, 4); |
|
4351 |
__ pinsrd(xmm_from0, Address(from, pos), 0); |
|
4352 |
__ BIND(L_processTail_2_insr[k]); |
|
4353 |
__ testptr(len_reg, 2); |
|
4354 |
__ jcc(Assembler::zero, L_processTail_1_insr[k]); |
|
4355 |
__ subptr(pos, 2); |
|
4356 |
__ pslldq(xmm_from0, 2); |
|
4357 |
__ pinsrw(xmm_from0, Address(from, pos), 0); |
|
4358 |
__ BIND(L_processTail_1_insr[k]); |
|
4359 |
__ testptr(len_reg, 1); |
|
4360 |
__ jcc(Assembler::zero, L_processTail_exit_insr[k]); |
|
4361 |
__ subptr(pos, 1); |
|
4362 |
__ pslldq(xmm_from0, 1); |
|
4363 |
__ pinsrb(xmm_from0, Address(from, pos), 0); |
|
4364 |
__ BIND(L_processTail_exit_insr[k]); |
|
4365 |
||
35537
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
4366 |
__ movdqu(Address(saved_encCounter_start, 0), xmm_result0); // 2. Perform pxor of the encrypted counter and plaintext Bytes. |
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
4367 |
__ pxor(xmm_result0, xmm_from0); // Also the encrypted counter is saved for next invocation. |
35154 | 4368 |
|
4369 |
__ testptr(len_reg, 8); |
|
35537
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
4370 |
__ jcc(Assembler::zero, L_processTail_4_extr[k]); // 3. Extract bytes from xmm_result0 into the dest. array |
35154 | 4371 |
__ pextrq(Address(to, pos), xmm_result0, 0); |
4372 |
__ psrldq(xmm_result0, 8); |
|
4373 |
__ addptr(pos, 8); |
|
4374 |
__ BIND(L_processTail_4_extr[k]); |
|
4375 |
__ testptr(len_reg, 4); |
|
4376 |
__ jcc(Assembler::zero, L_processTail_2_extr[k]); |
|
4377 |
__ pextrd(Address(to, pos), xmm_result0, 0); |
|
4378 |
__ psrldq(xmm_result0, 4); |
|
4379 |
__ addptr(pos, 4); |
|
4380 |
__ BIND(L_processTail_2_extr[k]); |
|
4381 |
__ testptr(len_reg, 2); |
|
4382 |
__ jcc(Assembler::zero, L_processTail_1_extr[k]); |
|
4383 |
__ pextrw(Address(to, pos), xmm_result0, 0); |
|
4384 |
__ psrldq(xmm_result0, 2); |
|
4385 |
__ addptr(pos, 2); |
|
4386 |
__ BIND(L_processTail_1_extr[k]); |
|
4387 |
__ testptr(len_reg, 1); |
|
4388 |
__ jcc(Assembler::zero, L_processTail_exit_extr[k]); |
|
4389 |
__ pextrb(Address(to, pos), xmm_result0, 0); |
|
4390 |
||
4391 |
__ BIND(L_processTail_exit_extr[k]); |
|
4392 |
__ movl(Address(used_addr, 0), len_reg); |
|
4393 |
__ jmp(L_exit); |
|
4394 |
||
4395 |
} |
|
4396 |
||
4397 |
__ BIND(L_exit); |
|
4398 |
__ pshufb(xmm_curr_counter, xmm_counter_shuf_mask); //counter is shuffled back. |
|
4399 |
__ movdqu(Address(counter, 0), xmm_curr_counter); //save counter back |
|
4400 |
__ pop(rbx); // pop the saved RBX. |
|
4401 |
#ifdef _WIN64 |
|
4402 |
__ movl(rax, len_mem); |
|
41333
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4403 |
__ movptr(r13, Address(rsp, saved_r13_offset * wordSize)); |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4404 |
__ movptr(r14, Address(rsp, saved_r14_offset * wordSize)); |
ce08d64b41c7
8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents:
40644
diff
changeset
|
4405 |
__ addptr(rsp, 2 * wordSize); |
35154 | 4406 |
#else |
4407 |
__ pop(rax); // return 'len' |
|
4408 |
#endif |
|
4409 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
4410 |
__ ret(0); |
|
4411 |
return start; |
|
4412 |
} |
|
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4413 |
|
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4414 |
void roundDec(XMMRegister xmm_reg) { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4415 |
__ vaesdec(xmm1, xmm1, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4416 |
__ vaesdec(xmm2, xmm2, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4417 |
__ vaesdec(xmm3, xmm3, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4418 |
__ vaesdec(xmm4, xmm4, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4419 |
__ vaesdec(xmm5, xmm5, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4420 |
__ vaesdec(xmm6, xmm6, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4421 |
__ vaesdec(xmm7, xmm7, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4422 |
__ vaesdec(xmm8, xmm8, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4423 |
} |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4424 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4425 |
void roundDeclast(XMMRegister xmm_reg) { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4426 |
__ vaesdeclast(xmm1, xmm1, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4427 |
__ vaesdeclast(xmm2, xmm2, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4428 |
__ vaesdeclast(xmm3, xmm3, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4429 |
__ vaesdeclast(xmm4, xmm4, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4430 |
__ vaesdeclast(xmm5, xmm5, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4431 |
__ vaesdeclast(xmm6, xmm6, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4432 |
__ vaesdeclast(xmm7, xmm7, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4433 |
__ vaesdeclast(xmm8, xmm8, xmm_reg, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4434 |
} |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4435 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4436 |
void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask = NULL) { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4437 |
__ movdqu(xmmdst, Address(key, offset)); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4438 |
if (xmm_shuf_mask != NULL) { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4439 |
__ pshufb(xmmdst, xmm_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4440 |
} else { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4441 |
__ pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4442 |
} |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4443 |
__ evshufi64x2(xmmdst, xmmdst, xmmdst, 0x0, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4444 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4445 |
} |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4446 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4447 |
address generate_cipherBlockChaining_decryptVectorAESCrypt() { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4448 |
assert(VM_Version::supports_vaes(), "need AES instructions and misaligned SSE support"); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4449 |
__ align(CodeEntryAlignment); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4450 |
StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt"); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4451 |
address start = __ pc(); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4452 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4453 |
const Register from = c_rarg0; // source array address |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4454 |
const Register to = c_rarg1; // destination array address |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4455 |
const Register key = c_rarg2; // key array address |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4456 |
const Register rvec = c_rarg3; // r byte array initialized from initvector array address |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4457 |
// and left with the results of the last encryption block |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4458 |
#ifndef _WIN64 |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4459 |
const Register len_reg = c_rarg4; // src len (must be multiple of blocksize 16) |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4460 |
#else |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4461 |
const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64 |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4462 |
const Register len_reg = r11; // pick the volatile windows register |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4463 |
#endif |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4464 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4465 |
Label Loop, Loop1, L_128, L_256, L_192, KEY_192, KEY_256, Loop2, Lcbc_dec_rem_loop, |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4466 |
Lcbc_dec_rem_last, Lcbc_dec_ret, Lcbc_dec_rem, Lcbc_exit; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4467 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4468 |
__ enter(); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4469 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4470 |
#ifdef _WIN64 |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4471 |
// on win64, fill len_reg from stack position |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4472 |
__ movl(len_reg, len_mem); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4473 |
#else |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4474 |
__ push(len_reg); // Save |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4475 |
#endif |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4476 |
__ push(rbx); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4477 |
__ vzeroupper(); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4478 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4479 |
// Temporary variable declaration for swapping key bytes |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4480 |
const XMMRegister xmm_key_shuf_mask = xmm1; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4481 |
__ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr())); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4482 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4483 |
// Calculate number of rounds from key size: 44 for 10-rounds, 52 for 12-rounds, 60 for 14-rounds |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4484 |
const Register rounds = rbx; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4485 |
__ movl(rounds, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT))); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4486 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4487 |
const XMMRegister IV = xmm0; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4488 |
// Load IV and broadcast value to 512-bits |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4489 |
__ evbroadcasti64x2(IV, Address(rvec, 0), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4490 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4491 |
// Temporary variables for storing round keys |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4492 |
const XMMRegister RK0 = xmm30; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4493 |
const XMMRegister RK1 = xmm9; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4494 |
const XMMRegister RK2 = xmm18; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4495 |
const XMMRegister RK3 = xmm19; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4496 |
const XMMRegister RK4 = xmm20; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4497 |
const XMMRegister RK5 = xmm21; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4498 |
const XMMRegister RK6 = xmm22; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4499 |
const XMMRegister RK7 = xmm23; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4500 |
const XMMRegister RK8 = xmm24; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4501 |
const XMMRegister RK9 = xmm25; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4502 |
const XMMRegister RK10 = xmm26; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4503 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4504 |
// Load and shuffle key |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4505 |
// the java expanded key ordering is rotated one position from what we want |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4506 |
// so we start from 1*16 here and hit 0*16 last |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4507 |
ev_load_key(RK1, key, 1 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4508 |
ev_load_key(RK2, key, 2 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4509 |
ev_load_key(RK3, key, 3 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4510 |
ev_load_key(RK4, key, 4 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4511 |
ev_load_key(RK5, key, 5 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4512 |
ev_load_key(RK6, key, 6 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4513 |
ev_load_key(RK7, key, 7 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4514 |
ev_load_key(RK8, key, 8 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4515 |
ev_load_key(RK9, key, 9 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4516 |
ev_load_key(RK10, key, 10 * 16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4517 |
ev_load_key(RK0, key, 0*16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4518 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4519 |
// Variables for storing source cipher text |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4520 |
const XMMRegister S0 = xmm10; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4521 |
const XMMRegister S1 = xmm11; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4522 |
const XMMRegister S2 = xmm12; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4523 |
const XMMRegister S3 = xmm13; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4524 |
const XMMRegister S4 = xmm14; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4525 |
const XMMRegister S5 = xmm15; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4526 |
const XMMRegister S6 = xmm16; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4527 |
const XMMRegister S7 = xmm17; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4528 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4529 |
// Variables for storing decrypted text |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4530 |
const XMMRegister B0 = xmm1; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4531 |
const XMMRegister B1 = xmm2; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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diff
changeset
|
4532 |
const XMMRegister B2 = xmm3; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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diff
changeset
|
4533 |
const XMMRegister B3 = xmm4; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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diff
changeset
|
4534 |
const XMMRegister B4 = xmm5; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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diff
changeset
|
4535 |
const XMMRegister B5 = xmm6; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4536 |
const XMMRegister B6 = xmm7; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4537 |
const XMMRegister B7 = xmm8; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4538 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
50525
diff
changeset
|
4539 |
__ cmpl(rounds, 44); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4540 |
__ jcc(Assembler::greater, KEY_192); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4541 |
__ jmp(Loop); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4542 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4543 |
__ BIND(KEY_192); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4544 |
const XMMRegister RK11 = xmm27; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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diff
changeset
|
4545 |
const XMMRegister RK12 = xmm28; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4546 |
ev_load_key(RK11, key, 11*16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4547 |
ev_load_key(RK12, key, 12*16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4548 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4549 |
__ cmpl(rounds, 52); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4550 |
__ jcc(Assembler::greater, KEY_256); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
50525
diff
changeset
|
4551 |
__ jmp(Loop); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4552 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4553 |
__ BIND(KEY_256); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4554 |
const XMMRegister RK13 = xmm29; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4555 |
const XMMRegister RK14 = xmm31; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4556 |
ev_load_key(RK13, key, 13*16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
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parents:
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diff
changeset
|
4557 |
ev_load_key(RK14, key, 14*16, xmm_key_shuf_mask); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4558 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4559 |
__ BIND(Loop); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4560 |
__ cmpl(len_reg, 512); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4561 |
__ jcc(Assembler::below, Lcbc_dec_rem); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4562 |
__ BIND(Loop1); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4563 |
__ subl(len_reg, 512); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4564 |
__ evmovdquq(S0, Address(from, 0 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4565 |
__ evmovdquq(S1, Address(from, 1 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4566 |
__ evmovdquq(S2, Address(from, 2 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4567 |
__ evmovdquq(S3, Address(from, 3 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4568 |
__ evmovdquq(S4, Address(from, 4 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4569 |
__ evmovdquq(S5, Address(from, 5 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4570 |
__ evmovdquq(S6, Address(from, 6 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4571 |
__ evmovdquq(S7, Address(from, 7 * 64), Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4572 |
__ leaq(from, Address(from, 8 * 64)); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
4573 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4574 |
__ evpxorq(B0, S0, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4575 |
__ evpxorq(B1, S1, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4576 |
__ evpxorq(B2, S2, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4577 |
__ evpxorq(B3, S3, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4578 |
__ evpxorq(B4, S4, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4579 |
__ evpxorq(B5, S5, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4580 |
__ evpxorq(B6, S6, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4581 |
__ evpxorq(B7, S7, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4582 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4583 |
__ evalignq(IV, S0, IV, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4584 |
__ evalignq(S0, S1, S0, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4585 |
__ evalignq(S1, S2, S1, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4586 |
__ evalignq(S2, S3, S2, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4587 |
__ evalignq(S3, S4, S3, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4588 |
__ evalignq(S4, S5, S4, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4589 |
__ evalignq(S5, S6, S5, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4590 |
__ evalignq(S6, S7, S6, 0x06); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4591 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4592 |
roundDec(RK2); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4593 |
roundDec(RK3); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4594 |
roundDec(RK4); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4595 |
roundDec(RK5); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4596 |
roundDec(RK6); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4597 |
roundDec(RK7); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4598 |
roundDec(RK8); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4599 |
roundDec(RK9); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4600 |
roundDec(RK10); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4601 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4602 |
__ cmpl(rounds, 44); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4603 |
__ jcc(Assembler::belowEqual, L_128); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4604 |
roundDec(RK11); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4605 |
roundDec(RK12); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4606 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4607 |
__ cmpl(rounds, 52); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4608 |
__ jcc(Assembler::belowEqual, L_192); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4609 |
roundDec(RK13); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4610 |
roundDec(RK14); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4611 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4612 |
__ BIND(L_256); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4613 |
roundDeclast(RK0); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4614 |
__ jmp(Loop2); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4615 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4616 |
__ BIND(L_128); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4617 |
roundDeclast(RK0); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4618 |
__ jmp(Loop2); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4619 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4620 |
__ BIND(L_192); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4621 |
roundDeclast(RK0); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4622 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4623 |
__ BIND(Loop2); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4624 |
__ evpxorq(B0, B0, IV, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4625 |
__ evpxorq(B1, B1, S0, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4626 |
__ evpxorq(B2, B2, S1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4627 |
__ evpxorq(B3, B3, S2, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4628 |
__ evpxorq(B4, B4, S3, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4629 |
__ evpxorq(B5, B5, S4, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4630 |
__ evpxorq(B6, B6, S5, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4631 |
__ evpxorq(B7, B7, S6, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4632 |
__ evmovdquq(IV, S7, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4633 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4634 |
__ evmovdquq(Address(to, 0 * 64), B0, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4635 |
__ evmovdquq(Address(to, 1 * 64), B1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4636 |
__ evmovdquq(Address(to, 2 * 64), B2, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4637 |
__ evmovdquq(Address(to, 3 * 64), B3, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4638 |
__ evmovdquq(Address(to, 4 * 64), B4, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4639 |
__ evmovdquq(Address(to, 5 * 64), B5, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4640 |
__ evmovdquq(Address(to, 6 * 64), B6, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4641 |
__ evmovdquq(Address(to, 7 * 64), B7, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4642 |
__ leaq(to, Address(to, 8 * 64)); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4643 |
__ jmp(Loop); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4644 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4645 |
__ BIND(Lcbc_dec_rem); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4646 |
__ evshufi64x2(IV, IV, IV, 0x03, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4647 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4648 |
__ BIND(Lcbc_dec_rem_loop); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4649 |
__ subl(len_reg, 16); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4650 |
__ jcc(Assembler::carrySet, Lcbc_dec_ret); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4651 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4652 |
__ movdqu(S0, Address(from, 0)); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4653 |
__ evpxorq(B0, S0, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4654 |
__ vaesdec(B0, B0, RK2, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4655 |
__ vaesdec(B0, B0, RK3, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4656 |
__ vaesdec(B0, B0, RK4, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4657 |
__ vaesdec(B0, B0, RK5, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4658 |
__ vaesdec(B0, B0, RK6, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4659 |
__ vaesdec(B0, B0, RK7, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4660 |
__ vaesdec(B0, B0, RK8, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4661 |
__ vaesdec(B0, B0, RK9, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4662 |
__ vaesdec(B0, B0, RK10, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4663 |
__ cmpl(rounds, 44); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4664 |
__ jcc(Assembler::belowEqual, Lcbc_dec_rem_last); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4665 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4666 |
__ vaesdec(B0, B0, RK11, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4667 |
__ vaesdec(B0, B0, RK12, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4668 |
__ cmpl(rounds, 52); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4669 |
__ jcc(Assembler::belowEqual, Lcbc_dec_rem_last); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4670 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4671 |
__ vaesdec(B0, B0, RK13, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4672 |
__ vaesdec(B0, B0, RK14, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4673 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4674 |
__ BIND(Lcbc_dec_rem_last); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4675 |
__ vaesdeclast(B0, B0, RK0, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4676 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4677 |
__ evpxorq(B0, B0, IV, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4678 |
__ evmovdquq(IV, S0, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4679 |
__ movdqu(Address(to, 0), B0); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4680 |
__ leaq(from, Address(from, 16)); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4681 |
__ leaq(to, Address(to, 16)); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4682 |
__ jmp(Lcbc_dec_rem_loop); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4683 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4684 |
__ BIND(Lcbc_dec_ret); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4685 |
__ movdqu(Address(rvec, 0), IV); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4686 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4687 |
// Zero out the round keys |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4688 |
__ evpxorq(RK0, RK0, RK0, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4689 |
__ evpxorq(RK1, RK1, RK1, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4690 |
__ evpxorq(RK2, RK2, RK2, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4691 |
__ evpxorq(RK3, RK3, RK3, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4692 |
__ evpxorq(RK4, RK4, RK4, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4693 |
__ evpxorq(RK5, RK5, RK5, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4694 |
__ evpxorq(RK6, RK6, RK6, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4695 |
__ evpxorq(RK7, RK7, RK7, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4696 |
__ evpxorq(RK8, RK8, RK8, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4697 |
__ evpxorq(RK9, RK9, RK9, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4698 |
__ evpxorq(RK10, RK10, RK10, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4699 |
__ cmpl(rounds, 44); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4700 |
__ jcc(Assembler::belowEqual, Lcbc_exit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4701 |
__ evpxorq(RK11, RK11, RK11, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4702 |
__ evpxorq(RK12, RK12, RK12, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4703 |
__ cmpl(rounds, 52); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4704 |
__ jcc(Assembler::belowEqual, Lcbc_exit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4705 |
__ evpxorq(RK13, RK13, RK13, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4706 |
__ evpxorq(RK14, RK14, RK14, Assembler::AVX_512bit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4707 |
|
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4708 |
__ BIND(Lcbc_exit); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4709 |
__ pop(rbx); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4710 |
#ifdef _WIN64 |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4711 |
__ movl(rax, len_mem); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4712 |
#else |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4713 |
__ pop(rax); // return length |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4714 |
#endif |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4715 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4716 |
__ ret(0); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4717 |
return start; |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4718 |
} |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
4719 |
|
52990
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4720 |
// Polynomial x^128+x^127+x^126+x^121+1 |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4721 |
address ghash_polynomial_addr() { |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4722 |
__ align(CodeEntryAlignment); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4723 |
StubCodeMark mark(this, "StubRoutines", "_ghash_poly_addr"); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4724 |
address start = __ pc(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4725 |
__ emit_data64(0x0000000000000001, relocInfo::none); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4726 |
__ emit_data64(0xc200000000000000, relocInfo::none); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4727 |
return start; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4728 |
} |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4729 |
|
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4730 |
address ghash_shufflemask_addr() { |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4731 |
__ align(CodeEntryAlignment); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4732 |
StubCodeMark mark(this, "StubRoutines", "_ghash_shuffmask_addr"); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4733 |
address start = __ pc(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4734 |
__ emit_data64(0x0f0f0f0f0f0f0f0f, relocInfo::none); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4735 |
__ emit_data64(0x0f0f0f0f0f0f0f0f, relocInfo::none); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4736 |
return start; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4737 |
} |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4738 |
|
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4739 |
// Ghash single and multi block operations using AVX instructions |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4740 |
address generate_avx_ghash_processBlocks() { |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4741 |
__ align(CodeEntryAlignment); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4742 |
|
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4743 |
StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks"); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4744 |
address start = __ pc(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4745 |
|
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4746 |
// arguments |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4747 |
const Register state = c_rarg0; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4748 |
const Register htbl = c_rarg1; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4749 |
const Register data = c_rarg2; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4750 |
const Register blocks = c_rarg3; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4751 |
__ enter(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4752 |
// Save state before entering routine |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4753 |
__ avx_ghash(state, htbl, data, blocks); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4754 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4755 |
__ ret(0); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4756 |
return start; |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4757 |
} |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
4758 |
|
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4759 |
// byte swap x86 long |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4760 |
address generate_ghash_long_swap_mask() { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4761 |
__ align(CodeEntryAlignment); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4762 |
StubCodeMark mark(this, "StubRoutines", "ghash_long_swap_mask"); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4763 |
address start = __ pc(); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4764 |
__ emit_data64(0x0f0e0d0c0b0a0908, relocInfo::none ); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4765 |
__ emit_data64(0x0706050403020100, relocInfo::none ); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4766 |
return start; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4767 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4768 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4769 |
// byte swap x86 byte array |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4770 |
address generate_ghash_byte_swap_mask() { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4771 |
__ align(CodeEntryAlignment); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4772 |
StubCodeMark mark(this, "StubRoutines", "ghash_byte_swap_mask"); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4773 |
address start = __ pc(); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4774 |
__ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none ); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4775 |
__ emit_data64(0x0001020304050607, relocInfo::none ); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4776 |
return start; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4777 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4778 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4779 |
/* Single and multi-block ghash operations */ |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4780 |
address generate_ghash_processBlocks() { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4781 |
__ align(CodeEntryAlignment); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4782 |
Label L_ghash_loop, L_exit; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4783 |
StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks"); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4784 |
address start = __ pc(); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4785 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4786 |
const Register state = c_rarg0; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4787 |
const Register subkeyH = c_rarg1; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4788 |
const Register data = c_rarg2; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4789 |
const Register blocks = c_rarg3; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4790 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4791 |
const XMMRegister xmm_temp0 = xmm0; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4792 |
const XMMRegister xmm_temp1 = xmm1; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4793 |
const XMMRegister xmm_temp2 = xmm2; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4794 |
const XMMRegister xmm_temp3 = xmm3; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4795 |
const XMMRegister xmm_temp4 = xmm4; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4796 |
const XMMRegister xmm_temp5 = xmm5; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4797 |
const XMMRegister xmm_temp6 = xmm6; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4798 |
const XMMRegister xmm_temp7 = xmm7; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4799 |
const XMMRegister xmm_temp8 = xmm8; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4800 |
const XMMRegister xmm_temp9 = xmm9; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4801 |
const XMMRegister xmm_temp10 = xmm10; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4802 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4803 |
__ enter(); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4804 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4805 |
__ movdqu(xmm_temp10, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr())); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4806 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4807 |
__ movdqu(xmm_temp0, Address(state, 0)); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4808 |
__ pshufb(xmm_temp0, xmm_temp10); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4809 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4810 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4811 |
__ BIND(L_ghash_loop); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4812 |
__ movdqu(xmm_temp2, Address(data, 0)); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4813 |
__ pshufb(xmm_temp2, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr())); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4814 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4815 |
__ movdqu(xmm_temp1, Address(subkeyH, 0)); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4816 |
__ pshufb(xmm_temp1, xmm_temp10); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4817 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4818 |
__ pxor(xmm_temp0, xmm_temp2); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4819 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4820 |
// |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4821 |
// Multiply with the hash key |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4822 |
// |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4823 |
__ movdqu(xmm_temp3, xmm_temp0); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4824 |
__ pclmulqdq(xmm_temp3, xmm_temp1, 0); // xmm3 holds a0*b0 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4825 |
__ movdqu(xmm_temp4, xmm_temp0); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4826 |
__ pclmulqdq(xmm_temp4, xmm_temp1, 16); // xmm4 holds a0*b1 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4827 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4828 |
__ movdqu(xmm_temp5, xmm_temp0); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4829 |
__ pclmulqdq(xmm_temp5, xmm_temp1, 1); // xmm5 holds a1*b0 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4830 |
__ movdqu(xmm_temp6, xmm_temp0); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4831 |
__ pclmulqdq(xmm_temp6, xmm_temp1, 17); // xmm6 holds a1*b1 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4832 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4833 |
__ pxor(xmm_temp4, xmm_temp5); // xmm4 holds a0*b1 + a1*b0 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4834 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4835 |
__ movdqu(xmm_temp5, xmm_temp4); // move the contents of xmm4 to xmm5 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4836 |
__ psrldq(xmm_temp4, 8); // shift by xmm4 64 bits to the right |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4837 |
__ pslldq(xmm_temp5, 8); // shift by xmm5 64 bits to the left |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4838 |
__ pxor(xmm_temp3, xmm_temp5); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4839 |
__ pxor(xmm_temp6, xmm_temp4); // Register pair <xmm6:xmm3> holds the result |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4840 |
// of the carry-less multiplication of |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4841 |
// xmm0 by xmm1. |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4842 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4843 |
// We shift the result of the multiplication by one bit position |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4844 |
// to the left to cope for the fact that the bits are reversed. |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4845 |
__ movdqu(xmm_temp7, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4846 |
__ movdqu(xmm_temp8, xmm_temp6); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4847 |
__ pslld(xmm_temp3, 1); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4848 |
__ pslld(xmm_temp6, 1); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4849 |
__ psrld(xmm_temp7, 31); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4850 |
__ psrld(xmm_temp8, 31); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4851 |
__ movdqu(xmm_temp9, xmm_temp7); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4852 |
__ pslldq(xmm_temp8, 4); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4853 |
__ pslldq(xmm_temp7, 4); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4854 |
__ psrldq(xmm_temp9, 12); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4855 |
__ por(xmm_temp3, xmm_temp7); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4856 |
__ por(xmm_temp6, xmm_temp8); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4857 |
__ por(xmm_temp6, xmm_temp9); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4858 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4859 |
// |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4860 |
// First phase of the reduction |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4861 |
// |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4862 |
// Move xmm3 into xmm7, xmm8, xmm9 in order to perform the shifts |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4863 |
// independently. |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4864 |
__ movdqu(xmm_temp7, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4865 |
__ movdqu(xmm_temp8, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4866 |
__ movdqu(xmm_temp9, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4867 |
__ pslld(xmm_temp7, 31); // packed right shift shifting << 31 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4868 |
__ pslld(xmm_temp8, 30); // packed right shift shifting << 30 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4869 |
__ pslld(xmm_temp9, 25); // packed right shift shifting << 25 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4870 |
__ pxor(xmm_temp7, xmm_temp8); // xor the shifted versions |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4871 |
__ pxor(xmm_temp7, xmm_temp9); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4872 |
__ movdqu(xmm_temp8, xmm_temp7); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4873 |
__ pslldq(xmm_temp7, 12); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4874 |
__ psrldq(xmm_temp8, 4); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4875 |
__ pxor(xmm_temp3, xmm_temp7); // first phase of the reduction complete |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4876 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4877 |
// |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4878 |
// Second phase of the reduction |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4879 |
// |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4880 |
// Make 3 copies of xmm3 in xmm2, xmm4, xmm5 for doing these |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4881 |
// shift operations. |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4882 |
__ movdqu(xmm_temp2, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4883 |
__ movdqu(xmm_temp4, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4884 |
__ movdqu(xmm_temp5, xmm_temp3); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4885 |
__ psrld(xmm_temp2, 1); // packed left shifting >> 1 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4886 |
__ psrld(xmm_temp4, 2); // packed left shifting >> 2 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4887 |
__ psrld(xmm_temp5, 7); // packed left shifting >> 7 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4888 |
__ pxor(xmm_temp2, xmm_temp4); // xor the shifted versions |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4889 |
__ pxor(xmm_temp2, xmm_temp5); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4890 |
__ pxor(xmm_temp2, xmm_temp8); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4891 |
__ pxor(xmm_temp3, xmm_temp2); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4892 |
__ pxor(xmm_temp6, xmm_temp3); // the result is in xmm6 |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4893 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4894 |
__ decrement(blocks); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4895 |
__ jcc(Assembler::zero, L_exit); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4896 |
__ movdqu(xmm_temp0, xmm_temp6); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4897 |
__ addptr(data, 16); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4898 |
__ jmp(L_ghash_loop); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4899 |
|
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4900 |
__ BIND(L_exit); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4901 |
__ pshufb(xmm_temp6, xmm_temp10); // Byte swap 16-byte result |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4902 |
__ movdqu(Address(state, 0), xmm_temp6); // store the result |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4903 |
__ leave(); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4904 |
__ ret(0); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4905 |
return start; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4906 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
4907 |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4908 |
//base64 character set |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4909 |
address base64_charset_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4910 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4911 |
StubCodeMark mark(this, "StubRoutines", "base64_charset"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4912 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4913 |
__ emit_data64(0x0000004200000041, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4914 |
__ emit_data64(0x0000004400000043, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4915 |
__ emit_data64(0x0000004600000045, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4916 |
__ emit_data64(0x0000004800000047, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4917 |
__ emit_data64(0x0000004a00000049, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4918 |
__ emit_data64(0x0000004c0000004b, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4919 |
__ emit_data64(0x0000004e0000004d, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4920 |
__ emit_data64(0x000000500000004f, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4921 |
__ emit_data64(0x0000005200000051, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4922 |
__ emit_data64(0x0000005400000053, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4923 |
__ emit_data64(0x0000005600000055, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4924 |
__ emit_data64(0x0000005800000057, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4925 |
__ emit_data64(0x0000005a00000059, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4926 |
__ emit_data64(0x0000006200000061, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4927 |
__ emit_data64(0x0000006400000063, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4928 |
__ emit_data64(0x0000006600000065, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4929 |
__ emit_data64(0x0000006800000067, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4930 |
__ emit_data64(0x0000006a00000069, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4931 |
__ emit_data64(0x0000006c0000006b, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4932 |
__ emit_data64(0x0000006e0000006d, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4933 |
__ emit_data64(0x000000700000006f, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4934 |
__ emit_data64(0x0000007200000071, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4935 |
__ emit_data64(0x0000007400000073, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4936 |
__ emit_data64(0x0000007600000075, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4937 |
__ emit_data64(0x0000007800000077, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4938 |
__ emit_data64(0x0000007a00000079, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4939 |
__ emit_data64(0x0000003100000030, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4940 |
__ emit_data64(0x0000003300000032, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4941 |
__ emit_data64(0x0000003500000034, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4942 |
__ emit_data64(0x0000003700000036, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4943 |
__ emit_data64(0x0000003900000038, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4944 |
__ emit_data64(0x0000002f0000002b, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4945 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4946 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4947 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4948 |
//base64 url character set |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4949 |
address base64url_charset_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4950 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4951 |
StubCodeMark mark(this, "StubRoutines", "base64url_charset"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4952 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4953 |
__ emit_data64(0x0000004200000041, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4954 |
__ emit_data64(0x0000004400000043, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4955 |
__ emit_data64(0x0000004600000045, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4956 |
__ emit_data64(0x0000004800000047, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4957 |
__ emit_data64(0x0000004a00000049, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4958 |
__ emit_data64(0x0000004c0000004b, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4959 |
__ emit_data64(0x0000004e0000004d, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4960 |
__ emit_data64(0x000000500000004f, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4961 |
__ emit_data64(0x0000005200000051, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4962 |
__ emit_data64(0x0000005400000053, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4963 |
__ emit_data64(0x0000005600000055, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4964 |
__ emit_data64(0x0000005800000057, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4965 |
__ emit_data64(0x0000005a00000059, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4966 |
__ emit_data64(0x0000006200000061, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4967 |
__ emit_data64(0x0000006400000063, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4968 |
__ emit_data64(0x0000006600000065, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4969 |
__ emit_data64(0x0000006800000067, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4970 |
__ emit_data64(0x0000006a00000069, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4971 |
__ emit_data64(0x0000006c0000006b, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4972 |
__ emit_data64(0x0000006e0000006d, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4973 |
__ emit_data64(0x000000700000006f, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4974 |
__ emit_data64(0x0000007200000071, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4975 |
__ emit_data64(0x0000007400000073, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4976 |
__ emit_data64(0x0000007600000075, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4977 |
__ emit_data64(0x0000007800000077, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4978 |
__ emit_data64(0x0000007a00000079, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4979 |
__ emit_data64(0x0000003100000030, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4980 |
__ emit_data64(0x0000003300000032, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4981 |
__ emit_data64(0x0000003500000034, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4982 |
__ emit_data64(0x0000003700000036, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4983 |
__ emit_data64(0x0000003900000038, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4984 |
__ emit_data64(0x0000005f0000002d, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4985 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4986 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4987 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4988 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4989 |
address base64_bswap_mask_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4990 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4991 |
StubCodeMark mark(this, "StubRoutines", "bswap_mask_base64"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4992 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4993 |
__ emit_data64(0x0504038002010080, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4994 |
__ emit_data64(0x0b0a098008070680, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4995 |
__ emit_data64(0x0908078006050480, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4996 |
__ emit_data64(0x0f0e0d800c0b0a80, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4997 |
__ emit_data64(0x0605048003020180, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4998 |
__ emit_data64(0x0c0b0a8009080780, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
4999 |
__ emit_data64(0x0504038002010080, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5000 |
__ emit_data64(0x0b0a098008070680, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5001 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5002 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5003 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5004 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5005 |
address base64_right_shift_mask_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5006 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5007 |
StubCodeMark mark(this, "StubRoutines", "right_shift_mask"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5008 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5009 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5010 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5011 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5012 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5013 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5014 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5015 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5016 |
__ emit_data64(0x0006000400020000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5017 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5018 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5019 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5020 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5021 |
address base64_left_shift_mask_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5022 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5023 |
StubCodeMark mark(this, "StubRoutines", "left_shift_mask"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5024 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5025 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5026 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5027 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5028 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5029 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5030 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5031 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5032 |
__ emit_data64(0x0000000200040000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5033 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5034 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5035 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5036 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5037 |
address base64_and_mask_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5038 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5039 |
StubCodeMark mark(this, "StubRoutines", "and_mask"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5040 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5041 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5042 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5043 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5044 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5045 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5046 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5047 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5048 |
__ emit_data64(0x3f003f003f000000, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5049 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5050 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5051 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5052 |
address base64_gather_mask_addr() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5053 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5054 |
StubCodeMark mark(this, "StubRoutines", "gather_mask"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5055 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5056 |
__ emit_data64(0xffffffffffffffff, relocInfo::none); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5057 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5058 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5059 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5060 |
// Code for generating Base64 encoding. |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5061 |
// Intrinsic function prototype in Base64.java: |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5062 |
// private void encodeBlock(byte[] src, int sp, int sl, byte[] dst, int dp, boolean isURL) { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5063 |
address generate_base64_encodeBlock() { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5064 |
__ align(CodeEntryAlignment); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5065 |
StubCodeMark mark(this, "StubRoutines", "implEncode"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5066 |
address start = __ pc(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5067 |
__ enter(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5068 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5069 |
// Save callee-saved registers before using them |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5070 |
__ push(r12); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5071 |
__ push(r13); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5072 |
__ push(r14); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5073 |
__ push(r15); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5074 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5075 |
// arguments |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5076 |
const Register source = c_rarg0; // Source Array |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5077 |
const Register start_offset = c_rarg1; // start offset |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5078 |
const Register end_offset = c_rarg2; // end offset |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5079 |
const Register dest = c_rarg3; // destination array |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5080 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5081 |
#ifndef _WIN64 |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5082 |
const Register dp = c_rarg4; // Position for writing to dest array |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5083 |
const Register isURL = c_rarg5;// Base64 or URL character set |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5084 |
#else |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5085 |
const Address dp_mem(rbp, 6 * wordSize); // length is on stack on Win64 |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5086 |
const Address isURL_mem(rbp, 7 * wordSize); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5087 |
const Register isURL = r10; // pick the volatile windows register |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5088 |
const Register dp = r12; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5089 |
__ movl(dp, dp_mem); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5090 |
__ movl(isURL, isURL_mem); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5091 |
#endif |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5092 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5093 |
const Register length = r14; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5094 |
Label L_process80, L_process32, L_process3, L_exit, L_processdata; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5095 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5096 |
// calculate length from offsets |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5097 |
__ movl(length, end_offset); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5098 |
__ subl(length, start_offset); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5099 |
__ cmpl(length, 0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5100 |
__ jcc(Assembler::lessEqual, L_exit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5101 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5102 |
__ lea(r11, ExternalAddress(StubRoutines::x86::base64_charset_addr())); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5103 |
// check if base64 charset(isURL=0) or base64 url charset(isURL=1) needs to be loaded |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5104 |
__ cmpl(isURL, 0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5105 |
__ jcc(Assembler::equal, L_processdata); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5106 |
__ lea(r11, ExternalAddress(StubRoutines::x86::base64url_charset_addr())); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5107 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5108 |
// load masks required for encoding data |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5109 |
__ BIND(L_processdata); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5110 |
__ movdqu(xmm16, ExternalAddress(StubRoutines::x86::base64_gather_mask_addr())); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5111 |
// Set 64 bits of K register. |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5112 |
__ evpcmpeqb(k3, xmm16, xmm16, Assembler::AVX_512bit); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5113 |
__ evmovdquq(xmm12, ExternalAddress(StubRoutines::x86::base64_bswap_mask_addr()), Assembler::AVX_256bit, r13); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5114 |
__ evmovdquq(xmm13, ExternalAddress(StubRoutines::x86::base64_right_shift_mask_addr()), Assembler::AVX_512bit, r13); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5115 |
__ evmovdquq(xmm14, ExternalAddress(StubRoutines::x86::base64_left_shift_mask_addr()), Assembler::AVX_512bit, r13); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5116 |
__ evmovdquq(xmm15, ExternalAddress(StubRoutines::x86::base64_and_mask_addr()), Assembler::AVX_512bit, r13); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5117 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5118 |
// Vector Base64 implementation, producing 96 bytes of encoded data |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
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diff
changeset
|
5119 |
__ BIND(L_process80); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5120 |
__ cmpl(length, 80); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5121 |
__ jcc(Assembler::below, L_process32); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5122 |
__ evmovdquq(xmm0, Address(source, start_offset, Address::times_1, 0), Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5123 |
__ evmovdquq(xmm1, Address(source, start_offset, Address::times_1, 24), Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5124 |
__ evmovdquq(xmm2, Address(source, start_offset, Address::times_1, 48), Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5125 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5126 |
//permute the input data in such a manner that we have continuity of the source |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5127 |
__ vpermq(xmm3, xmm0, 148, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5128 |
__ vpermq(xmm4, xmm1, 148, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5129 |
__ vpermq(xmm5, xmm2, 148, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5130 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5131 |
//shuffle input and group 3 bytes of data and to it add 0 as the 4th byte. |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5132 |
//we can deal with 12 bytes at a time in a 128 bit register |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5133 |
__ vpshufb(xmm3, xmm3, xmm12, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5134 |
__ vpshufb(xmm4, xmm4, xmm12, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5135 |
__ vpshufb(xmm5, xmm5, xmm12, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5136 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5137 |
//convert byte to word. Each 128 bit register will have 6 bytes for processing |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5138 |
__ vpmovzxbw(xmm3, xmm3, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5139 |
__ vpmovzxbw(xmm4, xmm4, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5140 |
__ vpmovzxbw(xmm5, xmm5, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5141 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5142 |
// Extract bits in the following pattern 6, 4+2, 2+4, 6 to convert 3, 8 bit numbers to 4, 6 bit numbers |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5143 |
__ evpsrlvw(xmm0, xmm3, xmm13, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5144 |
__ evpsrlvw(xmm1, xmm4, xmm13, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5145 |
__ evpsrlvw(xmm2, xmm5, xmm13, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5146 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5147 |
__ evpsllvw(xmm3, xmm3, xmm14, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5148 |
__ evpsllvw(xmm4, xmm4, xmm14, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5149 |
__ evpsllvw(xmm5, xmm5, xmm14, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5150 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5151 |
__ vpsrlq(xmm0, xmm0, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5152 |
__ vpsrlq(xmm1, xmm1, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5153 |
__ vpsrlq(xmm2, xmm2, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5154 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5155 |
__ vpsllq(xmm3, xmm3, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5156 |
__ vpsllq(xmm4, xmm4, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5157 |
__ vpsllq(xmm5, xmm5, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5158 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5159 |
__ vpandq(xmm3, xmm3, xmm15, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5160 |
__ vpandq(xmm4, xmm4, xmm15, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5161 |
__ vpandq(xmm5, xmm5, xmm15, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5162 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5163 |
// Get the final 4*6 bits base64 encoding |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5164 |
__ vporq(xmm3, xmm3, xmm0, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5165 |
__ vporq(xmm4, xmm4, xmm1, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5166 |
__ vporq(xmm5, xmm5, xmm2, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5167 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5168 |
// Shift |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5169 |
__ vpsrlq(xmm3, xmm3, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5170 |
__ vpsrlq(xmm4, xmm4, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5171 |
__ vpsrlq(xmm5, xmm5, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5172 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5173 |
// look up 6 bits in the base64 character set to fetch the encoding |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5174 |
// we are converting word to dword as gather instructions need dword indices for looking up encoding |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5175 |
__ vextracti64x4(xmm6, xmm3, 0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5176 |
__ vpmovzxwd(xmm0, xmm6, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5177 |
__ vextracti64x4(xmm6, xmm3, 1); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5178 |
__ vpmovzxwd(xmm1, xmm6, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5179 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5180 |
__ vextracti64x4(xmm6, xmm4, 0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5181 |
__ vpmovzxwd(xmm2, xmm6, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5182 |
__ vextracti64x4(xmm6, xmm4, 1); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5183 |
__ vpmovzxwd(xmm3, xmm6, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5184 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5185 |
__ vextracti64x4(xmm4, xmm5, 0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5186 |
__ vpmovzxwd(xmm6, xmm4, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5187 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5188 |
__ vextracti64x4(xmm4, xmm5, 1); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5189 |
__ vpmovzxwd(xmm7, xmm4, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5190 |
|
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5191 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5192 |
__ evpgatherdd(xmm4, k2, Address(r11, xmm0, Address::times_4, 0), Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5193 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5194 |
__ evpgatherdd(xmm5, k2, Address(r11, xmm1, Address::times_4, 0), Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5195 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5196 |
__ evpgatherdd(xmm8, k2, Address(r11, xmm2, Address::times_4, 0), Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5197 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5198 |
__ evpgatherdd(xmm9, k2, Address(r11, xmm3, Address::times_4, 0), Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5199 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5200 |
__ evpgatherdd(xmm10, k2, Address(r11, xmm6, Address::times_4, 0), Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5201 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5202 |
__ evpgatherdd(xmm11, k2, Address(r11, xmm7, Address::times_4, 0), Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5203 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5204 |
//Down convert dword to byte. Final output is 16*6 = 96 bytes long |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5205 |
__ evpmovdb(Address(dest, dp, Address::times_1, 0), xmm4, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5206 |
__ evpmovdb(Address(dest, dp, Address::times_1, 16), xmm5, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5207 |
__ evpmovdb(Address(dest, dp, Address::times_1, 32), xmm8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5208 |
__ evpmovdb(Address(dest, dp, Address::times_1, 48), xmm9, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5209 |
__ evpmovdb(Address(dest, dp, Address::times_1, 64), xmm10, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5210 |
__ evpmovdb(Address(dest, dp, Address::times_1, 80), xmm11, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5211 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5212 |
__ addq(dest, 96); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5213 |
__ addq(source, 72); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5214 |
__ subq(length, 72); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5215 |
__ jmp(L_process80); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5216 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5217 |
// Vector Base64 implementation generating 32 bytes of encoded data |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5218 |
__ BIND(L_process32); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5219 |
__ cmpl(length, 32); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5220 |
__ jcc(Assembler::below, L_process3); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5221 |
__ evmovdquq(xmm0, Address(source, start_offset), Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5222 |
__ vpermq(xmm0, xmm0, 148, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5223 |
__ vpshufb(xmm6, xmm0, xmm12, Assembler::AVX_256bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5224 |
__ vpmovzxbw(xmm6, xmm6, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5225 |
__ evpsrlvw(xmm2, xmm6, xmm13, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5226 |
__ evpsllvw(xmm3, xmm6, xmm14, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5227 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5228 |
__ vpsrlq(xmm2, xmm2, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5229 |
__ vpsllq(xmm3, xmm3, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5230 |
__ vpandq(xmm3, xmm3, xmm15, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5231 |
__ vporq(xmm1, xmm2, xmm3, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5232 |
__ vpsrlq(xmm1, xmm1, 8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5233 |
__ vextracti64x4(xmm9, xmm1, 0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5234 |
__ vpmovzxwd(xmm6, xmm9, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5235 |
__ vextracti64x4(xmm9, xmm1, 1); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5236 |
__ vpmovzxwd(xmm5, xmm9, Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5237 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5238 |
__ evpgatherdd(xmm8, k2, Address(r11, xmm6, Address::times_4, 0), Assembler::AVX_512bit); |
51976
390f529f4f22
8211251: Default mask register for avx512 instructions
kvn
parents:
51784
diff
changeset
|
5239 |
__ kmovql(k2, k3); |
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5240 |
__ evpgatherdd(xmm10, k2, Address(r11, xmm5, Address::times_4, 0), Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5241 |
__ evpmovdb(Address(dest, dp, Address::times_1, 0), xmm8, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5242 |
__ evpmovdb(Address(dest, dp, Address::times_1, 16), xmm10, Assembler::AVX_512bit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5243 |
__ subq(length, 24); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5244 |
__ addq(dest, 32); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5245 |
__ addq(source, 24); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5246 |
__ jmp(L_process32); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5247 |
|
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5248 |
// Scalar data processing takes 3 bytes at a time and produces 4 bytes of encoded data |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5249 |
/* This code corresponds to the scalar version of the following snippet in Base64.java |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5250 |
** int bits = (src[sp0++] & 0xff) << 16 |(src[sp0++] & 0xff) << 8 |(src[sp0++] & 0xff); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5251 |
** dst[dp0++] = (byte)base64[(bits >> > 18) & 0x3f]; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5252 |
** dst[dp0++] = (byte)base64[(bits >> > 12) & 0x3f]; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5253 |
** dst[dp0++] = (byte)base64[(bits >> > 6) & 0x3f]; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5254 |
** dst[dp0++] = (byte)base64[bits & 0x3f];*/ |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5255 |
__ BIND(L_process3); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5256 |
__ cmpl(length, 3); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5257 |
__ jcc(Assembler::below, L_exit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5258 |
// Read 1 byte at a time |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5259 |
__ movzbl(rax, Address(source, start_offset)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5260 |
__ shll(rax, 0x10); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5261 |
__ movl(r15, rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5262 |
__ movzbl(rax, Address(source, start_offset, Address::times_1, 1)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5263 |
__ shll(rax, 0x8); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5264 |
__ movzwl(rax, rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5265 |
__ orl(r15, rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5266 |
__ movzbl(rax, Address(source, start_offset, Address::times_1, 2)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5267 |
__ orl(rax, r15); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5268 |
// Save 3 bytes read in r15 |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5269 |
__ movl(r15, rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5270 |
__ shrl(rax, 0x12); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5271 |
__ andl(rax, 0x3f); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5272 |
// rax contains the index, r11 contains base64 lookup table |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5273 |
__ movb(rax, Address(r11, rax, Address::times_4)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5274 |
// Write the encoded byte to destination |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5275 |
__ movb(Address(dest, dp, Address::times_1, 0), rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5276 |
__ movl(rax, r15); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5277 |
__ shrl(rax, 0xc); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5278 |
__ andl(rax, 0x3f); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5279 |
__ movb(rax, Address(r11, rax, Address::times_4)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5280 |
__ movb(Address(dest, dp, Address::times_1, 1), rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5281 |
__ movl(rax, r15); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5282 |
__ shrl(rax, 0x6); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5283 |
__ andl(rax, 0x3f); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5284 |
__ movb(rax, Address(r11, rax, Address::times_4)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5285 |
__ movb(Address(dest, dp, Address::times_1, 2), rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5286 |
__ movl(rax, r15); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5287 |
__ andl(rax, 0x3f); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5288 |
__ movb(rax, Address(r11, rax, Address::times_4)); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5289 |
__ movb(Address(dest, dp, Address::times_1, 3), rax); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5290 |
__ subl(length, 3); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5291 |
__ addq(dest, 4); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5292 |
__ addq(source, 3); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5293 |
__ jmp(L_process3); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5294 |
__ BIND(L_exit); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5295 |
__ pop(r15); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5296 |
__ pop(r14); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5297 |
__ pop(r13); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5298 |
__ pop(r12); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5299 |
__ leave(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5300 |
__ ret(0); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5301 |
return start; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5302 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
5303 |
|
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5304 |
/** |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5305 |
* Arguments: |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5306 |
* |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5307 |
* Inputs: |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5308 |
* c_rarg0 - int crc |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5309 |
* c_rarg1 - byte* buf |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5310 |
* c_rarg2 - int length |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5311 |
* |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5312 |
* Ouput: |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5313 |
* rax - int crc result |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5314 |
*/ |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5315 |
address generate_updateBytesCRC32() { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5316 |
assert(UseCRC32Intrinsics, "need AVX and CLMUL instructions"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5317 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5318 |
__ align(CodeEntryAlignment); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5319 |
StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5320 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5321 |
address start = __ pc(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5322 |
// Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5323 |
// Unix: rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5324 |
// rscratch1: r10 |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5325 |
const Register crc = c_rarg0; // crc |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5326 |
const Register buf = c_rarg1; // source java byte array address |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5327 |
const Register len = c_rarg2; // length |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5328 |
const Register table = c_rarg3; // crc_table address (reuse register) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5329 |
const Register tmp = r11; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5330 |
assert_different_registers(crc, buf, len, table, tmp, rax); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5331 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5332 |
BLOCK_COMMENT("Entry:"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5333 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5334 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5335 |
__ kernel_crc32(crc, buf, len, table, tmp); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5336 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5337 |
__ movl(rax, crc); |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
5338 |
__ vzeroupper(); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5339 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5340 |
__ ret(0); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5341 |
|
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5342 |
return start; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
5343 |
} |
14132 | 5344 |
|
33066 | 5345 |
/** |
5346 |
* Arguments: |
|
5347 |
* |
|
5348 |
* Inputs: |
|
5349 |
* c_rarg0 - int crc |
|
5350 |
* c_rarg1 - byte* buf |
|
5351 |
* c_rarg2 - long length |
|
38238
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
5352 |
* c_rarg3 - table_start - optional (present only when doing a library_call, |
33066 | 5353 |
* not used by x86 algorithm) |
5354 |
* |
|
5355 |
* Ouput: |
|
5356 |
* rax - int crc result |
|
5357 |
*/ |
|
5358 |
address generate_updateBytesCRC32C(bool is_pclmulqdq_supported) { |
|
5359 |
assert(UseCRC32CIntrinsics, "need SSE4_2"); |
|
5360 |
__ align(CodeEntryAlignment); |
|
5361 |
StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32C"); |
|
5362 |
address start = __ pc(); |
|
5363 |
//reg.arg int#0 int#1 int#2 int#3 int#4 int#5 float regs |
|
5364 |
//Windows RCX RDX R8 R9 none none XMM0..XMM3 |
|
5365 |
//Lin / Sol RDI RSI RDX RCX R8 R9 XMM0..XMM7 |
|
5366 |
const Register crc = c_rarg0; // crc |
|
5367 |
const Register buf = c_rarg1; // source java byte array address |
|
5368 |
const Register len = c_rarg2; // length |
|
5369 |
const Register a = rax; |
|
5370 |
const Register j = r9; |
|
5371 |
const Register k = r10; |
|
5372 |
const Register l = r11; |
|
5373 |
#ifdef _WIN64 |
|
5374 |
const Register y = rdi; |
|
5375 |
const Register z = rsi; |
|
5376 |
#else |
|
5377 |
const Register y = rcx; |
|
5378 |
const Register z = r8; |
|
5379 |
#endif |
|
5380 |
assert_different_registers(crc, buf, len, a, j, k, l, y, z); |
|
5381 |
||
5382 |
BLOCK_COMMENT("Entry:"); |
|
5383 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
5384 |
#ifdef _WIN64 |
|
5385 |
__ push(y); |
|
5386 |
__ push(z); |
|
5387 |
#endif |
|
5388 |
__ crc32c_ipl_alg2_alt2(crc, buf, len, |
|
5389 |
a, j, k, |
|
5390 |
l, y, z, |
|
5391 |
c_farg0, c_farg1, c_farg2, |
|
5392 |
is_pclmulqdq_supported); |
|
5393 |
__ movl(rax, crc); |
|
5394 |
#ifdef _WIN64 |
|
5395 |
__ pop(z); |
|
5396 |
__ pop(y); |
|
5397 |
#endif |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
5398 |
__ vzeroupper(); |
33066 | 5399 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
5400 |
__ ret(0); |
|
5401 |
||
5402 |
return start; |
|
5403 |
} |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5404 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5405 |
/** |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5406 |
* Arguments: |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5407 |
* |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5408 |
* Input: |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5409 |
* c_rarg0 - x address |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5410 |
* c_rarg1 - x length |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5411 |
* c_rarg2 - y address |
49368
2ed1c37df3a5
8197405: Improve messages of AbstractMethodErrors and IncompatibleClassChangeErrors.
goetz
parents:
49347
diff
changeset
|
5412 |
* c_rarg3 - y length |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5413 |
* not Win64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5414 |
* c_rarg4 - z address |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5415 |
* c_rarg5 - z length |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5416 |
* Win64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5417 |
* rsp+40 - z address |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5418 |
* rsp+48 - z length |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5419 |
*/ |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5420 |
address generate_multiplyToLen() { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5421 |
__ align(CodeEntryAlignment); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5422 |
StubCodeMark mark(this, "StubRoutines", "multiplyToLen"); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5423 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5424 |
address start = __ pc(); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5425 |
// Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5426 |
// Unix: rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5427 |
const Register x = rdi; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5428 |
const Register xlen = rax; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5429 |
const Register y = rsi; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5430 |
const Register ylen = rcx; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5431 |
const Register z = r8; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5432 |
const Register zlen = r11; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5433 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5434 |
// Next registers will be saved on stack in multiply_to_len(). |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5435 |
const Register tmp1 = r12; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5436 |
const Register tmp2 = r13; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5437 |
const Register tmp3 = r14; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5438 |
const Register tmp4 = r15; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5439 |
const Register tmp5 = rbx; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5440 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5441 |
BLOCK_COMMENT("Entry:"); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5442 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5443 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5444 |
#ifndef _WIN64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5445 |
__ movptr(zlen, r9); // Save r9 in r11 - zlen |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5446 |
#endif |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5447 |
setup_arg_regs(4); // x => rdi, xlen => rsi, y => rdx |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5448 |
// ylen => rcx, z => r8, zlen => r11 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5449 |
// r9 and r10 may be used to save non-volatile registers |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5450 |
#ifdef _WIN64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5451 |
// last 2 arguments (#4, #5) are on stack on Win64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5452 |
__ movptr(z, Address(rsp, 6 * wordSize)); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5453 |
__ movptr(zlen, Address(rsp, 7 * wordSize)); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5454 |
#endif |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5455 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5456 |
__ movptr(xlen, rsi); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5457 |
__ movptr(y, rdx); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5458 |
__ multiply_to_len(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5459 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5460 |
restore_arg_regs(); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5461 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5462 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5463 |
__ ret(0); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5464 |
|
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5465 |
return start; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5466 |
} |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
5467 |
|
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5468 |
/** |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5469 |
* Arguments: |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5470 |
* |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5471 |
* Input: |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5472 |
* c_rarg0 - obja address |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5473 |
* c_rarg1 - objb address |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5474 |
* c_rarg3 - length length |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5475 |
* c_rarg4 - scale log2_array_indxscale |
38238
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
5476 |
* |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
5477 |
* Output: |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
5478 |
* rax - int >= mismatched index, < 0 bitwise complement of tail |
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5479 |
*/ |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5480 |
address generate_vectorizedMismatch() { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5481 |
__ align(CodeEntryAlignment); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5482 |
StubCodeMark mark(this, "StubRoutines", "vectorizedMismatch"); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5483 |
address start = __ pc(); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5484 |
|
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5485 |
BLOCK_COMMENT("Entry:"); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5486 |
__ enter(); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5487 |
|
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5488 |
#ifdef _WIN64 // Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5489 |
const Register scale = c_rarg0; //rcx, will exchange with r9 |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5490 |
const Register objb = c_rarg1; //rdx |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5491 |
const Register length = c_rarg2; //r8 |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5492 |
const Register obja = c_rarg3; //r9 |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5493 |
__ xchgq(obja, scale); //now obja and scale contains the correct contents |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5494 |
|
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5495 |
const Register tmp1 = r10; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5496 |
const Register tmp2 = r11; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5497 |
#endif |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5498 |
#ifndef _WIN64 // Unix: rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5499 |
const Register obja = c_rarg0; //U:rdi |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5500 |
const Register objb = c_rarg1; //U:rsi |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5501 |
const Register length = c_rarg2; //U:rdx |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5502 |
const Register scale = c_rarg3; //U:rcx |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5503 |
const Register tmp1 = r8; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5504 |
const Register tmp2 = r9; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5505 |
#endif |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5506 |
const Register result = rax; //return value |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5507 |
const XMMRegister vec0 = xmm0; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5508 |
const XMMRegister vec1 = xmm1; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5509 |
const XMMRegister vec2 = xmm2; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5510 |
|
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5511 |
__ vectorized_mismatch(obja, objb, length, scale, result, tmp1, tmp2, vec0, vec1, vec2); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5512 |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
5513 |
__ vzeroupper(); |
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5514 |
__ leave(); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5515 |
__ ret(0); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5516 |
|
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5517 |
return start; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5518 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34203
diff
changeset
|
5519 |
|
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5520 |
/** |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5521 |
* Arguments: |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5522 |
* |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5523 |
// Input: |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5524 |
// c_rarg0 - x address |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5525 |
// c_rarg1 - x length |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5526 |
// c_rarg2 - z address |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5527 |
// c_rarg3 - z lenth |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5528 |
* |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5529 |
*/ |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5530 |
address generate_squareToLen() { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5531 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5532 |
__ align(CodeEntryAlignment); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5533 |
StubCodeMark mark(this, "StubRoutines", "squareToLen"); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5534 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5535 |
address start = __ pc(); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5536 |
// Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5537 |
// Unix: rdi, rsi, rdx, rcx (c_rarg0, c_rarg1, ...) |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5538 |
const Register x = rdi; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5539 |
const Register len = rsi; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5540 |
const Register z = r8; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5541 |
const Register zlen = rcx; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5542 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5543 |
const Register tmp1 = r12; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5544 |
const Register tmp2 = r13; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5545 |
const Register tmp3 = r14; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5546 |
const Register tmp4 = r15; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5547 |
const Register tmp5 = rbx; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5548 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5549 |
BLOCK_COMMENT("Entry:"); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5550 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5551 |
|
51784
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
5552 |
setup_arg_regs(4); // x => rdi, len => rsi, z => rdx |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
5553 |
// zlen => rcx |
fbec908e2783
8203466: intermittent crash at jdk.internal.misc.Unsafe::getObjectVolatile (native)
coleenp
parents:
51756
diff
changeset
|
5554 |
// r9 and r10 may be used to save non-volatile registers |
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5555 |
__ movptr(r8, rdx); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5556 |
__ square_to_len(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx, rax); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5557 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5558 |
restore_arg_regs(); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5559 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5560 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5561 |
__ ret(0); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5562 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5563 |
return start; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5564 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5565 |
|
52142 | 5566 |
address generate_method_entry_barrier() { |
5567 |
__ align(CodeEntryAlignment); |
|
5568 |
StubCodeMark mark(this, "StubRoutines", "nmethod_entry_barrier"); |
|
5569 |
||
5570 |
Label deoptimize_label; |
|
5571 |
||
5572 |
address start = __ pc(); |
|
5573 |
||
5574 |
__ push(-1); // cookie, this is used for writing the new rsp when deoptimizing |
|
5575 |
||
5576 |
BLOCK_COMMENT("Entry:"); |
|
5577 |
__ enter(); // save rbp |
|
5578 |
||
5579 |
// save c_rarg0, because we want to use that value. |
|
5580 |
// We could do without it but then we depend on the number of slots used by pusha |
|
5581 |
__ push(c_rarg0); |
|
5582 |
||
5583 |
__ lea(c_rarg0, Address(rsp, wordSize * 3)); // 1 for cookie, 1 for rbp, 1 for c_rarg0 - this should be the return address |
|
5584 |
||
5585 |
__ pusha(); |
|
5586 |
||
5587 |
// The method may have floats as arguments, and we must spill them before calling |
|
5588 |
// the VM runtime. |
|
5589 |
assert(Argument::n_float_register_parameters_j == 8, "Assumption"); |
|
5590 |
const int xmm_size = wordSize * 2; |
|
5591 |
const int xmm_spill_size = xmm_size * Argument::n_float_register_parameters_j; |
|
5592 |
__ subptr(rsp, xmm_spill_size); |
|
5593 |
__ movdqu(Address(rsp, xmm_size * 7), xmm7); |
|
5594 |
__ movdqu(Address(rsp, xmm_size * 6), xmm6); |
|
5595 |
__ movdqu(Address(rsp, xmm_size * 5), xmm5); |
|
5596 |
__ movdqu(Address(rsp, xmm_size * 4), xmm4); |
|
5597 |
__ movdqu(Address(rsp, xmm_size * 3), xmm3); |
|
5598 |
__ movdqu(Address(rsp, xmm_size * 2), xmm2); |
|
5599 |
__ movdqu(Address(rsp, xmm_size * 1), xmm1); |
|
5600 |
__ movdqu(Address(rsp, xmm_size * 0), xmm0); |
|
5601 |
||
5602 |
__ call_VM_leaf(CAST_FROM_FN_PTR(address, static_cast<int (*)(address*)>(BarrierSetNMethod::nmethod_stub_entry_barrier)), 1); |
|
5603 |
||
5604 |
__ movdqu(xmm0, Address(rsp, xmm_size * 0)); |
|
5605 |
__ movdqu(xmm1, Address(rsp, xmm_size * 1)); |
|
5606 |
__ movdqu(xmm2, Address(rsp, xmm_size * 2)); |
|
5607 |
__ movdqu(xmm3, Address(rsp, xmm_size * 3)); |
|
5608 |
__ movdqu(xmm4, Address(rsp, xmm_size * 4)); |
|
5609 |
__ movdqu(xmm5, Address(rsp, xmm_size * 5)); |
|
5610 |
__ movdqu(xmm6, Address(rsp, xmm_size * 6)); |
|
5611 |
__ movdqu(xmm7, Address(rsp, xmm_size * 7)); |
|
5612 |
__ addptr(rsp, xmm_spill_size); |
|
5613 |
||
5614 |
__ cmpl(rax, 1); // 1 means deoptimize |
|
5615 |
__ jcc(Assembler::equal, deoptimize_label); |
|
5616 |
||
5617 |
__ popa(); |
|
5618 |
__ pop(c_rarg0); |
|
5619 |
||
5620 |
__ leave(); |
|
5621 |
||
5622 |
__ addptr(rsp, 1 * wordSize); // cookie |
|
5623 |
__ ret(0); |
|
5624 |
||
5625 |
||
5626 |
__ BIND(deoptimize_label); |
|
5627 |
||
5628 |
__ popa(); |
|
5629 |
__ pop(c_rarg0); |
|
5630 |
||
5631 |
__ leave(); |
|
5632 |
||
5633 |
// this can be taken out, but is good for verification purposes. getting a SIGSEGV |
|
5634 |
// here while still having a correct stack is valuable |
|
5635 |
__ testptr(rsp, Address(rsp, 0)); |
|
5636 |
||
5637 |
__ movptr(rsp, Address(rsp, 0)); // new rsp was written in the barrier |
|
5638 |
__ jmp(Address(rsp, -1 * wordSize)); // jmp target should be callers verified_entry_point |
|
5639 |
||
5640 |
return start; |
|
5641 |
} |
|
5642 |
||
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5643 |
/** |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5644 |
* Arguments: |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5645 |
* |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5646 |
* Input: |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5647 |
* c_rarg0 - out address |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5648 |
* c_rarg1 - in address |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5649 |
* c_rarg2 - offset |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5650 |
* c_rarg3 - len |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5651 |
* not Win64 |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5652 |
* c_rarg4 - k |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5653 |
* Win64 |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5654 |
* rsp+40 - k |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5655 |
*/ |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5656 |
address generate_mulAdd() { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5657 |
__ align(CodeEntryAlignment); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5658 |
StubCodeMark mark(this, "StubRoutines", "mulAdd"); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5659 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5660 |
address start = __ pc(); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5661 |
// Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5662 |
// Unix: rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5663 |
const Register out = rdi; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5664 |
const Register in = rsi; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5665 |
const Register offset = r11; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5666 |
const Register len = rcx; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5667 |
const Register k = r8; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5668 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5669 |
// Next registers will be saved on stack in mul_add(). |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5670 |
const Register tmp1 = r12; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5671 |
const Register tmp2 = r13; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5672 |
const Register tmp3 = r14; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5673 |
const Register tmp4 = r15; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5674 |
const Register tmp5 = rbx; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5675 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5676 |
BLOCK_COMMENT("Entry:"); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5677 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5678 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5679 |
setup_arg_regs(4); // out => rdi, in => rsi, offset => rdx |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5680 |
// len => rcx, k => r8 |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5681 |
// r9 and r10 may be used to save non-volatile registers |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5682 |
#ifdef _WIN64 |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5683 |
// last argument is on stack on Win64 |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5684 |
__ movl(k, Address(rsp, 6 * wordSize)); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5685 |
#endif |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5686 |
__ movptr(r11, rdx); // move offset in rdx to offset(r11) |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5687 |
__ mul_add(out, in, offset, len, k, tmp1, tmp2, tmp3, tmp4, tmp5, rdx, rax); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5688 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5689 |
restore_arg_regs(); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5690 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5691 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5692 |
__ ret(0); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5693 |
|
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5694 |
return start; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5695 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5696 |
|
33089 | 5697 |
address generate_libmExp() { |
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5698 |
StubCodeMark mark(this, "StubRoutines", "libmExp"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5699 |
|
33089 | 5700 |
address start = __ pc(); |
5701 |
||
5702 |
const XMMRegister x0 = xmm0; |
|
5703 |
const XMMRegister x1 = xmm1; |
|
5704 |
const XMMRegister x2 = xmm2; |
|
5705 |
const XMMRegister x3 = xmm3; |
|
5706 |
||
5707 |
const XMMRegister x4 = xmm4; |
|
5708 |
const XMMRegister x5 = xmm5; |
|
5709 |
const XMMRegister x6 = xmm6; |
|
5710 |
const XMMRegister x7 = xmm7; |
|
5711 |
||
5712 |
const Register tmp = r11; |
|
5713 |
||
5714 |
BLOCK_COMMENT("Entry:"); |
|
5715 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
5716 |
||
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43423
diff
changeset
|
5717 |
__ fast_exp(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp); |
33089 | 5718 |
|
33465 | 5719 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
5720 |
__ ret(0); |
|
5721 |
||
5722 |
return start; |
|
5723 |
||
5724 |
} |
|
5725 |
||
5726 |
address generate_libmLog() { |
|
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5727 |
StubCodeMark mark(this, "StubRoutines", "libmLog"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5728 |
|
33465 | 5729 |
address start = __ pc(); |
5730 |
||
5731 |
const XMMRegister x0 = xmm0; |
|
5732 |
const XMMRegister x1 = xmm1; |
|
5733 |
const XMMRegister x2 = xmm2; |
|
5734 |
const XMMRegister x3 = xmm3; |
|
5735 |
||
5736 |
const XMMRegister x4 = xmm4; |
|
5737 |
const XMMRegister x5 = xmm5; |
|
5738 |
const XMMRegister x6 = xmm6; |
|
5739 |
const XMMRegister x7 = xmm7; |
|
5740 |
||
5741 |
const Register tmp1 = r11; |
|
5742 |
const Register tmp2 = r8; |
|
5743 |
||
5744 |
BLOCK_COMMENT("Entry:"); |
|
5745 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
5746 |
||
5747 |
__ fast_log(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2); |
|
5748 |
||
33089 | 5749 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
5750 |
__ ret(0); |
|
5751 |
||
5752 |
return start; |
|
5753 |
||
5754 |
} |
|
5755 |
||
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5756 |
address generate_libmLog10() { |
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5757 |
StubCodeMark mark(this, "StubRoutines", "libmLog10"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5758 |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5759 |
address start = __ pc(); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5760 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5761 |
const XMMRegister x0 = xmm0; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5762 |
const XMMRegister x1 = xmm1; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5763 |
const XMMRegister x2 = xmm2; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5764 |
const XMMRegister x3 = xmm3; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5765 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5766 |
const XMMRegister x4 = xmm4; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5767 |
const XMMRegister x5 = xmm5; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5768 |
const XMMRegister x6 = xmm6; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5769 |
const XMMRegister x7 = xmm7; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5770 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5771 |
const Register tmp = r11; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5772 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5773 |
BLOCK_COMMENT("Entry:"); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5774 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5775 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5776 |
__ fast_log10(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5777 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5778 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5779 |
__ ret(0); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5780 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5781 |
return start; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5782 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5783 |
} |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5784 |
|
35146 | 5785 |
address generate_libmPow() { |
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5786 |
StubCodeMark mark(this, "StubRoutines", "libmPow"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5787 |
|
35146 | 5788 |
address start = __ pc(); |
5789 |
||
5790 |
const XMMRegister x0 = xmm0; |
|
5791 |
const XMMRegister x1 = xmm1; |
|
5792 |
const XMMRegister x2 = xmm2; |
|
5793 |
const XMMRegister x3 = xmm3; |
|
5794 |
||
5795 |
const XMMRegister x4 = xmm4; |
|
5796 |
const XMMRegister x5 = xmm5; |
|
5797 |
const XMMRegister x6 = xmm6; |
|
5798 |
const XMMRegister x7 = xmm7; |
|
5799 |
||
5800 |
const Register tmp1 = r8; |
|
5801 |
const Register tmp2 = r9; |
|
5802 |
const Register tmp3 = r10; |
|
5803 |
const Register tmp4 = r11; |
|
5804 |
||
5805 |
BLOCK_COMMENT("Entry:"); |
|
5806 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
5807 |
||
5808 |
__ fast_pow(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2, tmp3, tmp4); |
|
5809 |
||
5810 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
5811 |
__ ret(0); |
|
5812 |
||
5813 |
return start; |
|
5814 |
||
5815 |
} |
|
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
5816 |
|
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5817 |
address generate_libmSin() { |
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5818 |
StubCodeMark mark(this, "StubRoutines", "libmSin"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5819 |
|
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5820 |
address start = __ pc(); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5821 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5822 |
const XMMRegister x0 = xmm0; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5823 |
const XMMRegister x1 = xmm1; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5824 |
const XMMRegister x2 = xmm2; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5825 |
const XMMRegister x3 = xmm3; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5826 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5827 |
const XMMRegister x4 = xmm4; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5828 |
const XMMRegister x5 = xmm5; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5829 |
const XMMRegister x6 = xmm6; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5830 |
const XMMRegister x7 = xmm7; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5831 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5832 |
const Register tmp1 = r8; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5833 |
const Register tmp2 = r9; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5834 |
const Register tmp3 = r10; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5835 |
const Register tmp4 = r11; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5836 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5837 |
BLOCK_COMMENT("Entry:"); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5838 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5839 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5840 |
#ifdef _WIN64 |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5841 |
__ push(rsi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5842 |
__ push(rdi); |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5843 |
#endif |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5844 |
__ fast_sin(x0, x1, x2, x3, x4, x5, x6, x7, rax, rbx, rcx, rdx, tmp1, tmp2, tmp3, tmp4); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5845 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5846 |
#ifdef _WIN64 |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5847 |
__ pop(rdi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5848 |
__ pop(rsi); |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5849 |
#endif |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5850 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5851 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5852 |
__ ret(0); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5853 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5854 |
return start; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5855 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5856 |
} |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5857 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5858 |
address generate_libmCos() { |
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5859 |
StubCodeMark mark(this, "StubRoutines", "libmCos"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5860 |
|
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5861 |
address start = __ pc(); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5862 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5863 |
const XMMRegister x0 = xmm0; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5864 |
const XMMRegister x1 = xmm1; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5865 |
const XMMRegister x2 = xmm2; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5866 |
const XMMRegister x3 = xmm3; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5867 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5868 |
const XMMRegister x4 = xmm4; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5869 |
const XMMRegister x5 = xmm5; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5870 |
const XMMRegister x6 = xmm6; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5871 |
const XMMRegister x7 = xmm7; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5872 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5873 |
const Register tmp1 = r8; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5874 |
const Register tmp2 = r9; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5875 |
const Register tmp3 = r10; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5876 |
const Register tmp4 = r11; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5877 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5878 |
BLOCK_COMMENT("Entry:"); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5879 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5880 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5881 |
#ifdef _WIN64 |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5882 |
__ push(rsi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5883 |
__ push(rdi); |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5884 |
#endif |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5885 |
__ fast_cos(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2, tmp3, tmp4); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5886 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5887 |
#ifdef _WIN64 |
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5888 |
__ pop(rdi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5889 |
__ pop(rsi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5890 |
#endif |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5891 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5892 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5893 |
__ ret(0); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5894 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5895 |
return start; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5896 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5897 |
} |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5898 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5899 |
address generate_libmTan() { |
47810
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5900 |
StubCodeMark mark(this, "StubRoutines", "libmTan"); |
083c15bfba35
8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents:
47634
diff
changeset
|
5901 |
|
38018
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5902 |
address start = __ pc(); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5903 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5904 |
const XMMRegister x0 = xmm0; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5905 |
const XMMRegister x1 = xmm1; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5906 |
const XMMRegister x2 = xmm2; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5907 |
const XMMRegister x3 = xmm3; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5908 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5909 |
const XMMRegister x4 = xmm4; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5910 |
const XMMRegister x5 = xmm5; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5911 |
const XMMRegister x6 = xmm6; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5912 |
const XMMRegister x7 = xmm7; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5913 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5914 |
const Register tmp1 = r8; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5915 |
const Register tmp2 = r9; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5916 |
const Register tmp3 = r10; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5917 |
const Register tmp4 = r11; |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5918 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5919 |
BLOCK_COMMENT("Entry:"); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5920 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5921 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5922 |
#ifdef _WIN64 |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5923 |
__ push(rsi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5924 |
__ push(rdi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5925 |
#endif |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5926 |
__ fast_tan(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2, tmp3, tmp4); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5927 |
|
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5928 |
#ifdef _WIN64 |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5929 |
__ pop(rdi); |
1dc6c6f21231
8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents:
36825
diff
changeset
|
5930 |
__ pop(rsi); |
35540
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5931 |
#endif |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5932 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5933 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5934 |
__ ret(0); |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5935 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5936 |
return start; |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5937 |
|
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5938 |
} |
e001ad24dcdb
8143353: update for x86 sin and cos in the math lib
vdeshpande
parents:
35537
diff
changeset
|
5939 |
|
1 | 5940 |
#undef __ |
5941 |
#define __ masm-> |
|
5942 |
||
5943 |
// Continuation point for throwing of implicit exceptions that are |
|
5944 |
// not handled in the current activation. Fabricates an exception |
|
5945 |
// oop and initiates normal exception dispatching in this |
|
5946 |
// frame. Since we need to preserve callee-saved values (currently |
|
5947 |
// only for C2, but done for C1 as well) we need a callee-saved oop |
|
5948 |
// map and therefore have to make these stubs into RuntimeStubs |
|
5949 |
// rather than BufferBlobs. If the compiler needs all registers to |
|
5950 |
// be preserved between the fault point and the exception handler |
|
5951 |
// then it must assume responsibility for that in |
|
5952 |
// AbstractCompiler::continuation_for_implicit_null_exception or |
|
5953 |
// continuation_for_implicit_division_by_zero_exception. All other |
|
5954 |
// implicit exceptions (e.g., NullPointerException or |
|
5955 |
// AbstractMethodError on entry) are either at call sites or |
|
5956 |
// otherwise assume that stack unwinding will be initiated, so |
|
5957 |
// caller saved registers were assumed volatile in the compiler. |
|
5958 |
address generate_throw_exception(const char* name, |
|
5959 |
address runtime_entry, |
|
10004
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
5960 |
Register arg1 = noreg, |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
5961 |
Register arg2 = noreg) { |
1 | 5962 |
// Information about frame layout at time of blocking runtime call. |
5963 |
// Note that we only have to preserve callee-saved registers since |
|
5964 |
// the compilers are responsible for supplying a continuation point |
|
5965 |
// if they expect all registers to be preserved. |
|
5966 |
enum layout { |
|
5967 |
rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt, |
|
5968 |
rbp_off2, |
|
5969 |
return_off, |
|
5970 |
return_off2, |
|
5971 |
framesize // inclusive of return address |
|
5972 |
}; |
|
5973 |
||
5974 |
int insts_size = 512; |
|
5975 |
int locs_size = 64; |
|
5976 |
||
5977 |
CodeBuffer code(name, insts_size, locs_size); |
|
5978 |
OopMapSet* oop_maps = new OopMapSet(); |
|
5979 |
MacroAssembler* masm = new MacroAssembler(&code); |
|
5980 |
||
5981 |
address start = __ pc(); |
|
5982 |
||
5983 |
// This is an inlined and slightly modified version of call_VM |
|
5984 |
// which has the ability to fetch the return PC out of |
|
5985 |
// thread-local storage and also sets up last_Java_sp slightly |
|
5986 |
// differently than the real call_VM |
|
5987 |
||
5988 |
__ enter(); // required for proper stackwalking of RuntimeStub frame |
|
5989 |
||
5990 |
assert(is_even(framesize/2), "sp not 16-byte aligned"); |
|
5991 |
||
5992 |
// return address and rbp are already in place |
|
1066 | 5993 |
__ subptr(rsp, (framesize-4) << LogBytesPerInt); // prolog |
1 | 5994 |
|
5995 |
int frame_complete = __ pc() - start; |
|
5996 |
||
5997 |
// Set up last_Java_sp and last_Java_fp |
|
11725
49d1e1f1421f
7119286: JSR292: SIGSEGV in JNIHandleBlock::release_block(JNIHandleBlock*, Thread*)+0x3c
roland
parents:
11439
diff
changeset
|
5998 |
address the_pc = __ pc(); |
49d1e1f1421f
7119286: JSR292: SIGSEGV in JNIHandleBlock::release_block(JNIHandleBlock*, Thread*)+0x3c
roland
parents:
11439
diff
changeset
|
5999 |
__ set_last_Java_frame(rsp, rbp, the_pc); |
49d1e1f1421f
7119286: JSR292: SIGSEGV in JNIHandleBlock::release_block(JNIHandleBlock*, Thread*)+0x3c
roland
parents:
11439
diff
changeset
|
6000 |
__ andptr(rsp, -(StackAlignmentInBytes)); // Align stack |
1 | 6001 |
|
6002 |
// Call runtime |
|
10004
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6003 |
if (arg1 != noreg) { |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6004 |
assert(arg2 != c_rarg1, "clobbered"); |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6005 |
__ movptr(c_rarg1, arg1); |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6006 |
} |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6007 |
if (arg2 != noreg) { |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6008 |
__ movptr(c_rarg2, arg2); |
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6009 |
} |
1066 | 6010 |
__ movptr(c_rarg0, r15_thread); |
1 | 6011 |
BLOCK_COMMENT("call runtime_entry"); |
6012 |
__ call(RuntimeAddress(runtime_entry)); |
|
6013 |
||
6014 |
// Generate oop map |
|
6015 |
OopMap* map = new OopMap(framesize, 0); |
|
6016 |
||
11785
10f778832544
7144405: JumbleGC002 assert(m->offset() == pc_offset) failed: oopmap not found
roland
parents:
11725
diff
changeset
|
6017 |
oop_maps->add_gc_map(the_pc - start, map); |
1 | 6018 |
|
40644
39e631ed7145
8161598: Kitchensink fails: assert(nm->insts_contains(original_pc)) failed: original PC must be in nmethod/CompiledMethod
dlong
parents:
38699
diff
changeset
|
6019 |
__ reset_last_Java_frame(true); |
1 | 6020 |
|
6021 |
__ leave(); // required for proper stackwalking of RuntimeStub frame |
|
6022 |
||
6023 |
// check for pending exceptions |
|
6024 |
#ifdef ASSERT |
|
6025 |
Label L; |
|
1066 | 6026 |
__ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), |
6027 |
(int32_t) NULL_WORD); |
|
1 | 6028 |
__ jcc(Assembler::notEqual, L); |
6029 |
__ should_not_reach_here(); |
|
6030 |
__ bind(L); |
|
6031 |
#endif // ASSERT |
|
6032 |
__ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); |
|
6033 |
||
6034 |
||
6035 |
// codeBlob framesize is in words (not VMRegImpl::slot_size) |
|
6036 |
RuntimeStub* stub = |
|
6037 |
RuntimeStub::new_runtime_stub(name, |
|
6038 |
&code, |
|
6039 |
frame_complete, |
|
6040 |
(framesize >> (LogBytesPerWord - LogBytesPerInt)), |
|
6041 |
oop_maps, false); |
|
6042 |
return stub->entry_point(); |
|
6043 |
} |
|
6044 |
||
18958
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6045 |
void create_control_words() { |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6046 |
// Round to nearest, 53-bit mode, exceptions masked |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6047 |
StubRoutines::_fpu_cntrl_wrd_std = 0x027F; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6048 |
// Round to zero, 53-bit mode, exception mased |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6049 |
StubRoutines::_fpu_cntrl_wrd_trunc = 0x0D7F; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6050 |
// Round to nearest, 24-bit mode, exceptions masked |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6051 |
StubRoutines::_fpu_cntrl_wrd_24 = 0x007F; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6052 |
// Round to nearest, 64-bit mode, exceptions masked |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6053 |
StubRoutines::_mxcsr_std = 0x1F80; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6054 |
// Note: the following two constants are 80-bit values |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6055 |
// layout is critical for correct loading by FPU. |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6056 |
// Bias for strict fp multiply/divide |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6057 |
StubRoutines::_fpu_subnormal_bias1[0]= 0x00000000; // 2^(-15360) == 0x03ff 8000 0000 0000 0000 |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6058 |
StubRoutines::_fpu_subnormal_bias1[1]= 0x80000000; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6059 |
StubRoutines::_fpu_subnormal_bias1[2]= 0x03ff; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6060 |
// Un-Bias for strict fp multiply/divide |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6061 |
StubRoutines::_fpu_subnormal_bias2[0]= 0x00000000; // 2^(+15360) == 0x7bff 8000 0000 0000 0000 |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6062 |
StubRoutines::_fpu_subnormal_bias2[1]= 0x80000000; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6063 |
StubRoutines::_fpu_subnormal_bias2[2]= 0x7bff; |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6064 |
} |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6065 |
|
1 | 6066 |
// Initialization |
6067 |
void generate_initial() { |
|
6068 |
// Generates all stubs and initializes the entry points |
|
6069 |
||
18958
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6070 |
// This platform-specific settings are needed by generate_call_stub() |
7fdf6d23667d
8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents:
18507
diff
changeset
|
6071 |
create_control_words(); |
1 | 6072 |
|
6073 |
// entry points that exist in all platforms Note: This is code |
|
6074 |
// that could be shared among different platforms - however the |
|
6075 |
// benefit seems to be smaller than the disadvantage of having a |
|
6076 |
// much more complicated generator structure. See also comment in |
|
6077 |
// stubRoutines.hpp. |
|
6078 |
||
6079 |
StubRoutines::_forward_exception_entry = generate_forward_exception(); |
|
6080 |
||
6081 |
StubRoutines::_call_stub_entry = |
|
6082 |
generate_call_stub(StubRoutines::_call_stub_return_address); |
|
6083 |
||
6084 |
// is referenced by megamorphic call |
|
6085 |
StubRoutines::_catch_exception_entry = generate_catch_exception(); |
|
6086 |
||
6087 |
// atomic calls |
|
48468 | 6088 |
StubRoutines::_atomic_xchg_entry = generate_atomic_xchg(); |
6089 |
StubRoutines::_atomic_xchg_long_entry = generate_atomic_xchg_long(); |
|
6090 |
StubRoutines::_atomic_cmpxchg_entry = generate_atomic_cmpxchg(); |
|
6091 |
StubRoutines::_atomic_cmpxchg_byte_entry = generate_atomic_cmpxchg_byte(); |
|
6092 |
StubRoutines::_atomic_cmpxchg_long_entry = generate_atomic_cmpxchg_long(); |
|
6093 |
StubRoutines::_atomic_add_entry = generate_atomic_add(); |
|
6094 |
StubRoutines::_atomic_add_long_entry = generate_atomic_add_long(); |
|
6095 |
StubRoutines::_fence_entry = generate_orderaccess_fence(); |
|
1 | 6096 |
|
6097 |
// platform dependent |
|
1066 | 6098 |
StubRoutines::x86::_get_previous_fp_entry = generate_get_previous_fp(); |
11961
0abd4cd26e5a
7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents:
11785
diff
changeset
|
6099 |
StubRoutines::x86::_get_previous_sp_entry = generate_get_previous_sp(); |
1066 | 6100 |
|
6101 |
StubRoutines::x86::_verify_mxcsr_entry = generate_verify_mxcsr(); |
|
10004
190e88f7edd1
7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents:
8876
diff
changeset
|
6102 |
|
11411 | 6103 |
// Build this early so it's available for the interpreter. |
6104 |
StubRoutines::_throw_StackOverflowError_entry = |
|
6105 |
generate_throw_exception("StackOverflowError throw_exception", |
|
6106 |
CAST_FROM_FN_PTR(address, |
|
6107 |
SharedRuntime:: |
|
6108 |
throw_StackOverflowError)); |
|
35071
a0910b1d3e0d
8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents:
34203
diff
changeset
|
6109 |
StubRoutines::_throw_delayed_StackOverflowError_entry = |
a0910b1d3e0d
8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents:
34203
diff
changeset
|
6110 |
generate_throw_exception("delayed StackOverflowError throw_exception", |
a0910b1d3e0d
8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents:
34203
diff
changeset
|
6111 |
CAST_FROM_FN_PTR(address, |
a0910b1d3e0d
8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents:
34203
diff
changeset
|
6112 |
SharedRuntime:: |
a0910b1d3e0d
8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents:
34203
diff
changeset
|
6113 |
throw_delayed_StackOverflowError)); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
6114 |
if (UseCRC32Intrinsics) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
6115 |
// set table address before stub generation which use it |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
6116 |
StubRoutines::_crc_table_adr = (address)StubRoutines::x86::_crc_table; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
6117 |
StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32(); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
18073
diff
changeset
|
6118 |
} |
33066 | 6119 |
|
6120 |
if (UseCRC32CIntrinsics) { |
|
6121 |
bool supports_clmul = VM_Version::supports_clmul(); |
|
6122 |
StubRoutines::x86::generate_CRC32C_table(supports_clmul); |
|
6123 |
StubRoutines::_crc32c_table_addr = (address)StubRoutines::x86::_crc32c_table; |
|
6124 |
StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C(supports_clmul); |
|
6125 |
} |
|
42618
08162de8f053
8170430: x86 pow() stub from Intel libm is inconsistent with pow() from fdlib
vdeshpande
parents:
42039
diff
changeset
|
6126 |
if (VM_Version::supports_sse2() && UseLibmIntrinsic && InlineIntrinsics) { |
38699
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6127 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin) || |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6128 |
vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos) || |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6129 |
vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dtan)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6130 |
StubRoutines::x86::_ONEHALF_adr = (address)StubRoutines::x86::_ONEHALF; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6131 |
StubRoutines::x86::_P_2_adr = (address)StubRoutines::x86::_P_2; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6132 |
StubRoutines::x86::_SC_4_adr = (address)StubRoutines::x86::_SC_4; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6133 |
StubRoutines::x86::_Ctable_adr = (address)StubRoutines::x86::_Ctable; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6134 |
StubRoutines::x86::_SC_2_adr = (address)StubRoutines::x86::_SC_2; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6135 |
StubRoutines::x86::_SC_3_adr = (address)StubRoutines::x86::_SC_3; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6136 |
StubRoutines::x86::_SC_1_adr = (address)StubRoutines::x86::_SC_1; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6137 |
StubRoutines::x86::_PI_INV_TABLE_adr = (address)StubRoutines::x86::_PI_INV_TABLE; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6138 |
StubRoutines::x86::_PI_4_adr = (address)StubRoutines::x86::_PI_4; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6139 |
StubRoutines::x86::_PI32INV_adr = (address)StubRoutines::x86::_PI32INV; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6140 |
StubRoutines::x86::_SIGN_MASK_adr = (address)StubRoutines::x86::_SIGN_MASK; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6141 |
StubRoutines::x86::_P_1_adr = (address)StubRoutines::x86::_P_1; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6142 |
StubRoutines::x86::_P_3_adr = (address)StubRoutines::x86::_P_3; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6143 |
StubRoutines::x86::_NEG_ZERO_adr = (address)StubRoutines::x86::_NEG_ZERO; |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6144 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6145 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dexp)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6146 |
StubRoutines::_dexp = generate_libmExp(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6147 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6148 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dlog)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6149 |
StubRoutines::_dlog = generate_libmLog(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6150 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6151 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dlog10)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6152 |
StubRoutines::_dlog10 = generate_libmLog10(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6153 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6154 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dpow)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6155 |
StubRoutines::_dpow = generate_libmPow(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6156 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6157 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6158 |
StubRoutines::_dsin = generate_libmSin(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6159 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6160 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6161 |
StubRoutines::_dcos = generate_libmCos(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6162 |
} |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6163 |
if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dtan)) { |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6164 |
StubRoutines::_dtan = generate_libmTan(); |
f8bec5f6b09c
8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents:
38246
diff
changeset
|
6165 |
} |
33465 | 6166 |
} |
1 | 6167 |
} |
6168 |
||
6169 |
void generate_all() { |
|
6170 |
// Generates all stubs and initializes the entry points |
|
6171 |
||
6172 |
// These entry points require SharedInfo::stack0 to be set up in |
|
6173 |
// non-core builds and need to be relocatable, so they each |
|
6174 |
// fabricate a RuntimeStub internally. |
|
6175 |
StubRoutines::_throw_AbstractMethodError_entry = |
|
6176 |
generate_throw_exception("AbstractMethodError throw_exception", |
|
6177 |
CAST_FROM_FN_PTR(address, |
|
6178 |
SharedRuntime:: |
|
10545 | 6179 |
throw_AbstractMethodError)); |
1 | 6180 |
|
189
4248c8e21063
6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents:
1
diff
changeset
|
6181 |
StubRoutines::_throw_IncompatibleClassChangeError_entry = |
4248c8e21063
6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents:
1
diff
changeset
|
6182 |
generate_throw_exception("IncompatibleClassChangeError throw_exception", |
4248c8e21063
6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents:
1
diff
changeset
|
6183 |
CAST_FROM_FN_PTR(address, |
4248c8e21063
6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents:
1
diff
changeset
|
6184 |
SharedRuntime:: |
10545 | 6185 |
throw_IncompatibleClassChangeError)); |
1 | 6186 |
|
6187 |
StubRoutines::_throw_NullPointerException_at_call_entry = |
|
6188 |
generate_throw_exception("NullPointerException at call throw_exception", |
|
6189 |
CAST_FROM_FN_PTR(address, |
|
6190 |
SharedRuntime:: |
|
10545 | 6191 |
throw_NullPointerException_at_call)); |
1 | 6192 |
|
6193 |
// entry points that are platform specific |
|
1066 | 6194 |
StubRoutines::x86::_f2i_fixup = generate_f2i_fixup(); |
6195 |
StubRoutines::x86::_f2l_fixup = generate_f2l_fixup(); |
|
6196 |
StubRoutines::x86::_d2i_fixup = generate_d2i_fixup(); |
|
6197 |
StubRoutines::x86::_d2l_fixup = generate_d2l_fixup(); |
|
6198 |
||
6199 |
StubRoutines::x86::_float_sign_mask = generate_fp_mask("float_sign_mask", 0x7FFFFFFF7FFFFFFF); |
|
6200 |
StubRoutines::x86::_float_sign_flip = generate_fp_mask("float_sign_flip", 0x8000000080000000); |
|
6201 |
StubRoutines::x86::_double_sign_mask = generate_fp_mask("double_sign_mask", 0x7FFFFFFFFFFFFFFF); |
|
6202 |
StubRoutines::x86::_double_sign_flip = generate_fp_mask("double_sign_flip", 0x8000000000000000); |
|
54750 | 6203 |
StubRoutines::x86::_vector_float_sign_mask = generate_vector_mask("vector_float_sign_mask", 0x7FFFFFFF7FFFFFFF); |
6204 |
StubRoutines::x86::_vector_float_sign_flip = generate_vector_mask("vector_float_sign_flip", 0x8000000080000000); |
|
6205 |
StubRoutines::x86::_vector_double_sign_mask = generate_vector_mask("vector_double_sign_mask", 0x7FFFFFFFFFFFFFFF); |
|
6206 |
StubRoutines::x86::_vector_double_sign_flip = generate_vector_mask("vector_double_sign_flip", 0x8000000000000000); |
|
6207 |
StubRoutines::x86::_vector_short_to_byte_mask = generate_vector_mask("vector_short_to_byte_mask", 0x00ff00ff00ff00ff); |
|
6208 |
StubRoutines::x86::_vector_byte_perm_mask = generate_vector_byte_perm_mask("vector_byte_perm_mask"); |
|
6209 |
StubRoutines::x86::_vector_long_sign_mask = generate_vector_mask("vector_long_sign_mask", 0x8000000000000000); |
|
1 | 6210 |
|
6211 |
// support for verify_oop (must happen after universe_init) |
|
6212 |
StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop(); |
|
6213 |
||
57804 | 6214 |
// data cache line writeback |
6215 |
StubRoutines::_data_cache_writeback = generate_data_cache_writeback(); |
|
6216 |
StubRoutines::_data_cache_writeback_sync = generate_data_cache_writeback_sync(); |
|
6217 |
||
1 | 6218 |
// arraycopy stubs used by compilers |
6219 |
generate_arraycopy_stubs(); |
|
4478 | 6220 |
|
14132 | 6221 |
// don't bother generating these AES intrinsic stubs unless global flag is set |
6222 |
if (UseAESIntrinsics) { |
|
6223 |
StubRoutines::x86::_key_shuffle_mask_addr = generate_key_shuffle_mask(); // needed by the others |
|
6224 |
StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock(); |
|
6225 |
StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock(); |
|
6226 |
StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt(); |
|
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
6227 |
if (VM_Version::supports_vaes() && VM_Version::supports_avx512vl() && VM_Version::supports_avx512dq() ) { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
6228 |
StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptVectorAESCrypt(); |
57786
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
6229 |
StubRoutines::_electronicCodeBook_encryptAESCrypt = generate_electronicCodeBook_encryptAESCrypt(); |
948ac3112da8
8225625: AES Electronic Codebook (ECB) encryption and decryption optimization using AVX512 + VAES instructions
srukmannagar
parents:
55490
diff
changeset
|
6230 |
StubRoutines::_electronicCodeBook_decryptAESCrypt = generate_electronicCodeBook_decryptAESCrypt(); |
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
6231 |
} else { |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
6232 |
StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt_Parallel(); |
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50525
diff
changeset
|
6233 |
} |
14132 | 6234 |
} |
58977
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6235 |
if (UseAESCTRIntrinsics) { |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6236 |
if (VM_Version::supports_vaes() && VM_Version::supports_avx512bw() && VM_Version::supports_avx512vl()) { |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6237 |
StubRoutines::x86::_counter_mask_addr = counter_mask_addr(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6238 |
StubRoutines::_counterMode_AESCrypt = generate_counterMode_VectorAESCrypt(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6239 |
} else { |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6240 |
StubRoutines::x86::_counter_shuffle_mask_addr = generate_counter_shuffle_mask(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6241 |
StubRoutines::_counterMode_AESCrypt = generate_counterMode_AESCrypt_Parallel(); |
c6a789f495fe
8233741: AES Countermode (AES-CTR) optimization using AVX512 + VAES instructions
kvn
parents:
58462
diff
changeset
|
6242 |
} |
35154 | 6243 |
} |
18740 | 6244 |
|
36555 | 6245 |
if (UseSHA1Intrinsics) { |
6246 |
StubRoutines::x86::_upper_word_mask_addr = generate_upper_word_mask(); |
|
6247 |
StubRoutines::x86::_shuffle_byte_flip_mask_addr = generate_shuffle_byte_flip_mask(); |
|
6248 |
StubRoutines::_sha1_implCompress = generate_sha1_implCompress(false, "sha1_implCompress"); |
|
6249 |
StubRoutines::_sha1_implCompressMB = generate_sha1_implCompress(true, "sha1_implCompressMB"); |
|
6250 |
} |
|
6251 |
if (UseSHA256Intrinsics) { |
|
6252 |
StubRoutines::x86::_k256_adr = (address)StubRoutines::x86::_k256; |
|
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6253 |
char* dst = (char*)StubRoutines::x86::_k256_W; |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6254 |
char* src = (char*)StubRoutines::x86::_k256; |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6255 |
for (int ii = 0; ii < 16; ++ii) { |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6256 |
memcpy(dst + 32 * ii, src + 16 * ii, 16); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6257 |
memcpy(dst + 32 * ii + 16, src + 16 * ii, 16); |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6258 |
} |
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
38051
diff
changeset
|
6259 |
StubRoutines::x86::_k256_W_adr = (address)StubRoutines::x86::_k256_W; |
36555 | 6260 |
StubRoutines::x86::_pshuffle_byte_flip_mask_addr = generate_pshuffle_byte_flip_mask(); |
6261 |
StubRoutines::_sha256_implCompress = generate_sha256_implCompress(false, "sha256_implCompress"); |
|
6262 |
StubRoutines::_sha256_implCompressMB = generate_sha256_implCompress(true, "sha256_implCompressMB"); |
|
6263 |
} |
|
42039 | 6264 |
if (UseSHA512Intrinsics) { |
6265 |
StubRoutines::x86::_k512_W_addr = (address)StubRoutines::x86::_k512_W; |
|
6266 |
StubRoutines::x86::_pshuffle_byte_flip_mask_addr_sha512 = generate_pshuffle_byte_flip_mask_sha512(); |
|
6267 |
StubRoutines::_sha512_implCompress = generate_sha512_implCompress(false, "sha512_implCompress"); |
|
6268 |
StubRoutines::_sha512_implCompressMB = generate_sha512_implCompress(true, "sha512_implCompressMB"); |
|
6269 |
} |
|
36555 | 6270 |
|
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
6271 |
// Generate GHASH intrinsics code |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
6272 |
if (UseGHASHIntrinsics) { |
52990
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6273 |
StubRoutines::x86::_ghash_long_swap_mask_addr = generate_ghash_long_swap_mask(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6274 |
StubRoutines::x86::_ghash_byte_swap_mask_addr = generate_ghash_byte_swap_mask(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6275 |
if (VM_Version::supports_avx()) { |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6276 |
StubRoutines::x86::_ghash_shuffmask_addr = ghash_shufflemask_addr(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6277 |
StubRoutines::x86::_ghash_poly_addr = ghash_polynomial_addr(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6278 |
StubRoutines::_ghash_processBlocks = generate_avx_ghash_processBlocks(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6279 |
} else { |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6280 |
StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks(); |
1ed8de9045a7
8214074: Ghash optimization using AVX instructions
ascarpino
parents:
52142
diff
changeset
|
6281 |
} |
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
6282 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
6283 |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6284 |
if (UseBASE64Intrinsics) { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6285 |
StubRoutines::x86::_and_mask = base64_and_mask_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6286 |
StubRoutines::x86::_bswap_mask = base64_bswap_mask_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6287 |
StubRoutines::x86::_base64_charset = base64_charset_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6288 |
StubRoutines::x86::_url_charset = base64url_charset_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6289 |
StubRoutines::x86::_gather_mask = base64_gather_mask_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6290 |
StubRoutines::x86::_left_shift_mask = base64_left_shift_mask_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6291 |
StubRoutines::x86::_right_shift_mask = base64_right_shift_mask_addr(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6292 |
StubRoutines::_base64_encodeBlock = generate_base64_encodeBlock(); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6293 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50728
diff
changeset
|
6294 |
|
18740 | 6295 |
// Safefetch stubs. |
6296 |
generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry, |
|
6297 |
&StubRoutines::_safefetch32_fault_pc, |
|
6298 |
&StubRoutines::_safefetch32_continuation_pc); |
|
6299 |
generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry, |
|
6300 |
&StubRoutines::_safefetchN_fault_pc, |
|
6301 |
&StubRoutines::_safefetchN_continuation_pc); |
|
52142 | 6302 |
|
6303 |
BarrierSetNMethod* bs_nm = BarrierSet::barrier_set()->barrier_set_nmethod(); |
|
6304 |
if (bs_nm != NULL) { |
|
6305 |
StubRoutines::x86::_method_entry_barrier = generate_method_entry_barrier(); |
|
6306 |
} |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
6307 |
#ifdef COMPILER2 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
6308 |
if (UseMultiplyToLenIntrinsic) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
6309 |
StubRoutines::_multiplyToLen = generate_multiplyToLen(); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
22505
diff
changeset
|
6310 |
} |
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
6311 |
if (UseSquareToLenIntrinsic) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
6312 |
StubRoutines::_squareToLen = generate_squareToLen(); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
6313 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
6314 |
if (UseMulAddIntrinsic) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
6315 |
StubRoutines::_mulAdd = generate_mulAdd(); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
6316 |
} |
31583
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6317 |
#ifndef _WINDOWS |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6318 |
if (UseMontgomeryMultiplyIntrinsic) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6319 |
StubRoutines::_montgomeryMultiply |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6320 |
= CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_multiply); |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6321 |
} |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6322 |
if (UseMontgomerySquareIntrinsic) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6323 |
StubRoutines::_montgomerySquare |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6324 |
= CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_square); |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6325 |
} |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6326 |
#endif // WINDOWS |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
6327 |
#endif // COMPILER2 |
38238
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
6328 |
|
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
6329 |
if (UseVectorizedMismatchIntrinsic) { |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
6330 |
StubRoutines::_vectorizedMismatch = generate_vectorizedMismatch(); |
1bbcc430c78d
8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents:
38135
diff
changeset
|
6331 |
} |
1 | 6332 |
} |
6333 |
||
6334 |
public: |
|
6335 |
StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) { |
|
6336 |
if (all) { |
|
6337 |
generate_all(); |
|
6338 |
} else { |
|
6339 |
generate_initial(); |
|
6340 |
} |
|
6341 |
} |
|
6342 |
}; // end class declaration |
|
6343 |
||
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
6344 |
#define UCM_TABLE_MAX_ENTRIES 16 |
1 | 6345 |
void StubGenerator_generate(CodeBuffer* code, bool all) { |
55490
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
6346 |
if (UnsafeCopyMemory::_table == NULL) { |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
6347 |
UnsafeCopyMemory::create_table(UCM_TABLE_MAX_ENTRIES); |
3f3dc00a69a5
8191278: MappedByteBuffer bulk access memory failures are not handled gracefully
jcm
parents:
54786
diff
changeset
|
6348 |
} |
1 | 6349 |
StubGenerator g(code, all); |
6350 |
} |