src/hotspot/cpu/x86/stubGenerator_x86_64.cpp
author eosterlund
Mon, 19 Mar 2018 07:38:18 +0100
changeset 49455 848864ed9b17
parent 49368 2ed1c37df3a5
child 49484 ee8fa73b90f9
permissions -rw-r--r--
8199604: Rename CardTableModRefBS to CardTableBarrierSet Reviewed-by: stefank, pliden
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/*
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 * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#include "precompiled.hpp"
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#include "asm/macroAssembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "ci/ciUtilities.hpp"
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#include "gc/shared/cardTable.hpp"
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#include "gc/shared/cardTableBarrierSet.hpp"
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#include "interpreter/interpreter.hpp"
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#include "nativeInst_x86.hpp"
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#include "oops/instanceOop.hpp"
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#include "oops/method.hpp"
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#include "oops/objArrayKlass.hpp"
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#include "oops/oop.inline.hpp"
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#include "prims/methodHandles.hpp"
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#include "runtime/frame.inline.hpp"
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#include "runtime/handles.inline.hpp"
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#include "runtime/sharedRuntime.hpp"
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#include "runtime/stubCodeGenerator.hpp"
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#include "runtime/stubRoutines.hpp"
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#include "runtime/thread.inline.hpp"
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#ifdef COMPILER2
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#include "opto/runtime.hpp"
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#endif
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// Declaration and definition of StubGenerator (no .hpp file).
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// For a more detailed description of the stub routine structure
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// see the comment in stubRoutines.hpp
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#define __ _masm->
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#define TIMES_OOP (UseCompressedOops ? Address::times_4 : Address::times_8)
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#define a__ ((Assembler*)_masm)->
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#ifdef PRODUCT
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#define BLOCK_COMMENT(str) /* nothing */
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#else
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#define BLOCK_COMMENT(str) __ block_comment(str)
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#endif
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#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
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const int MXCSR_MASK = 0xFFC0;  // Mask out any pending exceptions
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// Stub Code definitions
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class StubGenerator: public StubCodeGenerator {
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 private:
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#ifdef PRODUCT
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#define inc_counter_np(counter) ((void)0)
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#else
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  void inc_counter_np_(int& counter) {
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    // This can destroy rscratch1 if counter is far from the code cache
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    __ incrementl(ExternalAddress((address)&counter));
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  }
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#define inc_counter_np(counter) \
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  BLOCK_COMMENT("inc_counter " #counter); \
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  inc_counter_np_(counter);
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#endif
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  // Call stubs are used to call Java from C
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  //
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  // Linux Arguments:
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  //    c_rarg0:   call wrapper address                   address
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  //    c_rarg1:   result                                 address
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  //    c_rarg2:   result type                            BasicType
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  //    c_rarg3:   method                                 Method*
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  //    c_rarg4:   (interpreter) entry point              address
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  //    c_rarg5:   parameters                             intptr_t*
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  //    16(rbp): parameter size (in words)              int
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  //    24(rbp): thread                                 Thread*
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  //
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  //     [ return_from_Java     ] <--- rsp
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  //     [ argument word n      ]
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  //      ...
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  // -12 [ argument word 1      ]
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  // -11 [ saved r15            ] <--- rsp_after_call
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  // -10 [ saved r14            ]
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  //  -9 [ saved r13            ]
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  //  -8 [ saved r12            ]
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  //  -7 [ saved rbx            ]
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  //  -6 [ call wrapper         ]
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  //  -5 [ result               ]
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  //  -4 [ result type          ]
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  //  -3 [ method               ]
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  //  -2 [ entry point          ]
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  //  -1 [ parameters           ]
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  //   0 [ saved rbp            ] <--- rbp
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  //   1 [ return address       ]
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  //   2 [ parameter size       ]
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  //   3 [ thread               ]
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  //
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  // Windows Arguments:
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  //    c_rarg0:   call wrapper address                   address
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  //    c_rarg1:   result                                 address
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  //    c_rarg2:   result type                            BasicType
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  //    c_rarg3:   method                                 Method*
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  //    48(rbp): (interpreter) entry point              address
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  //    56(rbp): parameters                             intptr_t*
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  //    64(rbp): parameter size (in words)              int
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  //    72(rbp): thread                                 Thread*
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  //
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  //     [ return_from_Java     ] <--- rsp
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  //     [ argument word n      ]
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  //      ...
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  // -60 [ argument word 1      ]
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  // -59 [ saved xmm31          ] <--- rsp after_call
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  //     [ saved xmm16-xmm30    ] (EVEX enabled, else the space is blank)
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  // -27 [ saved xmm15          ]
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  //     [ saved xmm7-xmm14     ]
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  //  -9 [ saved xmm6           ] (each xmm register takes 2 slots)
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  //  -7 [ saved r15            ]
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  //  -6 [ saved r14            ]
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  //  -5 [ saved r13            ]
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  //  -4 [ saved r12            ]
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  //  -3 [ saved rdi            ]
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  //  -2 [ saved rsi            ]
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  //  -1 [ saved rbx            ]
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  //   0 [ saved rbp            ] <--- rbp
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  //   1 [ return address       ]
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  //   2 [ call wrapper         ]
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  //   3 [ result               ]
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  //   4 [ result type          ]
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  //   5 [ method               ]
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  //   6 [ entry point          ]
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  //   7 [ parameters           ]
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  //   8 [ parameter size       ]
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  //   9 [ thread               ]
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  //
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  //    Windows reserves the callers stack space for arguments 1-4.
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  //    We spill c_rarg0-c_rarg3 to this space.
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  // Call stub stack layout word offsets from rbp
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  enum call_stub_layout {
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#ifdef _WIN64
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    xmm_save_first     = 6,  // save from xmm6
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    xmm_save_last      = 31, // to xmm31
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    xmm_save_base      = -9,
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    rsp_after_call_off = xmm_save_base - 2 * (xmm_save_last - xmm_save_first), // -27
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    r15_off            = -7,
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    r14_off            = -6,
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    r13_off            = -5,
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    r12_off            = -4,
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    rdi_off            = -3,
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    rsi_off            = -2,
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    rbx_off            = -1,
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    rbp_off            =  0,
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    retaddr_off        =  1,
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    call_wrapper_off   =  2,
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    result_off         =  3,
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    result_type_off    =  4,
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    method_off         =  5,
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    entry_point_off    =  6,
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    parameters_off     =  7,
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    parameter_size_off =  8,
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    thread_off         =  9
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#else
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    rsp_after_call_off = -12,
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    mxcsr_off          = rsp_after_call_off,
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    r15_off            = -11,
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    r14_off            = -10,
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    r13_off            = -9,
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    r12_off            = -8,
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    rbx_off            = -7,
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    call_wrapper_off   = -6,
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    result_off         = -5,
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    result_type_off    = -4,
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    method_off         = -3,
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    entry_point_off    = -2,
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    parameters_off     = -1,
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    rbp_off            =  0,
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    retaddr_off        =  1,
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    parameter_size_off =  2,
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    thread_off         =  3
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#endif
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  };
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#ifdef _WIN64
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  Address xmm_save(int reg) {
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    assert(reg >= xmm_save_first && reg <= xmm_save_last, "XMM register number out of range");
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    return Address(rbp, (xmm_save_base - (reg - xmm_save_first) * 2) * wordSize);
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  }
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#endif
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1
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  address generate_call_stub(address& return_address) {
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    assert((int)frame::entry_frame_after_call_words == -(int)rsp_after_call_off + 1 &&
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           (int)frame::entry_frame_call_wrapper_offset == (int)call_wrapper_off,
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           "adjust this code");
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    StubCodeMark mark(this, "StubRoutines", "call_stub");
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    address start = __ pc();
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    // same as in generate_catch_exception()!
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    const Address rsp_after_call(rbp, rsp_after_call_off * wordSize);
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    const Address call_wrapper  (rbp, call_wrapper_off   * wordSize);
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    const Address result        (rbp, result_off         * wordSize);
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    const Address result_type   (rbp, result_type_off    * wordSize);
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    const Address method        (rbp, method_off         * wordSize);
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    const Address entry_point   (rbp, entry_point_off    * wordSize);
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    const Address parameters    (rbp, parameters_off     * wordSize);
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    const Address parameter_size(rbp, parameter_size_off * wordSize);
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    // same as in generate_catch_exception()!
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    const Address thread        (rbp, thread_off         * wordSize);
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    const Address r15_save(rbp, r15_off * wordSize);
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    const Address r14_save(rbp, r14_off * wordSize);
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    const Address r13_save(rbp, r13_off * wordSize);
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    const Address r12_save(rbp, r12_off * wordSize);
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    const Address rbx_save(rbp, rbx_off * wordSize);
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    // stub code
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    __ enter();
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    __ subptr(rsp, -rsp_after_call_off * wordSize);
1
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    // save register parameters
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#ifndef _WIN64
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    __ movptr(parameters,   c_rarg5); // parameters
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    __ movptr(entry_point,  c_rarg4); // entry_point
1
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#endif
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    __ movptr(method,       c_rarg3); // method
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    __ movl(result_type,  c_rarg2);   // result type
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    __ movptr(result,       c_rarg1); // result
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    __ movptr(call_wrapper, c_rarg0); // call wrapper
1
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    // save regs belonging to calling function
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    __ movptr(rbx_save, rbx);
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    __ movptr(r12_save, r12);
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    __ movptr(r13_save, r13);
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    __ movptr(r14_save, r14);
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    __ movptr(r15_save, r15);
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    if (UseAVX > 2) {
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      __ movl(rbx, 0xffff);
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      __ kmovwl(k1, rbx);
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    }
1
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#ifdef _WIN64
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    int last_reg = 15;
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    if (UseAVX > 2) {
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      last_reg = 31;
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    }
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    if (VM_Version::supports_evex()) {
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      for (int i = xmm_save_first; i <= last_reg; i++) {
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        __ vextractf32x4(xmm_save(i), as_XMMRegister(i), 0);
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      }
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    } else {
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      for (int i = xmm_save_first; i <= last_reg; i++) {
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        __ movdqu(xmm_save(i), as_XMMRegister(i));
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      }
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    }
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1
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    const Address rdi_save(rbp, rdi_off * wordSize);
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    const Address rsi_save(rbp, rsi_off * wordSize);
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    __ movptr(rsi_save, rsi);
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    __ movptr(rdi_save, rdi);
1
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#else
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    const Address mxcsr_save(rbp, mxcsr_off * wordSize);
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    {
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      Label skip_ldmx;
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      __ stmxcsr(mxcsr_save);
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      __ movl(rax, mxcsr_save);
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      __ andl(rax, MXCSR_MASK);    // Only check control and mask bits
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      ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
1
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      __ cmp32(rax, mxcsr_std);
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      __ jcc(Assembler::equal, skip_ldmx);
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      __ ldmxcsr(mxcsr_std);
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      __ bind(skip_ldmx);
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    }
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#endif
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    // Load up thread register
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    __ movptr(r15_thread, thread);
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    __ reinit_heapbase();
1
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   296
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#ifdef ASSERT
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    // make sure we have no pending exceptions
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    {
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      Label L;
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      __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
1
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      __ jcc(Assembler::equal, L);
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      __ stop("StubRoutines::call_stub: entered with pending exception");
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      __ bind(L);
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    }
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#endif
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    // pass parameters if any
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    BLOCK_COMMENT("pass parameters if any");
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    Label parameters_done;
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    __ movl(c_rarg3, parameter_size);
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    __ testl(c_rarg3, c_rarg3);
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    __ jcc(Assembler::zero, parameters_done);
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   314
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    Label loop;
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    __ movptr(c_rarg2, parameters);       // parameter pointer
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    __ movl(c_rarg1, c_rarg3);            // parameter counter is in c_rarg1
1
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    __ BIND(loop);
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    __ movptr(rax, Address(c_rarg2, 0));// get parameter
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    __ addptr(c_rarg2, wordSize);       // advance to next parameter
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   321
    __ decrementl(c_rarg1);             // decrement counter
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    __ push(rax);                       // pass parameter
1
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    __ jcc(Assembler::notZero, loop);
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   324
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    // call Java function
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    __ BIND(parameters_done);
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   327
    __ movptr(rbx, method);             // get Method*
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    __ movptr(c_rarg1, entry_point);    // get entry_point
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    __ mov(r13, rsp);                   // set sender sp
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    BLOCK_COMMENT("call Java function");
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    __ call(c_rarg1);
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   332
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   333
    BLOCK_COMMENT("call_stub_return_address:");
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    return_address = __ pc();
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   335
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    // store result depending on type (everything that is not
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    // T_OBJECT, T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT)
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    __ movptr(c_rarg0, result);
1
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   339
    Label is_long, is_float, is_double, exit;
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   340
    __ movl(c_rarg1, result_type);
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   341
    __ cmpl(c_rarg1, T_OBJECT);
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   342
    __ jcc(Assembler::equal, is_long);
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   343
    __ cmpl(c_rarg1, T_LONG);
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   344
    __ jcc(Assembler::equal, is_long);
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   345
    __ cmpl(c_rarg1, T_FLOAT);
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   346
    __ jcc(Assembler::equal, is_float);
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   347
    __ cmpl(c_rarg1, T_DOUBLE);
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   348
    __ jcc(Assembler::equal, is_double);
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   349
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   350
    // handle T_INT case
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   351
    __ movl(Address(c_rarg0, 0), rax);
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diff changeset
   352
489c9b5090e2 Initial load
duke
parents:
diff changeset
   353
    __ BIND(exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   354
489c9b5090e2 Initial load
duke
parents:
diff changeset
   355
    // pop parameters
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   356
    __ lea(rsp, rsp_after_call);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   357
489c9b5090e2 Initial load
duke
parents:
diff changeset
   358
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   359
    // verify that threads correspond
489c9b5090e2 Initial load
duke
parents:
diff changeset
   360
    {
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   361
     Label L1, L2, L3;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   362
      __ cmpptr(r15_thread, thread);
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   363
      __ jcc(Assembler::equal, L1);
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   364
      __ stop("StubRoutines::call_stub: r15_thread is corrupted");
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   365
      __ bind(L1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   366
      __ get_thread(rbx);
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   367
      __ cmpptr(r15_thread, thread);
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   368
      __ jcc(Assembler::equal, L2);
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   369
      __ stop("StubRoutines::call_stub: r15_thread is modified by call");
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   370
      __ bind(L2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   371
      __ cmpptr(r15_thread, rbx);
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   372
      __ jcc(Assembler::equal, L3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   373
      __ stop("StubRoutines::call_stub: threads must correspond");
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   374
      __ bind(L3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   375
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   376
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   377
489c9b5090e2 Initial load
duke
parents:
diff changeset
   378
    // restore regs belonging to calling function
8874
b2030880129c 6741940: Nonvolatile XMM registers not preserved across JNI calls
iveresov
parents: 8498
diff changeset
   379
#ifdef _WIN64
31410
2a222ae1205f 8081247: AVX 512 extended support
mcberg
parents: 31404
diff changeset
   380
    // emit the restores for xmm regs
34162
16b54851eaf6 8140779: Code generation fixes for avx512
iveresov
parents: 33465
diff changeset
   381
    if (VM_Version::supports_evex()) {
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   382
      for (int i = xmm_save_first; i <= last_reg; i++) {
36561
b18243f4d955 8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents: 36555
diff changeset
   383
        __ vinsertf32x4(as_XMMRegister(i), as_XMMRegister(i), xmm_save(i), 0);
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   384
      }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   385
    } else {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   386
      for (int i = xmm_save_first; i <= last_reg; i++) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   387
        __ movdqu(as_XMMRegister(i), xmm_save(i));
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
   388
      }
8874
b2030880129c 6741940: Nonvolatile XMM registers not preserved across JNI calls
iveresov
parents: 8498
diff changeset
   389
    }
b2030880129c 6741940: Nonvolatile XMM registers not preserved across JNI calls
iveresov
parents: 8498
diff changeset
   390
#endif
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   391
    __ movptr(r15, r15_save);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   392
    __ movptr(r14, r14_save);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   393
    __ movptr(r13, r13_save);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   394
    __ movptr(r12, r12_save);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   395
    __ movptr(rbx, rbx_save);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   396
489c9b5090e2 Initial load
duke
parents:
diff changeset
   397
#ifdef _WIN64
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   398
    __ movptr(rdi, rdi_save);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   399
    __ movptr(rsi, rsi_save);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   400
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   401
    __ ldmxcsr(mxcsr_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   402
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   403
489c9b5090e2 Initial load
duke
parents:
diff changeset
   404
    // restore rsp
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   405
    __ addptr(rsp, -rsp_after_call_off * wordSize);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   406
489c9b5090e2 Initial load
duke
parents:
diff changeset
   407
    // return
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
   408
    __ vzeroupper();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   409
    __ pop(rbp);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   410
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   411
489c9b5090e2 Initial load
duke
parents:
diff changeset
   412
    // handle return types different from T_INT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   413
    __ BIND(is_long);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   414
    __ movq(Address(c_rarg0, 0), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   415
    __ jmp(exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   416
489c9b5090e2 Initial load
duke
parents:
diff changeset
   417
    __ BIND(is_float);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   418
    __ movflt(Address(c_rarg0, 0), xmm0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   419
    __ jmp(exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   420
489c9b5090e2 Initial load
duke
parents:
diff changeset
   421
    __ BIND(is_double);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   422
    __ movdbl(Address(c_rarg0, 0), xmm0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   423
    __ jmp(exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   424
489c9b5090e2 Initial load
duke
parents:
diff changeset
   425
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   426
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   427
489c9b5090e2 Initial load
duke
parents:
diff changeset
   428
  // Return point for a Java call if there's an exception thrown in
489c9b5090e2 Initial load
duke
parents:
diff changeset
   429
  // Java code.  The exception is caught and transformed into a
489c9b5090e2 Initial load
duke
parents:
diff changeset
   430
  // pending exception stored in JavaThread that can be tested from
489c9b5090e2 Initial load
duke
parents:
diff changeset
   431
  // within the VM.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   432
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   433
  // Note: Usually the parameters are removed by the callee. In case
489c9b5090e2 Initial load
duke
parents:
diff changeset
   434
  // of an exception crossing an activation frame boundary, that is
489c9b5090e2 Initial load
duke
parents:
diff changeset
   435
  // not the case if the callee is compiled code => need to setup the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   436
  // rsp.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   437
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   438
  // rax: exception oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
   439
489c9b5090e2 Initial load
duke
parents:
diff changeset
   440
  address generate_catch_exception() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   441
    StubCodeMark mark(this, "StubRoutines", "catch_exception");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   442
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   443
489c9b5090e2 Initial load
duke
parents:
diff changeset
   444
    // same as in generate_call_stub():
489c9b5090e2 Initial load
duke
parents:
diff changeset
   445
    const Address rsp_after_call(rbp, rsp_after_call_off * wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   446
    const Address thread        (rbp, thread_off         * wordSize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   447
489c9b5090e2 Initial load
duke
parents:
diff changeset
   448
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   449
    // verify that threads correspond
489c9b5090e2 Initial load
duke
parents:
diff changeset
   450
    {
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   451
      Label L1, L2, L3;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   452
      __ cmpptr(r15_thread, thread);
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   453
      __ jcc(Assembler::equal, L1);
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   454
      __ stop("StubRoutines::catch_exception: r15_thread is corrupted");
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   455
      __ bind(L1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   456
      __ get_thread(rbx);
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   457
      __ cmpptr(r15_thread, thread);
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   458
      __ jcc(Assembler::equal, L2);
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   459
      __ stop("StubRoutines::catch_exception: r15_thread is modified by call");
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   460
      __ bind(L2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   461
      __ cmpptr(r15_thread, rbx);
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   462
      __ jcc(Assembler::equal, L3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   463
      __ stop("StubRoutines::catch_exception: threads must correspond");
32590
66edb61f17d4 8133646: Internal Error: x86/vm/macroAssembler_x86.cpp:886 DEBUG MESSAGE: StubRoutines::call_stub: threads must correspond
dholmes
parents: 31584
diff changeset
   464
      __ bind(L3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   465
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   466
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   467
489c9b5090e2 Initial load
duke
parents:
diff changeset
   468
    // set pending exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   469
    __ verify_oop(rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   470
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   471
    __ movptr(Address(r15_thread, Thread::pending_exception_offset()), rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   472
    __ lea(rscratch1, ExternalAddress((address)__FILE__));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   473
    __ movptr(Address(r15_thread, Thread::exception_file_offset()), rscratch1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   474
    __ movl(Address(r15_thread, Thread::exception_line_offset()), (int)  __LINE__);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   475
489c9b5090e2 Initial load
duke
parents:
diff changeset
   476
    // complete return to VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
   477
    assert(StubRoutines::_call_stub_return_address != NULL,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   478
           "_call_stub_return_address must have been generated before");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   479
    __ jump(RuntimeAddress(StubRoutines::_call_stub_return_address));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   480
489c9b5090e2 Initial load
duke
parents:
diff changeset
   481
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   482
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   483
489c9b5090e2 Initial load
duke
parents:
diff changeset
   484
  // Continuation point for runtime calls returning with a pending
489c9b5090e2 Initial load
duke
parents:
diff changeset
   485
  // exception.  The pending exception check happened in the runtime
489c9b5090e2 Initial load
duke
parents:
diff changeset
   486
  // or native call stub.  The pending exception in Thread is
489c9b5090e2 Initial load
duke
parents:
diff changeset
   487
  // converted into a Java-level exception.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   488
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   489
  // Contract with Java-level exception handlers:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   490
  // rax: exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   491
  // rdx: throwing pc
489c9b5090e2 Initial load
duke
parents:
diff changeset
   492
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   493
  // NOTE: At entry of this stub, exception-pc must be on stack !!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   494
489c9b5090e2 Initial load
duke
parents:
diff changeset
   495
  address generate_forward_exception() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   496
    StubCodeMark mark(this, "StubRoutines", "forward exception");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   497
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   498
489c9b5090e2 Initial load
duke
parents:
diff changeset
   499
    // Upon entry, the sp points to the return address returning into
489c9b5090e2 Initial load
duke
parents:
diff changeset
   500
    // Java (interpreted or compiled) code; i.e., the return address
489c9b5090e2 Initial load
duke
parents:
diff changeset
   501
    // becomes the throwing pc.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   502
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   503
    // Arguments pushed before the runtime call are still on the stack
489c9b5090e2 Initial load
duke
parents:
diff changeset
   504
    // but the exception handler will reset the stack pointer ->
489c9b5090e2 Initial load
duke
parents:
diff changeset
   505
    // ignore them.  A potential result in registers can be ignored as
489c9b5090e2 Initial load
duke
parents:
diff changeset
   506
    // well.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   507
489c9b5090e2 Initial load
duke
parents:
diff changeset
   508
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   509
    // make sure this code is only executed if there is a pending exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   510
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   511
      Label L;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   512
      __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t) NULL);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   513
      __ jcc(Assembler::notEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   514
      __ stop("StubRoutines::forward exception: no pending exception (1)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   515
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   516
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   517
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   518
489c9b5090e2 Initial load
duke
parents:
diff changeset
   519
    // compute exception handler into rbx
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   520
    __ movptr(c_rarg0, Address(rsp, 0));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   521
    BLOCK_COMMENT("call exception_handler_for_return_address");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   522
    __ call_VM_leaf(CAST_FROM_FN_PTR(address,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   523
                         SharedRuntime::exception_handler_for_return_address),
5046
27e801a857cb 6919934: JSR 292 needs to support x86 C1
twisti
parents: 4740
diff changeset
   524
                    r15_thread, c_rarg0);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   525
    __ mov(rbx, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   526
489c9b5090e2 Initial load
duke
parents:
diff changeset
   527
    // setup rax & rdx, remove return address & clear pending exception
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   528
    __ pop(rdx);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   529
    __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
1888
bbf498fb4354 6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents: 1437
diff changeset
   530
    __ movptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   531
489c9b5090e2 Initial load
duke
parents:
diff changeset
   532
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
   533
    // make sure exception is set
489c9b5090e2 Initial load
duke
parents:
diff changeset
   534
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   535
      Label L;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   536
      __ testptr(rax, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   537
      __ jcc(Assembler::notEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   538
      __ stop("StubRoutines::forward exception: no pending exception (2)");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   539
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   540
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   541
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
   542
489c9b5090e2 Initial load
duke
parents:
diff changeset
   543
    // continue at exception handler (return address removed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   544
    // rax: exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
   545
    // rbx: exception handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
   546
    // rdx: throwing pc
489c9b5090e2 Initial load
duke
parents:
diff changeset
   547
    __ verify_oop(rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   548
    __ jmp(rbx);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   549
489c9b5090e2 Initial load
duke
parents:
diff changeset
   550
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   551
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   552
489c9b5090e2 Initial load
duke
parents:
diff changeset
   553
  // Support for jint atomic::xchg(jint exchange_value, volatile jint* dest)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   554
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   555
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   556
  //    c_rarg0: exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   557
  //    c_rarg0: dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   558
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   559
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   560
  //    *dest <- ex, return (orig *dest)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   561
  address generate_atomic_xchg() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   562
    StubCodeMark mark(this, "StubRoutines", "atomic_xchg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   563
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   564
489c9b5090e2 Initial load
duke
parents:
diff changeset
   565
    __ movl(rax, c_rarg0); // Copy to eax we need a return value anyhow
489c9b5090e2 Initial load
duke
parents:
diff changeset
   566
    __ xchgl(rax, Address(c_rarg1, 0)); // automatic LOCK
489c9b5090e2 Initial load
duke
parents:
diff changeset
   567
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   568
489c9b5090e2 Initial load
duke
parents:
diff changeset
   569
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   570
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   571
47634
6a0c42c40cd1 8188220: Remove Atomic::*_ptr() uses and overloads from hotspot
coleenp
parents: 47216
diff changeset
   572
  // Support for intptr_t atomic::xchg_long(jlong exchange_value, volatile jlong* dest)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   573
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   574
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   575
  //    c_rarg0: exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   576
  //    c_rarg1: dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   577
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   578
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   579
  //    *dest <- ex, return (orig *dest)
47634
6a0c42c40cd1 8188220: Remove Atomic::*_ptr() uses and overloads from hotspot
coleenp
parents: 47216
diff changeset
   580
  address generate_atomic_xchg_long() {
6a0c42c40cd1 8188220: Remove Atomic::*_ptr() uses and overloads from hotspot
coleenp
parents: 47216
diff changeset
   581
    StubCodeMark mark(this, "StubRoutines", "atomic_xchg_long");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   582
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   583
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   584
    __ movptr(rax, c_rarg0); // Copy to eax we need a return value anyhow
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   585
    __ xchgptr(rax, Address(c_rarg1, 0)); // automatic LOCK
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   586
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   587
489c9b5090e2 Initial load
duke
parents:
diff changeset
   588
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   589
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   590
489c9b5090e2 Initial load
duke
parents:
diff changeset
   591
  // Support for jint atomic::atomic_cmpxchg(jint exchange_value, volatile jint* dest,
489c9b5090e2 Initial load
duke
parents:
diff changeset
   592
  //                                         jint compare_value)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   593
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   594
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   595
  //    c_rarg0: exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   596
  //    c_rarg1: dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   597
  //    c_rarg2: compare_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   598
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   599
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   600
  //    if ( compare_value == *dest ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   601
  //       *dest = exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   602
  //       return compare_value;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   603
  //    else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   604
  //       return *dest;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   605
  address generate_atomic_cmpxchg() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   606
    StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   607
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   608
489c9b5090e2 Initial load
duke
parents:
diff changeset
   609
    __ movl(rax, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   610
   if ( os::is_MP() ) __ lock();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   611
    __ cmpxchgl(c_rarg0, Address(c_rarg1, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   612
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   613
489c9b5090e2 Initial load
duke
parents:
diff changeset
   614
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   615
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   616
48468
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   617
  // Support for int8_t atomic::atomic_cmpxchg(int8_t exchange_value, volatile int8_t* dest,
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   618
  //                                           int8_t compare_value)
27691
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   619
  //
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   620
  // Arguments :
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   621
  //    c_rarg0: exchange_value
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   622
  //    c_rarg1: dest
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   623
  //    c_rarg2: compare_value
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   624
  //
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   625
  // Result:
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   626
  //    if ( compare_value == *dest ) {
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   627
  //       *dest = exchange_value
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   628
  //       return compare_value;
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   629
  //    else
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   630
  //       return *dest;
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   631
  address generate_atomic_cmpxchg_byte() {
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   632
    StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg_byte");
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   633
    address start = __ pc();
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   634
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   635
    __ movsbq(rax, c_rarg2);
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   636
   if ( os::is_MP() ) __ lock();
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   637
    __ cmpxchgb(c_rarg0, Address(c_rarg1, 0));
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   638
    __ ret(0);
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   639
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   640
    return start;
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   641
  }
733f189ad1f7 8058255: Native jbyte Atomic::cmpxchg for supported x86 platforms
jwilhelm
parents: 26434
diff changeset
   642
48468
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   643
  // Support for int64_t atomic::atomic_cmpxchg(int64_t exchange_value,
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   644
  //                                            volatile int64_t* dest,
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   645
  //                                            int64_t compare_value)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   646
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   647
  //    c_rarg0: exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   648
  //    c_rarg1: dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   649
  //    c_rarg2: compare_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   650
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   651
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   652
  //    if ( compare_value == *dest ) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   653
  //       *dest = exchange_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   654
  //       return compare_value;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   655
  //    else
489c9b5090e2 Initial load
duke
parents:
diff changeset
   656
  //       return *dest;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   657
  address generate_atomic_cmpxchg_long() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   658
    StubCodeMark mark(this, "StubRoutines", "atomic_cmpxchg_long");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   659
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   660
489c9b5090e2 Initial load
duke
parents:
diff changeset
   661
    __ movq(rax, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   662
   if ( os::is_MP() ) __ lock();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   663
    __ cmpxchgq(c_rarg0, Address(c_rarg1, 0));
489c9b5090e2 Initial load
duke
parents:
diff changeset
   664
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   665
489c9b5090e2 Initial load
duke
parents:
diff changeset
   666
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   667
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   668
489c9b5090e2 Initial load
duke
parents:
diff changeset
   669
  // Support for jint atomic::add(jint add_value, volatile jint* dest)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   670
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   671
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   672
  //    c_rarg0: add_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   673
  //    c_rarg1: dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   674
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   675
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   676
  //    *dest += add_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   677
  //    return *dest;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   678
  address generate_atomic_add() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   679
    StubCodeMark mark(this, "StubRoutines", "atomic_add");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   680
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   681
489c9b5090e2 Initial load
duke
parents:
diff changeset
   682
    __ movl(rax, c_rarg0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   683
   if ( os::is_MP() ) __ lock();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   684
    __ xaddl(Address(c_rarg1, 0), c_rarg0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   685
    __ addl(rax, c_rarg0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   686
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   687
489c9b5090e2 Initial load
duke
parents:
diff changeset
   688
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   689
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   690
489c9b5090e2 Initial load
duke
parents:
diff changeset
   691
  // Support for intptr_t atomic::add_ptr(intptr_t add_value, volatile intptr_t* dest)
489c9b5090e2 Initial load
duke
parents:
diff changeset
   692
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   693
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   694
  //    c_rarg0: add_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   695
  //    c_rarg1: dest
489c9b5090e2 Initial load
duke
parents:
diff changeset
   696
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   697
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   698
  //    *dest += add_value
489c9b5090e2 Initial load
duke
parents:
diff changeset
   699
  //    return *dest;
48468
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   700
  address generate_atomic_add_long() {
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
   701
    StubCodeMark mark(this, "StubRoutines", "atomic_add_long");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   702
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   703
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   704
    __ movptr(rax, c_rarg0); // Copy to eax we need a return value anyhow
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   705
   if ( os::is_MP() ) __ lock();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   706
    __ xaddptr(Address(c_rarg1, 0), c_rarg0);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   707
    __ addptr(rax, c_rarg0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   708
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   709
489c9b5090e2 Initial load
duke
parents:
diff changeset
   710
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   711
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   712
489c9b5090e2 Initial load
duke
parents:
diff changeset
   713
  // Support for intptr_t OrderAccess::fence()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   714
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   715
  // Arguments :
489c9b5090e2 Initial load
duke
parents:
diff changeset
   716
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   717
  // Result:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   718
  address generate_orderaccess_fence() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   719
    StubCodeMark mark(this, "StubRoutines", "orderaccess_fence");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   720
    address start = __ pc();
2338
a8660a1b709b 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 2259
diff changeset
   721
    __ membar(Assembler::StoreLoad);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   722
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   723
489c9b5090e2 Initial load
duke
parents:
diff changeset
   724
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   725
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   726
489c9b5090e2 Initial load
duke
parents:
diff changeset
   727
  // Support for intptr_t get_previous_fp()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   728
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   729
  // This routine is used to find the previous frame pointer for the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   730
  // caller (current_frame_guess). This is used as part of debugging
489c9b5090e2 Initial load
duke
parents:
diff changeset
   731
  // ps() is seemingly lost trying to find frames.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   732
  // This code assumes that caller current_frame_guess) has a frame.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   733
  address generate_get_previous_fp() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   734
    StubCodeMark mark(this, "StubRoutines", "get_previous_fp");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   735
    const Address old_fp(rbp, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   736
    const Address older_fp(rax, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   737
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   738
489c9b5090e2 Initial load
duke
parents:
diff changeset
   739
    __ enter();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   740
    __ movptr(rax, old_fp); // callers fp
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   741
    __ movptr(rax, older_fp); // the frame for ps()
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   742
    __ pop(rbp);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   743
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   744
489c9b5090e2 Initial load
duke
parents:
diff changeset
   745
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   746
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   747
11961
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   748
  // Support for intptr_t get_previous_sp()
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   749
  //
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   750
  // This routine is used to find the previous stack pointer for the
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   751
  // caller.
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   752
  address generate_get_previous_sp() {
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   753
    StubCodeMark mark(this, "StubRoutines", "get_previous_sp");
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   754
    address start = __ pc();
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   755
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   756
    __ movptr(rax, rsp);
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   757
    __ addptr(rax, 8); // return address is at the top of the stack.
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   758
    __ ret(0);
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   759
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   760
    return start;
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   761
  }
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
   762
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   763
  //----------------------------------------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
   764
  // Support for void verify_mxcsr()
489c9b5090e2 Initial load
duke
parents:
diff changeset
   765
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   766
  // This routine is used with -Xcheck:jni to verify that native
489c9b5090e2 Initial load
duke
parents:
diff changeset
   767
  // JNI code does not return to Java code without restoring the
489c9b5090e2 Initial load
duke
parents:
diff changeset
   768
  // MXCSR register to our expected state.
489c9b5090e2 Initial load
duke
parents:
diff changeset
   769
489c9b5090e2 Initial load
duke
parents:
diff changeset
   770
  address generate_verify_mxcsr() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   771
    StubCodeMark mark(this, "StubRoutines", "verify_mxcsr");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   772
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   773
489c9b5090e2 Initial load
duke
parents:
diff changeset
   774
    const Address mxcsr_save(rsp, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   775
489c9b5090e2 Initial load
duke
parents:
diff changeset
   776
    if (CheckJNICalls) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   777
      Label ok_ret;
18958
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
   778
      ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   779
      __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   780
      __ subptr(rsp, wordSize);      // allocate a temp location
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   781
      __ stmxcsr(mxcsr_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   782
      __ movl(rax, mxcsr_save);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   783
      __ andl(rax, MXCSR_MASK);    // Only check control and mask bits
18958
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
   784
      __ cmp32(rax, mxcsr_std);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   785
      __ jcc(Assembler::equal, ok_ret);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   786
489c9b5090e2 Initial load
duke
parents:
diff changeset
   787
      __ warn("MXCSR changed by native JNI code, use -XX:+RestoreMXCSROnJNICall");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   788
18958
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
   789
      __ ldmxcsr(mxcsr_std);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   790
489c9b5090e2 Initial load
duke
parents:
diff changeset
   791
      __ bind(ok_ret);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   792
      __ addptr(rsp, wordSize);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   793
      __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   794
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   795
489c9b5090e2 Initial load
duke
parents:
diff changeset
   796
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   797
489c9b5090e2 Initial load
duke
parents:
diff changeset
   798
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   799
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   800
489c9b5090e2 Initial load
duke
parents:
diff changeset
   801
  address generate_f2i_fixup() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   802
    StubCodeMark mark(this, "StubRoutines", "f2i_fixup");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   803
    Address inout(rsp, 5 * wordSize); // return address + 4 saves
489c9b5090e2 Initial load
duke
parents:
diff changeset
   804
489c9b5090e2 Initial load
duke
parents:
diff changeset
   805
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   806
489c9b5090e2 Initial load
duke
parents:
diff changeset
   807
    Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   808
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   809
    __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   810
    __ push(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   811
    __ push(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   812
    __ push(c_rarg1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   813
489c9b5090e2 Initial load
duke
parents:
diff changeset
   814
    __ movl(rax, 0x7f800000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   815
    __ xorl(c_rarg3, c_rarg3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   816
    __ movl(c_rarg2, inout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   817
    __ movl(c_rarg1, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   818
    __ andl(c_rarg1, 0x7fffffff);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   819
    __ cmpl(rax, c_rarg1); // NaN? -> 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   820
    __ jcc(Assembler::negative, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   821
    __ testl(c_rarg2, c_rarg2); // signed ? min_jint : max_jint
489c9b5090e2 Initial load
duke
parents:
diff changeset
   822
    __ movl(c_rarg3, 0x80000000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   823
    __ movl(rax, 0x7fffffff);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   824
    __ cmovl(Assembler::positive, c_rarg3, rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   825
489c9b5090e2 Initial load
duke
parents:
diff changeset
   826
    __ bind(L);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   827
    __ movptr(inout, c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   828
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   829
    __ pop(c_rarg1);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   830
    __ pop(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   831
    __ pop(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   832
    __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   833
489c9b5090e2 Initial load
duke
parents:
diff changeset
   834
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   835
489c9b5090e2 Initial load
duke
parents:
diff changeset
   836
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   837
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   838
489c9b5090e2 Initial load
duke
parents:
diff changeset
   839
  address generate_f2l_fixup() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   840
    StubCodeMark mark(this, "StubRoutines", "f2l_fixup");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   841
    Address inout(rsp, 5 * wordSize); // return address + 4 saves
489c9b5090e2 Initial load
duke
parents:
diff changeset
   842
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   843
489c9b5090e2 Initial load
duke
parents:
diff changeset
   844
    Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   845
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   846
    __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   847
    __ push(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   848
    __ push(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   849
    __ push(c_rarg1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   850
489c9b5090e2 Initial load
duke
parents:
diff changeset
   851
    __ movl(rax, 0x7f800000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   852
    __ xorl(c_rarg3, c_rarg3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   853
    __ movl(c_rarg2, inout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   854
    __ movl(c_rarg1, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   855
    __ andl(c_rarg1, 0x7fffffff);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   856
    __ cmpl(rax, c_rarg1); // NaN? -> 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   857
    __ jcc(Assembler::negative, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   858
    __ testl(c_rarg2, c_rarg2); // signed ? min_jlong : max_jlong
489c9b5090e2 Initial load
duke
parents:
diff changeset
   859
    __ mov64(c_rarg3, 0x8000000000000000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   860
    __ mov64(rax, 0x7fffffffffffffff);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   861
    __ cmov(Assembler::positive, c_rarg3, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   862
489c9b5090e2 Initial load
duke
parents:
diff changeset
   863
    __ bind(L);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   864
    __ movptr(inout, c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   865
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   866
    __ pop(c_rarg1);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   867
    __ pop(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   868
    __ pop(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   869
    __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   870
489c9b5090e2 Initial load
duke
parents:
diff changeset
   871
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   872
489c9b5090e2 Initial load
duke
parents:
diff changeset
   873
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   874
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   875
489c9b5090e2 Initial load
duke
parents:
diff changeset
   876
  address generate_d2i_fixup() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   877
    StubCodeMark mark(this, "StubRoutines", "d2i_fixup");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   878
    Address inout(rsp, 6 * wordSize); // return address + 5 saves
489c9b5090e2 Initial load
duke
parents:
diff changeset
   879
489c9b5090e2 Initial load
duke
parents:
diff changeset
   880
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   881
489c9b5090e2 Initial load
duke
parents:
diff changeset
   882
    Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   883
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   884
    __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   885
    __ push(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   886
    __ push(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   887
    __ push(c_rarg1);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   888
    __ push(c_rarg0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   889
489c9b5090e2 Initial load
duke
parents:
diff changeset
   890
    __ movl(rax, 0x7ff00000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   891
    __ movq(c_rarg2, inout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   892
    __ movl(c_rarg3, c_rarg2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   893
    __ mov(c_rarg1, c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   894
    __ mov(c_rarg0, c_rarg2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   895
    __ negl(c_rarg3);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   896
    __ shrptr(c_rarg1, 0x20);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   897
    __ orl(c_rarg3, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   898
    __ andl(c_rarg1, 0x7fffffff);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   899
    __ xorl(c_rarg2, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   900
    __ shrl(c_rarg3, 0x1f);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   901
    __ orl(c_rarg1, c_rarg3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   902
    __ cmpl(rax, c_rarg1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   903
    __ jcc(Assembler::negative, L); // NaN -> 0
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   904
    __ testptr(c_rarg0, c_rarg0); // signed ? min_jint : max_jint
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   905
    __ movl(c_rarg2, 0x80000000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   906
    __ movl(rax, 0x7fffffff);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   907
    __ cmov(Assembler::positive, c_rarg2, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   908
489c9b5090e2 Initial load
duke
parents:
diff changeset
   909
    __ bind(L);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   910
    __ movptr(inout, c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   911
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   912
    __ pop(c_rarg0);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   913
    __ pop(c_rarg1);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   914
    __ pop(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   915
    __ pop(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   916
    __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   917
489c9b5090e2 Initial load
duke
parents:
diff changeset
   918
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   919
489c9b5090e2 Initial load
duke
parents:
diff changeset
   920
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   921
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   922
489c9b5090e2 Initial load
duke
parents:
diff changeset
   923
  address generate_d2l_fixup() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   924
    StubCodeMark mark(this, "StubRoutines", "d2l_fixup");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   925
    Address inout(rsp, 6 * wordSize); // return address + 5 saves
489c9b5090e2 Initial load
duke
parents:
diff changeset
   926
489c9b5090e2 Initial load
duke
parents:
diff changeset
   927
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   928
489c9b5090e2 Initial load
duke
parents:
diff changeset
   929
    Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   930
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   931
    __ push(rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   932
    __ push(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   933
    __ push(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   934
    __ push(c_rarg1);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   935
    __ push(c_rarg0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   936
489c9b5090e2 Initial load
duke
parents:
diff changeset
   937
    __ movl(rax, 0x7ff00000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   938
    __ movq(c_rarg2, inout);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   939
    __ movl(c_rarg3, c_rarg2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   940
    __ mov(c_rarg1, c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   941
    __ mov(c_rarg0, c_rarg2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   942
    __ negl(c_rarg3);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   943
    __ shrptr(c_rarg1, 0x20);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   944
    __ orl(c_rarg3, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   945
    __ andl(c_rarg1, 0x7fffffff);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   946
    __ xorl(c_rarg2, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   947
    __ shrl(c_rarg3, 0x1f);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   948
    __ orl(c_rarg1, c_rarg3);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   949
    __ cmpl(rax, c_rarg1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   950
    __ jcc(Assembler::negative, L); // NaN -> 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
   951
    __ testq(c_rarg0, c_rarg0); // signed ? min_jlong : max_jlong
489c9b5090e2 Initial load
duke
parents:
diff changeset
   952
    __ mov64(c_rarg2, 0x8000000000000000);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   953
    __ mov64(rax, 0x7fffffffffffffff);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   954
    __ cmovq(Assembler::positive, c_rarg2, rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   955
489c9b5090e2 Initial load
duke
parents:
diff changeset
   956
    __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   957
    __ movq(inout, c_rarg2);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   958
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   959
    __ pop(c_rarg0);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   960
    __ pop(c_rarg1);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   961
    __ pop(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   962
    __ pop(c_rarg3);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
   963
    __ pop(rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   964
489c9b5090e2 Initial load
duke
parents:
diff changeset
   965
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   966
489c9b5090e2 Initial load
duke
parents:
diff changeset
   967
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   968
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   969
489c9b5090e2 Initial load
duke
parents:
diff changeset
   970
  address generate_fp_mask(const char *stub_name, int64_t mask) {
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
   971
    __ align(CodeEntryAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   972
    StubCodeMark mark(this, "StubRoutines", stub_name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
   973
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
   974
489c9b5090e2 Initial load
duke
parents:
diff changeset
   975
    __ emit_data64( mask, relocInfo::none );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   976
    __ emit_data64( mask, relocInfo::none );
489c9b5090e2 Initial load
duke
parents:
diff changeset
   977
489c9b5090e2 Initial load
duke
parents:
diff changeset
   978
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
   979
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
   980
489c9b5090e2 Initial load
duke
parents:
diff changeset
   981
  // Non-destructive plausibility checks for oops
489c9b5090e2 Initial load
duke
parents:
diff changeset
   982
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   983
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   984
  //    all args on stack!
489c9b5090e2 Initial load
duke
parents:
diff changeset
   985
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
   986
  // Stack after saving c_rarg3:
489c9b5090e2 Initial load
duke
parents:
diff changeset
   987
  //    [tos + 0]: saved c_rarg3
489c9b5090e2 Initial load
duke
parents:
diff changeset
   988
  //    [tos + 1]: saved c_rarg2
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
   989
  //    [tos + 2]: saved r12 (several TemplateTable methods use it)
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
   990
  //    [tos + 3]: saved flags
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
   991
  //    [tos + 4]: return address
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
   992
  //  * [tos + 5]: error message (char*)
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
   993
  //  * [tos + 6]: object to verify (oop)
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
   994
  //  * [tos + 7]: saved rax - saved by caller and bashed
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
   995
  //  * [tos + 8]: saved r10 (rscratch1) - saved by caller
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
   996
  //  * = popped on exit
489c9b5090e2 Initial load
duke
parents:
diff changeset
   997
  address generate_verify_oop() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
   998
    StubCodeMark mark(this, "StubRoutines", "verify_oop");
489c9b5090e2 Initial load
duke
parents:
diff changeset
   999
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1000
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1001
    Label exit, error;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1002
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1003
    __ pushf();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1004
    __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1005
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1006
    __ push(r12);
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1007
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1008
    // save c_rarg2 and c_rarg3
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1009
    __ push(c_rarg2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1010
    __ push(c_rarg3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1011
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1012
    enum {
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1013
           // After previous pushes.
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1014
           oop_to_verify = 6 * wordSize,
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1015
           saved_rax     = 7 * wordSize,
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
  1016
           saved_r10     = 8 * wordSize,
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1017
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1018
           // Before the call to MacroAssembler::debug(), see below.
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1019
           return_addr   = 16 * wordSize,
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1020
           error_msg     = 17 * wordSize
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1021
    };
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1022
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1023
    // get object
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1024
    __ movptr(rax, Address(rsp, oop_to_verify));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1025
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1026
    // make sure object is 'reasonable'
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1027
    __ testptr(rax, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1028
    __ jcc(Assembler::zero, exit); // if obj is NULL it is OK
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1029
    // Check if the oop is in the right area of memory
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1030
    __ movptr(c_rarg2, rax);
1888
bbf498fb4354 6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents: 1437
diff changeset
  1031
    __ movptr(c_rarg3, (intptr_t) Universe::verify_oop_mask());
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1032
    __ andptr(c_rarg2, c_rarg3);
1888
bbf498fb4354 6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents: 1437
diff changeset
  1033
    __ movptr(c_rarg3, (intptr_t) Universe::verify_oop_bits());
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1034
    __ cmpptr(c_rarg2, c_rarg3);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1035
    __ jcc(Assembler::notZero, error);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1036
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1037
    // set r12 to heapbase for load_klass()
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1038
    __ reinit_heapbase();
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1039
13728
882756847a04 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 13391
diff changeset
  1040
    // make sure klass is 'reasonable', which is not zero.
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1041
    __ load_klass(rax, rax);  // get klass
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1042
    __ testptr(rax, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1043
    __ jcc(Assembler::zero, error); // if klass is NULL it is broken
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1044
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1045
    // return if everything seems ok
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1046
    __ bind(exit);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1047
    __ movptr(rax, Address(rsp, saved_rax));     // get saved rax back
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
  1048
    __ movptr(rscratch1, Address(rsp, saved_r10)); // get saved r10 back
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1049
    __ pop(c_rarg3);                             // restore c_rarg3
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1050
    __ pop(c_rarg2);                             // restore c_rarg2
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1051
    __ pop(r12);                                 // restore r12
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1052
    __ popf();                                   // restore flags
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
  1053
    __ ret(4 * wordSize);                        // pop caller saved stuff
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1054
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1055
    // handle errors
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1056
    __ bind(error);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1057
    __ movptr(rax, Address(rsp, saved_rax));     // get saved rax back
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
  1058
    __ movptr(rscratch1, Address(rsp, saved_r10)); // get saved r10 back
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1059
    __ pop(c_rarg3);                             // get saved c_rarg3 back
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1060
    __ pop(c_rarg2);                             // get saved c_rarg2 back
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1061
    __ pop(r12);                                 // get saved r12 back
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1062
    __ popf();                                   // get saved flags off stack --
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1063
                                                 // will be ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1064
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1065
    __ pusha();                                  // push registers
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1066
                                                 // (rip is already
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1067
                                                 // already pushed)
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1068
    // debug(char* msg, int64_t pc, int64_t regs[])
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1069
    // We've popped the registers we'd saved (c_rarg3, c_rarg2 and flags), and
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1070
    // pushed all the registers, so now the stack looks like:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1071
    //     [tos +  0] 16 saved registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1072
    //     [tos + 16] return address
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1073
    //   * [tos + 17] error message (char*)
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1074
    //   * [tos + 18] object to verify (oop)
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1075
    //   * [tos + 19] saved rax - saved by caller and bashed
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
  1076
    //   * [tos + 20] saved r10 (rscratch1) - saved by caller
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1077
    //   * = popped on exit
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1078
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1079
    __ movptr(c_rarg0, Address(rsp, error_msg));    // pass address of error message
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1080
    __ movptr(c_rarg1, Address(rsp, return_addr));  // pass return address
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1081
    __ movq(c_rarg2, rsp);                          // pass address of regs on stack
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1082
    __ mov(r12, rsp);                               // remember rsp
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1083
    __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1084
    __ andptr(rsp, -16);                            // align stack as required by ABI
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1085
    BLOCK_COMMENT("call MacroAssembler::debug");
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1086
    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1087
    __ mov(rsp, r12);                               // restore rsp
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1088
    __ popa();                                      // pop registers (includes r12)
5706
0c91076143f9 6958254: -XX:+VerifyOops is broken on x86
kvn
parents: 5547
diff changeset
  1089
    __ ret(4 * wordSize);                           // pop caller saved stuff
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1090
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1091
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1092
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1093
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1094
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1095
  // Verify that a register contains clean 32-bits positive value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1096
  // (high 32-bits are 0) so it could be used in 64-bits shifts.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1097
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1098
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1099
  //    Rint  -  32-bits value
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1100
  //    Rtmp  -  scratch
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1101
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1102
  void assert_clean_int(Register Rint, Register Rtmp) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1103
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1104
    Label L;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1105
    assert_different_registers(Rtmp, Rint);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1106
    __ movslq(Rtmp, Rint);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1107
    __ cmpq(Rtmp, Rint);
371
1aacedc9db7c 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 360
diff changeset
  1108
    __ jcc(Assembler::equal, L);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1109
    __ stop("high 32-bits of int value are not 0");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1110
    __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1111
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1112
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1113
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1114
  //  Generate overlap test for array copy stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1115
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1116
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1117
  //     c_rarg0 - from
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1118
  //     c_rarg1 - to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1119
  //     c_rarg2 - element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1120
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1121
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1122
  //     rax   - &from[element count - 1]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1123
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1124
  void array_overlap_test(address no_overlap_target, Address::ScaleFactor sf) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1125
    assert(no_overlap_target != NULL, "must be generated");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1126
    array_overlap_test(no_overlap_target, NULL, sf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1127
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1128
  void array_overlap_test(Label& L_no_overlap, Address::ScaleFactor sf) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1129
    array_overlap_test(NULL, &L_no_overlap, sf);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1130
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1131
  void array_overlap_test(address no_overlap_target, Label* NOLp, Address::ScaleFactor sf) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1132
    const Register from     = c_rarg0;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1133
    const Register to       = c_rarg1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1134
    const Register count    = c_rarg2;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1135
    const Register end_from = rax;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1136
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1137
    __ cmpptr(to, from);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1138
    __ lea(end_from, Address(from, count, sf, 0));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1139
    if (NOLp == NULL) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1140
      ExternalAddress no_overlap(no_overlap_target);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1141
      __ jump_cc(Assembler::belowEqual, no_overlap);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1142
      __ cmpptr(to, end_from);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1143
      __ jump_cc(Assembler::aboveEqual, no_overlap);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1144
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1145
      __ jcc(Assembler::belowEqual, (*NOLp));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1146
      __ cmpptr(to, end_from);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1147
      __ jcc(Assembler::aboveEqual, (*NOLp));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1148
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1149
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1150
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1151
  // Shuffle first three arg regs on Windows into Linux/Solaris locations.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1152
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1153
  // Outputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1154
  //    rdi - rcx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1155
  //    rsi - rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1156
  //    rdx - r8
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1157
  //    rcx - r9
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1158
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1159
  // Registers r9 and r10 are used to save rdi and rsi on Windows, which latter
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1160
  // are non-volatile.  r9 and r10 should not be used by the caller.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1161
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1162
  void setup_arg_regs(int nargs = 3) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1163
    const Register saved_rdi = r9;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1164
    const Register saved_rsi = r10;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1165
    assert(nargs == 3 || nargs == 4, "else fix");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1166
#ifdef _WIN64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1167
    assert(c_rarg0 == rcx && c_rarg1 == rdx && c_rarg2 == r8 && c_rarg3 == r9,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1168
           "unexpected argument registers");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1169
    if (nargs >= 4)
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1170
      __ mov(rax, r9);  // r9 is also saved_rdi
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1171
    __ movptr(saved_rdi, rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1172
    __ movptr(saved_rsi, rsi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1173
    __ mov(rdi, rcx); // c_rarg0
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1174
    __ mov(rsi, rdx); // c_rarg1
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1175
    __ mov(rdx, r8);  // c_rarg2
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1176
    if (nargs >= 4)
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1177
      __ mov(rcx, rax); // c_rarg3 (via rax)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1178
#else
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1179
    assert(c_rarg0 == rdi && c_rarg1 == rsi && c_rarg2 == rdx && c_rarg3 == rcx,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1180
           "unexpected argument registers");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1181
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1182
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1183
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1184
  void restore_arg_regs() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1185
    const Register saved_rdi = r9;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1186
    const Register saved_rsi = r10;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1187
#ifdef _WIN64
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1188
    __ movptr(rdi, saved_rdi);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1189
    __ movptr(rsi, saved_rsi);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1190
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1191
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1192
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1193
  // Generate code for an array write pre barrier
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1194
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1195
  //     addr    -  starting address
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1196
  //     count   -  element count
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1197
  //     tmp     - scratch register
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1198
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1199
  //     Destroy no registers!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1200
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1201
  void  gen_write_ref_array_pre_barrier(Register addr, Register count, bool dest_uninitialized) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1202
    BarrierSet* bs = Universe::heap()->barrier_set();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1203
    switch (bs->kind()) {
49347
edb65305d3ac 8195148: Collapse G1SATBCardTableModRefBS and G1SATBCardTableLoggingModRefBS into a single G1BarrierSet
eosterlund
parents: 49164
diff changeset
  1204
      case BarrierSet::G1BarrierSet:
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1205
        // With G1, don't generate the call if we statically know that the target in uninitialized
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1206
        if (!dest_uninitialized) {
48807
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1207
          Label filtered;
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1208
          Address in_progress(r15_thread, in_bytes(JavaThread::satb_mark_queue_offset() +
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1209
                                                   SATBMarkQueue::byte_offset_of_active()));
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1210
          // Is marking active?
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1211
          if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1212
            __ cmpl(in_progress, 0);
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1213
          } else {
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1214
            assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1215
            __ cmpb(in_progress, 0);
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1216
          }
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1217
          __ jcc(Assembler::equal, filtered);
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1218
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1219
           __ pusha();                      // push registers
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1220
           if (count == c_rarg0) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1221
             if (addr == c_rarg1) {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1222
               // exactly backwards!!
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1223
               __ xchgptr(c_rarg1, c_rarg0);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1224
             } else {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1225
               __ movptr(c_rarg1, count);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1226
               __ movptr(c_rarg0, addr);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1227
             }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1228
           } else {
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1229
             __ movptr(c_rarg0, addr);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1230
             __ movptr(c_rarg1, count);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1231
           }
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1232
           __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre), 2);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1233
           __ popa();
48807
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1234
fd8ccb37fce9 8195776: [x86,sparc] A row of minor fixes and enhancements.
goetz
parents: 48468
diff changeset
  1235
           __ bind(filtered);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1236
        }
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1237
         break;
49455
848864ed9b17 8199604: Rename CardTableModRefBS to CardTableBarrierSet
eosterlund
parents: 49368
diff changeset
  1238
      case BarrierSet::CardTableBarrierSet:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1239
        break;
1374
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1240
      default:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1241
        ShouldNotReachHere();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1242
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1243
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1244
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1245
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1246
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1247
  // Generate code for an array write post barrier
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1248
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1249
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1250
  //     start    - register containing starting address of destination array
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1251
  //     count    - elements count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1252
  //     scratch  - scratch register
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1253
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1254
  //  The input registers are overwritten.
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1255
  //
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1256
  void  gen_write_ref_array_post_barrier(Register start, Register count, Register scratch) {
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1257
    assert_different_registers(start, count, scratch);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1258
    BarrierSet* bs = Universe::heap()->barrier_set();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1259
    switch (bs->kind()) {
49347
edb65305d3ac 8195148: Collapse G1SATBCardTableModRefBS and G1SATBCardTableLoggingModRefBS into a single G1BarrierSet
eosterlund
parents: 49164
diff changeset
  1260
      case BarrierSet::G1BarrierSet:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1261
        {
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1262
          __ pusha();             // push registers (overkill)
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1263
          if (c_rarg0 == count) { // On win64 c_rarg0 == rcx
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1264
            assert_different_registers(c_rarg1, start);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1265
            __ mov(c_rarg1, count);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1266
            __ mov(c_rarg0, start);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1267
          } else {
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1268
            assert_different_registers(c_rarg0, count);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1269
            __ mov(c_rarg0, start);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1270
            __ mov(c_rarg1, count);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1271
          }
4740
d708800308b7 6918006: G1: spill space must be reserved on the stack for barrier calls on Windows x64
apetrusenko
parents: 4645
diff changeset
  1272
          __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post), 2);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1273
          __ popa();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1274
        }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1275
        break;
49455
848864ed9b17 8199604: Rename CardTableModRefBS to CardTableBarrierSet
eosterlund
parents: 49368
diff changeset
  1276
      case BarrierSet::CardTableBarrierSet:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1277
        {
48104
62d5973082e3 8185591: guarantee(_byte_map[_guard_index] == last_card) failed: card table guard has been modified
aharlap
parents: 47810
diff changeset
  1278
          Label L_loop, L_done;
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1279
          const Register end = count;
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1280
48104
62d5973082e3 8185591: guarantee(_byte_map[_guard_index] == last_card) failed: card table guard has been modified
aharlap
parents: 47810
diff changeset
  1281
          __ testl(count, count);
62d5973082e3 8185591: guarantee(_byte_map[_guard_index] == last_card) failed: card table guard has been modified
aharlap
parents: 47810
diff changeset
  1282
          __ jcc(Assembler::zero, L_done); // zero count - nothing to do
62d5973082e3 8185591: guarantee(_byte_map[_guard_index] == last_card) failed: card table guard has been modified
aharlap
parents: 47810
diff changeset
  1283
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1284
          __ leaq(end, Address(start, count, TIMES_OOP, 0));  // end == start+count*oop_size
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1285
          __ subptr(end, BytesPerHeapOop); // end - 1 to make inclusive
49164
7e958a8ebcd3 8195142: Refactor out card table from CardTableModRefBS to flatten the BarrierSet hierarchy
eosterlund
parents: 48807
diff changeset
  1286
          __ shrptr(start, CardTable::card_shift);
7e958a8ebcd3 8195142: Refactor out card table from CardTableModRefBS to flatten the BarrierSet hierarchy
eosterlund
parents: 48807
diff changeset
  1287
          __ shrptr(end,   CardTable::card_shift);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1288
          __ subptr(end, start); // end --> cards count
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1289
49164
7e958a8ebcd3 8195142: Refactor out card table from CardTableModRefBS to flatten the BarrierSet hierarchy
eosterlund
parents: 48807
diff changeset
  1290
          int64_t disp = ci_card_table_address_as<int64_t>();
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1291
          __ mov64(scratch, disp);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1292
          __ addptr(start, scratch);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1293
        __ BIND(L_loop);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1294
          __ movb(Address(start, count, Address::times_1), 0);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1295
          __ decrement(count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1296
          __ jcc(Assembler::greaterEqual, L_loop);
48104
62d5973082e3 8185591: guarantee(_byte_map[_guard_index] == last_card) failed: card table guard has been modified
aharlap
parents: 47810
diff changeset
  1297
        __ BIND(L_done);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1298
        }
1374
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1299
        break;
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1300
      default:
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1301
        ShouldNotReachHere();
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1302
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1303
    }
4c24294029a9 6711316: Open source the Garbage-First garbage collector
ysr
parents: 371
diff changeset
  1304
  }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1305
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1306
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1307
  // Copy big chunks forward
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1308
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1309
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1310
  //   end_from     - source arrays end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1311
  //   end_to       - destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1312
  //   qword_count  - 64-bits element count, negative
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1313
  //   to           - scratch
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1314
  //   L_copy_bytes - entry label
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1315
  //   L_copy_8_bytes  - exit  label
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1316
  //
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1317
  void copy_bytes_forward(Register end_from, Register end_to,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1318
                             Register qword_count, Register to,
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1319
                             Label& L_copy_bytes, Label& L_copy_8_bytes) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1320
    DEBUG_ONLY(__ stop("enter at entry label, not here"));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1321
    Label L_loop;
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  1322
    __ align(OptoLoopAlignment);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1323
    if (UseUnalignedLoadStores) {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1324
      Label L_end;
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1325
      if (UseAVX > 2) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1326
        __ movl(to, 0xffff);
35113
b11bd150ed8a 8144771: Use AVX3 instructions for string compare
kvn
parents: 35110
diff changeset
  1327
        __ kmovwl(k1, to);
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1328
      }
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1329
      // Copy 64-bytes per iteration
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1330
      __ BIND(L_loop);
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
  1331
      if (UseAVX > 2) {
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1332
        __ evmovdqul(xmm0, Address(end_from, qword_count, Address::times_8, -56), Assembler::AVX_512bit);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1333
        __ evmovdqul(Address(end_to, qword_count, Address::times_8, -56), xmm0, Assembler::AVX_512bit);
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
  1334
      } else if (UseAVX == 2) {
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1335
        __ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1336
        __ vmovdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1337
        __ vmovdqu(xmm1, Address(end_from, qword_count, Address::times_8, -24));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1338
        __ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1339
      } else {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1340
        __ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -56));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1341
        __ movdqu(Address(end_to, qword_count, Address::times_8, -56), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1342
        __ movdqu(xmm1, Address(end_from, qword_count, Address::times_8, -40));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1343
        __ movdqu(Address(end_to, qword_count, Address::times_8, -40), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1344
        __ movdqu(xmm2, Address(end_from, qword_count, Address::times_8, -24));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1345
        __ movdqu(Address(end_to, qword_count, Address::times_8, -24), xmm2);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1346
        __ movdqu(xmm3, Address(end_from, qword_count, Address::times_8, - 8));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1347
        __ movdqu(Address(end_to, qword_count, Address::times_8, - 8), xmm3);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1348
      }
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1349
      __ BIND(L_copy_bytes);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1350
      __ addptr(qword_count, 8);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1351
      __ jcc(Assembler::lessEqual, L_loop);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1352
      __ subptr(qword_count, 4);  // sub(8) and add(4)
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1353
      __ jccb(Assembler::greater, L_end);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1354
      // Copy trailing 32 bytes
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1355
      if (UseAVX >= 2) {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1356
        __ vmovdqu(xmm0, Address(end_from, qword_count, Address::times_8, -24));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1357
        __ vmovdqu(Address(end_to, qword_count, Address::times_8, -24), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1358
      } else {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1359
        __ movdqu(xmm0, Address(end_from, qword_count, Address::times_8, -24));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1360
        __ movdqu(Address(end_to, qword_count, Address::times_8, -24), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1361
        __ movdqu(xmm1, Address(end_from, qword_count, Address::times_8, - 8));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1362
        __ movdqu(Address(end_to, qword_count, Address::times_8, - 8), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1363
      }
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1364
      __ addptr(qword_count, 4);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1365
      __ BIND(L_end);
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
  1366
      if (UseAVX >= 2) {
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
  1367
        // clean upper bits of YMM registers
30299
1f6f7d1e0c1e 8078113: 8011102 changes may cause incorrect results
kvn
parents: 29695
diff changeset
  1368
        __ vpxor(xmm0, xmm0);
1f6f7d1e0c1e 8078113: 8011102 changes may cause incorrect results
kvn
parents: 29695
diff changeset
  1369
        __ vpxor(xmm1, xmm1);
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
  1370
      }
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1371
    } else {
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1372
      // Copy 32-bytes per iteration
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1373
      __ BIND(L_loop);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1374
      __ movq(to, Address(end_from, qword_count, Address::times_8, -24));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1375
      __ movq(Address(end_to, qword_count, Address::times_8, -24), to);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1376
      __ movq(to, Address(end_from, qword_count, Address::times_8, -16));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1377
      __ movq(Address(end_to, qword_count, Address::times_8, -16), to);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1378
      __ movq(to, Address(end_from, qword_count, Address::times_8, - 8));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1379
      __ movq(Address(end_to, qword_count, Address::times_8, - 8), to);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1380
      __ movq(to, Address(end_from, qword_count, Address::times_8, - 0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1381
      __ movq(Address(end_to, qword_count, Address::times_8, - 0), to);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1382
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1383
      __ BIND(L_copy_bytes);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1384
      __ addptr(qword_count, 4);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1385
      __ jcc(Assembler::lessEqual, L_loop);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1386
    }
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1387
    __ subptr(qword_count, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1388
    __ jcc(Assembler::less, L_copy_8_bytes); // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1389
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1390
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1391
  // Copy big chunks backward
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1392
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1393
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1394
  //   from         - source arrays address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1395
  //   dest         - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1396
  //   qword_count  - 64-bits element count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1397
  //   to           - scratch
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1398
  //   L_copy_bytes - entry label
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1399
  //   L_copy_8_bytes  - exit  label
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1400
  //
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1401
  void copy_bytes_backward(Register from, Register dest,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1402
                              Register qword_count, Register to,
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1403
                              Label& L_copy_bytes, Label& L_copy_8_bytes) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1404
    DEBUG_ONLY(__ stop("enter at entry label, not here"));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1405
    Label L_loop;
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  1406
    __ align(OptoLoopAlignment);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1407
    if (UseUnalignedLoadStores) {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1408
      Label L_end;
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1409
      if (UseAVX > 2) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1410
        __ movl(to, 0xffff);
35113
b11bd150ed8a 8144771: Use AVX3 instructions for string compare
kvn
parents: 35110
diff changeset
  1411
        __ kmovwl(k1, to);
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  1412
      }
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1413
      // Copy 64-bytes per iteration
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1414
      __ BIND(L_loop);
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
  1415
      if (UseAVX > 2) {
34203
6817dadf6c7e 8142980: SKX SpecJvm2008 - Derby
mcberg
parents: 34162
diff changeset
  1416
        __ evmovdqul(xmm0, Address(from, qword_count, Address::times_8, 0), Assembler::AVX_512bit);
6817dadf6c7e 8142980: SKX SpecJvm2008 - Derby
mcberg
parents: 34162
diff changeset
  1417
        __ evmovdqul(Address(dest, qword_count, Address::times_8, 0), xmm0, Assembler::AVX_512bit);
30624
2e1803c8a26d 8076276: Add support for AVX512
kvn
parents: 30299
diff changeset
  1418
      } else if (UseAVX == 2) {
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1419
        __ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 32));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1420
        __ vmovdqu(Address(dest, qword_count, Address::times_8, 32), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1421
        __ vmovdqu(xmm1, Address(from, qword_count, Address::times_8,  0));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1422
        __ vmovdqu(Address(dest, qword_count, Address::times_8,  0), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1423
      } else {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1424
        __ movdqu(xmm0, Address(from, qword_count, Address::times_8, 48));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1425
        __ movdqu(Address(dest, qword_count, Address::times_8, 48), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1426
        __ movdqu(xmm1, Address(from, qword_count, Address::times_8, 32));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1427
        __ movdqu(Address(dest, qword_count, Address::times_8, 32), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1428
        __ movdqu(xmm2, Address(from, qword_count, Address::times_8, 16));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1429
        __ movdqu(Address(dest, qword_count, Address::times_8, 16), xmm2);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1430
        __ movdqu(xmm3, Address(from, qword_count, Address::times_8,  0));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1431
        __ movdqu(Address(dest, qword_count, Address::times_8,  0), xmm3);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1432
      }
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1433
      __ BIND(L_copy_bytes);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1434
      __ subptr(qword_count, 8);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1435
      __ jcc(Assembler::greaterEqual, L_loop);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1436
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1437
      __ addptr(qword_count, 4);  // add(8) and sub(4)
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1438
      __ jccb(Assembler::less, L_end);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1439
      // Copy trailing 32 bytes
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1440
      if (UseAVX >= 2) {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1441
        __ vmovdqu(xmm0, Address(from, qword_count, Address::times_8, 0));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1442
        __ vmovdqu(Address(dest, qword_count, Address::times_8, 0), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1443
      } else {
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1444
        __ movdqu(xmm0, Address(from, qword_count, Address::times_8, 16));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1445
        __ movdqu(Address(dest, qword_count, Address::times_8, 16), xmm0);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1446
        __ movdqu(xmm1, Address(from, qword_count, Address::times_8,  0));
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1447
        __ movdqu(Address(dest, qword_count, Address::times_8,  0), xmm1);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1448
      }
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1449
      __ subptr(qword_count, 4);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1450
      __ BIND(L_end);
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
  1451
      if (UseAVX >= 2) {
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
  1452
        // clean upper bits of YMM registers
30299
1f6f7d1e0c1e 8078113: 8011102 changes may cause incorrect results
kvn
parents: 29695
diff changeset
  1453
        __ vpxor(xmm0, xmm0);
1f6f7d1e0c1e 8078113: 8011102 changes may cause incorrect results
kvn
parents: 29695
diff changeset
  1454
        __ vpxor(xmm1, xmm1);
16624
9dbd4b210bf9 8011102: Clear AVX registers after return from JNI call
kvn
parents: 15115
diff changeset
  1455
      }
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1456
    } else {
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1457
      // Copy 32-bytes per iteration
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1458
      __ BIND(L_loop);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1459
      __ movq(to, Address(from, qword_count, Address::times_8, 24));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1460
      __ movq(Address(dest, qword_count, Address::times_8, 24), to);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1461
      __ movq(to, Address(from, qword_count, Address::times_8, 16));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1462
      __ movq(Address(dest, qword_count, Address::times_8, 16), to);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1463
      __ movq(to, Address(from, qword_count, Address::times_8,  8));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1464
      __ movq(Address(dest, qword_count, Address::times_8,  8), to);
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1465
      __ movq(to, Address(from, qword_count, Address::times_8,  0));
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1466
      __ movq(Address(dest, qword_count, Address::times_8,  0), to);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1467
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1468
      __ BIND(L_copy_bytes);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1469
      __ subptr(qword_count, 4);
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1470
      __ jcc(Assembler::greaterEqual, L_loop);
1437
d1846c1c04c4 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 1394
diff changeset
  1471
    }
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1472
    __ addptr(qword_count, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1473
    __ jcc(Assembler::greater, L_copy_8_bytes); // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1474
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1475
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1476
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1477
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1478
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1479
  //             ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1480
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1481
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1482
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1483
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1484
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1485
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1486
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1487
  // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1488
  // we let the hardware handle it.  The one to eight bytes within words,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1489
  // dwords or qwords that span cache line boundaries will still be loaded
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1490
  // and stored atomically.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1491
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1492
  // Side Effects:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1493
  //   disjoint_byte_copy_entry is set to the no-overlap entry point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1494
  //   used by generate_conjoint_byte_copy().
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1495
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1496
  address generate_disjoint_byte_copy(bool aligned, address* entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1497
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1498
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1499
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1500
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1501
    Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes, L_copy_2_bytes;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1502
    Label L_copy_byte, L_exit;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1503
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1504
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1505
    const Register count       = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1506
    const Register byte_count  = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1507
    const Register qword_count = count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1508
    const Register end_from    = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1509
    const Register end_to      = to;   // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1510
    // End pointers are inclusive, and if count is not zero they point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1511
    // to the last unit copied:  end_to[0] := end_from[0]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1512
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1513
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1514
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1515
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1516
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1517
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1518
       // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1519
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1520
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1521
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1522
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1523
                      // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1524
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1525
    // 'from', 'to' and 'count' are now valid
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1526
    __ movptr(byte_count, count);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1527
    __ shrptr(count, 3); // count => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1528
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1529
    // Copy from low to high addresses.  Use 'to' as scratch.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1530
    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1531
    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1532
    __ negptr(qword_count); // make the count negative
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1533
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1534
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1535
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1536
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1537
    __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1538
    __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1539
    __ increment(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1540
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1541
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1542
    // Check for and copy trailing dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1543
  __ BIND(L_copy_4_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1544
    __ testl(byte_count, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1545
    __ jccb(Assembler::zero, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1546
    __ movl(rax, Address(end_from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1547
    __ movl(Address(end_to, 8), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1548
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1549
    __ addptr(end_from, 4);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1550
    __ addptr(end_to, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1551
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1552
    // Check for and copy trailing word
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1553
  __ BIND(L_copy_2_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1554
    __ testl(byte_count, 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1555
    __ jccb(Assembler::zero, L_copy_byte);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1556
    __ movw(rax, Address(end_from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1557
    __ movw(Address(end_to, 8), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1558
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1559
    __ addptr(end_from, 2);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1560
    __ addptr(end_to, 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1561
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1562
    // Check for and copy trailing byte
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1563
  __ BIND(L_copy_byte);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1564
    __ testl(byte_count, 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1565
    __ jccb(Assembler::zero, L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1566
    __ movb(rax, Address(end_from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1567
    __ movb(Address(end_to, 8), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1568
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1569
  __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1570
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1571
    inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1572
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1573
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1574
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1575
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1576
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1577
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1578
    copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1579
    __ jmp(L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1580
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1581
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1582
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1583
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1584
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1585
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1586
  //             ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1587
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1588
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1589
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1590
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1591
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1592
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1593
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1594
  // If 'from' and/or 'to' are aligned on 4-, 2-, or 1-byte boundaries,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1595
  // we let the hardware handle it.  The one to eight bytes within words,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1596
  // dwords or qwords that span cache line boundaries will still be loaded
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1597
  // and stored atomically.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1598
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1599
  address generate_conjoint_byte_copy(bool aligned, address nooverlap_target,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1600
                                      address* entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1601
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1602
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1603
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1604
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1605
    Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes, L_copy_2_bytes;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1606
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1607
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1608
    const Register count       = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1609
    const Register byte_count  = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1610
    const Register qword_count = count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1611
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1612
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1613
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1614
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1615
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1616
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1617
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1618
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1619
    }
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1620
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1621
    array_overlap_test(nooverlap_target, Address::times_1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1622
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1623
                      // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1624
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1625
    // 'from', 'to' and 'count' are now valid
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1626
    __ movptr(byte_count, count);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1627
    __ shrptr(count, 3);   // count => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1628
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1629
    // Copy from high to low addresses.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1630
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1631
    // Check for and copy trailing byte
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1632
    __ testl(byte_count, 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1633
    __ jcc(Assembler::zero, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1634
    __ movb(rax, Address(from, byte_count, Address::times_1, -1));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1635
    __ movb(Address(to, byte_count, Address::times_1, -1), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1636
    __ decrement(byte_count); // Adjust for possible trailing word
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1637
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1638
    // Check for and copy trailing word
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1639
  __ BIND(L_copy_2_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1640
    __ testl(byte_count, 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1641
    __ jcc(Assembler::zero, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1642
    __ movw(rax, Address(from, byte_count, Address::times_1, -2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1643
    __ movw(Address(to, byte_count, Address::times_1, -2), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1644
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1645
    // Check for and copy trailing dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1646
  __ BIND(L_copy_4_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1647
    __ testl(byte_count, 4);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1648
    __ jcc(Assembler::zero, L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1649
    __ movl(rax, Address(from, qword_count, Address::times_8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1650
    __ movl(Address(to, qword_count, Address::times_8), rax);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1651
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1652
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1653
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1654
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1655
    __ movq(rax, Address(from, qword_count, Address::times_8, -8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1656
    __ movq(Address(to, qword_count, Address::times_8, -8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1657
    __ decrement(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1658
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1659
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1660
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1661
    inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1662
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1663
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1664
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1665
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1666
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1667
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1668
    copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1669
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1670
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1671
    inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1672
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1673
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1674
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1675
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1676
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1677
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1678
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1679
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1680
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1681
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1682
  //             ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1683
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1684
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1685
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1686
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1687
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1688
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1689
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1690
  // If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1691
  // let the hardware handle it.  The two or four words within dwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1692
  // or qwords that span cache line boundaries will still be loaded
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1693
  // and stored atomically.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1694
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1695
  // Side Effects:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1696
  //   disjoint_short_copy_entry is set to the no-overlap entry point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1697
  //   used by generate_conjoint_short_copy().
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1698
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1699
  address generate_disjoint_short_copy(bool aligned, address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1700
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1701
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1702
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1703
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1704
    Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes,L_copy_2_bytes,L_exit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1705
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1706
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1707
    const Register count       = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1708
    const Register word_count  = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1709
    const Register qword_count = count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1710
    const Register end_from    = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1711
    const Register end_to      = to;   // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1712
    // End pointers are inclusive, and if count is not zero they point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1713
    // to the last unit copied:  end_to[0] := end_from[0]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1714
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1715
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1716
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1717
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1718
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1719
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1720
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1721
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1722
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1723
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1724
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1725
                      // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1726
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1727
    // 'from', 'to' and 'count' are now valid
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1728
    __ movptr(word_count, count);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1729
    __ shrptr(count, 2); // count => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1730
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1731
    // Copy from low to high addresses.  Use 'to' as scratch.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1732
    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1733
    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1734
    __ negptr(qword_count);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1735
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1736
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1737
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1738
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1739
    __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1740
    __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1741
    __ increment(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1742
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1743
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1744
    // Original 'dest' is trashed, so we can't use it as a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1745
    // base register for a possible trailing word copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1746
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1747
    // Check for and copy trailing dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1748
  __ BIND(L_copy_4_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1749
    __ testl(word_count, 2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1750
    __ jccb(Assembler::zero, L_copy_2_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1751
    __ movl(rax, Address(end_from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1752
    __ movl(Address(end_to, 8), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1753
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1754
    __ addptr(end_from, 4);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1755
    __ addptr(end_to, 4);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1756
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1757
    // Check for and copy trailing word
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1758
  __ BIND(L_copy_2_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1759
    __ testl(word_count, 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1760
    __ jccb(Assembler::zero, L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1761
    __ movw(rax, Address(end_from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1762
    __ movw(Address(end_to, 8), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1763
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1764
  __ BIND(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1765
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1766
    inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1767
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1768
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1769
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1770
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1771
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1772
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1773
    copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1774
    __ jmp(L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1775
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1776
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1777
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1778
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1779
  address generate_fill(BasicType t, bool aligned, const char *name) {
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1780
    __ align(CodeEntryAlignment);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1781
    StubCodeMark mark(this, "StubRoutines", name);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1782
    address start = __ pc();
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1783
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1784
    BLOCK_COMMENT("Entry:");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1785
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1786
    const Register to       = c_rarg0;  // source array address
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1787
    const Register value    = c_rarg1;  // value
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1788
    const Register count    = c_rarg2;  // elements count
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1789
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1790
    __ enter(); // required for proper stackwalking of RuntimeStub frame
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1791
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1792
    __ generate_fill(t, aligned, to, value, count, rax, xmm0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1793
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1794
    __ vzeroupper();
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1795
    __ leave(); // required for proper stackwalking of RuntimeStub frame
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1796
    __ ret(0);
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1797
    return start;
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1798
  }
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  1799
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1800
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1801
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1802
  //             ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1803
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1804
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1805
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1806
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1807
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1808
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1809
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1810
  // If 'from' and/or 'to' are aligned on 4- or 2-byte boundaries, we
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1811
  // let the hardware handle it.  The two or four words within dwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1812
  // or qwords that span cache line boundaries will still be loaded
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1813
  // and stored atomically.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1814
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1815
  address generate_conjoint_short_copy(bool aligned, address nooverlap_target,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1816
                                       address *entry, const char *name) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1817
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1818
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1819
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1820
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1821
    Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1822
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1823
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1824
    const Register count       = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1825
    const Register word_count  = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1826
    const Register qword_count = count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1827
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1828
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1829
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1830
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1831
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1832
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1833
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1834
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1835
    }
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1836
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1837
    array_overlap_test(nooverlap_target, Address::times_2);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1838
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1839
                      // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1840
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1841
    // 'from', 'to' and 'count' are now valid
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1842
    __ movptr(word_count, count);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1843
    __ shrptr(count, 2); // count => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1844
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1845
    // Copy from high to low addresses.  Use 'to' as scratch.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1846
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1847
    // Check for and copy trailing word
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1848
    __ testl(word_count, 1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1849
    __ jccb(Assembler::zero, L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1850
    __ movw(rax, Address(from, word_count, Address::times_2, -2));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1851
    __ movw(Address(to, word_count, Address::times_2, -2), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1852
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1853
    // Check for and copy trailing dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1854
  __ BIND(L_copy_4_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1855
    __ testl(word_count, 2);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1856
    __ jcc(Assembler::zero, L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1857
    __ movl(rax, Address(from, qword_count, Address::times_8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1858
    __ movl(Address(to, qword_count, Address::times_8), rax);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1859
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1860
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1861
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1862
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1863
    __ movq(rax, Address(from, qword_count, Address::times_8, -8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1864
    __ movq(Address(to, qword_count, Address::times_8, -8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1865
    __ decrement(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1866
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1867
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1868
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1869
    inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1870
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1871
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1872
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1873
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1874
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1875
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1876
    copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1877
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1878
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1879
    inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1880
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1881
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1882
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1883
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1884
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1885
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1886
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1887
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1888
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1889
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1890
  //             ignored
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1891
  //   is_oop  - true => oop array, so generate store check code
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1892
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1893
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1894
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1895
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1896
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1897
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1898
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1899
  // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1900
  // the hardware handle it.  The two dwords within qwords that span
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1901
  // cache line boundaries will still be loaded and stored atomicly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1902
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1903
  // Side Effects:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1904
  //   disjoint_int_copy_entry is set to the no-overlap entry point
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1905
  //   used by generate_conjoint_int_oop_copy().
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1906
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1907
  address generate_disjoint_int_oop_copy(bool aligned, bool is_oop, address* entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1908
                                         const char *name, bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1909
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1910
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1911
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1912
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1913
    Label L_copy_bytes, L_copy_8_bytes, L_copy_4_bytes, L_exit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1914
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1915
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1916
    const Register count       = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1917
    const Register dword_count = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1918
    const Register qword_count = count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1919
    const Register end_from    = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1920
    const Register end_to      = to;   // destination array end address
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1921
    const Register saved_to    = r11;  // saved destination array address
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1922
    // End pointers are inclusive, and if count is not zero they point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1923
    // to the last unit copied:  end_to[0] := end_from[0]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1924
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1925
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1926
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1927
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1928
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1929
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1930
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1931
      BLOCK_COMMENT("Entry:");
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1932
    }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1933
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1934
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1935
                      // r9 and r10 may be used to save non-volatile registers
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1936
    if (is_oop) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1937
      __ movq(saved_to, to);
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1938
      gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1939
    }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1940
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1941
    // 'from', 'to' and 'count' are now valid
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1942
    __ movptr(dword_count, count);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1943
    __ shrptr(count, 1); // count => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1944
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1945
    // Copy from low to high addresses.  Use 'to' as scratch.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1946
    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1947
    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1948
    __ negptr(qword_count);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1949
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1950
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1951
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1952
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1953
    __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1954
    __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1955
    __ increment(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1956
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1957
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1958
    // Check for and copy trailing dword
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1959
  __ BIND(L_copy_4_bytes);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1960
    __ testl(dword_count, 1); // Only byte test since the value is 0 or 1
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1961
    __ jccb(Assembler::zero, L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1962
    __ movl(rax, Address(end_from, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1963
    __ movl(Address(end_to, 8), rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1964
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1965
  __ BIND(L_exit);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1966
    if (is_oop) {
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  1967
      gen_write_ref_array_post_barrier(saved_to, dword_count, rax);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1968
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1969
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  1970
    inc_counter_np(SharedRuntime::_jint_array_copy_ctr); // Update counter after rscratch1 is free
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  1971
    __ vzeroupper();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  1972
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1973
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1974
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1975
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1976
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  1977
    copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1978
    __ jmp(L_copy_4_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1979
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1980
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1981
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1982
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1983
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1984
  //   aligned - true => Input and output aligned on a HeapWord == 8-byte boundary
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1985
  //             ignored
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  1986
  //   is_oop  - true => oop array, so generate store check code
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1987
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1988
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1989
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1990
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1991
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1992
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1993
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1994
  // If 'from' and/or 'to' are aligned on 4-byte boundaries, we let
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1995
  // the hardware handle it.  The two dwords within qwords that span
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1996
  // cache line boundaries will still be loaded and stored atomicly.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  1997
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  1998
  address generate_conjoint_int_oop_copy(bool aligned, bool is_oop, address nooverlap_target,
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  1999
                                         address *entry, const char *name,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2000
                                         bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2001
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2002
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2003
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2004
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2005
    Label L_copy_bytes, L_copy_8_bytes, L_copy_2_bytes, L_exit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2006
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2007
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2008
    const Register count       = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2009
    const Register dword_count = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2010
    const Register qword_count = count;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2011
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2012
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2013
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2014
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2015
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2016
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2017
       // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2018
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2019
    }
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2020
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2021
    array_overlap_test(nooverlap_target, Address::times_4);
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2022
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2023
                      // r9 and r10 may be used to save non-volatile registers
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2024
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2025
    if (is_oop) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2026
      // no registers are destroyed by this call
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2027
      gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2028
    }
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2029
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2030
    assert_clean_int(count, rax); // Make sure 'count' is clean int.
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2031
    // 'from', 'to' and 'count' are now valid
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2032
    __ movptr(dword_count, count);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2033
    __ shrptr(count, 1); // count => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2034
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2035
    // Copy from high to low addresses.  Use 'to' as scratch.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2036
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2037
    // Check for and copy trailing dword
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2038
    __ testl(dword_count, 1);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2039
    __ jcc(Assembler::zero, L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2040
    __ movl(rax, Address(from, dword_count, Address::times_4, -4));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2041
    __ movl(Address(to, dword_count, Address::times_4, -4), rax);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2042
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2043
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2044
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2045
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2046
    __ movq(rax, Address(from, qword_count, Address::times_8, -8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2047
    __ movq(Address(to, qword_count, Address::times_8, -8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2048
    __ decrement(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2049
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2050
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2051
    if (is_oop) {
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2052
      __ jmp(L_exit);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2053
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2054
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2055
    inc_counter_np(SharedRuntime::_jint_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2056
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  2057
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2058
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2059
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2060
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2061
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2062
    copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2063
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2064
  __ BIND(L_exit);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2065
    if (is_oop) {
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2066
      gen_write_ref_array_post_barrier(to, dword_count, rax);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2067
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2068
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2069
    inc_counter_np(SharedRuntime::_jint_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2070
    __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  2071
    __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2072
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2073
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2074
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2075
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2076
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2077
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2078
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2079
  //   aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2080
  //             ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2081
  //   is_oop  - true => oop array, so generate store check code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2082
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2083
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2084
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2085
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2086
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2087
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2088
  //
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2089
 // Side Effects:
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2090
  //   disjoint_oop_copy_entry or disjoint_long_copy_entry is set to the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2091
  //   no-overlap entry point used by generate_conjoint_long_oop_copy().
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2092
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2093
  address generate_disjoint_long_oop_copy(bool aligned, bool is_oop, address *entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2094
                                          const char *name, bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2095
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2096
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2097
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2098
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2099
    Label L_copy_bytes, L_copy_8_bytes, L_exit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2100
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2101
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2102
    const Register qword_count = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2103
    const Register end_from    = from; // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2104
    const Register end_to      = rcx;  // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2105
    const Register saved_to    = to;
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2106
    const Register saved_count = r11;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2107
    // End pointers are inclusive, and if count is not zero they point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2108
    // to the last unit copied:  end_to[0] := end_from[0]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2109
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2110
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2111
    // Save no-overlap entry point for generate_conjoint_long_oop_copy()
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2112
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2113
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2114
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2115
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2116
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2117
      BLOCK_COMMENT("Entry:");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2118
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2119
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2120
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2121
                      // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2122
    // 'from', 'to' and 'qword_count' are now valid
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2123
    if (is_oop) {
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2124
      // Save to and count for store barrier
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2125
      __ movptr(saved_count, qword_count);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2126
      // no registers are destroyed by this call
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2127
      gen_write_ref_array_pre_barrier(to, qword_count, dest_uninitialized);
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2128
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2129
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2130
    // Copy from low to high addresses.  Use 'to' as scratch.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2131
    __ lea(end_from, Address(from, qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2132
    __ lea(end_to,   Address(to,   qword_count, Address::times_8, -8));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2133
    __ negptr(qword_count);
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2134
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2135
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2136
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2137
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2138
    __ movq(rax, Address(end_from, qword_count, Address::times_8, 8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2139
    __ movq(Address(end_to, qword_count, Address::times_8, 8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2140
    __ increment(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2141
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2142
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2143
    if (is_oop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2144
      __ jmp(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2145
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2146
      restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2147
      inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2148
      __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  2149
      __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2150
      __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2151
      __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2152
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2153
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2154
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2155
    copy_bytes_forward(end_from, end_to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2156
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2157
    if (is_oop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2158
    __ BIND(L_exit);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2159
      gen_write_ref_array_post_barrier(saved_to, saved_count, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2160
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2161
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2162
    if (is_oop) {
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2163
      inc_counter_np(SharedRuntime::_oop_array_copy_ctr); // Update counter after rscratch1 is free
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2164
    } else {
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2165
      inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2166
    }
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  2167
    __ vzeroupper();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2168
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2169
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2170
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2171
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2172
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2173
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2174
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2175
  // Arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2176
  //   aligned - true => Input and output aligned on a HeapWord boundary == 8 bytes
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2177
  //             ignored
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2178
  //   is_oop  - true => oop array, so generate store check code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2179
  //   name    - stub name string
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2180
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2181
  // Inputs:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2182
  //   c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2183
  //   c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2184
  //   c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2185
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2186
  address generate_conjoint_long_oop_copy(bool aligned, bool is_oop,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2187
                                          address nooverlap_target, address *entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2188
                                          const char *name, bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2189
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2190
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2191
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2192
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2193
    Label L_copy_bytes, L_copy_8_bytes, L_exit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2194
    const Register from        = rdi;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2195
    const Register to          = rsi;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2196
    const Register qword_count = rdx;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2197
    const Register saved_count = rcx;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2198
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2199
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2200
    assert_clean_int(c_rarg2, rax);    // Make sure 'count' is clean int.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2201
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2202
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2203
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2204
      // caller can pass a 64-bit byte count here (from Unsafe.copyMemory)
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2205
      BLOCK_COMMENT("Entry:");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2206
    }
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2207
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2208
    array_overlap_test(nooverlap_target, Address::times_8);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2209
    setup_arg_regs(); // from => rdi, to => rsi, count => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2210
                      // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2211
    // 'from', 'to' and 'qword_count' are now valid
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2212
    if (is_oop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2213
      // Save to and count for store barrier
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2214
      __ movptr(saved_count, qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2215
      // No registers are destroyed by this call
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2216
      gen_write_ref_array_pre_barrier(to, saved_count, dest_uninitialized);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2217
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2218
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2219
    __ jmp(L_copy_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2220
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2221
    // Copy trailing qwords
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2222
  __ BIND(L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2223
    __ movq(rax, Address(from, qword_count, Address::times_8, -8));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2224
    __ movq(Address(to, qword_count, Address::times_8, -8), rax);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2225
    __ decrement(qword_count);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2226
    __ jcc(Assembler::notZero, L_copy_8_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2227
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2228
    if (is_oop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2229
      __ jmp(L_exit);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2230
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2231
      restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2232
      inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2233
      __ xorptr(rax, rax); // return 0
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  2234
      __ vzeroupper();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2235
      __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2236
      __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2237
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2238
15115
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2239
    // Copy in multi-bytes chunks
f8ef87f6f07f 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 14834
diff changeset
  2240
    copy_bytes_backward(from, to, qword_count, rax, L_copy_bytes, L_copy_8_bytes);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2241
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2242
    if (is_oop) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2243
    __ BIND(L_exit);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2244
      gen_write_ref_array_post_barrier(to, saved_count, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2245
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2246
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2247
    if (is_oop) {
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2248
      inc_counter_np(SharedRuntime::_oop_array_copy_ctr); // Update counter after rscratch1 is free
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2249
    } else {
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2250
      inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); // Update counter after rscratch1 is free
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2251
    }
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  2252
    __ vzeroupper();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2253
    __ xorptr(rax, rax); // return 0
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2254
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2255
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2256
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2257
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2258
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2259
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2260
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2261
  // Helper for generating a dynamic type check.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2262
  // Smashes no registers.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2263
  void generate_type_check(Register sub_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2264
                           Register super_check_offset,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2265
                           Register super_klass,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2266
                           Label& L_success) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2267
    assert_different_registers(sub_klass, super_check_offset, super_klass);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2268
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2269
    BLOCK_COMMENT("type_check:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2270
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2271
    Label L_miss;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2272
2256
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1888
diff changeset
  2273
    __ check_klass_subtype_fast_path(sub_klass, super_klass, noreg,        &L_success, &L_miss, NULL,
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1888
diff changeset
  2274
                                     super_check_offset);
82d4e10b7c6b 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 1888
diff changeset
  2275
    __ check_klass_subtype_slow_path(sub_klass, super_klass, noreg, noreg, &L_success, NULL);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2276
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2277
    // Fall through on failure!
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2278
    __ BIND(L_miss);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2279
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2280
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2281
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2282
  //  Generate checkcasting array copy stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2283
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2284
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2285
  //    c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2286
  //    c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2287
  //    c_rarg2   - element count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2288
  //    c_rarg3   - size_t ckoff (super_check_offset)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2289
  // not Win64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2290
  //    c_rarg4   - oop ckval (super_klass)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2291
  // Win64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2292
  //    rsp+40    - oop ckval (super_klass)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2293
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2294
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2295
  //    rax ==  0  -  success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2296
  //    rax == -1^K - failure, where K is partial transfer count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2297
  //
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2298
  address generate_checkcast_copy(const char *name, address *entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2299
                                  bool dest_uninitialized = false) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2300
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2301
    Label L_load_element, L_store_element, L_do_card_marks, L_done;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2302
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2303
    // Input registers (after setup_arg_regs)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2304
    const Register from        = rdi;   // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2305
    const Register to          = rsi;   // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2306
    const Register length      = rdx;   // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2307
    const Register ckoff       = rcx;   // super_check_offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2308
    const Register ckval       = r8;    // super_klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2309
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2310
    // Registers used as temps (r13, r14 are save-on-entry)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2311
    const Register end_from    = from;  // source array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2312
    const Register end_to      = r13;   // destination array end address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2313
    const Register count       = rdx;   // -(count_remaining)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2314
    const Register r14_length  = r14;   // saved copy of length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2315
    // End pointers are inclusive, and if length is not zero they point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2316
    // to the last unit copied:  end_to[0] := end_from[0]
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2317
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2318
    const Register rax_oop    = rax;    // actual oop copied
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2319
    const Register r11_klass  = r11;    // oop._klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2320
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2321
    //---------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2322
    // Assembler stub will be used for this call to arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2323
    // if the two arrays are subtypes of Object[] but the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2324
    // destination array type is not equal to or a supertype
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2325
    // of the source type.  Each element must be separately
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2326
    // checked.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2327
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2328
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2329
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2330
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2331
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2332
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2333
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2334
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2335
    // caller guarantees that the arrays really are different
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2336
    // otherwise, we would have to make conjoint checks
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2337
    { Label L;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2338
      array_overlap_test(L, TIMES_OOP);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2339
      __ stop("checkcast_copy within a single array");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2340
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2341
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2342
#endif //ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2343
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2344
    setup_arg_regs(4); // from => rdi, to => rsi, length => rdx
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2345
                       // ckoff => rcx, ckval => r8
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2346
                       // r9 and r10 may be used to save non-volatile registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2347
#ifdef _WIN64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2348
    // last argument (#4) is on stack on Win64
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2349
    __ movptr(ckval, Address(rsp, 6 * wordSize));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2350
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2351
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2352
    // Caller of this entry point must set up the argument registers.
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2353
    if (entry != NULL) {
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2354
      *entry = __ pc();
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2355
      BLOCK_COMMENT("Entry:");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2356
    }
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2357
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2358
    // allocate spill slots for r13, r14
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2359
    enum {
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2360
      saved_r13_offset,
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2361
      saved_r14_offset,
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2362
      saved_rbp_offset
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2363
    };
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2364
    __ subptr(rsp, saved_rbp_offset * wordSize);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2365
    __ movptr(Address(rsp, saved_r13_offset * wordSize), r13);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2366
    __ movptr(Address(rsp, saved_r14_offset * wordSize), r14);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2367
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2368
    // check that int operands are properly extended to size_t
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2369
    assert_clean_int(length, rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2370
    assert_clean_int(ckoff, rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2371
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2372
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2373
    BLOCK_COMMENT("assert consistent ckoff/ckval");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2374
    // The ckoff and ckval must be mutually consistent,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2375
    // even though caller generates both.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2376
    { Label L;
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 11194
diff changeset
  2377
      int sco_offset = in_bytes(Klass::super_check_offset_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2378
      __ cmpl(ckoff, Address(ckval, sco_offset));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2379
      __ jcc(Assembler::equal, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2380
      __ stop("super_check_offset inconsistent");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2381
      __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2382
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2383
#endif //ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2384
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2385
    // Loop-invariant addresses.  They are exclusive end pointers.
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2386
    Address end_from_addr(from, length, TIMES_OOP, 0);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2387
    Address   end_to_addr(to,   length, TIMES_OOP, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2388
    // Loop-variant addresses.  They assume post-incremented count < 0.
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2389
    Address from_element_addr(end_from, count, TIMES_OOP, 0);
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2390
    Address   to_element_addr(end_to,   count, TIMES_OOP, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2391
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2392
    gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2393
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2394
    // Copy from low to high addresses, indexed from the end of each array.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2395
    __ lea(end_from, end_from_addr);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2396
    __ lea(end_to,   end_to_addr);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2397
    __ movptr(r14_length, length);        // save a copy of the length
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2398
    assert(length == count, "");          // else fix next line:
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2399
    __ negptr(count);                     // negate and test the length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2400
    __ jcc(Assembler::notZero, L_load_element);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2401
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2402
    // Empty array:  Nothing to do.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2403
    __ xorptr(rax, rax);                  // return 0 on (trivial) success
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2404
    __ jmp(L_done);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2405
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2406
    // ======== begin loop ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2407
    // (Loop is rotated; its entry is L_load_element.)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2408
    // Loop control:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2409
    //   for (count = -count; count != 0; count++)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2410
    // Base pointers src, dst are biased by 8*(count-1),to last element.
5249
5cac34e6fe54 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 5050
diff changeset
  2411
    __ align(OptoLoopAlignment);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2412
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2413
    __ BIND(L_store_element);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2414
    __ store_heap_oop(to_element_addr, rax_oop);  // store the oop
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2415
    __ increment(count);               // increment the count toward zero
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2416
    __ jcc(Assembler::zero, L_do_card_marks);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2417
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2418
    // ======== loop entry is here ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2419
    __ BIND(L_load_element);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2420
    __ load_heap_oop(rax_oop, from_element_addr); // load the oop
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2421
    __ testptr(rax_oop, rax_oop);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2422
    __ jcc(Assembler::zero, L_store_element);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2423
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2424
    __ load_klass(r11_klass, rax_oop);// query the object klass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2425
    generate_type_check(r11_klass, ckoff, ckval, L_store_element);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2426
    // ======== end loop ========
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2427
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2428
    // It was a real error; we must depend on the caller to finish the job.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2429
    // Register rdx = -1 * number of *remaining* oops, r14 = *total* oops.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2430
    // Emit GC store barriers for the oops we have copied (r14 + rdx),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2431
    // and report their number to the caller.
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2432
    assert_different_registers(rax, r14_length, count, to, end_to, rcx, rscratch1);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2433
    Label L_post_barrier;
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2434
    __ addptr(r14_length, count);     // K = (original - remaining) oops
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2435
    __ movptr(rax, r14_length);       // save the value
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2436
    __ notptr(rax);                   // report (-1^K) to caller (does not affect flags)
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2437
    __ jccb(Assembler::notZero, L_post_barrier);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2438
    __ jmp(L_done); // K == 0, nothing was copied, skip post barrier
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2439
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2440
    // Come here on success only.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2441
    __ BIND(L_do_card_marks);
17622
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2442
    __ xorptr(rax, rax);              // return 0 on success
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2443
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2444
    __ BIND(L_post_barrier);
4037daf22a17 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 16624
diff changeset
  2445
    gen_write_ref_array_post_barrier(to, r14_length, rscratch1);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2446
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2447
    // Common exit point (success or failure).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2448
    __ BIND(L_done);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2449
    __ movptr(r13, Address(rsp, saved_r13_offset * wordSize));
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2450
    __ movptr(r14, Address(rsp, saved_r14_offset * wordSize));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2451
    restore_arg_regs();
11194
ee1235a09fc3 7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
never
parents: 11190
diff changeset
  2452
    inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr); // Update counter after rscratch1 is free
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2453
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2454
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2455
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2456
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2457
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2458
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2459
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2460
  //  Generate 'unsafe' array copy stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2461
  //  Though just as safe as the other stubs, it takes an unscaled
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2462
  //  size_t argument instead of an element count.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2463
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2464
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2465
  //    c_rarg0   - source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2466
  //    c_rarg1   - destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2467
  //    c_rarg2   - byte count, treated as ssize_t, can be zero
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2468
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2469
  // Examines the alignment of the operands and dispatches
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2470
  // to a long, int, short, or byte copy loop.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2471
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2472
  address generate_unsafe_copy(const char *name,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2473
                               address byte_copy_entry, address short_copy_entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2474
                               address int_copy_entry, address long_copy_entry) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2475
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2476
    Label L_long_aligned, L_int_aligned, L_short_aligned;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2477
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2478
    // Input registers (before setup_arg_regs)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2479
    const Register from        = c_rarg0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2480
    const Register to          = c_rarg1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2481
    const Register size        = c_rarg2;  // byte count (size_t)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2482
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2483
    // Register used as a temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2484
    const Register bits        = rax;      // test copy of low bits
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2485
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2486
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2487
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2488
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2489
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2490
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2491
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2492
    // bump this on entry, not on exit:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2493
    inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2494
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2495
    __ mov(bits, from);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2496
    __ orptr(bits, to);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2497
    __ orptr(bits, size);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2498
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2499
    __ testb(bits, BytesPerLong-1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2500
    __ jccb(Assembler::zero, L_long_aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2501
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2502
    __ testb(bits, BytesPerInt-1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2503
    __ jccb(Assembler::zero, L_int_aligned);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2504
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2505
    __ testb(bits, BytesPerShort-1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2506
    __ jump_cc(Assembler::notZero, RuntimeAddress(byte_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2507
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2508
    __ BIND(L_short_aligned);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2509
    __ shrptr(size, LogBytesPerShort); // size => short_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2510
    __ jump(RuntimeAddress(short_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2511
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2512
    __ BIND(L_int_aligned);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2513
    __ shrptr(size, LogBytesPerInt); // size => int_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2514
    __ jump(RuntimeAddress(int_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2515
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2516
    __ BIND(L_long_aligned);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2517
    __ shrptr(size, LogBytesPerLong); // size => qword_count
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2518
    __ jump(RuntimeAddress(long_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2519
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2520
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2521
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2522
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2523
  // Perform range checks on the proposed arraycopy.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2524
  // Kills temp, but nothing else.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2525
  // Also, clean the sign bits of src_pos and dst_pos.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2526
  void arraycopy_range_checks(Register src,     // source array oop (c_rarg0)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2527
                              Register src_pos, // source position (c_rarg1)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2528
                              Register dst,     // destination array oo (c_rarg2)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2529
                              Register dst_pos, // destination position (c_rarg3)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2530
                              Register length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2531
                              Register temp,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2532
                              Label& L_failed) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2533
    BLOCK_COMMENT("arraycopy_range_checks:");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2534
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2535
    //  if (src_pos + length > arrayOop(src)->length())  FAIL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2536
    __ movl(temp, length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2537
    __ addl(temp, src_pos);             // src_pos + length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2538
    __ cmpl(temp, Address(src, arrayOopDesc::length_offset_in_bytes()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2539
    __ jcc(Assembler::above, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2540
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2541
    //  if (dst_pos + length > arrayOop(dst)->length())  FAIL;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2542
    __ movl(temp, length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2543
    __ addl(temp, dst_pos);             // dst_pos + length
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2544
    __ cmpl(temp, Address(dst, arrayOopDesc::length_offset_in_bytes()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2545
    __ jcc(Assembler::above, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2546
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2547
    // Have to clean up high 32-bits of 'src_pos' and 'dst_pos'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2548
    // Move with sign extension can be used since they are positive.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2549
    __ movslq(src_pos, src_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2550
    __ movslq(dst_pos, dst_pos);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2551
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2552
    BLOCK_COMMENT("arraycopy_range_checks done");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2553
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2554
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2555
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2556
  //  Generate generic array copy stubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2557
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2558
  //  Input:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2559
  //    c_rarg0    -  src oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2560
  //    c_rarg1    -  src_pos (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2561
  //    c_rarg2    -  dst oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2562
  //    c_rarg3    -  dst_pos (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2563
  // not Win64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2564
  //    c_rarg4    -  element count (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2565
  // Win64
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2566
  //    rsp+40     -  element count (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2567
  //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2568
  //  Output:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2569
  //    rax ==  0  -  success
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2570
  //    rax == -1^K - failure, where K is partial transfer count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2571
  //
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2572
  address generate_generic_copy(const char *name,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2573
                                address byte_copy_entry, address short_copy_entry,
8876
f82367de21f5 7026307: DEBUG MESSAGE: broken null klass on amd64
iveresov
parents: 8874
diff changeset
  2574
                                address int_copy_entry, address oop_copy_entry,
f82367de21f5 7026307: DEBUG MESSAGE: broken null klass on amd64
iveresov
parents: 8874
diff changeset
  2575
                                address long_copy_entry, address checkcast_copy_entry) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2576
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2577
    Label L_failed, L_failed_0, L_objArray;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2578
    Label L_copy_bytes, L_copy_shorts, L_copy_ints, L_copy_longs;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2579
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2580
    // Input registers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2581
    const Register src        = c_rarg0;  // source array oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2582
    const Register src_pos    = c_rarg1;  // source position
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2583
    const Register dst        = c_rarg2;  // destination array oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2584
    const Register dst_pos    = c_rarg3;  // destination position
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2585
#ifndef _WIN64
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2586
    const Register length     = c_rarg4;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2587
#else
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2588
    const Address  length(rsp, 6 * wordSize);  // elements count is on stack on Win64
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2589
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2590
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2591
    { int modulus = CodeEntryAlignment;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2592
      int target  = modulus - 5; // 5 = sizeof jmp(L_failed)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2593
      int advance = target - (__ offset() % modulus);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2594
      if (advance < 0)  advance += modulus;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2595
      if (advance > 0)  __ nop(advance);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2596
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2597
    StubCodeMark mark(this, "StubRoutines", name);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2598
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2599
    // Short-hop target to L_failed.  Makes for denser prologue code.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2600
    __ BIND(L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2601
    __ jmp(L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2602
    assert(__ offset() % CodeEntryAlignment == 0, "no further alignment needed");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2603
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2604
    __ align(CodeEntryAlignment);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2605
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2606
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2607
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2608
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2609
    // bump this on entry, not on exit:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2610
    inc_counter_np(SharedRuntime::_generic_array_copy_ctr);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2611
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2612
    //-----------------------------------------------------------------------
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2613
    // Assembler stub will be used for this call to arraycopy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2614
    // if the following conditions are met:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2615
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2616
    // (1) src and dst must not be null.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2617
    // (2) src_pos must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2618
    // (3) dst_pos must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2619
    // (4) length  must not be negative.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2620
    // (5) src klass and dst klass should be the same and not NULL.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2621
    // (6) src and dst should be arrays.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2622
    // (7) src_pos + length must not exceed length of src.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2623
    // (8) dst_pos + length must not exceed length of dst.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2624
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2625
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2626
    //  if (src == NULL) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2627
    __ testptr(src, src);         // src oop
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2628
    size_t j1off = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2629
    __ jccb(Assembler::zero, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2630
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2631
    //  if (src_pos < 0) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2632
    __ testl(src_pos, src_pos); // src_pos (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2633
    __ jccb(Assembler::negative, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2634
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2635
    //  if (dst == NULL) return -1;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2636
    __ testptr(dst, dst);         // dst oop
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2637
    __ jccb(Assembler::zero, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2638
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2639
    //  if (dst_pos < 0) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2640
    __ testl(dst_pos, dst_pos); // dst_pos (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2641
    size_t j4off = __ offset();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2642
    __ jccb(Assembler::negative, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2643
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2644
    // The first four tests are very dense code,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2645
    // but not quite dense enough to put four
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2646
    // jumps in a 16-byte instruction fetch buffer.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2647
    // That's good, because some branch predicters
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2648
    // do not like jumps so close together.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2649
    // Make sure of this.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2650
    guarantee(((j1off ^ j4off) & ~15) != 0, "I$ line of 1st & 4th jumps");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2651
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2652
    // registers used as temp
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2653
    const Register r11_length    = r11; // elements count to copy
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2654
    const Register r10_src_klass = r10; // array klass
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2655
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2656
    //  if (length < 0) return -1;
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2657
    __ movl(r11_length, length);        // length (elements count, 32-bits value)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2658
    __ testl(r11_length, r11_length);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2659
    __ jccb(Assembler::negative, L_failed_0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2660
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2661
    __ load_klass(r10_src_klass, src);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2662
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2663
    //  assert(src->klass() != NULL);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2664
    {
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2665
      BLOCK_COMMENT("assert klasses not null {");
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2666
      Label L1, L2;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2667
      __ testptr(r10_src_klass, r10_src_klass);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2668
      __ jcc(Assembler::notZero, L2);   // it is broken if klass is NULL
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2669
      __ bind(L1);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2670
      __ stop("broken null klass");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2671
      __ bind(L2);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2672
      __ load_klass(rax, dst);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2673
      __ cmpq(rax, 0);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2674
      __ jcc(Assembler::equal, L1);     // this would be broken also
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2675
      BLOCK_COMMENT("} assert klasses not null done");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2676
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2677
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2678
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2679
    // Load layout helper (32-bits)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2680
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2681
    //  |array_tag|     | header_size | element_type |     |log2_element_size|
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2682
    // 32        30    24            16              8     2                 0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2683
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2684
    //   array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2685
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2686
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 11194
diff changeset
  2687
    const int lh_offset = in_bytes(Klass::layout_helper_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2688
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2689
    // Handle objArrays completely differently...
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2690
    const jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2691
    __ cmpl(Address(r10_src_klass, lh_offset), objArray_lh);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2692
    __ jcc(Assembler::equal, L_objArray);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2693
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2694
    //  if (src->klass() != dst->klass()) return -1;
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2695
    __ load_klass(rax, dst);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2696
    __ cmpq(r10_src_klass, rax);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2697
    __ jcc(Assembler::notEqual, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2698
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2699
    const Register rax_lh = rax;  // layout helper
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2700
    __ movl(rax_lh, Address(r10_src_klass, lh_offset));
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2701
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2702
    //  if (!src->is_Array()) return -1;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2703
    __ cmpl(rax_lh, Klass::_lh_neutral_value);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2704
    __ jcc(Assembler::greaterEqual, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2705
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2706
    // At this point, it is known to be a typeArray (array_tag 0x3).
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2707
#ifdef ASSERT
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2708
    {
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2709
      BLOCK_COMMENT("assert primitive array {");
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2710
      Label L;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2711
      __ cmpl(rax_lh, (Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2712
      __ jcc(Assembler::greaterEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2713
      __ stop("must be a primitive array");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2714
      __ bind(L);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2715
      BLOCK_COMMENT("} assert primitive array done");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2716
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2717
#endif
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2718
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2719
    arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2720
                           r10, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2721
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  2722
    // TypeArrayKlass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2723
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2724
    // src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2725
    // dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2726
    //
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2727
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2728
    const Register r10_offset = r10;    // array offset
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2729
    const Register rax_elsize = rax_lh; // element size
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2730
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2731
    __ movl(r10_offset, rax_lh);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2732
    __ shrl(r10_offset, Klass::_lh_header_size_shift);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2733
    __ andptr(r10_offset, Klass::_lh_header_size_mask);   // array_offset
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2734
    __ addptr(src, r10_offset);           // src array offset
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2735
    __ addptr(dst, r10_offset);           // dst array offset
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2736
    BLOCK_COMMENT("choose copy loop based on element size");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2737
    __ andl(rax_lh, Klass::_lh_log2_element_size_mask); // rax_lh -> rax_elsize
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2738
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2739
    // next registers should be set before the jump to corresponding stub
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2740
    const Register from     = c_rarg0;  // source array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2741
    const Register to       = c_rarg1;  // destination array address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2742
    const Register count    = c_rarg2;  // elements count
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2743
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2744
    // 'from', 'to', 'count' registers should be set in such order
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2745
    // since they are the same as 'src', 'src_pos', 'dst'.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2746
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2747
  __ BIND(L_copy_bytes);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2748
    __ cmpl(rax_elsize, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2749
    __ jccb(Assembler::notEqual, L_copy_shorts);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2750
    __ lea(from, Address(src, src_pos, Address::times_1, 0));// src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2751
    __ lea(to,   Address(dst, dst_pos, Address::times_1, 0));// dst_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2752
    __ movl2ptr(count, r11_length); // length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2753
    __ jump(RuntimeAddress(byte_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2754
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2755
  __ BIND(L_copy_shorts);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2756
    __ cmpl(rax_elsize, LogBytesPerShort);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2757
    __ jccb(Assembler::notEqual, L_copy_ints);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2758
    __ lea(from, Address(src, src_pos, Address::times_2, 0));// src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2759
    __ lea(to,   Address(dst, dst_pos, Address::times_2, 0));// dst_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2760
    __ movl2ptr(count, r11_length); // length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2761
    __ jump(RuntimeAddress(short_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2762
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2763
  __ BIND(L_copy_ints);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2764
    __ cmpl(rax_elsize, LogBytesPerInt);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2765
    __ jccb(Assembler::notEqual, L_copy_longs);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2766
    __ lea(from, Address(src, src_pos, Address::times_4, 0));// src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2767
    __ lea(to,   Address(dst, dst_pos, Address::times_4, 0));// dst_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2768
    __ movl2ptr(count, r11_length); // length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2769
    __ jump(RuntimeAddress(int_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2770
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2771
  __ BIND(L_copy_longs);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2772
#ifdef ASSERT
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2773
    {
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2774
      BLOCK_COMMENT("assert long copy {");
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2775
      Label L;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2776
      __ cmpl(rax_elsize, LogBytesPerLong);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2777
      __ jcc(Assembler::equal, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2778
      __ stop("must be long copy, but elsize is wrong");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2779
      __ bind(L);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2780
      BLOCK_COMMENT("} assert long copy done");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2781
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2782
#endif
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2783
    __ lea(from, Address(src, src_pos, Address::times_8, 0));// src_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2784
    __ lea(to,   Address(dst, dst_pos, Address::times_8, 0));// dst_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2785
    __ movl2ptr(count, r11_length); // length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2786
    __ jump(RuntimeAddress(long_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2787
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  2788
    // ObjArrayKlass
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2789
  __ BIND(L_objArray);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2790
    // live at this point:  r10_src_klass, r11_length, src[_pos], dst[_pos]
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2791
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2792
    Label L_plain_copy, L_checkcast_copy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2793
    //  test array classes for subtyping
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2794
    __ load_klass(rax, dst);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2795
    __ cmpq(r10_src_klass, rax); // usual case is exact equality
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2796
    __ jcc(Assembler::notEqual, L_checkcast_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2797
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2798
    // Identically typed arrays can be copied without element-wise checks.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2799
    arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2800
                           r10, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2801
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2802
    __ lea(from, Address(src, src_pos, TIMES_OOP,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2803
                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2804
    __ lea(to,   Address(dst, dst_pos, TIMES_OOP,
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2805
                 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2806
    __ movl2ptr(count, r11_length); // length
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2807
  __ BIND(L_plain_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2808
    __ jump(RuntimeAddress(oop_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2809
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2810
  __ BIND(L_checkcast_copy);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2811
    // live at this point:  r10_src_klass, r11_length, rax (dst_klass)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2812
    {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2813
      // Before looking at dst.length, make sure dst is also an objArray.
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2814
      __ cmpl(Address(rax, lh_offset), objArray_lh);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2815
      __ jcc(Assembler::notEqual, L_failed);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2816
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2817
      // It is safe to examine both src.length and dst.length.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2818
      arraycopy_range_checks(src, src_pos, dst, dst_pos, r11_length,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2819
                             rax, L_failed);
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2820
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2821
      const Register r11_dst_klass = r11;
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2822
      __ load_klass(r11_dst_klass, dst); // reload
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2823
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2824
      // Marshal the base address arguments now, freeing registers.
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2825
      __ lea(from, Address(src, src_pos, TIMES_OOP,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2826
                   arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2827
      __ lea(to,   Address(dst, dst_pos, TIMES_OOP,
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2828
                   arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2829
      __ movl(count, length);           // length (reloaded)
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2830
      Register sco_temp = c_rarg3;      // this register is free now
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2831
      assert_different_registers(from, to, count, sco_temp,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2832
                                 r11_dst_klass, r10_src_klass);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2833
      assert_clean_int(count, sco_temp);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2834
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2835
      // Generate the type check.
11430
718fc06da49a 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 11194
diff changeset
  2836
      const int sco_offset = in_bytes(Klass::super_check_offset_offset());
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2837
      __ movl(sco_temp, Address(r11_dst_klass, sco_offset));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2838
      assert_clean_int(sco_temp, rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2839
      generate_type_check(r10_src_klass, sco_temp, r11_dst_klass, L_plain_copy);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2840
13952
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  2841
      // Fetch destination element klass from the ObjArrayKlass header.
e3cf184080bc 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 13728
diff changeset
  2842
      int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2843
      __ movptr(r11_dst_klass, Address(r11_dst_klass, ek_offset));
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2844
      __ movl(  sco_temp,      Address(r11_dst_klass, sco_offset));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2845
      assert_clean_int(sco_temp, rax);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2846
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2847
      // the checkcast_copy loop needs two extra arguments:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2848
      assert(c_rarg3 == sco_temp, "#3 already in place");
7431
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2849
      // Set up arguments for checkcast_copy_entry.
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2850
      setup_arg_regs(4);
e9f07f8aef47 6998985: faulty generic arraycopy on windows x86_64: 4th arg overwritten with oop
twisti
parents: 7397
diff changeset
  2851
      __ movptr(r8, r11_dst_klass);  // dst.klass.element_klass, r8 is c_rarg4 on Linux/Solaris
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2852
      __ jump(RuntimeAddress(checkcast_copy_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2853
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2854
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2855
  __ BIND(L_failed);
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2856
    __ xorptr(rax, rax);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  2857
    __ notptr(rax); // return -1
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2858
    __ leave();   // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2859
    __ ret(0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2860
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2861
    return start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2862
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2863
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2864
  void generate_arraycopy_stubs() {
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2865
    address entry;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2866
    address entry_jbyte_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2867
    address entry_jshort_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2868
    address entry_jint_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2869
    address entry_oop_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2870
    address entry_jlong_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2871
    address entry_checkcast_arraycopy;
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2872
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2873
    StubRoutines::_jbyte_disjoint_arraycopy  = generate_disjoint_byte_copy(false, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2874
                                                                           "jbyte_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2875
    StubRoutines::_jbyte_arraycopy           = generate_conjoint_byte_copy(false, entry, &entry_jbyte_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2876
                                                                           "jbyte_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2877
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2878
    StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2879
                                                                            "jshort_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2880
    StubRoutines::_jshort_arraycopy          = generate_conjoint_short_copy(false, entry, &entry_jshort_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2881
                                                                            "jshort_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2882
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2883
    StubRoutines::_jint_disjoint_arraycopy   = generate_disjoint_int_oop_copy(false, false, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2884
                                                                              "jint_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2885
    StubRoutines::_jint_arraycopy            = generate_conjoint_int_oop_copy(false, false, entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2886
                                                                              &entry_jint_arraycopy, "jint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2887
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2888
    StubRoutines::_jlong_disjoint_arraycopy  = generate_disjoint_long_oop_copy(false, false, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2889
                                                                               "jlong_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2890
    StubRoutines::_jlong_arraycopy           = generate_conjoint_long_oop_copy(false, false, entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2891
                                                                               &entry_jlong_arraycopy, "jlong_arraycopy");
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2892
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2893
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2894
    if (UseCompressedOops) {
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2895
      StubRoutines::_oop_disjoint_arraycopy  = generate_disjoint_int_oop_copy(false, true, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2896
                                                                              "oop_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2897
      StubRoutines::_oop_arraycopy           = generate_conjoint_int_oop_copy(false, true, entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2898
                                                                              &entry_oop_arraycopy, "oop_arraycopy");
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2899
      StubRoutines::_oop_disjoint_arraycopy_uninit  = generate_disjoint_int_oop_copy(false, true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2900
                                                                                     "oop_disjoint_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2901
                                                                                     /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2902
      StubRoutines::_oop_arraycopy_uninit           = generate_conjoint_int_oop_copy(false, true, entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2903
                                                                                     NULL, "oop_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2904
                                                                                     /*dest_uninitialized*/true);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2905
    } else {
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2906
      StubRoutines::_oop_disjoint_arraycopy  = generate_disjoint_long_oop_copy(false, true, &entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2907
                                                                               "oop_disjoint_arraycopy");
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2908
      StubRoutines::_oop_arraycopy           = generate_conjoint_long_oop_copy(false, true, entry,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2909
                                                                               &entry_oop_arraycopy, "oop_arraycopy");
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2910
      StubRoutines::_oop_disjoint_arraycopy_uninit  = generate_disjoint_long_oop_copy(false, true, &entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2911
                                                                                      "oop_disjoint_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2912
                                                                                      /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2913
      StubRoutines::_oop_arraycopy_uninit           = generate_conjoint_long_oop_copy(false, true, entry,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2914
                                                                                      NULL, "oop_arraycopy_uninit",
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2915
                                                                                      /*dest_uninitialized*/true);
360
21d113ecbf6a 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 189
diff changeset
  2916
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2917
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2918
    StubRoutines::_checkcast_arraycopy        = generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2919
    StubRoutines::_checkcast_arraycopy_uninit = generate_checkcast_copy("checkcast_arraycopy_uninit", NULL,
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2920
                                                                        /*dest_uninitialized*/true);
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2921
8487
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2922
    StubRoutines::_unsafe_arraycopy    = generate_unsafe_copy("unsafe_arraycopy",
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2923
                                                              entry_jbyte_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2924
                                                              entry_jshort_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2925
                                                              entry_jint_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2926
                                                              entry_jlong_arraycopy);
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2927
    StubRoutines::_generic_arraycopy   = generate_generic_copy("generic_arraycopy",
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2928
                                                               entry_jbyte_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2929
                                                               entry_jshort_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2930
                                                               entry_jint_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2931
                                                               entry_oop_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2932
                                                               entry_jlong_arraycopy,
bf96596f06d2 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 7431
diff changeset
  2933
                                                               entry_checkcast_arraycopy);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2934
6433
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2935
    StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2936
    StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2937
    StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2938
    StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2939
    StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2940
    StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill");
b0e4fafdc38b 4809552: Optimize Arrays.fill(...)
never
parents: 5706
diff changeset
  2941
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2942
    // We don't generate specialized code for HeapWord-aligned source
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2943
    // arrays, so just use the code we've already generated
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2944
    StubRoutines::_arrayof_jbyte_disjoint_arraycopy  = StubRoutines::_jbyte_disjoint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2945
    StubRoutines::_arrayof_jbyte_arraycopy           = StubRoutines::_jbyte_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2946
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2947
    StubRoutines::_arrayof_jshort_disjoint_arraycopy = StubRoutines::_jshort_disjoint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2948
    StubRoutines::_arrayof_jshort_arraycopy          = StubRoutines::_jshort_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2949
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2950
    StubRoutines::_arrayof_jint_disjoint_arraycopy   = StubRoutines::_jint_disjoint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2951
    StubRoutines::_arrayof_jint_arraycopy            = StubRoutines::_jint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2952
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2953
    StubRoutines::_arrayof_jlong_disjoint_arraycopy  = StubRoutines::_jlong_disjoint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2954
    StubRoutines::_arrayof_jlong_arraycopy           = StubRoutines::_jlong_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2955
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2956
    StubRoutines::_arrayof_oop_disjoint_arraycopy    = StubRoutines::_oop_disjoint_arraycopy;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2957
    StubRoutines::_arrayof_oop_arraycopy             = StubRoutines::_oop_arraycopy;
8498
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2958
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2959
    StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit    = StubRoutines::_oop_disjoint_arraycopy_uninit;
6398004126b9 6627983: G1: Bad oop deference during marking
iveresov
parents: 8487
diff changeset
  2960
    StubRoutines::_arrayof_oop_arraycopy_uninit             = StubRoutines::_oop_arraycopy_uninit;
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2961
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  2962
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2963
  // AES intrinsic stubs
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2964
  enum {AESBlockSize = 16};
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2965
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2966
  address generate_key_shuffle_mask() {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2967
    __ align(16);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2968
    StubCodeMark mark(this, "StubRoutines", "key_shuffle_mask");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2969
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2970
    __ emit_data64( 0x0405060700010203, relocInfo::none );
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2971
    __ emit_data64( 0x0c0d0e0f08090a0b, relocInfo::none );
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2972
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2973
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2974
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2975
  address generate_counter_shuffle_mask() {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2976
    __ align(16);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2977
    StubCodeMark mark(this, "StubRoutines", "counter_shuffle_mask");
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2978
    address start = __ pc();
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2979
    __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2980
    __ emit_data64(0x0001020304050607, relocInfo::none);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2981
    return start;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2982
  }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2983
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2984
  // Utility routine for loading a 128-bit key word in little endian format
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2985
  // can optionally specify that the shuffle mask is already in an xmmregister
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2986
  void load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2987
    __ movdqu(xmmdst, Address(key, offset));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2988
    if (xmm_shuf_mask != NULL) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2989
      __ pshufb(xmmdst, xmm_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2990
    } else {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2991
      __ pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2992
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2993
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  2994
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2995
  // Utility routine for increase 128bit counter (iv in CTR mode)
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2996
  void inc_counter(Register reg, XMMRegister xmmdst, int inc_delta, Label& next_block) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2997
    __ pextrq(reg, xmmdst, 0x0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2998
    __ addq(reg, inc_delta);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  2999
    __ pinsrq(xmmdst, reg, 0x0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3000
    __ jcc(Assembler::carryClear, next_block); // jump if no carry
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3001
    __ pextrq(reg, xmmdst, 0x01); // Carry
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3002
    __ addq(reg, 0x01);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3003
    __ pinsrq(xmmdst, reg, 0x01); //Carry end
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3004
    __ BIND(next_block);          // next instruction
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3005
  }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3006
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3007
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3008
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3009
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3010
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3011
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3012
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3013
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3014
  address generate_aescrypt_encryptBlock() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3015
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3016
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3017
    StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3018
    Label L_doLast;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3019
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3020
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3021
    const Register from        = c_rarg0;  // source array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3022
    const Register to          = c_rarg1;  // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3023
    const Register key         = c_rarg2;  // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3024
    const Register keylen      = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3025
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3026
    const XMMRegister xmm_result = xmm0;
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3027
    const XMMRegister xmm_key_shuf_mask = xmm1;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3028
    // On win64 xmm6-xmm15 must be preserved so don't use them.
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3029
    const XMMRegister xmm_temp1  = xmm2;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3030
    const XMMRegister xmm_temp2  = xmm3;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3031
    const XMMRegister xmm_temp3  = xmm4;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3032
    const XMMRegister xmm_temp4  = xmm5;
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3033
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3034
    __ enter(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3035
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3036
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3037
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3038
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3039
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3040
      __ movl(rax, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3041
      __ kmovql(k1, rax);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3042
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3043
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3044
    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3045
    __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3046
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3047
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3048
    __ movdqu(xmm_result, Address(from, 0));  // get 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3049
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3050
    // For encryption, the java expanded key ordering is just what we need
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3051
    // we don't know if the key is aligned, hence not using load-execute form
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3052
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3053
    load_key(xmm_temp1, key, 0x00, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3054
    __ pxor(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3055
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3056
    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3057
    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3058
    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3059
    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3060
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3061
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3062
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3063
    __ aesenc(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3064
    __ aesenc(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3065
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3066
    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3067
    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3068
    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3069
    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3070
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3071
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3072
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3073
    __ aesenc(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3074
    __ aesenc(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3075
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3076
    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3077
    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3078
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3079
    __ cmpl(keylen, 44);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3080
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3081
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3082
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3083
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3084
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3085
    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3086
    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3087
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3088
    __ cmpl(keylen, 52);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3089
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3090
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3091
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3092
    __ aesenc(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3093
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3094
    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3095
    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3096
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3097
    __ BIND(L_doLast);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3098
    __ aesenc(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3099
    __ aesenclast(xmm_result, xmm_temp2);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3100
    __ movdqu(Address(to, 0), xmm_result);        // store the result
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3101
    __ xorptr(rax, rax); // return 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3102
    __ leave(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3103
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3104
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3105
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3106
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3107
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3108
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3109
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3110
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3111
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3112
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3113
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3114
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3115
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3116
  address generate_aescrypt_decryptBlock() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3117
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3118
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3119
    StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3120
    Label L_doLast;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3121
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3122
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3123
    const Register from        = c_rarg0;  // source array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3124
    const Register to          = c_rarg1;  // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3125
    const Register key         = c_rarg2;  // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3126
    const Register keylen      = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3127
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3128
    const XMMRegister xmm_result = xmm0;
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3129
    const XMMRegister xmm_key_shuf_mask = xmm1;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3130
    // On win64 xmm6-xmm15 must be preserved so don't use them.
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3131
    const XMMRegister xmm_temp1  = xmm2;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3132
    const XMMRegister xmm_temp2  = xmm3;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3133
    const XMMRegister xmm_temp3  = xmm4;
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3134
    const XMMRegister xmm_temp4  = xmm5;
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3135
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3136
    __ enter(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3137
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3138
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3139
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3140
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3141
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3142
      __ movl(rax, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3143
      __ kmovql(k1, rax);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3144
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3145
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3146
    // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3147
    __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3148
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3149
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3150
    __ movdqu(xmm_result, Address(from, 0));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3151
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3152
    // for decryption java expanded key ordering is rotated one position from what we want
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3153
    // so we start from 0x10 here and hit 0x00 last
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3154
    // we don't know if the key is aligned, hence not using load-execute form
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3155
    load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3156
    load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3157
    load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3158
    load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3159
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3160
    __ pxor  (xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3161
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3162
    __ aesdec(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3163
    __ aesdec(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3164
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3165
    load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3166
    load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3167
    load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3168
    load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3169
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3170
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3171
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3172
    __ aesdec(xmm_result, xmm_temp3);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3173
    __ aesdec(xmm_result, xmm_temp4);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3174
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3175
    load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3176
    load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3177
    load_key(xmm_temp3, key, 0x00, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3178
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3179
    __ cmpl(keylen, 44);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3180
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3181
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3182
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3183
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3184
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3185
    load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3186
    load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3187
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3188
    __ cmpl(keylen, 52);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3189
    __ jccb(Assembler::equal, L_doLast);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3190
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3191
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3192
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3193
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3194
    load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3195
    load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3196
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3197
    __ BIND(L_doLast);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3198
    __ aesdec(xmm_result, xmm_temp1);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3199
    __ aesdec(xmm_result, xmm_temp2);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3200
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3201
    // for decryption the aesdeclast operation is always on key+0x00
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3202
    __ aesdeclast(xmm_result, xmm_temp3);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3203
    __ movdqu(Address(to, 0), xmm_result);  // store the result
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3204
    __ xorptr(rax, rax); // return 0
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3205
    __ leave(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3206
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3207
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3208
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3209
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3210
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3211
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3212
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3213
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3214
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3215
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3216
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3217
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3218
  //   c_rarg3   - r vector byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3219
  //   c_rarg4   - input length
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3220
  //
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3221
  // Output:
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3222
  //   rax       - input length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3223
  //
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3224
  address generate_cipherBlockChaining_encryptAESCrypt() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3225
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3226
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3227
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3228
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3229
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3230
    Label L_exit, L_key_192_256, L_key_256, L_loopTop_128, L_loopTop_192, L_loopTop_256;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3231
    const Register from        = c_rarg0;  // source array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3232
    const Register to          = c_rarg1;  // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3233
    const Register key         = c_rarg2;  // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3234
    const Register rvec        = c_rarg3;  // r byte array initialized from initvector array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3235
                                           // and left with the results of the last encryption block
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3236
#ifndef _WIN64
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3237
    const Register len_reg     = c_rarg4;  // src len (must be multiple of blocksize 16)
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3238
#else
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3239
    const Address  len_mem(rbp, 6 * wordSize);  // length is on stack on Win64
43423
bcaab17f72a5 8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents: 42618
diff changeset
  3240
    const Register len_reg     = r11;      // pick the volatile windows register
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3241
#endif
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3242
    const Register pos         = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3243
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3244
    // xmm register assignments for the loops below
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3245
    const XMMRegister xmm_result = xmm0;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3246
    const XMMRegister xmm_temp   = xmm1;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3247
    // keys 0-10 preloaded into xmm2-xmm12
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3248
    const int XMM_REG_NUM_KEY_FIRST = 2;
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3249
    const int XMM_REG_NUM_KEY_LAST  = 15;
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3250
    const XMMRegister xmm_key0   = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3251
    const XMMRegister xmm_key10  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+10);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3252
    const XMMRegister xmm_key11  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+11);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3253
    const XMMRegister xmm_key12  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+12);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3254
    const XMMRegister xmm_key13  = as_XMMRegister(XMM_REG_NUM_KEY_FIRST+13);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3255
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3256
    __ enter(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3257
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3258
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3259
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3260
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3261
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3262
      __ movl(rax, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3263
      __ kmovql(k1, rax);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3264
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3265
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3266
#ifdef _WIN64
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3267
    // on win64, fill len_reg from stack position
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3268
    __ movl(len_reg, len_mem);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3269
#else
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3270
    __ push(len_reg); // Save
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3271
#endif
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3272
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3273
    const XMMRegister xmm_key_shuf_mask = xmm_temp;  // used temporarily to swap key bytes up front
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3274
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3275
    // load up xmm regs xmm2 thru xmm12 with key 0x00 - 0xa0
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3276
    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x00; rnum <= XMM_REG_NUM_KEY_FIRST+10; rnum++) {
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3277
      load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3278
      offset += 0x10;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3279
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3280
    __ movdqu(xmm_result, Address(rvec, 0x00));   // initialize xmm_result with r vec
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3281
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3282
    // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3283
    __ movl(rax, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3284
    __ cmpl(rax, 44);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3285
    __ jcc(Assembler::notEqual, L_key_192_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3286
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3287
    // 128 bit code follows here
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3288
    __ movptr(pos, 0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3289
    __ align(OptoLoopAlignment);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3290
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3291
    __ BIND(L_loopTop_128);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3292
    __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3293
    __ pxor  (xmm_result, xmm_temp);               // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3294
    __ pxor  (xmm_result, xmm_key0);               // do the aes rounds
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3295
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_FIRST + 9; rnum++) {
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3296
      __ aesenc(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3297
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3298
    __ aesenclast(xmm_result, xmm_key10);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3299
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3300
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3301
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3302
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3303
    __ jcc(Assembler::notEqual, L_loopTop_128);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3304
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3305
    __ BIND(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3306
    __ movdqu(Address(rvec, 0), xmm_result);     // final value of r stored in rvec of CipherBlockChaining object
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3307
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3308
#ifdef _WIN64
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3309
    __ movl(rax, len_mem);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3310
#else
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3311
    __ pop(rax); // return length
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3312
#endif
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3313
    __ leave(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3314
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3315
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3316
    __ BIND(L_key_192_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3317
    // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3318
    load_key(xmm_key11, key, 0xb0, xmm_key_shuf_mask);
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3319
    load_key(xmm_key12, key, 0xc0, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3320
    __ cmpl(rax, 52);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3321
    __ jcc(Assembler::notEqual, L_key_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3322
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3323
    // 192-bit code follows here (could be changed to use more xmm registers)
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3324
    __ movptr(pos, 0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3325
    __ align(OptoLoopAlignment);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3326
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3327
    __ BIND(L_loopTop_192);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3328
    __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3329
    __ pxor  (xmm_result, xmm_temp);               // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3330
    __ pxor  (xmm_result, xmm_key0);               // do the aes rounds
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3331
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_FIRST + 11; rnum++) {
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3332
      __ aesenc(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3333
    }
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3334
    __ aesenclast(xmm_result, xmm_key12);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3335
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3336
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3337
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3338
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3339
    __ jcc(Assembler::notEqual, L_loopTop_192);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3340
    __ jmp(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3341
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3342
    __ BIND(L_key_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3343
    // 256-bit code follows here (could be changed to use more xmm registers)
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3344
    load_key(xmm_key13, key, 0xd0, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3345
    __ movptr(pos, 0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3346
    __ align(OptoLoopAlignment);
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3347
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3348
    __ BIND(L_loopTop_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3349
    __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0));   // get next 16 bytes of input
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3350
    __ pxor  (xmm_result, xmm_temp);               // xor with the current r vector
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3351
    __ pxor  (xmm_result, xmm_key0);               // do the aes rounds
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3352
    for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum  <= XMM_REG_NUM_KEY_FIRST + 13; rnum++) {
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3353
      __ aesenc(xmm_result, as_XMMRegister(rnum));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3354
    }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3355
    load_key(xmm_temp, key, 0xe0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3356
    __ aesenclast(xmm_result, xmm_temp);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3357
    __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result);     // store into the next 16 bytes of output
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3358
    // no need to store r to memory until we exit
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3359
    __ addptr(pos, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3360
    __ subptr(len_reg, AESBlockSize);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3361
    __ jcc(Assembler::notEqual, L_loopTop_256);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3362
    __ jmp(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3363
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3364
    return start;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3365
  }
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3366
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3367
  // Safefetch stubs.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3368
  void generate_safefetch(const char* name, int size, address* entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3369
                          address* fault_pc, address* continuation_pc) {
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3370
    // safefetch signatures:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3371
    //   int      SafeFetch32(int*      adr, int      errValue);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3372
    //   intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3373
    //
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3374
    // arguments:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3375
    //   c_rarg0 = adr
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3376
    //   c_rarg1 = errValue
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3377
    //
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3378
    // result:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3379
    //   PPC_RET  = *adr or errValue
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3380
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3381
    StubCodeMark mark(this, "StubRoutines", name);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3382
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3383
    // Entry point, pc or function descriptor.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3384
    *entry = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3385
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3386
    // Load *adr into c_rarg1, may fault.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3387
    *fault_pc = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3388
    switch (size) {
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3389
      case 4:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3390
        // int32_t
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3391
        __ movl(c_rarg1, Address(c_rarg0, 0));
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3392
        break;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3393
      case 8:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3394
        // int64_t
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3395
        __ movq(c_rarg1, Address(c_rarg0, 0));
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3396
        break;
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3397
      default:
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3398
        ShouldNotReachHere();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3399
    }
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3400
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3401
    // return errValue or *adr
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3402
    *continuation_pc = __ pc();
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3403
    __ movq(rax, c_rarg1);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3404
    __ ret(0);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  3405
  }
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3406
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3407
  // This is a version of CBC/AES Decrypt which does 4 blocks in a loop at a time
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3408
  // to hide instruction latency
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3409
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3410
  // Arguments:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3411
  //
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3412
  // Inputs:
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3413
  //   c_rarg0   - source byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3414
  //   c_rarg1   - destination byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3415
  //   c_rarg2   - K (key) in little endian int array
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3416
  //   c_rarg3   - r vector byte array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3417
  //   c_rarg4   - input length
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3418
  //
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3419
  // Output:
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3420
  //   rax       - input length
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3421
  //
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3422
  address generate_cipherBlockChaining_decryptAESCrypt_Parallel() {
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3423
    assert(UseAES, "need AES instructions and misaligned SSE support");
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3424
    __ align(CodeEntryAlignment);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3425
    StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3426
    address start = __ pc();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3427
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3428
    const Register from        = c_rarg0;  // source array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3429
    const Register to          = c_rarg1;  // destination array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3430
    const Register key         = c_rarg2;  // key array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3431
    const Register rvec        = c_rarg3;  // r byte array initialized from initvector array address
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3432
                                           // and left with the results of the last encryption block
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3433
#ifndef _WIN64
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3434
    const Register len_reg     = c_rarg4;  // src len (must be multiple of blocksize 16)
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3435
#else
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3436
    const Address  len_mem(rbp, 6 * wordSize);  // length is on stack on Win64
43423
bcaab17f72a5 8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents: 42618
diff changeset
  3437
    const Register len_reg     = r11;      // pick the volatile windows register
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3438
#endif
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3439
    const Register pos         = rax;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3440
36825
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3441
    const int PARALLEL_FACTOR = 4;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3442
    const int ROUNDS[3] = { 10, 12, 14 }; // aes rounds for key128, key192, key256
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3443
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3444
    Label L_exit;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3445
    Label L_singleBlock_loopTopHead[3]; // 128, 192, 256
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3446
    Label L_singleBlock_loopTopHead2[3]; // 128, 192, 256
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3447
    Label L_singleBlock_loopTop[3]; // 128, 192, 256
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3448
    Label L_multiBlock_loopTopHead[3]; // 128, 192, 256
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3449
    Label L_multiBlock_loopTop[3]; // 128, 192, 256
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3450
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3451
    // keys 0-10 preloaded into xmm5-xmm15
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3452
    const int XMM_REG_NUM_KEY_FIRST = 5;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3453
    const int XMM_REG_NUM_KEY_LAST  = 15;
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3454
    const XMMRegister xmm_key_first = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3455
    const XMMRegister xmm_key_last  = as_XMMRegister(XMM_REG_NUM_KEY_LAST);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3456
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3457
    __ enter(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3458
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3459
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3460
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3461
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3462
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3463
      __ movl(rax, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3464
      __ kmovql(k1, rax);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3465
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  3466
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3467
#ifdef _WIN64
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3468
    // on win64, fill len_reg from stack position
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3469
    __ movl(len_reg, len_mem);
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3470
#else
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3471
    __ push(len_reg); // Save
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3472
#endif
36825
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3473
    __ push(rbx);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3474
    // the java expanded key ordering is rotated one position from what we want
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3475
    // so we start from 0x10 here and hit 0x00 last
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3476
    const XMMRegister xmm_key_shuf_mask = xmm1;  // used temporarily to swap key bytes up front
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3477
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3478
    // load up xmm regs 5 thru 15 with key 0x10 - 0xa0 - 0x00
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3479
    for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x10; rnum < XMM_REG_NUM_KEY_LAST; rnum++) {
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3480
      load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3481
      offset += 0x10;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3482
    }
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3483
    load_key(xmm_key_last, key, 0x00, xmm_key_shuf_mask);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3484
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3485
    const XMMRegister xmm_prev_block_cipher = xmm1;  // holds cipher of previous block
14834
f29c91f2f22b 8004835: Improve AES intrinsics on x86
kvn
parents: 14633
diff changeset
  3486
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3487
    // registers holding the four results in the parallelized loop
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3488
    const XMMRegister xmm_result0 = xmm0;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3489
    const XMMRegister xmm_result1 = xmm2;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3490
    const XMMRegister xmm_result2 = xmm3;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3491
    const XMMRegister xmm_result3 = xmm4;
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3492
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3493
    __ movdqu(xmm_prev_block_cipher, Address(rvec, 0x00));   // initialize with initial rvec
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3494
36825
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3495
    __ xorptr(pos, pos);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3496
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3497
    // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
36825
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3498
    __ movl(rbx, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3499
    __ cmpl(rbx, 52);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3500
    __ jcc(Assembler::equal, L_multiBlock_loopTopHead[1]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3501
    __ cmpl(rbx, 60);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3502
    __ jcc(Assembler::equal, L_multiBlock_loopTopHead[2]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3503
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3504
#define DoFour(opc, src_reg)           \
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3505
  __ opc(xmm_result0, src_reg);         \
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3506
  __ opc(xmm_result1, src_reg);         \
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3507
  __ opc(xmm_result2, src_reg);         \
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3508
  __ opc(xmm_result3, src_reg);         \
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3509
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3510
    for (int k = 0; k < 3; ++k) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3511
      __ BIND(L_multiBlock_loopTopHead[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3512
      if (k != 0) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3513
        __ cmpptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // see if at least 4 blocks left
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3514
        __ jcc(Assembler::less, L_singleBlock_loopTopHead2[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3515
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3516
      if (k == 1) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3517
        __ subptr(rsp, 6 * wordSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3518
        __ movdqu(Address(rsp, 0), xmm15); //save last_key from xmm15
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3519
        load_key(xmm15, key, 0xb0); // 0xb0; 192-bit key goes up to 0xc0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3520
        __ movdqu(Address(rsp, 2 * wordSize), xmm15);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3521
        load_key(xmm1, key, 0xc0);  // 0xc0;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3522
        __ movdqu(Address(rsp, 4 * wordSize), xmm1);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3523
      } else if (k == 2) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3524
        __ subptr(rsp, 10 * wordSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3525
        __ movdqu(Address(rsp, 0), xmm15); //save last_key from xmm15
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3526
        load_key(xmm15, key, 0xd0); // 0xd0; 256-bit key goes upto 0xe0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3527
        __ movdqu(Address(rsp, 6 * wordSize), xmm15);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3528
        load_key(xmm1, key, 0xe0);  // 0xe0;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3529
        __ movdqu(Address(rsp, 8 * wordSize), xmm1);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3530
        load_key(xmm15, key, 0xb0); // 0xb0;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3531
        __ movdqu(Address(rsp, 2 * wordSize), xmm15);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3532
        load_key(xmm1, key, 0xc0);  // 0xc0;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3533
        __ movdqu(Address(rsp, 4 * wordSize), xmm1);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3534
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3535
      __ align(OptoLoopAlignment);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3536
      __ BIND(L_multiBlock_loopTop[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3537
      __ cmpptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // see if at least 4 blocks left
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3538
      __ jcc(Assembler::less, L_singleBlock_loopTopHead[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3539
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3540
      if  (k != 0) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3541
        __ movdqu(xmm15, Address(rsp, 2 * wordSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3542
        __ movdqu(xmm1, Address(rsp, 4 * wordSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3543
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3544
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3545
      __ movdqu(xmm_result0, Address(from, pos, Address::times_1, 0 * AESBlockSize)); // get next 4 blocks into xmmresult registers
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3546
      __ movdqu(xmm_result1, Address(from, pos, Address::times_1, 1 * AESBlockSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3547
      __ movdqu(xmm_result2, Address(from, pos, Address::times_1, 2 * AESBlockSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3548
      __ movdqu(xmm_result3, Address(from, pos, Address::times_1, 3 * AESBlockSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3549
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3550
      DoFour(pxor, xmm_key_first);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3551
      if (k == 0) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3552
        for (int rnum = 1; rnum < ROUNDS[k]; rnum++) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3553
          DoFour(aesdec, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3554
        }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3555
        DoFour(aesdeclast, xmm_key_last);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3556
      } else if (k == 1) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3557
        for (int rnum = 1; rnum <= ROUNDS[k]-2; rnum++) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3558
          DoFour(aesdec, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3559
        }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3560
        __ movdqu(xmm_key_last, Address(rsp, 0)); // xmm15 needs to be loaded again.
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3561
        DoFour(aesdec, xmm1);  // key : 0xc0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3562
        __ movdqu(xmm_prev_block_cipher, Address(rvec, 0x00));  // xmm1 needs to be loaded again
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3563
        DoFour(aesdeclast, xmm_key_last);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3564
      } else if (k == 2) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3565
        for (int rnum = 1; rnum <= ROUNDS[k] - 4; rnum++) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3566
          DoFour(aesdec, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3567
        }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3568
        DoFour(aesdec, xmm1);  // key : 0xc0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3569
        __ movdqu(xmm15, Address(rsp, 6 * wordSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3570
        __ movdqu(xmm1, Address(rsp, 8 * wordSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3571
        DoFour(aesdec, xmm15);  // key : 0xd0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3572
        __ movdqu(xmm_key_last, Address(rsp, 0)); // xmm15 needs to be loaded again.
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3573
        DoFour(aesdec, xmm1);  // key : 0xe0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3574
        __ movdqu(xmm_prev_block_cipher, Address(rvec, 0x00));  // xmm1 needs to be loaded again
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3575
        DoFour(aesdeclast, xmm_key_last);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3576
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3577
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3578
      // for each result, xor with the r vector of previous cipher block
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3579
      __ pxor(xmm_result0, xmm_prev_block_cipher);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3580
      __ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 0 * AESBlockSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3581
      __ pxor(xmm_result1, xmm_prev_block_cipher);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3582
      __ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 1 * AESBlockSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3583
      __ pxor(xmm_result2, xmm_prev_block_cipher);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3584
      __ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 2 * AESBlockSize));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3585
      __ pxor(xmm_result3, xmm_prev_block_cipher);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3586
      __ movdqu(xmm_prev_block_cipher, Address(from, pos, Address::times_1, 3 * AESBlockSize));   // this will carry over to next set of blocks
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3587
      if (k != 0) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3588
        __ movdqu(Address(rvec, 0x00), xmm_prev_block_cipher);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3589
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3590
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3591
      __ movdqu(Address(to, pos, Address::times_1, 0 * AESBlockSize), xmm_result0);     // store 4 results into the next 64 bytes of output
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3592
      __ movdqu(Address(to, pos, Address::times_1, 1 * AESBlockSize), xmm_result1);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3593
      __ movdqu(Address(to, pos, Address::times_1, 2 * AESBlockSize), xmm_result2);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3594
      __ movdqu(Address(to, pos, Address::times_1, 3 * AESBlockSize), xmm_result3);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3595
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3596
      __ addptr(pos, PARALLEL_FACTOR * AESBlockSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3597
      __ subptr(len_reg, PARALLEL_FACTOR * AESBlockSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3598
      __ jmp(L_multiBlock_loopTop[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3599
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3600
      // registers used in the non-parallelized loops
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3601
      // xmm register assignments for the loops below
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3602
      const XMMRegister xmm_result = xmm0;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3603
      const XMMRegister xmm_prev_block_cipher_save = xmm2;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3604
      const XMMRegister xmm_key11 = xmm3;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3605
      const XMMRegister xmm_key12 = xmm4;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3606
      const XMMRegister key_tmp = xmm4;
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3607
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3608
      __ BIND(L_singleBlock_loopTopHead[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3609
      if (k == 1) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3610
        __ addptr(rsp, 6 * wordSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3611
      } else if (k == 2) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3612
        __ addptr(rsp, 10 * wordSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3613
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3614
      __ cmpptr(len_reg, 0); // any blocks left??
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3615
      __ jcc(Assembler::equal, L_exit);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3616
      __ BIND(L_singleBlock_loopTopHead2[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3617
      if (k == 1) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3618
        load_key(xmm_key11, key, 0xb0); // 0xb0; 192-bit key goes upto 0xc0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3619
        load_key(xmm_key12, key, 0xc0); // 0xc0; 192-bit key goes upto 0xc0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3620
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3621
      if (k == 2) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3622
        load_key(xmm_key11, key, 0xb0); // 0xb0; 256-bit key goes upto 0xe0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3623
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3624
      __ align(OptoLoopAlignment);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3625
      __ BIND(L_singleBlock_loopTop[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3626
      __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of cipher input
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3627
      __ movdqa(xmm_prev_block_cipher_save, xmm_result); // save for next r vector
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3628
      __ pxor(xmm_result, xmm_key_first); // do the aes dec rounds
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3629
      for (int rnum = 1; rnum <= 9 ; rnum++) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3630
          __ aesdec(xmm_result, as_XMMRegister(rnum + XMM_REG_NUM_KEY_FIRST));
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3631
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3632
      if (k == 1) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3633
        __ aesdec(xmm_result, xmm_key11);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3634
        __ aesdec(xmm_result, xmm_key12);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3635
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3636
      if (k == 2) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3637
        __ aesdec(xmm_result, xmm_key11);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3638
        load_key(key_tmp, key, 0xc0);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3639
        __ aesdec(xmm_result, key_tmp);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3640
        load_key(key_tmp, key, 0xd0);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3641
        __ aesdec(xmm_result, key_tmp);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3642
        load_key(key_tmp, key, 0xe0);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3643
        __ aesdec(xmm_result, key_tmp);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3644
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3645
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3646
      __ aesdeclast(xmm_result, xmm_key_last); // xmm15 always came from key+0
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3647
      __ pxor(xmm_result, xmm_prev_block_cipher); // xor with the current r vector
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3648
      __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3649
      // no need to store r to memory until we exit
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3650
      __ movdqa(xmm_prev_block_cipher, xmm_prev_block_cipher_save); // set up next r vector with cipher input from this block
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3651
      __ addptr(pos, AESBlockSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3652
      __ subptr(len_reg, AESBlockSize);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3653
      __ jcc(Assembler::notEqual, L_singleBlock_loopTop[k]);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3654
      if (k != 2) {
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3655
        __ jmp(L_exit);
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3656
      }
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3657
    } //for 128/192/256
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3658
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3659
    __ BIND(L_exit);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3660
    __ movdqu(Address(rvec, 0), xmm_prev_block_cipher);     // final value of r stored in rvec of CipherBlockChaining object
36825
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3661
    __ pop(rbx);
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3662
#ifdef _WIN64
22505
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3663
    __ movl(rax, len_mem);
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3664
#else
4523090c9674 8002074: Support for AES on SPARC
kvn
parents: 19319
diff changeset
  3665
    __ pop(rax); // return length
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3666
#endif
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3667
    __ leave(); // required for proper stackwalking of RuntimeStub frame
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3668
    __ ret(0);
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3669
    return start;
36825
6ebe5519b753 8152354: Update for x86 AES CBC Decryption
vdeshpande
parents: 36561
diff changeset
  3670
}
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  3671
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3672
  address generate_upper_word_mask() {
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3673
    __ align(64);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3674
    StubCodeMark mark(this, "StubRoutines", "upper_word_mask");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3675
    address start = __ pc();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3676
    __ emit_data64(0x0000000000000000, relocInfo::none);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3677
    __ emit_data64(0xFFFFFFFF00000000, relocInfo::none);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3678
    return start;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3679
  }
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3680
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3681
  address generate_shuffle_byte_flip_mask() {
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3682
    __ align(64);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3683
    StubCodeMark mark(this, "StubRoutines", "shuffle_byte_flip_mask");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3684
    address start = __ pc();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3685
    __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3686
    __ emit_data64(0x0001020304050607, relocInfo::none);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3687
    return start;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3688
  }
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3689
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3690
  // ofs and limit are use for multi-block byte array.
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3691
  // int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit)
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3692
  address generate_sha1_implCompress(bool multi_block, const char *name) {
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3693
    __ align(CodeEntryAlignment);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3694
    StubCodeMark mark(this, "StubRoutines", name);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3695
    address start = __ pc();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3696
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3697
    Register buf = c_rarg0;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3698
    Register state = c_rarg1;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3699
    Register ofs = c_rarg2;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3700
    Register limit = c_rarg3;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3701
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3702
    const XMMRegister abcd = xmm0;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3703
    const XMMRegister e0 = xmm1;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3704
    const XMMRegister e1 = xmm2;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3705
    const XMMRegister msg0 = xmm3;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3706
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3707
    const XMMRegister msg1 = xmm4;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3708
    const XMMRegister msg2 = xmm5;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3709
    const XMMRegister msg3 = xmm6;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3710
    const XMMRegister shuf_mask = xmm7;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3711
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3712
    __ enter();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3713
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3714
    __ subptr(rsp, 4 * wordSize);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3715
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3716
    __ fast_sha1(abcd, e0, e1, msg0, msg1, msg2, msg3, shuf_mask,
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3717
      buf, state, ofs, limit, rsp, multi_block);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3718
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3719
    __ addptr(rsp, 4 * wordSize);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3720
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3721
    __ leave();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3722
    __ ret(0);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3723
    return start;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3724
  }
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3725
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3726
  address generate_pshuffle_byte_flip_mask() {
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3727
    __ align(64);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3728
    StubCodeMark mark(this, "StubRoutines", "pshuffle_byte_flip_mask");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3729
    address start = __ pc();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3730
    __ emit_data64(0x0405060700010203, relocInfo::none);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3731
    __ emit_data64(0x0c0d0e0f08090a0b, relocInfo::none);
38135
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3732
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3733
    if (VM_Version::supports_avx2()) {
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3734
      __ emit_data64(0x0405060700010203, relocInfo::none); // second copy
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3735
      __ emit_data64(0x0c0d0e0f08090a0b, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3736
      // _SHUF_00BA
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3737
      __ emit_data64(0x0b0a090803020100, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3738
      __ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3739
      __ emit_data64(0x0b0a090803020100, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3740
      __ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3741
      // _SHUF_DC00
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3742
      __ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3743
      __ emit_data64(0x0b0a090803020100, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3744
      __ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3745
      __ emit_data64(0x0b0a090803020100, relocInfo::none);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3746
    }
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3747
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3748
    return start;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3749
  }
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3750
42039
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3751
  //Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3752
  address generate_pshuffle_byte_flip_mask_sha512() {
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3753
    __ align(32);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3754
    StubCodeMark mark(this, "StubRoutines", "pshuffle_byte_flip_mask_sha512");
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3755
    address start = __ pc();
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3756
    if (VM_Version::supports_avx2()) {
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3757
      __ emit_data64(0x0001020304050607, relocInfo::none); // PSHUFFLE_BYTE_FLIP_MASK
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3758
      __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3759
      __ emit_data64(0x1011121314151617, relocInfo::none);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3760
      __ emit_data64(0x18191a1b1c1d1e1f, relocInfo::none);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3761
      __ emit_data64(0x0000000000000000, relocInfo::none); //MASK_YMM_LO
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3762
      __ emit_data64(0x0000000000000000, relocInfo::none);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3763
      __ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3764
      __ emit_data64(0xFFFFFFFFFFFFFFFF, relocInfo::none);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3765
    }
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3766
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3767
    return start;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3768
  }
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3769
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3770
// ofs and limit are use for multi-block byte array.
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3771
// int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit)
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3772
  address generate_sha256_implCompress(bool multi_block, const char *name) {
38135
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3773
    assert(VM_Version::supports_sha() || VM_Version::supports_avx2(), "");
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3774
    __ align(CodeEntryAlignment);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3775
    StubCodeMark mark(this, "StubRoutines", name);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3776
    address start = __ pc();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3777
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3778
    Register buf = c_rarg0;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3779
    Register state = c_rarg1;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3780
    Register ofs = c_rarg2;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3781
    Register limit = c_rarg3;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3782
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3783
    const XMMRegister msg = xmm0;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3784
    const XMMRegister state0 = xmm1;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3785
    const XMMRegister state1 = xmm2;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3786
    const XMMRegister msgtmp0 = xmm3;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3787
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3788
    const XMMRegister msgtmp1 = xmm4;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3789
    const XMMRegister msgtmp2 = xmm5;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3790
    const XMMRegister msgtmp3 = xmm6;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3791
    const XMMRegister msgtmp4 = xmm7;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3792
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3793
    const XMMRegister shuf_mask = xmm8;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3794
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3795
    __ enter();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3796
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3797
    __ subptr(rsp, 4 * wordSize);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3798
38135
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3799
    if (VM_Version::supports_sha()) {
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3800
      __ fast_sha256(msg, state0, state1, msgtmp0, msgtmp1, msgtmp2, msgtmp3, msgtmp4,
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3801
        buf, state, ofs, limit, rsp, multi_block, shuf_mask);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3802
    } else if (VM_Version::supports_avx2()) {
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3803
      __ sha256_AVX2(msg, state0, state1, msgtmp0, msgtmp1, msgtmp2, msgtmp3, msgtmp4,
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3804
        buf, state, ofs, limit, rsp, multi_block, shuf_mask);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  3805
    }
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3806
    __ addptr(rsp, 4 * wordSize);
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  3807
    __ vzeroupper();
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3808
    __ leave();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3809
    __ ret(0);
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3810
    return start;
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3811
  }
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  3812
42039
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3813
  address generate_sha512_implCompress(bool multi_block, const char *name) {
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3814
    assert(VM_Version::supports_avx2(), "");
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3815
    assert(VM_Version::supports_bmi2(), "");
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3816
    __ align(CodeEntryAlignment);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3817
    StubCodeMark mark(this, "StubRoutines", name);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3818
    address start = __ pc();
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3819
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3820
    Register buf = c_rarg0;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3821
    Register state = c_rarg1;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3822
    Register ofs = c_rarg2;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3823
    Register limit = c_rarg3;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3824
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3825
    const XMMRegister msg = xmm0;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3826
    const XMMRegister state0 = xmm1;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3827
    const XMMRegister state1 = xmm2;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3828
    const XMMRegister msgtmp0 = xmm3;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3829
    const XMMRegister msgtmp1 = xmm4;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3830
    const XMMRegister msgtmp2 = xmm5;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3831
    const XMMRegister msgtmp3 = xmm6;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3832
    const XMMRegister msgtmp4 = xmm7;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3833
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3834
    const XMMRegister shuf_mask = xmm8;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3835
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3836
    __ enter();
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3837
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3838
    __ sha512_AVX2(msg, state0, state1, msgtmp0, msgtmp1, msgtmp2, msgtmp3, msgtmp4,
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3839
    buf, state, ofs, limit, rsp, multi_block, shuf_mask);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3840
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  3841
    __ vzeroupper();
42039
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3842
    __ leave();
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3843
    __ ret(0);
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3844
    return start;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3845
  }
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  3846
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3847
  // This is a version of CTR/AES crypt which does 6 blocks in a loop at a time
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3848
  // to hide instruction latency
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3849
  //
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3850
  // Arguments:
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3851
  //
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3852
  // Inputs:
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3853
  //   c_rarg0   - source byte array address
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3854
  //   c_rarg1   - destination byte array address
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3855
  //   c_rarg2   - K (key) in little endian int array
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3856
  //   c_rarg3   - counter vector byte array address
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3857
  //   Linux
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3858
  //     c_rarg4   -          input length
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3859
  //     c_rarg5   -          saved encryptedCounter start
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3860
  //     rbp + 6 * wordSize - saved used length
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3861
  //   Windows
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3862
  //     rbp + 6 * wordSize - input length
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3863
  //     rbp + 7 * wordSize - saved encryptedCounter start
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3864
  //     rbp + 8 * wordSize - saved used length
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3865
  //
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3866
  // Output:
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3867
  //   rax       - input length
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3868
  //
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3869
  address generate_counterMode_AESCrypt_Parallel() {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3870
    assert(UseAES, "need AES instructions and misaligned SSE support");
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3871
    __ align(CodeEntryAlignment);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3872
    StubCodeMark mark(this, "StubRoutines", "counterMode_AESCrypt");
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3873
    address start = __ pc();
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3874
    const Register from = c_rarg0; // source array address
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3875
    const Register to = c_rarg1; // destination array address
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3876
    const Register key = c_rarg2; // key array address
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3877
    const Register counter = c_rarg3; // counter byte array initialized from counter array address
35537
bed5e2dc57a1 8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents: 35154
diff changeset
  3878
                                      // and updated with the incremented counter in the end
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3879
#ifndef _WIN64
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3880
    const Register len_reg = c_rarg4;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3881
    const Register saved_encCounter_start = c_rarg5;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3882
    const Register used_addr = r10;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3883
    const Address  used_mem(rbp, 2 * wordSize);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3884
    const Register used = r11;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3885
#else
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3886
    const Address len_mem(rbp, 6 * wordSize); // length is on stack on Win64
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3887
    const Address saved_encCounter_mem(rbp, 7 * wordSize); // length is on stack on Win64
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3888
    const Address used_mem(rbp, 8 * wordSize); // length is on stack on Win64
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3889
    const Register len_reg = r10; // pick the first volatile windows register
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3890
    const Register saved_encCounter_start = r11;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3891
    const Register used_addr = r13;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3892
    const Register used = r14;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3893
#endif
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3894
    const Register pos = rax;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3895
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3896
    const int PARALLEL_FACTOR = 6;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3897
    const XMMRegister xmm_counter_shuf_mask = xmm0;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3898
    const XMMRegister xmm_key_shuf_mask = xmm1; // used temporarily to swap key bytes up front
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3899
    const XMMRegister xmm_curr_counter = xmm2;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3900
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3901
    const XMMRegister xmm_key_tmp0 = xmm3;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3902
    const XMMRegister xmm_key_tmp1 = xmm4;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3903
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3904
    // registers holding the four results in the parallelized loop
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3905
    const XMMRegister xmm_result0 = xmm5;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3906
    const XMMRegister xmm_result1 = xmm6;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3907
    const XMMRegister xmm_result2 = xmm7;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3908
    const XMMRegister xmm_result3 = xmm8;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3909
    const XMMRegister xmm_result4 = xmm9;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3910
    const XMMRegister xmm_result5 = xmm10;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3911
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3912
    const XMMRegister xmm_from0 = xmm11;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3913
    const XMMRegister xmm_from1 = xmm12;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3914
    const XMMRegister xmm_from2 = xmm13;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3915
    const XMMRegister xmm_from3 = xmm14; //the last one is xmm14. we have to preserve it on WIN64.
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3916
    const XMMRegister xmm_from4 = xmm3; //reuse xmm3~4. Because xmm_key_tmp0~1 are useless when loading input text
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3917
    const XMMRegister xmm_from5 = xmm4;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3918
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3919
    //for key_128, key_192, key_256
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3920
    const int rounds[3] = {10, 12, 14};
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3921
    Label L_exit_preLoop, L_preLoop_start;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3922
    Label L_multiBlock_loopTop[3];
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3923
    Label L_singleBlockLoopTop[3];
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3924
    Label L__incCounter[3][6]; //for 6 blocks
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3925
    Label L__incCounter_single[3]; //for single block, key128, key192, key256
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3926
    Label L_processTail_insr[3], L_processTail_4_insr[3], L_processTail_2_insr[3], L_processTail_1_insr[3], L_processTail_exit_insr[3];
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3927
    Label L_processTail_extr[3], L_processTail_4_extr[3], L_processTail_2_extr[3], L_processTail_1_extr[3], L_processTail_exit_extr[3];
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3928
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3929
    Label L_exit;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3930
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3931
    __ enter(); // required for proper stackwalking of RuntimeStub frame
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3932
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3933
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3934
    // context for the registers used, where all instructions below are using 128-bit mode
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3935
    // On EVEX without VL and BW, these instructions will all be AVX.
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3936
    if (VM_Version::supports_avx512vlbw()) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3937
        __ movl(rax, 0xffff);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3938
        __ kmovql(k1, rax);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3939
    }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3940
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3941
#ifdef _WIN64
41333
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3942
    // allocate spill slots for r13, r14
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3943
    enum {
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3944
        saved_r13_offset,
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3945
        saved_r14_offset
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3946
    };
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3947
    __ subptr(rsp, 2 * wordSize);
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3948
    __ movptr(Address(rsp, saved_r13_offset * wordSize), r13);
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  3949
    __ movptr(Address(rsp, saved_r14_offset * wordSize), r14);
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3950
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3951
    // on win64, fill len_reg from stack position
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3952
    __ movl(len_reg, len_mem);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3953
    __ movptr(saved_encCounter_start, saved_encCounter_mem);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3954
    __ movptr(used_addr, used_mem);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3955
    __ movl(used, Address(used_addr, 0));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3956
#else
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3957
    __ push(len_reg); // Save
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3958
    __ movptr(used_addr, used_mem);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3959
    __ movl(used, Address(used_addr, 0));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3960
#endif
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3961
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3962
    __ push(rbx); // Save RBX
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3963
    __ movdqu(xmm_curr_counter, Address(counter, 0x00)); // initialize counter with initial counter
43423
bcaab17f72a5 8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents: 42618
diff changeset
  3964
    __ movdqu(xmm_counter_shuf_mask, ExternalAddress(StubRoutines::x86::counter_shuffle_mask_addr()), pos); // pos as scratch
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3965
    __ pshufb(xmm_curr_counter, xmm_counter_shuf_mask); //counter is shuffled
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3966
    __ movptr(pos, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3967
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3968
    // Use the partially used encrpyted counter from last invocation
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3969
    __ BIND(L_preLoop_start);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3970
    __ cmpptr(used, 16);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3971
    __ jcc(Assembler::aboveEqual, L_exit_preLoop);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3972
      __ cmpptr(len_reg, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3973
      __ jcc(Assembler::lessEqual, L_exit_preLoop);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3974
      __ movb(rbx, Address(saved_encCounter_start, used));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3975
      __ xorb(rbx, Address(from, pos));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3976
      __ movb(Address(to, pos), rbx);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3977
      __ addptr(pos, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3978
      __ addptr(used, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3979
      __ subptr(len_reg, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3980
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3981
    __ jmp(L_preLoop_start);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3982
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3983
    __ BIND(L_exit_preLoop);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3984
    __ movl(Address(used_addr, 0), used);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3985
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3986
    // key length could be only {11, 13, 15} * 4 = {44, 52, 60}
43423
bcaab17f72a5 8171974: Fix for R10 Register clobbering with usage of ExternalAddress
vdeshpande
parents: 42618
diff changeset
  3987
    __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()), rbx); // rbx as scratch
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3988
    __ movl(rbx, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3989
    __ cmpl(rbx, 52);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3990
    __ jcc(Assembler::equal, L_multiBlock_loopTop[1]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3991
    __ cmpl(rbx, 60);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3992
    __ jcc(Assembler::equal, L_multiBlock_loopTop[2]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3993
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3994
#define CTR_DoSix(opc, src_reg)                \
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3995
    __ opc(xmm_result0, src_reg);              \
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3996
    __ opc(xmm_result1, src_reg);              \
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3997
    __ opc(xmm_result2, src_reg);              \
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3998
    __ opc(xmm_result3, src_reg);              \
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  3999
    __ opc(xmm_result4, src_reg);              \
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4000
    __ opc(xmm_result5, src_reg);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4001
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4002
    // k == 0 :  generate code for key_128
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4003
    // k == 1 :  generate code for key_192
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4004
    // k == 2 :  generate code for key_256
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4005
    for (int k = 0; k < 3; ++k) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4006
      //multi blocks starts here
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4007
      __ align(OptoLoopAlignment);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4008
      __ BIND(L_multiBlock_loopTop[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4009
      __ cmpptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // see if at least PARALLEL_FACTOR blocks left
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4010
      __ jcc(Assembler::less, L_singleBlockLoopTop[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4011
      load_key(xmm_key_tmp0, key, 0x00, xmm_key_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4012
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4013
      //load, then increase counters
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4014
      CTR_DoSix(movdqa, xmm_curr_counter);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4015
      inc_counter(rbx, xmm_result1, 0x01, L__incCounter[k][0]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4016
      inc_counter(rbx, xmm_result2, 0x02, L__incCounter[k][1]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4017
      inc_counter(rbx, xmm_result3, 0x03, L__incCounter[k][2]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4018
      inc_counter(rbx, xmm_result4, 0x04, L__incCounter[k][3]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4019
      inc_counter(rbx, xmm_result5,  0x05, L__incCounter[k][4]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4020
      inc_counter(rbx, xmm_curr_counter, 0x06, L__incCounter[k][5]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4021
      CTR_DoSix(pshufb, xmm_counter_shuf_mask); // after increased, shuffled counters back for PXOR
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4022
      CTR_DoSix(pxor, xmm_key_tmp0);   //PXOR with Round 0 key
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4023
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4024
      //load two ROUND_KEYs at a time
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4025
      for (int i = 1; i < rounds[k]; ) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4026
        load_key(xmm_key_tmp1, key, (0x10 * i), xmm_key_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4027
        load_key(xmm_key_tmp0, key, (0x10 * (i+1)), xmm_key_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4028
        CTR_DoSix(aesenc, xmm_key_tmp1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4029
        i++;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4030
        if (i != rounds[k]) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4031
          CTR_DoSix(aesenc, xmm_key_tmp0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4032
        } else {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4033
          CTR_DoSix(aesenclast, xmm_key_tmp0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4034
        }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4035
        i++;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4036
      }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4037
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4038
      // get next PARALLEL_FACTOR blocks into xmm_result registers
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4039
      __ movdqu(xmm_from0, Address(from, pos, Address::times_1, 0 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4040
      __ movdqu(xmm_from1, Address(from, pos, Address::times_1, 1 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4041
      __ movdqu(xmm_from2, Address(from, pos, Address::times_1, 2 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4042
      __ movdqu(xmm_from3, Address(from, pos, Address::times_1, 3 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4043
      __ movdqu(xmm_from4, Address(from, pos, Address::times_1, 4 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4044
      __ movdqu(xmm_from5, Address(from, pos, Address::times_1, 5 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4045
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4046
      __ pxor(xmm_result0, xmm_from0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4047
      __ pxor(xmm_result1, xmm_from1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4048
      __ pxor(xmm_result2, xmm_from2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4049
      __ pxor(xmm_result3, xmm_from3);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4050
      __ pxor(xmm_result4, xmm_from4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4051
      __ pxor(xmm_result5, xmm_from5);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4052
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4053
      // store 6 results into the next 64 bytes of output
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4054
      __ movdqu(Address(to, pos, Address::times_1, 0 * AESBlockSize), xmm_result0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4055
      __ movdqu(Address(to, pos, Address::times_1, 1 * AESBlockSize), xmm_result1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4056
      __ movdqu(Address(to, pos, Address::times_1, 2 * AESBlockSize), xmm_result2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4057
      __ movdqu(Address(to, pos, Address::times_1, 3 * AESBlockSize), xmm_result3);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4058
      __ movdqu(Address(to, pos, Address::times_1, 4 * AESBlockSize), xmm_result4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4059
      __ movdqu(Address(to, pos, Address::times_1, 5 * AESBlockSize), xmm_result5);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4060
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4061
      __ addptr(pos, PARALLEL_FACTOR * AESBlockSize); // increase the length of crypt text
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4062
      __ subptr(len_reg, PARALLEL_FACTOR * AESBlockSize); // decrease the remaining length
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4063
      __ jmp(L_multiBlock_loopTop[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4064
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4065
      // singleBlock starts here
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4066
      __ align(OptoLoopAlignment);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4067
      __ BIND(L_singleBlockLoopTop[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4068
      __ cmpptr(len_reg, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4069
      __ jcc(Assembler::lessEqual, L_exit);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4070
      load_key(xmm_key_tmp0, key, 0x00, xmm_key_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4071
      __ movdqa(xmm_result0, xmm_curr_counter);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4072
      inc_counter(rbx, xmm_curr_counter, 0x01, L__incCounter_single[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4073
      __ pshufb(xmm_result0, xmm_counter_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4074
      __ pxor(xmm_result0, xmm_key_tmp0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4075
      for (int i = 1; i < rounds[k]; i++) {
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4076
        load_key(xmm_key_tmp0, key, (0x10 * i), xmm_key_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4077
        __ aesenc(xmm_result0, xmm_key_tmp0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4078
      }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4079
      load_key(xmm_key_tmp0, key, (rounds[k] * 0x10), xmm_key_shuf_mask);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4080
      __ aesenclast(xmm_result0, xmm_key_tmp0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4081
      __ cmpptr(len_reg, AESBlockSize);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4082
      __ jcc(Assembler::less, L_processTail_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4083
        __ movdqu(xmm_from0, Address(from, pos, Address::times_1, 0 * AESBlockSize));
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4084
        __ pxor(xmm_result0, xmm_from0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4085
        __ movdqu(Address(to, pos, Address::times_1, 0 * AESBlockSize), xmm_result0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4086
        __ addptr(pos, AESBlockSize);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4087
        __ subptr(len_reg, AESBlockSize);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4088
        __ jmp(L_singleBlockLoopTop[k]);
35537
bed5e2dc57a1 8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents: 35154
diff changeset
  4089
      __ BIND(L_processTail_insr[k]);                               // Process the tail part of the input array
bed5e2dc57a1 8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents: 35154
diff changeset
  4090
        __ addptr(pos, len_reg);                                    // 1. Insert bytes from src array into xmm_from0 register
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4091
        __ testptr(len_reg, 8);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4092
        __ jcc(Assembler::zero, L_processTail_4_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4093
          __ subptr(pos,8);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4094
          __ pinsrq(xmm_from0, Address(from, pos), 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4095
        __ BIND(L_processTail_4_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4096
        __ testptr(len_reg, 4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4097
        __ jcc(Assembler::zero, L_processTail_2_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4098
          __ subptr(pos,4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4099
          __ pslldq(xmm_from0, 4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4100
          __ pinsrd(xmm_from0, Address(from, pos), 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4101
        __ BIND(L_processTail_2_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4102
        __ testptr(len_reg, 2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4103
        __ jcc(Assembler::zero, L_processTail_1_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4104
          __ subptr(pos, 2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4105
          __ pslldq(xmm_from0, 2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4106
          __ pinsrw(xmm_from0, Address(from, pos), 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4107
        __ BIND(L_processTail_1_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4108
        __ testptr(len_reg, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4109
        __ jcc(Assembler::zero, L_processTail_exit_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4110
          __ subptr(pos, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4111
          __ pslldq(xmm_from0, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4112
          __ pinsrb(xmm_from0, Address(from, pos), 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4113
        __ BIND(L_processTail_exit_insr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4114
35537
bed5e2dc57a1 8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents: 35154
diff changeset
  4115
        __ movdqu(Address(saved_encCounter_start, 0), xmm_result0);  // 2. Perform pxor of the encrypted counter and plaintext Bytes.
bed5e2dc57a1 8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents: 35154
diff changeset
  4116
        __ pxor(xmm_result0, xmm_from0);                             //    Also the encrypted counter is saved for next invocation.
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4117
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4118
        __ testptr(len_reg, 8);
35537
bed5e2dc57a1 8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents: 35154
diff changeset
  4119
        __ jcc(Assembler::zero, L_processTail_4_extr[k]);            // 3. Extract bytes from xmm_result0 into the dest. array
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4120
          __ pextrq(Address(to, pos), xmm_result0, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4121
          __ psrldq(xmm_result0, 8);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4122
          __ addptr(pos, 8);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4123
        __ BIND(L_processTail_4_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4124
        __ testptr(len_reg, 4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4125
        __ jcc(Assembler::zero, L_processTail_2_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4126
          __ pextrd(Address(to, pos), xmm_result0, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4127
          __ psrldq(xmm_result0, 4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4128
          __ addptr(pos, 4);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4129
        __ BIND(L_processTail_2_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4130
        __ testptr(len_reg, 2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4131
        __ jcc(Assembler::zero, L_processTail_1_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4132
          __ pextrw(Address(to, pos), xmm_result0, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4133
          __ psrldq(xmm_result0, 2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4134
          __ addptr(pos, 2);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4135
        __ BIND(L_processTail_1_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4136
        __ testptr(len_reg, 1);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4137
        __ jcc(Assembler::zero, L_processTail_exit_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4138
          __ pextrb(Address(to, pos), xmm_result0, 0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4139
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4140
        __ BIND(L_processTail_exit_extr[k]);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4141
        __ movl(Address(used_addr, 0), len_reg);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4142
        __ jmp(L_exit);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4143
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4144
    }
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4145
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4146
    __ BIND(L_exit);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4147
    __ pshufb(xmm_curr_counter, xmm_counter_shuf_mask); //counter is shuffled back.
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4148
    __ movdqu(Address(counter, 0), xmm_curr_counter); //save counter back
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4149
    __ pop(rbx); // pop the saved RBX.
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4150
#ifdef _WIN64
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4151
    __ movl(rax, len_mem);
41333
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  4152
    __ movptr(r13, Address(rsp, saved_r13_offset * wordSize));
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  4153
    __ movptr(r14, Address(rsp, saved_r14_offset * wordSize));
ce08d64b41c7 8078122: YMM registers upper 128 bits may get clobbered by a JNI call on windows
kvn
parents: 40644
diff changeset
  4154
    __ addptr(rsp, 2 * wordSize);
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4155
#else
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4156
    __ pop(rax); // return 'len'
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4157
#endif
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4158
    __ leave(); // required for proper stackwalking of RuntimeStub frame
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4159
    __ ret(0);
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4160
    return start;
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  4161
  }
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4162
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4163
  // byte swap x86 long
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4164
  address generate_ghash_long_swap_mask() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4165
    __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4166
    StubCodeMark mark(this, "StubRoutines", "ghash_long_swap_mask");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4167
    address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4168
    __ emit_data64(0x0f0e0d0c0b0a0908, relocInfo::none );
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4169
    __ emit_data64(0x0706050403020100, relocInfo::none );
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4170
  return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4171
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4172
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4173
  // byte swap x86 byte array
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4174
  address generate_ghash_byte_swap_mask() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4175
    __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4176
    StubCodeMark mark(this, "StubRoutines", "ghash_byte_swap_mask");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4177
    address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4178
    __ emit_data64(0x08090a0b0c0d0e0f, relocInfo::none );
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4179
    __ emit_data64(0x0001020304050607, relocInfo::none );
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4180
  return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4181
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4182
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4183
  /* Single and multi-block ghash operations */
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4184
  address generate_ghash_processBlocks() {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4185
    __ align(CodeEntryAlignment);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4186
    Label L_ghash_loop, L_exit;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4187
    StubCodeMark mark(this, "StubRoutines", "ghash_processBlocks");
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4188
    address start = __ pc();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4189
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4190
    const Register state        = c_rarg0;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4191
    const Register subkeyH      = c_rarg1;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4192
    const Register data         = c_rarg2;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4193
    const Register blocks       = c_rarg3;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4194
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4195
    const XMMRegister xmm_temp0 = xmm0;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4196
    const XMMRegister xmm_temp1 = xmm1;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4197
    const XMMRegister xmm_temp2 = xmm2;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4198
    const XMMRegister xmm_temp3 = xmm3;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4199
    const XMMRegister xmm_temp4 = xmm4;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4200
    const XMMRegister xmm_temp5 = xmm5;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4201
    const XMMRegister xmm_temp6 = xmm6;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4202
    const XMMRegister xmm_temp7 = xmm7;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4203
    const XMMRegister xmm_temp8 = xmm8;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4204
    const XMMRegister xmm_temp9 = xmm9;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4205
    const XMMRegister xmm_temp10 = xmm10;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4206
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4207
    __ enter();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4208
32727
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4209
    // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4210
    // context for the registers used, where all instructions below are using 128-bit mode
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4211
    // On EVEX without VL and BW, these instructions will all be AVX.
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4212
    if (VM_Version::supports_avx512vlbw()) {
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4213
      __ movl(rax, 0xffff);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4214
      __ kmovql(k1, rax);
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4215
    }
320855c2baef 8132160: support for AVX 512 call frames and stack management
mcberg
parents: 32596
diff changeset
  4216
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4217
    __ movdqu(xmm_temp10, ExternalAddress(StubRoutines::x86::ghash_long_swap_mask_addr()));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4218
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4219
    __ movdqu(xmm_temp0, Address(state, 0));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4220
    __ pshufb(xmm_temp0, xmm_temp10);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4221
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4222
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4223
    __ BIND(L_ghash_loop);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4224
    __ movdqu(xmm_temp2, Address(data, 0));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4225
    __ pshufb(xmm_temp2, ExternalAddress(StubRoutines::x86::ghash_byte_swap_mask_addr()));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4226
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4227
    __ movdqu(xmm_temp1, Address(subkeyH, 0));
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4228
    __ pshufb(xmm_temp1, xmm_temp10);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4229
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4230
    __ pxor(xmm_temp0, xmm_temp2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4231
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4232
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4233
    // Multiply with the hash key
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4234
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4235
    __ movdqu(xmm_temp3, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4236
    __ pclmulqdq(xmm_temp3, xmm_temp1, 0);      // xmm3 holds a0*b0
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4237
    __ movdqu(xmm_temp4, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4238
    __ pclmulqdq(xmm_temp4, xmm_temp1, 16);     // xmm4 holds a0*b1
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4239
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4240
    __ movdqu(xmm_temp5, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4241
    __ pclmulqdq(xmm_temp5, xmm_temp1, 1);      // xmm5 holds a1*b0
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4242
    __ movdqu(xmm_temp6, xmm_temp0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4243
    __ pclmulqdq(xmm_temp6, xmm_temp1, 17);     // xmm6 holds a1*b1
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4244
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4245
    __ pxor(xmm_temp4, xmm_temp5);      // xmm4 holds a0*b1 + a1*b0
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4246
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4247
    __ movdqu(xmm_temp5, xmm_temp4);    // move the contents of xmm4 to xmm5
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4248
    __ psrldq(xmm_temp4, 8);    // shift by xmm4 64 bits to the right
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4249
    __ pslldq(xmm_temp5, 8);    // shift by xmm5 64 bits to the left
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4250
    __ pxor(xmm_temp3, xmm_temp5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4251
    __ pxor(xmm_temp6, xmm_temp4);      // Register pair <xmm6:xmm3> holds the result
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4252
                                        // of the carry-less multiplication of
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4253
                                        // xmm0 by xmm1.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4254
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4255
    // We shift the result of the multiplication by one bit position
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4256
    // to the left to cope for the fact that the bits are reversed.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4257
    __ movdqu(xmm_temp7, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4258
    __ movdqu(xmm_temp8, xmm_temp6);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4259
    __ pslld(xmm_temp3, 1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4260
    __ pslld(xmm_temp6, 1);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4261
    __ psrld(xmm_temp7, 31);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4262
    __ psrld(xmm_temp8, 31);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4263
    __ movdqu(xmm_temp9, xmm_temp7);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4264
    __ pslldq(xmm_temp8, 4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4265
    __ pslldq(xmm_temp7, 4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4266
    __ psrldq(xmm_temp9, 12);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4267
    __ por(xmm_temp3, xmm_temp7);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4268
    __ por(xmm_temp6, xmm_temp8);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4269
    __ por(xmm_temp6, xmm_temp9);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4270
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4271
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4272
    // First phase of the reduction
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4273
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4274
    // Move xmm3 into xmm7, xmm8, xmm9 in order to perform the shifts
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4275
    // independently.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4276
    __ movdqu(xmm_temp7, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4277
    __ movdqu(xmm_temp8, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4278
    __ movdqu(xmm_temp9, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4279
    __ pslld(xmm_temp7, 31);    // packed right shift shifting << 31
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4280
    __ pslld(xmm_temp8, 30);    // packed right shift shifting << 30
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4281
    __ pslld(xmm_temp9, 25);    // packed right shift shifting << 25
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4282
    __ pxor(xmm_temp7, xmm_temp8);      // xor the shifted versions
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4283
    __ pxor(xmm_temp7, xmm_temp9);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4284
    __ movdqu(xmm_temp8, xmm_temp7);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4285
    __ pslldq(xmm_temp7, 12);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4286
    __ psrldq(xmm_temp8, 4);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4287
    __ pxor(xmm_temp3, xmm_temp7);      // first phase of the reduction complete
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4288
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4289
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4290
    // Second phase of the reduction
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4291
    //
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4292
    // Make 3 copies of xmm3 in xmm2, xmm4, xmm5 for doing these
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4293
    // shift operations.
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4294
    __ movdqu(xmm_temp2, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4295
    __ movdqu(xmm_temp4, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4296
    __ movdqu(xmm_temp5, xmm_temp3);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4297
    __ psrld(xmm_temp2, 1);     // packed left shifting >> 1
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4298
    __ psrld(xmm_temp4, 2);     // packed left shifting >> 2
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4299
    __ psrld(xmm_temp5, 7);     // packed left shifting >> 7
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4300
    __ pxor(xmm_temp2, xmm_temp4);      // xor the shifted versions
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4301
    __ pxor(xmm_temp2, xmm_temp5);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4302
    __ pxor(xmm_temp2, xmm_temp8);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4303
    __ pxor(xmm_temp3, xmm_temp2);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4304
    __ pxor(xmm_temp6, xmm_temp3);      // the result is in xmm6
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4305
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4306
    __ decrement(blocks);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4307
    __ jcc(Assembler::zero, L_exit);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4308
    __ movdqu(xmm_temp0, xmm_temp6);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4309
    __ addptr(data, 16);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4310
    __ jmp(L_ghash_loop);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4311
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4312
    __ BIND(L_exit);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4313
    __ pshufb(xmm_temp6, xmm_temp10);          // Byte swap 16-byte result
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4314
    __ movdqu(Address(state, 0), xmm_temp6);   // store the result
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4315
    __ leave();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4316
    __ ret(0);
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4317
    return start;
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4318
  }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  4319
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4320
  /**
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4321
   *  Arguments:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4322
   *
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4323
   * Inputs:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4324
   *   c_rarg0   - int crc
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4325
   *   c_rarg1   - byte* buf
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4326
   *   c_rarg2   - int length
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4327
   *
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4328
   * Ouput:
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4329
   *       rax   - int crc result
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4330
   */
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4331
  address generate_updateBytesCRC32() {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4332
    assert(UseCRC32Intrinsics, "need AVX and CLMUL instructions");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4333
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4334
    __ align(CodeEntryAlignment);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4335
    StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4336
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4337
    address start = __ pc();
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4338
    // Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4339
    // Unix:  rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4340
    // rscratch1: r10
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4341
    const Register crc   = c_rarg0;  // crc
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4342
    const Register buf   = c_rarg1;  // source java byte array address
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4343
    const Register len   = c_rarg2;  // length
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4344
    const Register table = c_rarg3;  // crc_table address (reuse register)
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4345
    const Register tmp   = r11;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4346
    assert_different_registers(crc, buf, len, table, tmp, rax);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4347
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4348
    BLOCK_COMMENT("Entry:");
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4349
    __ enter(); // required for proper stackwalking of RuntimeStub frame
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4350
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4351
    __ kernel_crc32(crc, buf, len, table, tmp);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4352
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4353
    __ movl(rax, crc);
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  4354
    __ vzeroupper();
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4355
    __ leave(); // required for proper stackwalking of RuntimeStub frame
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4356
    __ ret(0);
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4357
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4358
    return start;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  4359
  }
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  4360
33066
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4361
  /**
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4362
  *  Arguments:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4363
  *
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4364
  * Inputs:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4365
  *   c_rarg0   - int crc
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4366
  *   c_rarg1   - byte* buf
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4367
  *   c_rarg2   - long length
38238
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  4368
  *   c_rarg3   - table_start - optional (present only when doing a library_call,
33066
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4369
  *              not used by x86 algorithm)
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4370
  *
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4371
  * Ouput:
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4372
  *       rax   - int crc result
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4373
  */
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4374
  address generate_updateBytesCRC32C(bool is_pclmulqdq_supported) {
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4375
      assert(UseCRC32CIntrinsics, "need SSE4_2");
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4376
      __ align(CodeEntryAlignment);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4377
      StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32C");
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4378
      address start = __ pc();
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4379
      //reg.arg        int#0        int#1        int#2        int#3        int#4        int#5        float regs
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4380
      //Windows        RCX          RDX          R8           R9           none         none         XMM0..XMM3
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4381
      //Lin / Sol      RDI          RSI          RDX          RCX          R8           R9           XMM0..XMM7
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4382
      const Register crc = c_rarg0;  // crc
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4383
      const Register buf = c_rarg1;  // source java byte array address
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4384
      const Register len = c_rarg2;  // length
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4385
      const Register a = rax;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4386
      const Register j = r9;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4387
      const Register k = r10;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4388
      const Register l = r11;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4389
#ifdef _WIN64
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4390
      const Register y = rdi;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4391
      const Register z = rsi;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4392
#else
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4393
      const Register y = rcx;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4394
      const Register z = r8;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4395
#endif
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4396
      assert_different_registers(crc, buf, len, a, j, k, l, y, z);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4397
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4398
      BLOCK_COMMENT("Entry:");
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4399
      __ enter(); // required for proper stackwalking of RuntimeStub frame
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4400
#ifdef _WIN64
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4401
      __ push(y);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4402
      __ push(z);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4403
#endif
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4404
      __ crc32c_ipl_alg2_alt2(crc, buf, len,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4405
                              a, j, k,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4406
                              l, y, z,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4407
                              c_farg0, c_farg1, c_farg2,
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4408
                              is_pclmulqdq_supported);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4409
      __ movl(rax, crc);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4410
#ifdef _WIN64
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4411
      __ pop(z);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4412
      __ pop(y);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4413
#endif
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  4414
      __ vzeroupper();
33066
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4415
      __ leave(); // required for proper stackwalking of RuntimeStub frame
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4416
      __ ret(0);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4417
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4418
      return start;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  4419
  }
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4420
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4421
  /**
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4422
   *  Arguments:
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4423
   *
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4424
   *  Input:
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4425
   *    c_rarg0   - x address
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4426
   *    c_rarg1   - x length
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4427
   *    c_rarg2   - y address
49368
2ed1c37df3a5 8197405: Improve messages of AbstractMethodErrors and IncompatibleClassChangeErrors.
goetz
parents: 49347
diff changeset
  4428
   *    c_rarg3   - y length
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4429
   * not Win64
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4430
   *    c_rarg4   - z address
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4431
   *    c_rarg5   - z length
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4432
   * Win64
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4433
   *    rsp+40    - z address
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4434
   *    rsp+48    - z length
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4435
   */
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4436
  address generate_multiplyToLen() {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4437
    __ align(CodeEntryAlignment);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4438
    StubCodeMark mark(this, "StubRoutines", "multiplyToLen");
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4439
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4440
    address start = __ pc();
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4441
    // Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4442
    // Unix:  rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4443
    const Register x     = rdi;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4444
    const Register xlen  = rax;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4445
    const Register y     = rsi;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4446
    const Register ylen  = rcx;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4447
    const Register z     = r8;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4448
    const Register zlen  = r11;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4449
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4450
    // Next registers will be saved on stack in multiply_to_len().
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4451
    const Register tmp1  = r12;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4452
    const Register tmp2  = r13;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4453
    const Register tmp3  = r14;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4454
    const Register tmp4  = r15;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4455
    const Register tmp5  = rbx;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4456
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4457
    BLOCK_COMMENT("Entry:");
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4458
    __ enter(); // required for proper stackwalking of RuntimeStub frame
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4459
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4460
#ifndef _WIN64
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4461
    __ movptr(zlen, r9); // Save r9 in r11 - zlen
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4462
#endif
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4463
    setup_arg_regs(4); // x => rdi, xlen => rsi, y => rdx
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4464
                       // ylen => rcx, z => r8, zlen => r11
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4465
                       // r9 and r10 may be used to save non-volatile registers
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4466
#ifdef _WIN64
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4467
    // last 2 arguments (#4, #5) are on stack on Win64
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4468
    __ movptr(z, Address(rsp, 6 * wordSize));
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4469
    __ movptr(zlen, Address(rsp, 7 * wordSize));
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4470
#endif
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4471
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4472
    __ movptr(xlen, rsi);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4473
    __ movptr(y,    rdx);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4474
    __ multiply_to_len(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4475
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4476
    restore_arg_regs();
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4477
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4478
    __ leave(); // required for proper stackwalking of RuntimeStub frame
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4479
    __ ret(0);
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4480
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4481
    return start;
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4482
  }
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  4483
35110
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4484
  /**
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4485
  *  Arguments:
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4486
  *
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4487
  *  Input:
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4488
  *    c_rarg0   - obja     address
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4489
  *    c_rarg1   - objb     address
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4490
  *    c_rarg3   - length   length
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4491
  *    c_rarg4   - scale    log2_array_indxscale
38238
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  4492
  *
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  4493
  *  Output:
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  4494
  *        rax   - int >= mismatched index, < 0 bitwise complement of tail
35110
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4495
  */
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4496
  address generate_vectorizedMismatch() {
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4497
    __ align(CodeEntryAlignment);
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4498
    StubCodeMark mark(this, "StubRoutines", "vectorizedMismatch");
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4499
    address start = __ pc();
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4500
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4501
    BLOCK_COMMENT("Entry:");
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4502
    __ enter();
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4503
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4504
#ifdef _WIN64  // Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4505
    const Register scale = c_rarg0;  //rcx, will exchange with r9
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4506
    const Register objb = c_rarg1;   //rdx
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4507
    const Register length = c_rarg2; //r8
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4508
    const Register obja = c_rarg3;   //r9
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4509
    __ xchgq(obja, scale);  //now obja and scale contains the correct contents
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4510
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4511
    const Register tmp1 = r10;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4512
    const Register tmp2 = r11;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4513
#endif
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4514
#ifndef _WIN64 // Unix:  rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4515
    const Register obja = c_rarg0;   //U:rdi
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4516
    const Register objb = c_rarg1;   //U:rsi
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4517
    const Register length = c_rarg2; //U:rdx
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4518
    const Register scale = c_rarg3;  //U:rcx
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4519
    const Register tmp1 = r8;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4520
    const Register tmp2 = r9;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4521
#endif
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4522
    const Register result = rax; //return value
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4523
    const XMMRegister vec0 = xmm0;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4524
    const XMMRegister vec1 = xmm1;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4525
    const XMMRegister vec2 = xmm2;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4526
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4527
    __ vectorized_mismatch(obja, objb, length, scale, result, tmp1, tmp2, vec0, vec1, vec2);
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4528
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  4529
    __ vzeroupper();
35110
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4530
    __ leave();
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4531
    __ ret(0);
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4532
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4533
    return start;
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4534
  }
f19bcdf40799 8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents: 34203
diff changeset
  4535
31129
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4536
/**
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4537
   *  Arguments:
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4538
   *
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4539
  //  Input:
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4540
  //    c_rarg0   - x address
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4541
  //    c_rarg1   - x length
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4542
  //    c_rarg2   - z address
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4543
  //    c_rarg3   - z lenth
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4544
   *
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4545
   */
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4546
  address generate_squareToLen() {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4547
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4548
    __ align(CodeEntryAlignment);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4549
    StubCodeMark mark(this, "StubRoutines", "squareToLen");
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4550
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4551
    address start = __ pc();
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4552
    // Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4553
    // Unix:  rdi, rsi, rdx, rcx (c_rarg0, c_rarg1, ...)
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4554
    const Register x      = rdi;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4555
    const Register len    = rsi;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4556
    const Register z      = r8;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4557
    const Register zlen   = rcx;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4558
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4559
   const Register tmp1      = r12;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4560
   const Register tmp2      = r13;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4561
   const Register tmp3      = r14;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4562
   const Register tmp4      = r15;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4563
   const Register tmp5      = rbx;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4564
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4565
    BLOCK_COMMENT("Entry:");
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4566
    __ enter(); // required for proper stackwalking of RuntimeStub frame
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4567
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4568
       setup_arg_regs(4); // x => rdi, len => rsi, z => rdx
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4569
                          // zlen => rcx
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4570
                          // r9 and r10 may be used to save non-volatile registers
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4571
    __ movptr(r8, rdx);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4572
    __ square_to_len(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx, rax);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4573
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4574
    restore_arg_regs();
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4575
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4576
    __ leave(); // required for proper stackwalking of RuntimeStub frame
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4577
    __ ret(0);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4578
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4579
    return start;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4580
  }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4581
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4582
   /**
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4583
   *  Arguments:
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4584
   *
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4585
   *  Input:
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4586
   *    c_rarg0   - out address
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4587
   *    c_rarg1   - in address
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4588
   *    c_rarg2   - offset
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4589
   *    c_rarg3   - len
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4590
   * not Win64
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4591
   *    c_rarg4   - k
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4592
   * Win64
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4593
   *    rsp+40    - k
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4594
   */
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4595
  address generate_mulAdd() {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4596
    __ align(CodeEntryAlignment);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4597
    StubCodeMark mark(this, "StubRoutines", "mulAdd");
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4598
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4599
    address start = __ pc();
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4600
    // Win64: rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4601
    // Unix:  rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4602
    const Register out     = rdi;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4603
    const Register in      = rsi;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4604
    const Register offset  = r11;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4605
    const Register len     = rcx;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4606
    const Register k       = r8;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4607
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4608
    // Next registers will be saved on stack in mul_add().
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4609
    const Register tmp1  = r12;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4610
    const Register tmp2  = r13;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4611
    const Register tmp3  = r14;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4612
    const Register tmp4  = r15;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4613
    const Register tmp5  = rbx;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4614
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4615
    BLOCK_COMMENT("Entry:");
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4616
    __ enter(); // required for proper stackwalking of RuntimeStub frame
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4617
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4618
    setup_arg_regs(4); // out => rdi, in => rsi, offset => rdx
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4619
                       // len => rcx, k => r8
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4620
                       // r9 and r10 may be used to save non-volatile registers
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4621
#ifdef _WIN64
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4622
    // last argument is on stack on Win64
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4623
    __ movl(k, Address(rsp, 6 * wordSize));
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4624
#endif
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4625
    __ movptr(r11, rdx);  // move offset in rdx to offset(r11)
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4626
    __ mul_add(out, in, offset, len, k, tmp1, tmp2, tmp3, tmp4, tmp5, rdx, rax);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4627
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4628
    restore_arg_regs();
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4629
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4630
    __ leave(); // required for proper stackwalking of RuntimeStub frame
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4631
    __ ret(0);
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4632
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4633
    return start;
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4634
  }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4635
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4636
  address generate_libmExp() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4637
    StubCodeMark mark(this, "StubRoutines", "libmExp");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4638
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4639
    address start = __ pc();
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4640
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4641
    const XMMRegister x0  = xmm0;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4642
    const XMMRegister x1  = xmm1;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4643
    const XMMRegister x2  = xmm2;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4644
    const XMMRegister x3  = xmm3;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4645
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4646
    const XMMRegister x4  = xmm4;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4647
    const XMMRegister x5  = xmm5;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4648
    const XMMRegister x6  = xmm6;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4649
    const XMMRegister x7  = xmm7;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4650
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4651
    const Register tmp   = r11;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4652
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4653
    BLOCK_COMMENT("Entry:");
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4654
    __ enter(); // required for proper stackwalking of RuntimeStub frame
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4655
46440
61025eecb743 8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents: 43423
diff changeset
  4656
    __ fast_exp(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp);
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4657
33465
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4658
    __ leave(); // required for proper stackwalking of RuntimeStub frame
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4659
    __ ret(0);
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4660
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4661
    return start;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4662
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4663
  }
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4664
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4665
  address generate_libmLog() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4666
    StubCodeMark mark(this, "StubRoutines", "libmLog");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4667
33465
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4668
    address start = __ pc();
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4669
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4670
    const XMMRegister x0 = xmm0;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4671
    const XMMRegister x1 = xmm1;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4672
    const XMMRegister x2 = xmm2;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4673
    const XMMRegister x3 = xmm3;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4674
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4675
    const XMMRegister x4 = xmm4;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4676
    const XMMRegister x5 = xmm5;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4677
    const XMMRegister x6 = xmm6;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4678
    const XMMRegister x7 = xmm7;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4679
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4680
    const Register tmp1 = r11;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4681
    const Register tmp2 = r8;
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4682
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4683
    BLOCK_COMMENT("Entry:");
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4684
    __ enter(); // required for proper stackwalking of RuntimeStub frame
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4685
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4686
    __ fast_log(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2);
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  4687
33089
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4688
    __ leave(); // required for proper stackwalking of RuntimeStub frame
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4689
    __ ret(0);
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4690
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4691
    return start;
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4692
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4693
  }
f4e956ed8b43 8132207: update for x86 exp in the math lib
iveresov
parents: 33066
diff changeset
  4694
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4695
  address generate_libmLog10() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4696
    StubCodeMark mark(this, "StubRoutines", "libmLog10");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4697
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4698
    address start = __ pc();
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4699
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4700
    const XMMRegister x0 = xmm0;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4701
    const XMMRegister x1 = xmm1;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4702
    const XMMRegister x2 = xmm2;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4703
    const XMMRegister x3 = xmm3;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4704
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4705
    const XMMRegister x4 = xmm4;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4706
    const XMMRegister x5 = xmm5;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4707
    const XMMRegister x6 = xmm6;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4708
    const XMMRegister x7 = xmm7;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4709
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4710
    const Register tmp = r11;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4711
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4712
    BLOCK_COMMENT("Entry:");
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4713
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4714
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4715
    __ fast_log10(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4716
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4717
    __ leave(); // required for proper stackwalking of RuntimeStub frame
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4718
    __ ret(0);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4719
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4720
    return start;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4721
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4722
  }
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4723
35146
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4724
  address generate_libmPow() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4725
    StubCodeMark mark(this, "StubRoutines", "libmPow");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4726
35146
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4727
    address start = __ pc();
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4728
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4729
    const XMMRegister x0 = xmm0;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4730
    const XMMRegister x1 = xmm1;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4731
    const XMMRegister x2 = xmm2;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4732
    const XMMRegister x3 = xmm3;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4733
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4734
    const XMMRegister x4 = xmm4;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4735
    const XMMRegister x5 = xmm5;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4736
    const XMMRegister x6 = xmm6;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4737
    const XMMRegister x7 = xmm7;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4738
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4739
    const Register tmp1 = r8;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4740
    const Register tmp2 = r9;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4741
    const Register tmp3 = r10;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4742
    const Register tmp4 = r11;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4743
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4744
    BLOCK_COMMENT("Entry:");
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4745
    __ enter(); // required for proper stackwalking of RuntimeStub frame
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4746
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4747
    __ fast_pow(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2, tmp3, tmp4);
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4748
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4749
    __ leave(); // required for proper stackwalking of RuntimeStub frame
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4750
    __ ret(0);
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4751
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4752
    return start;
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4753
9ebfec283f56 8145688: Update for x86 pow in the math lib
kvn
parents: 35135
diff changeset
  4754
  }
31129
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  4755
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4756
  address generate_libmSin() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4757
    StubCodeMark mark(this, "StubRoutines", "libmSin");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4758
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4759
    address start = __ pc();
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4760
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4761
    const XMMRegister x0 = xmm0;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4762
    const XMMRegister x1 = xmm1;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4763
    const XMMRegister x2 = xmm2;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4764
    const XMMRegister x3 = xmm3;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4765
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4766
    const XMMRegister x4 = xmm4;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4767
    const XMMRegister x5 = xmm5;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4768
    const XMMRegister x6 = xmm6;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4769
    const XMMRegister x7 = xmm7;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4770
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4771
    const Register tmp1 = r8;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4772
    const Register tmp2 = r9;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4773
    const Register tmp3 = r10;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4774
    const Register tmp4 = r11;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4775
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4776
    BLOCK_COMMENT("Entry:");
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4777
    __ enter(); // required for proper stackwalking of RuntimeStub frame
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4778
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4779
#ifdef _WIN64
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4780
    __ push(rsi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4781
    __ push(rdi);
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4782
#endif
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4783
    __ fast_sin(x0, x1, x2, x3, x4, x5, x6, x7, rax, rbx, rcx, rdx, tmp1, tmp2, tmp3, tmp4);
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4784
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4785
#ifdef _WIN64
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4786
    __ pop(rdi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4787
    __ pop(rsi);
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4788
#endif
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4789
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4790
    __ leave(); // required for proper stackwalking of RuntimeStub frame
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4791
    __ ret(0);
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4792
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4793
    return start;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4794
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4795
  }
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4796
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4797
  address generate_libmCos() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4798
    StubCodeMark mark(this, "StubRoutines", "libmCos");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4799
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4800
    address start = __ pc();
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4801
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4802
    const XMMRegister x0 = xmm0;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4803
    const XMMRegister x1 = xmm1;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4804
    const XMMRegister x2 = xmm2;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4805
    const XMMRegister x3 = xmm3;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4806
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4807
    const XMMRegister x4 = xmm4;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4808
    const XMMRegister x5 = xmm5;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4809
    const XMMRegister x6 = xmm6;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4810
    const XMMRegister x7 = xmm7;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4811
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4812
    const Register tmp1 = r8;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4813
    const Register tmp2 = r9;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4814
    const Register tmp3 = r10;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4815
    const Register tmp4 = r11;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4816
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4817
    BLOCK_COMMENT("Entry:");
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4818
    __ enter(); // required for proper stackwalking of RuntimeStub frame
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4819
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4820
#ifdef _WIN64
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4821
    __ push(rsi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4822
    __ push(rdi);
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4823
#endif
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4824
    __ fast_cos(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2, tmp3, tmp4);
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4825
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4826
#ifdef _WIN64
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4827
    __ pop(rdi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4828
    __ pop(rsi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4829
#endif
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4830
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4831
    __ leave(); // required for proper stackwalking of RuntimeStub frame
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4832
    __ ret(0);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4833
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4834
    return start;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4835
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4836
  }
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4837
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4838
  address generate_libmTan() {
47810
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4839
    StubCodeMark mark(this, "StubRoutines", "libmTan");
083c15bfba35 8190887: Stub code marking missing from some x86 generated stub routines
psandoz
parents: 47634
diff changeset
  4840
38018
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4841
    address start = __ pc();
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4842
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4843
    const XMMRegister x0 = xmm0;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4844
    const XMMRegister x1 = xmm1;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4845
    const XMMRegister x2 = xmm2;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4846
    const XMMRegister x3 = xmm3;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4847
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4848
    const XMMRegister x4 = xmm4;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4849
    const XMMRegister x5 = xmm5;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4850
    const XMMRegister x6 = xmm6;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4851
    const XMMRegister x7 = xmm7;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4852
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4853
    const Register tmp1 = r8;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4854
    const Register tmp2 = r9;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4855
    const Register tmp3 = r10;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4856
    const Register tmp4 = r11;
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4857
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4858
    BLOCK_COMMENT("Entry:");
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4859
    __ enter(); // required for proper stackwalking of RuntimeStub frame
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4860
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4861
#ifdef _WIN64
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4862
    __ push(rsi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4863
    __ push(rdi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4864
#endif
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4865
    __ fast_tan(x0, x1, x2, x3, x4, x5, x6, x7, rax, rcx, rdx, tmp1, tmp2, tmp3, tmp4);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4866
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4867
#ifdef _WIN64
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4868
    __ pop(rdi);
1dc6c6f21231 8152907: Update for x86 tan and log10 in the math lib
vdeshpande
parents: 36825
diff changeset
  4869
    __ pop(rsi);
35540
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4870
#endif
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4871
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4872
    __ leave(); // required for proper stackwalking of RuntimeStub frame
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4873
    __ ret(0);
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4874
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4875
    return start;
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4876
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4877
  }
e001ad24dcdb 8143353: update for x86 sin and cos in the math lib
vdeshpande
parents: 35537
diff changeset
  4878
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4879
#undef __
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4880
#define __ masm->
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4881
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4882
  // Continuation point for throwing of implicit exceptions that are
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4883
  // not handled in the current activation. Fabricates an exception
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4884
  // oop and initiates normal exception dispatching in this
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4885
  // frame. Since we need to preserve callee-saved values (currently
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4886
  // only for C2, but done for C1 as well) we need a callee-saved oop
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4887
  // map and therefore have to make these stubs into RuntimeStubs
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4888
  // rather than BufferBlobs.  If the compiler needs all registers to
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4889
  // be preserved between the fault point and the exception handler
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4890
  // then it must assume responsibility for that in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4891
  // AbstractCompiler::continuation_for_implicit_null_exception or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4892
  // continuation_for_implicit_division_by_zero_exception. All other
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4893
  // implicit exceptions (e.g., NullPointerException or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4894
  // AbstractMethodError on entry) are either at call sites or
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4895
  // otherwise assume that stack unwinding will be initiated, so
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4896
  // caller saved registers were assumed volatile in the compiler.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4897
  address generate_throw_exception(const char* name,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4898
                                   address runtime_entry,
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4899
                                   Register arg1 = noreg,
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4900
                                   Register arg2 = noreg) {
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4901
    // Information about frame layout at time of blocking runtime call.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4902
    // Note that we only have to preserve callee-saved registers since
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4903
    // the compilers are responsible for supplying a continuation point
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4904
    // if they expect all registers to be preserved.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4905
    enum layout {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4906
      rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4907
      rbp_off2,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4908
      return_off,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4909
      return_off2,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4910
      framesize // inclusive of return address
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4911
    };
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4912
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4913
    int insts_size = 512;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4914
    int locs_size  = 64;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4915
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4916
    CodeBuffer code(name, insts_size, locs_size);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4917
    OopMapSet* oop_maps  = new OopMapSet();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4918
    MacroAssembler* masm = new MacroAssembler(&code);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4919
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4920
    address start = __ pc();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4921
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4922
    // This is an inlined and slightly modified version of call_VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4923
    // which has the ability to fetch the return PC out of
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4924
    // thread-local storage and also sets up last_Java_sp slightly
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4925
    // differently than the real call_VM
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4926
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4927
    __ enter(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4928
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4929
    assert(is_even(framesize/2), "sp not 16-byte aligned");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4930
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4931
    // return address and rbp are already in place
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  4932
    __ subptr(rsp, (framesize-4) << LogBytesPerInt); // prolog
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4933
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4934
    int frame_complete = __ pc() - start;
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4935
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4936
    // Set up last_Java_sp and last_Java_fp
11725
49d1e1f1421f 7119286: JSR292: SIGSEGV in JNIHandleBlock::release_block(JNIHandleBlock*, Thread*)+0x3c
roland
parents: 11439
diff changeset
  4937
    address the_pc = __ pc();
49d1e1f1421f 7119286: JSR292: SIGSEGV in JNIHandleBlock::release_block(JNIHandleBlock*, Thread*)+0x3c
roland
parents: 11439
diff changeset
  4938
    __ set_last_Java_frame(rsp, rbp, the_pc);
49d1e1f1421f 7119286: JSR292: SIGSEGV in JNIHandleBlock::release_block(JNIHandleBlock*, Thread*)+0x3c
roland
parents: 11439
diff changeset
  4939
    __ andptr(rsp, -(StackAlignmentInBytes));    // Align stack
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4940
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4941
    // Call runtime
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4942
    if (arg1 != noreg) {
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4943
      assert(arg2 != c_rarg1, "clobbered");
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4944
      __ movptr(c_rarg1, arg1);
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4945
    }
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4946
    if (arg2 != noreg) {
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4947
      __ movptr(c_rarg2, arg2);
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  4948
    }
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  4949
    __ movptr(c_rarg0, r15_thread);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4950
    BLOCK_COMMENT("call runtime_entry");
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4951
    __ call(RuntimeAddress(runtime_entry));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4952
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4953
    // Generate oop map
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4954
    OopMap* map = new OopMap(framesize, 0);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4955
11785
10f778832544 7144405: JumbleGC002 assert(m->offset() == pc_offset) failed: oopmap not found
roland
parents: 11725
diff changeset
  4956
    oop_maps->add_gc_map(the_pc - start, map);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4957
40644
39e631ed7145 8161598: Kitchensink fails: assert(nm->insts_contains(original_pc)) failed: original PC must be in nmethod/CompiledMethod
dlong
parents: 38699
diff changeset
  4958
    __ reset_last_Java_frame(true);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4959
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4960
    __ leave(); // required for proper stackwalking of RuntimeStub frame
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4961
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4962
    // check for pending exceptions
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4963
#ifdef ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4964
    Label L;
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  4965
    __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()),
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  4966
            (int32_t) NULL_WORD);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4967
    __ jcc(Assembler::notEqual, L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4968
    __ should_not_reach_here();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4969
    __ bind(L);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4970
#endif // ASSERT
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4971
    __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4972
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4973
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4974
    // codeBlob framesize is in words (not VMRegImpl::slot_size)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4975
    RuntimeStub* stub =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4976
      RuntimeStub::new_runtime_stub(name,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4977
                                    &code,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4978
                                    frame_complete,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4979
                                    (framesize >> (LogBytesPerWord - LogBytesPerInt)),
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4980
                                    oop_maps, false);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4981
    return stub->entry_point();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4982
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  4983
18958
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4984
  void create_control_words() {
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4985
    // Round to nearest, 53-bit mode, exceptions masked
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4986
    StubRoutines::_fpu_cntrl_wrd_std   = 0x027F;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4987
    // Round to zero, 53-bit mode, exception mased
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4988
    StubRoutines::_fpu_cntrl_wrd_trunc = 0x0D7F;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4989
    // Round to nearest, 24-bit mode, exceptions masked
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4990
    StubRoutines::_fpu_cntrl_wrd_24    = 0x007F;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4991
    // Round to nearest, 64-bit mode, exceptions masked
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4992
    StubRoutines::_fpu_cntrl_wrd_64    = 0x037F;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4993
    // Round to nearest, 64-bit mode, exceptions masked
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4994
    StubRoutines::_mxcsr_std           = 0x1F80;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4995
    // Note: the following two constants are 80-bit values
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4996
    //       layout is critical for correct loading by FPU.
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4997
    // Bias for strict fp multiply/divide
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4998
    StubRoutines::_fpu_subnormal_bias1[0]= 0x00000000; // 2^(-15360) == 0x03ff 8000 0000 0000 0000
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  4999
    StubRoutines::_fpu_subnormal_bias1[1]= 0x80000000;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5000
    StubRoutines::_fpu_subnormal_bias1[2]= 0x03ff;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5001
    // Un-Bias for strict fp multiply/divide
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5002
    StubRoutines::_fpu_subnormal_bias2[0]= 0x00000000; // 2^(+15360) == 0x7bff 8000 0000 0000 0000
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5003
    StubRoutines::_fpu_subnormal_bias2[1]= 0x80000000;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5004
    StubRoutines::_fpu_subnormal_bias2[2]= 0x7bff;
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5005
  }
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5006
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5007
  // Initialization
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5008
  void generate_initial() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5009
    // Generates all stubs and initializes the entry points
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5010
18958
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5011
    // This platform-specific settings are needed by generate_call_stub()
7fdf6d23667d 8020433: Crash when using -XX:+RestoreMXCSROnJNICalls
kvn
parents: 18507
diff changeset
  5012
    create_control_words();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5013
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5014
    // entry points that exist in all platforms Note: This is code
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5015
    // that could be shared among different platforms - however the
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5016
    // benefit seems to be smaller than the disadvantage of having a
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5017
    // much more complicated generator structure. See also comment in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5018
    // stubRoutines.hpp.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5019
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5020
    StubRoutines::_forward_exception_entry = generate_forward_exception();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5021
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5022
    StubRoutines::_call_stub_entry =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5023
      generate_call_stub(StubRoutines::_call_stub_return_address);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5024
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5025
    // is referenced by megamorphic call
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5026
    StubRoutines::_catch_exception_entry = generate_catch_exception();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5027
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5028
    // atomic calls
48468
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5029
    StubRoutines::_atomic_xchg_entry          = generate_atomic_xchg();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5030
    StubRoutines::_atomic_xchg_long_entry     = generate_atomic_xchg_long();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5031
    StubRoutines::_atomic_cmpxchg_entry       = generate_atomic_cmpxchg();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5032
    StubRoutines::_atomic_cmpxchg_byte_entry  = generate_atomic_cmpxchg_byte();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5033
    StubRoutines::_atomic_cmpxchg_long_entry  = generate_atomic_cmpxchg_long();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5034
    StubRoutines::_atomic_add_entry           = generate_atomic_add();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5035
    StubRoutines::_atomic_add_long_entry      = generate_atomic_add_long();
7cc7de9bf4a4 8186903: Remove j-types from Atomic
coleenp
parents: 48104
diff changeset
  5036
    StubRoutines::_fence_entry                = generate_orderaccess_fence();
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5037
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5038
    // platform dependent
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5039
    StubRoutines::x86::_get_previous_fp_entry = generate_get_previous_fp();
11961
0abd4cd26e5a 7147740: add assertions to check stack alignment on VM entry from generated code (x64)
roland
parents: 11785
diff changeset
  5040
    StubRoutines::x86::_get_previous_sp_entry = generate_get_previous_sp();
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5041
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5042
    StubRoutines::x86::_verify_mxcsr_entry    = generate_verify_mxcsr();
10004
190e88f7edd1 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 8876
diff changeset
  5043
11411
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 11194
diff changeset
  5044
    // Build this early so it's available for the interpreter.
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 11194
diff changeset
  5045
    StubRoutines::_throw_StackOverflowError_entry =
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 11194
diff changeset
  5046
      generate_throw_exception("StackOverflowError throw_exception",
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 11194
diff changeset
  5047
                               CAST_FROM_FN_PTR(address,
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 11194
diff changeset
  5048
                                                SharedRuntime::
16b151e1e088 7116216: StackOverflow GC crash
bdelsart
parents: 11194
diff changeset
  5049
                                                throw_StackOverflowError));
35071
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34203
diff changeset
  5050
    StubRoutines::_throw_delayed_StackOverflowError_entry =
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34203
diff changeset
  5051
      generate_throw_exception("delayed StackOverflowError throw_exception",
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34203
diff changeset
  5052
                               CAST_FROM_FN_PTR(address,
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34203
diff changeset
  5053
                                                SharedRuntime::
a0910b1d3e0d 8046936: JEP 270: Reserved Stack Areas for Critical Sections
fparain
parents: 34203
diff changeset
  5054
                                                throw_delayed_StackOverflowError));
18507
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  5055
    if (UseCRC32Intrinsics) {
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  5056
      // set table address before stub generation which use it
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  5057
      StubRoutines::_crc_table_adr = (address)StubRoutines::x86::_crc_table;
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  5058
      StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32();
61bfc8995bb3 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 18073
diff changeset
  5059
    }
33066
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5060
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5061
    if (UseCRC32CIntrinsics) {
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5062
      bool supports_clmul = VM_Version::supports_clmul();
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5063
      StubRoutines::x86::generate_CRC32C_table(supports_clmul);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5064
      StubRoutines::_crc32c_table_addr = (address)StubRoutines::x86::_crc32c_table;
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5065
      StubRoutines::_updateBytesCRC32C = generate_updateBytesCRC32C(supports_clmul);
d98eab8215c4 8134553: CRC32C implementations for x86/x64 targets
kvn
parents: 32727
diff changeset
  5066
    }
42618
08162de8f053 8170430: x86 pow() stub from Intel libm is inconsistent with pow() from fdlib
vdeshpande
parents: 42039
diff changeset
  5067
    if (VM_Version::supports_sse2() && UseLibmIntrinsic && InlineIntrinsics) {
38699
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5068
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin) ||
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5069
          vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos) ||
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5070
          vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dtan)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5071
        StubRoutines::x86::_ONEHALF_adr = (address)StubRoutines::x86::_ONEHALF;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5072
        StubRoutines::x86::_P_2_adr = (address)StubRoutines::x86::_P_2;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5073
        StubRoutines::x86::_SC_4_adr = (address)StubRoutines::x86::_SC_4;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5074
        StubRoutines::x86::_Ctable_adr = (address)StubRoutines::x86::_Ctable;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5075
        StubRoutines::x86::_SC_2_adr = (address)StubRoutines::x86::_SC_2;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5076
        StubRoutines::x86::_SC_3_adr = (address)StubRoutines::x86::_SC_3;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5077
        StubRoutines::x86::_SC_1_adr = (address)StubRoutines::x86::_SC_1;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5078
        StubRoutines::x86::_PI_INV_TABLE_adr = (address)StubRoutines::x86::_PI_INV_TABLE;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5079
        StubRoutines::x86::_PI_4_adr = (address)StubRoutines::x86::_PI_4;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5080
        StubRoutines::x86::_PI32INV_adr = (address)StubRoutines::x86::_PI32INV;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5081
        StubRoutines::x86::_SIGN_MASK_adr = (address)StubRoutines::x86::_SIGN_MASK;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5082
        StubRoutines::x86::_P_1_adr = (address)StubRoutines::x86::_P_1;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5083
        StubRoutines::x86::_P_3_adr = (address)StubRoutines::x86::_P_3;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5084
        StubRoutines::x86::_NEG_ZERO_adr = (address)StubRoutines::x86::_NEG_ZERO;
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5085
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5086
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dexp)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5087
        StubRoutines::_dexp = generate_libmExp();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5088
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5089
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dlog)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5090
        StubRoutines::_dlog = generate_libmLog();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5091
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5092
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dlog10)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5093
        StubRoutines::_dlog10 = generate_libmLog10();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5094
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5095
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dpow)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5096
        StubRoutines::_dpow = generate_libmPow();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5097
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5098
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dsin)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5099
        StubRoutines::_dsin = generate_libmSin();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5100
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5101
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dcos)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5102
        StubRoutines::_dcos = generate_libmCos();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5103
      }
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5104
      if (vmIntrinsics::is_intrinsic_available(vmIntrinsics::_dtan)) {
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5105
        StubRoutines::_dtan = generate_libmTan();
f8bec5f6b09c 8154473: Update for CompilerDirectives to control stub generation and intrinsics
vdeshpande
parents: 38246
diff changeset
  5106
      }
33465
6063f28a6efb 8139575: Update for x86 log in the math lib
iveresov
parents: 33089
diff changeset
  5107
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5108
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5109
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5110
  void generate_all() {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5111
    // Generates all stubs and initializes the entry points
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5112
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5113
    // These entry points require SharedInfo::stack0 to be set up in
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5114
    // non-core builds and need to be relocatable, so they each
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5115
    // fabricate a RuntimeStub internally.
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5116
    StubRoutines::_throw_AbstractMethodError_entry =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5117
      generate_throw_exception("AbstractMethodError throw_exception",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5118
                               CAST_FROM_FN_PTR(address,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5119
                                                SharedRuntime::
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  5120
                                                throw_AbstractMethodError));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5121
189
4248c8e21063 6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents: 1
diff changeset
  5122
    StubRoutines::_throw_IncompatibleClassChangeError_entry =
4248c8e21063 6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents: 1
diff changeset
  5123
      generate_throw_exception("IncompatibleClassChangeError throw_exception",
4248c8e21063 6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents: 1
diff changeset
  5124
                               CAST_FROM_FN_PTR(address,
4248c8e21063 6664627: Merge changes made only in hotspot 11 forward to jdk 7
dcubed
parents: 1
diff changeset
  5125
                                                SharedRuntime::
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  5126
                                                throw_IncompatibleClassChangeError));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5127
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5128
    StubRoutines::_throw_NullPointerException_at_call_entry =
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5129
      generate_throw_exception("NullPointerException at call throw_exception",
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5130
                               CAST_FROM_FN_PTR(address,
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5131
                                                SharedRuntime::
10545
fec876499aae 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 10004
diff changeset
  5132
                                                throw_NullPointerException_at_call));
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5133
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5134
    // entry points that are platform specific
1066
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5135
    StubRoutines::x86::_f2i_fixup = generate_f2i_fixup();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5136
    StubRoutines::x86::_f2l_fixup = generate_f2l_fixup();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5137
    StubRoutines::x86::_d2i_fixup = generate_d2i_fixup();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5138
    StubRoutines::x86::_d2l_fixup = generate_d2l_fixup();
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5139
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5140
    StubRoutines::x86::_float_sign_mask  = generate_fp_mask("float_sign_mask",  0x7FFFFFFF7FFFFFFF);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5141
    StubRoutines::x86::_float_sign_flip  = generate_fp_mask("float_sign_flip",  0x8000000080000000);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5142
    StubRoutines::x86::_double_sign_mask = generate_fp_mask("double_sign_mask", 0x7FFFFFFFFFFFFFFF);
717c3345024f 5108146: Merge i486 and amd64 cpu directories
never
parents: 957
diff changeset
  5143
    StubRoutines::x86::_double_sign_flip = generate_fp_mask("double_sign_flip", 0x8000000000000000);
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5144
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5145
    // support for verify_oop (must happen after universe_init)
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5146
    StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5147
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5148
    // arraycopy stubs used by compilers
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5149
    generate_arraycopy_stubs();
4478
c3a8af0fc6b0 6829192: JSR 292 needs to support 64-bit x86
twisti
parents: 3262
diff changeset
  5150
14132
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5151
    // don't bother generating these AES intrinsic stubs unless global flag is set
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5152
    if (UseAESIntrinsics) {
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5153
      StubRoutines::x86::_key_shuffle_mask_addr = generate_key_shuffle_mask();  // needed by the others
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5154
      StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5155
      StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5156
      StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5157
      StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt_Parallel();
3c1437abcefd 7184394: add intrinsics to use AES instructions
kvn
parents: 13952
diff changeset
  5158
    }
35154
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  5159
    if (UseAESCTRIntrinsics){
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  5160
      StubRoutines::x86::_counter_shuffle_mask_addr = generate_counter_shuffle_mask();
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  5161
      StubRoutines::_counterMode_AESCrypt = generate_counterMode_AESCrypt_Parallel();
a9b3c1984a01 8143925: Enhancing CounterMode.crypt() for AES
kvn
parents: 35146
diff changeset
  5162
    }
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5163
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5164
    if (UseSHA1Intrinsics) {
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5165
      StubRoutines::x86::_upper_word_mask_addr = generate_upper_word_mask();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5166
      StubRoutines::x86::_shuffle_byte_flip_mask_addr = generate_shuffle_byte_flip_mask();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5167
      StubRoutines::_sha1_implCompress = generate_sha1_implCompress(false, "sha1_implCompress");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5168
      StubRoutines::_sha1_implCompressMB = generate_sha1_implCompress(true, "sha1_implCompressMB");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5169
    }
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5170
    if (UseSHA256Intrinsics) {
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5171
      StubRoutines::x86::_k256_adr = (address)StubRoutines::x86::_k256;
38135
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5172
      char* dst = (char*)StubRoutines::x86::_k256_W;
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5173
      char* src = (char*)StubRoutines::x86::_k256;
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5174
      for (int ii = 0; ii < 16; ++ii) {
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5175
        memcpy(dst + 32 * ii,      src + 16 * ii, 16);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5176
        memcpy(dst + 32 * ii + 16, src + 16 * ii, 16);
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5177
      }
e06e2d071465 8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents: 38051
diff changeset
  5178
      StubRoutines::x86::_k256_W_adr = (address)StubRoutines::x86::_k256_W;
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5179
      StubRoutines::x86::_pshuffle_byte_flip_mask_addr = generate_pshuffle_byte_flip_mask();
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5180
      StubRoutines::_sha256_implCompress = generate_sha256_implCompress(false, "sha256_implCompress");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5181
      StubRoutines::_sha256_implCompressMB = generate_sha256_implCompress(true, "sha256_implCompressMB");
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5182
    }
42039
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  5183
    if (UseSHA512Intrinsics) {
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  5184
      StubRoutines::x86::_k512_W_addr = (address)StubRoutines::x86::_k512_W;
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  5185
      StubRoutines::x86::_pshuffle_byte_flip_mask_addr_sha512 = generate_pshuffle_byte_flip_mask_sha512();
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  5186
      StubRoutines::_sha512_implCompress = generate_sha512_implCompress(false, "sha512_implCompress");
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  5187
      StubRoutines::_sha512_implCompressMB = generate_sha512_implCompress(true, "sha512_implCompressMB");
db627462f2c9 8165381: Update for x86 SHA512 using AVX2
kvn
parents: 41333
diff changeset
  5188
    }
36555
4f37fd7a5a09 8150767: Enables SHA Extensions on x86
vdeshpande
parents: 35540
diff changeset
  5189
31404
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5190
    // Generate GHASH intrinsics code
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5191
    if (UseGHASHIntrinsics) {
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5192
      StubRoutines::x86::_ghash_long_swap_mask_addr = generate_ghash_long_swap_mask();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5193
      StubRoutines::x86::_ghash_byte_swap_mask_addr = generate_ghash_byte_swap_mask();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5194
      StubRoutines::_ghash_processBlocks = generate_ghash_processBlocks();
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5195
    }
63e8fcd70bfc 8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents: 31129
diff changeset
  5196
18740
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5197
    // Safefetch stubs.
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5198
    generate_safefetch("SafeFetch32", sizeof(int),     &StubRoutines::_safefetch32_entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5199
                                                       &StubRoutines::_safefetch32_fault_pc,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5200
                                                       &StubRoutines::_safefetch32_continuation_pc);
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5201
    generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5202
                                                       &StubRoutines::_safefetchN_fault_pc,
db44b1599483 8016697: Use stubs to implement safefetch
goetz
parents: 18507
diff changeset
  5203
                                                       &StubRoutines::_safefetchN_continuation_pc);
26434
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  5204
#ifdef COMPILER2
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  5205
    if (UseMultiplyToLenIntrinsic) {
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  5206
      StubRoutines::_multiplyToLen = generate_multiplyToLen();
09ad55e5f486 8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents: 22505
diff changeset
  5207
    }
31129
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  5208
    if (UseSquareToLenIntrinsic) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  5209
      StubRoutines::_squareToLen = generate_squareToLen();
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  5210
    }
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  5211
    if (UseMulAddIntrinsic) {
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  5212
      StubRoutines::_mulAdd = generate_mulAdd();
02ee7609f0e1 8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents: 30624
diff changeset
  5213
    }
31583
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5214
#ifndef _WINDOWS
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5215
    if (UseMontgomeryMultiplyIntrinsic) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5216
      StubRoutines::_montgomeryMultiply
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5217
        = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_multiply);
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5218
    }
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5219
    if (UseMontgomerySquareIntrinsic) {
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5220
      StubRoutines::_montgomerySquare
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5221
        = CAST_FROM_FN_PTR(address, SharedRuntime::montgomery_square);
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5222
    }
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5223
#endif // WINDOWS
eb5bea7b4835 8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents: 31129
diff changeset
  5224
#endif // COMPILER2
38238
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  5225
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  5226
    if (UseVectorizedMismatchIntrinsic) {
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  5227
      StubRoutines::_vectorizedMismatch = generate_vectorizedMismatch();
1bbcc430c78d 8151268: Wire up the x86 _vectorizedMismatch stub routine in C1
psandoz
parents: 38135
diff changeset
  5228
    }
1
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5229
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5230
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5231
 public:
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5232
  StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5233
    if (all) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5234
      generate_all();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5235
    } else {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5236
      generate_initial();
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5237
    }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5238
  }
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5239
}; // end class declaration
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5240
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5241
void StubGenerator_generate(CodeBuffer* code, bool all) {
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5242
  StubGenerator g(code, all);
489c9b5090e2 Initial load
duke
parents:
diff changeset
  5243
}