author | kvn |
Mon, 01 Oct 2018 11:54:34 -0700 | |
changeset 51976 | 390f529f4f22 |
parent 51868 | 92960b0e6191 |
child 52573 | 6e8c1206cca1 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#include "precompiled.hpp" |
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#include "jvm.h" |
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#include "asm/macroAssembler.hpp" |
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#include "asm/macroAssembler.inline.hpp" |
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#include "logging/log.hpp" |
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#include "logging/logStream.hpp" |
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#include "memory/resourceArea.hpp" |
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#include "runtime/java.hpp" |
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#include "runtime/os.hpp" |
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#include "runtime/stubCodeGenerator.hpp" |
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#include "vm_version_x86.hpp" |
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int VM_Version::_cpu; |
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int VM_Version::_model; |
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int VM_Version::_stepping; |
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VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; |
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// Address of instruction which causes SEGV |
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address VM_Version::_cpuinfo_segv_addr = 0; |
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// Address of instruction after the one which causes SEGV |
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address VM_Version::_cpuinfo_cont_addr = 0; |
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static BufferBlob* stub_blob; |
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static const int stub_size = 1100; |
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extern "C" { |
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typedef void (*get_cpu_info_stub_t)(void*); |
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} |
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static get_cpu_info_stub_t get_cpu_info_stub = NULL; |
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class VM_Version_StubGenerator: public StubCodeGenerator { |
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public: |
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VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} |
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address generate_get_cpu_info() { |
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// Flags to test CPU type. |
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const uint32_t HS_EFL_AC = 0x40000; |
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const uint32_t HS_EFL_ID = 0x200000; |
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// Values for when we don't have a CPUID instruction. |
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const int CPU_FAMILY_SHIFT = 8; |
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const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); |
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const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); |
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bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2); |
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Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
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Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup; |
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Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check; |
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StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); |
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# define __ _masm-> |
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address start = __ pc(); |
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// |
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// void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); |
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// |
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// LP64: rcx and rdx are first and second argument registers on windows |
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__ push(rbp); |
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#ifdef _LP64 |
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__ mov(rbp, c_rarg0); // cpuid_info address |
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#else |
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__ movptr(rbp, Address(rsp, 8)); // cpuid_info address |
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#endif |
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__ push(rbx); |
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__ push(rsi); |
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__ pushf(); // preserve rbx, and flags |
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__ pop(rax); |
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__ push(rax); |
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__ mov(rcx, rax); |
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// |
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// if we are unable to change the AC flag, we have a 386 |
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// |
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__ xorl(rax, HS_EFL_AC); |
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__ push(rax); |
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__ popf(); |
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__ pushf(); |
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__ pop(rax); |
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__ cmpptr(rax, rcx); |
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__ jccb(Assembler::notEqual, detect_486); |
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__ movl(rax, CPU_FAMILY_386); |
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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__ jmp(done); |
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// |
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// If we are unable to change the ID flag, we have a 486 which does |
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// not support the "cpuid" instruction. |
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// |
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__ bind(detect_486); |
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__ mov(rax, rcx); |
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__ xorl(rax, HS_EFL_ID); |
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__ push(rax); |
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__ popf(); |
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__ pushf(); |
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__ pop(rax); |
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__ cmpptr(rcx, rax); |
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__ jccb(Assembler::notEqual, detect_586); |
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__ bind(cpu486); |
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__ movl(rax, CPU_FAMILY_486); |
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__ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); |
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__ jmp(done); |
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// |
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// At this point, we have a chip which supports the "cpuid" instruction |
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// |
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__ bind(detect_586); |
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__ xorl(rax, rax); |
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__ cpuid(); |
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__ orl(rax, rax); |
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__ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input |
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// value of at least 1, we give up and |
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// assume a 486 |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
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__ jccb(Assembler::belowEqual, std_cpuid4); |
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// |
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// cpuid(0xB) Processor Topology |
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// |
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__ movl(rax, 0xb); |
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__ xorl(rcx, rcx); // Threads level |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ movl(rax, 0xb); |
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__ movl(rcx, 1); // Cores level |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid topology level |
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__ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
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__ andl(rax, 0xffff); |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid4); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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__ movl(rax, 0xb); |
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__ movl(rcx, 2); // Packages level |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid topology level |
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__ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level |
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__ andl(rax, 0xffff); |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid4); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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// |
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// cpuid(0x4) Deterministic cache params |
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// |
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__ bind(std_cpuid4); |
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__ movl(rax, 4); |
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__ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
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__ jccb(Assembler::greater, std_cpuid1); |
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__ xorl(rcx, rcx); // L1 cache |
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__ cpuid(); |
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__ push(rax); |
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__ andl(rax, 0x1f); // Determine if valid cache parameters used |
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__ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache |
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__ pop(rax); |
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__ jccb(Assembler::equal, std_cpuid1); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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||
218 |
// |
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// Standard cpuid(0x1) |
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// |
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__ bind(std_cpuid1); |
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__ movl(rax, 1); |
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__ cpuid(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rbx); |
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__ movl(Address(rsi, 8), rcx); |
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__ movl(Address(rsi,12), rdx); |
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||
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// |
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// Check if OS has enabled XGETBV instruction to access XCR0 |
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// (OSXSAVE feature flag) and CPU supports AVX |
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// |
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__ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx |
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__ cmpl(rcx, 0x18000000); |
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__ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported |
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238 |
// |
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239 |
// XCR0, XFEATURE_ENABLED_MASK register |
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240 |
// |
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241 |
__ xorl(rcx, rcx); // zero for XCR0 register |
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__ xgetbv(); |
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__ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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__ movl(Address(rsi, 4), rdx); |
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||
247 |
// |
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248 |
// cpuid(0x7) Structured Extended Features |
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249 |
// |
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250 |
__ bind(sef_cpuid); |
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251 |
__ movl(rax, 7); |
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252 |
__ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? |
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__ jccb(Assembler::greater, ext_cpuid); |
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254 |
||
255 |
__ xorl(rcx, rcx); |
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256 |
__ cpuid(); |
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257 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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259 |
__ movl(Address(rsi, 4), rbx); |
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49384 | 260 |
__ movl(Address(rsi, 8), rcx); |
261 |
__ movl(Address(rsi, 12), rdx); |
|
11427 | 262 |
|
263 |
// |
|
264 |
// Extended cpuid(0x80000000) |
|
265 |
// |
|
266 |
__ bind(ext_cpuid); |
|
2111 | 267 |
__ movl(rax, 0x80000000); |
268 |
__ cpuid(); |
|
269 |
__ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? |
|
270 |
__ jcc(Assembler::belowEqual, done); |
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271 |
__ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? |
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__ jcc(Assembler::belowEqual, ext_cpuid1); |
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__ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid5); |
2111 | 275 |
__ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid7); |
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__ cmpl(rax, 0x80000008); // Is cpuid(0x80000009 and above) supported? |
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__ jccb(Assembler::belowEqual, ext_cpuid8); |
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__ cmpl(rax, 0x8000001E); // Is cpuid(0x8000001E) supported? |
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__ jccb(Assembler::below, ext_cpuid8); |
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// |
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// Extended cpuid(0x8000001E) |
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// |
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__ movl(rax, 0x8000001E); |
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__ cpuid(); |
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286 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset()))); |
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__ movl(Address(rsi, 0), rax); |
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47216
diff
changeset
|
288 |
__ movl(Address(rsi, 4), rbx); |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
289 |
__ movl(Address(rsi, 8), rcx); |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
290 |
__ movl(Address(rsi,12), rdx); |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
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diff
changeset
|
291 |
|
2111 | 292 |
// |
293 |
// Extended cpuid(0x80000008) |
|
294 |
// |
|
47582
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
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diff
changeset
|
295 |
__ bind(ext_cpuid8); |
2111 | 296 |
__ movl(rax, 0x80000008); |
297 |
__ cpuid(); |
|
298 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); |
|
299 |
__ movl(Address(rsi, 0), rax); |
|
300 |
__ movl(Address(rsi, 4), rbx); |
|
301 |
__ movl(Address(rsi, 8), rcx); |
|
302 |
__ movl(Address(rsi,12), rdx); |
|
303 |
||
304 |
// |
|
11417
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
305 |
// Extended cpuid(0x80000007) |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
306 |
// |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
307 |
__ bind(ext_cpuid7); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
308 |
__ movl(rax, 0x80000007); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
309 |
__ cpuid(); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
310 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
311 |
__ movl(Address(rsi, 0), rax); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
312 |
__ movl(Address(rsi, 4), rbx); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
313 |
__ movl(Address(rsi, 8), rcx); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
314 |
__ movl(Address(rsi,12), rdx); |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
315 |
|
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
316 |
// |
2111 | 317 |
// Extended cpuid(0x80000005) |
318 |
// |
|
319 |
__ bind(ext_cpuid5); |
|
320 |
__ movl(rax, 0x80000005); |
|
321 |
__ cpuid(); |
|
322 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); |
|
323 |
__ movl(Address(rsi, 0), rax); |
|
324 |
__ movl(Address(rsi, 4), rbx); |
|
325 |
__ movl(Address(rsi, 8), rcx); |
|
326 |
__ movl(Address(rsi,12), rdx); |
|
327 |
||
328 |
// |
|
329 |
// Extended cpuid(0x80000001) |
|
330 |
// |
|
331 |
__ bind(ext_cpuid1); |
|
332 |
__ movl(rax, 0x80000001); |
|
333 |
__ cpuid(); |
|
334 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); |
|
335 |
__ movl(Address(rsi, 0), rax); |
|
336 |
__ movl(Address(rsi, 4), rbx); |
|
337 |
__ movl(Address(rsi, 8), rcx); |
|
338 |
__ movl(Address(rsi,12), rdx); |
|
339 |
||
340 |
// |
|
30624 | 341 |
// Check if OS has enabled XGETBV instruction to access XCR0 |
342 |
// (OSXSAVE feature flag) and CPU supports AVX |
|
343 |
// |
|
344 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
|
345 |
__ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx |
|
346 |
__ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx |
|
347 |
__ cmpl(rcx, 0x18000000); |
|
348 |
__ jccb(Assembler::notEqual, done); // jump if AVX is not supported |
|
349 |
||
350 |
__ movl(rax, 0x6); |
|
351 |
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm |
|
352 |
__ cmpl(rax, 0x6); |
|
353 |
__ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported |
|
354 |
||
355 |
// we need to bridge farther than imm8, so we use this island as a thunk |
|
356 |
__ bind(done); |
|
357 |
__ jmp(wrapup); |
|
358 |
||
359 |
__ bind(start_simd_check); |
|
360 |
// |
|
361 |
// Some OSs have a bug when upper 128/256bits of YMM/ZMM |
|
362 |
// registers are not restored after a signal processing. |
|
363 |
// Generate SEGV here (reference through NULL) |
|
364 |
// and check upper YMM/ZMM bits after it. |
|
2111 | 365 |
// |
30624 | 366 |
intx saved_useavx = UseAVX; |
367 |
intx saved_usesse = UseSSE; |
|
368 |
// check _cpuid_info.sef_cpuid7_ebx.bits.avx512f |
|
369 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
|
370 |
__ movl(rax, 0x10000); |
|
371 |
__ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm |
|
372 |
__ cmpl(rax, 0x10000); |
|
373 |
__ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported |
|
374 |
// check _cpuid_info.xem_xcr0_eax.bits.opmask |
|
375 |
// check _cpuid_info.xem_xcr0_eax.bits.zmm512 |
|
376 |
// check _cpuid_info.xem_xcr0_eax.bits.zmm32 |
|
377 |
__ movl(rax, 0xE0); |
|
378 |
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm |
|
379 |
__ cmpl(rax, 0xE0); |
|
380 |
__ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported |
|
381 |
||
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
382 |
// If UseAVX is unitialized or is set by the user to include EVEX |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
383 |
if (use_evex) { |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
384 |
// EVEX setup: run in lowest evex mode |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
385 |
VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
386 |
UseAVX = 3; |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
387 |
UseSSE = 2; |
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
388 |
#ifdef _WINDOWS |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
389 |
// xmm5-xmm15 are not preserved by caller on windows |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
390 |
// https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
391 |
__ subptr(rsp, 64); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
392 |
__ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit); |
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
393 |
#ifdef _LP64 |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
394 |
__ subptr(rsp, 64); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
395 |
__ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
396 |
__ subptr(rsp, 64); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
397 |
__ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit); |
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
398 |
#endif // _LP64 |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
399 |
#endif // _WINDOWS |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
400 |
|
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
401 |
// load value into all 64 bytes of zmm7 register |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
402 |
__ movl(rcx, VM_Version::ymm_test_value()); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
403 |
__ movdl(xmm0, rcx); |
51857 | 404 |
__ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit); |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
405 |
__ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit); |
30624 | 406 |
#ifdef _LP64 |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
407 |
__ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
408 |
__ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit); |
30624 | 409 |
#endif |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
410 |
VM_Version::clean_cpuFeatures(); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
411 |
__ jmp(save_restore_except); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
412 |
} |
30624 | 413 |
|
414 |
__ bind(legacy_setup); |
|
415 |
// AVX setup |
|
416 |
VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts |
|
417 |
UseAVX = 1; |
|
418 |
UseSSE = 2; |
|
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
419 |
#ifdef _WINDOWS |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
420 |
__ subptr(rsp, 32); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
421 |
__ vmovdqu(Address(rsp, 0), xmm7); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
422 |
#ifdef _LP64 |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
423 |
__ subptr(rsp, 32); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
424 |
__ vmovdqu(Address(rsp, 0), xmm8); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
425 |
__ subptr(rsp, 32); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
426 |
__ vmovdqu(Address(rsp, 0), xmm15); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
427 |
#endif // _LP64 |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
428 |
#endif // _WINDOWS |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
429 |
|
30624 | 430 |
// load value into all 32 bytes of ymm7 register |
431 |
__ movl(rcx, VM_Version::ymm_test_value()); |
|
432 |
||
433 |
__ movdl(xmm0, rcx); |
|
434 |
__ pshufd(xmm0, xmm0, 0x00); |
|
36561
b18243f4d955
8151002: Make Assembler methods vextract and vinsert match actual instructions
mikael
parents:
36555
diff
changeset
|
435 |
__ vinsertf128_high(xmm0, xmm0); |
30624 | 436 |
__ vmovdqu(xmm7, xmm0); |
437 |
#ifdef _LP64 |
|
438 |
__ vmovdqu(xmm8, xmm0); |
|
439 |
__ vmovdqu(xmm15, xmm0); |
|
440 |
#endif |
|
441 |
VM_Version::clean_cpuFeatures(); |
|
442 |
||
443 |
__ bind(save_restore_except); |
|
444 |
__ xorl(rsi, rsi); |
|
445 |
VM_Version::set_cpuinfo_segv_addr(__ pc()); |
|
446 |
// Generate SEGV |
|
447 |
__ movl(rax, Address(rsi, 0)); |
|
448 |
||
449 |
VM_Version::set_cpuinfo_cont_addr(__ pc()); |
|
450 |
// Returns here after signal. Save xmm0 to check it later. |
|
451 |
||
452 |
// check _cpuid_info.sef_cpuid7_ebx.bits.avx512f |
|
453 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); |
|
454 |
__ movl(rax, 0x10000); |
|
455 |
__ andl(rax, Address(rsi, 4)); |
|
456 |
__ cmpl(rax, 0x10000); |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
457 |
__ jcc(Assembler::notEqual, legacy_save_restore); |
30624 | 458 |
// check _cpuid_info.xem_xcr0_eax.bits.opmask |
459 |
// check _cpuid_info.xem_xcr0_eax.bits.zmm512 |
|
460 |
// check _cpuid_info.xem_xcr0_eax.bits.zmm32 |
|
461 |
__ movl(rax, 0xE0); |
|
462 |
__ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm |
|
463 |
__ cmpl(rax, 0xE0); |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
464 |
__ jcc(Assembler::notEqual, legacy_save_restore); |
30624 | 465 |
|
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
466 |
// If UseAVX is unitialized or is set by the user to include EVEX |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
467 |
if (use_evex) { |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
468 |
// EVEX check: run in lowest evex mode |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
469 |
VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
470 |
UseAVX = 3; |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
471 |
UseSSE = 2; |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
472 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset()))); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
473 |
__ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
474 |
__ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit); |
30624 | 475 |
#ifdef _LP64 |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
476 |
__ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
477 |
__ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit); |
30624 | 478 |
#endif |
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
479 |
|
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
480 |
#ifdef _WINDOWS |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
481 |
#ifdef _LP64 |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
482 |
__ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
483 |
__ addptr(rsp, 64); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
484 |
__ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
485 |
__ addptr(rsp, 64); |
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
486 |
#endif // _LP64 |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
487 |
__ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
488 |
__ addptr(rsp, 64); |
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
489 |
#endif // _WINDOWS |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
490 |
generate_vzeroupper(wrapup); |
42586
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
491 |
VM_Version::clean_cpuFeatures(); |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
492 |
UseAVX = saved_useavx; |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
493 |
UseSSE = saved_usesse; |
e14fee6a1839
8170039: Change UseAVX < 3 on SKX/KNL to not emit evex vector check
mcberg
parents:
42076
diff
changeset
|
494 |
__ jmp(wrapup); |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
495 |
} |
30624 | 496 |
|
497 |
__ bind(legacy_save_restore); |
|
498 |
// AVX check |
|
499 |
VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts |
|
500 |
UseAVX = 1; |
|
501 |
UseSSE = 2; |
|
502 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); |
|
503 |
__ vmovdqu(Address(rsi, 0), xmm0); |
|
504 |
__ vmovdqu(Address(rsi, 32), xmm7); |
|
505 |
#ifdef _LP64 |
|
506 |
__ vmovdqu(Address(rsi, 64), xmm8); |
|
507 |
__ vmovdqu(Address(rsi, 96), xmm15); |
|
508 |
#endif |
|
42076
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
509 |
|
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
510 |
#ifdef _WINDOWS |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
511 |
#ifdef _LP64 |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
512 |
__ vmovdqu(xmm15, Address(rsp, 0)); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
513 |
__ addptr(rsp, 32); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
514 |
__ vmovdqu(xmm8, Address(rsp, 0)); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
515 |
__ addptr(rsp, 32); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
516 |
#endif // _LP64 |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
517 |
__ vmovdqu(xmm7, Address(rsp, 0)); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
518 |
__ addptr(rsp, 32); |
d6c3ecec1d34
8067744: XMM/SSE float register values corrupted by JNI_CreateVM call in JRE 8 (Windows)
kvn
parents:
42039
diff
changeset
|
519 |
#endif // _WINDOWS |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
520 |
generate_vzeroupper(wrapup); |
30624 | 521 |
VM_Version::clean_cpuFeatures(); |
522 |
UseAVX = saved_useavx; |
|
523 |
UseSSE = saved_usesse; |
|
524 |
||
525 |
__ bind(wrapup); |
|
2111 | 526 |
__ popf(); |
527 |
__ pop(rsi); |
|
528 |
__ pop(rbx); |
|
529 |
__ pop(rbp); |
|
530 |
__ ret(0); |
|
531 |
||
532 |
# undef __ |
|
533 |
||
534 |
return start; |
|
535 |
}; |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
536 |
void generate_vzeroupper(Label& L_wrapup) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
537 |
# define __ _masm-> |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
538 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
539 |
__ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG' |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
540 |
__ jcc(Assembler::notEqual, L_wrapup); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
541 |
__ movl(rcx, 0x0FFF0FF0); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
542 |
__ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
543 |
__ andl(rcx, Address(rsi, 0)); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
544 |
__ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200 |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
545 |
__ jcc(Assembler::equal, L_wrapup); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
546 |
__ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
547 |
__ jcc(Assembler::equal, L_wrapup); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
548 |
__ vzeroupper(); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
549 |
# undef __ |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
550 |
} |
2111 | 551 |
}; |
552 |
||
553 |
void VM_Version::get_processor_features() { |
|
554 |
||
555 |
_cpu = 4; // 486 by default |
|
556 |
_model = 0; |
|
557 |
_stepping = 0; |
|
35148 | 558 |
_features = 0; |
2111 | 559 |
_logical_processors_per_package = 1; |
25633
4cd9c4622c8c
8049717: expose L1_data_cache_line_size for diagnostic/sanity checks
dcubed
parents:
25468
diff
changeset
|
560 |
// i486 internal cache is both I&D and has a 16-byte line size |
4cd9c4622c8c
8049717: expose L1_data_cache_line_size for diagnostic/sanity checks
dcubed
parents:
25468
diff
changeset
|
561 |
_L1_data_cache_line_size = 16; |
2111 | 562 |
|
35102 | 563 |
// Get raw processor info |
23527
397b6816032d
8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents:
23491
diff
changeset
|
564 |
|
35102 | 565 |
get_cpu_info_stub(&_cpuid_info); |
23527
397b6816032d
8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents:
23491
diff
changeset
|
566 |
|
35102 | 567 |
assert_is_initialized(); |
568 |
_cpu = extended_cpu_family(); |
|
569 |
_model = extended_cpu_model(); |
|
570 |
_stepping = cpu_stepping(); |
|
2111 | 571 |
|
35102 | 572 |
if (cpu_family() > 4) { // it supports CPUID |
35148 | 573 |
_features = feature_flags(); |
35102 | 574 |
// Logical processors are only available on P4s and above, |
575 |
// and only if hyperthreading is available. |
|
576 |
_logical_processors_per_package = logical_processor_count(); |
|
577 |
_L1_data_cache_line_size = L1_line_size(); |
|
2111 | 578 |
} |
579 |
||
580 |
_supports_cx8 = supports_cmpxchg8(); |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
581 |
// xchg and xadd instructions |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
582 |
_supports_atomic_getset4 = true; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
583 |
_supports_atomic_getadd4 = true; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
584 |
LP64_ONLY(_supports_atomic_getset8 = true); |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13885
diff
changeset
|
585 |
LP64_ONLY(_supports_atomic_getadd8 = true); |
2111 | 586 |
|
587 |
#ifdef _LP64 |
|
588 |
// OS should support SSE for x64 and hardware should support at least SSE2. |
|
589 |
if (!VM_Version::supports_sse2()) { |
|
590 |
vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); |
|
591 |
} |
|
4430 | 592 |
// in 64 bit the use of SSE2 is the minimum |
593 |
if (UseSSE < 2) UseSSE = 2; |
|
2111 | 594 |
#endif |
595 |
||
10010
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
596 |
#ifdef AMD64 |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
597 |
// flush_icache_stub have to be generated first. |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
598 |
// That is why Icache line size is hard coded in ICache class, |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
599 |
// see icache_x86.hpp. It is also the reason why we can't use |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
600 |
// clflush instruction in 32-bit VM since it could be running |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
601 |
// on CPU which does not support it. |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
602 |
// |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
603 |
// The only thing we can do is to verify that flushed |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
604 |
// ICache::line_size has correct value. |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
605 |
guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
606 |
// clflush_size is size in quadwords (8 bytes). |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
607 |
guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
608 |
#endif |
72de7c910672
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
9325
diff
changeset
|
609 |
|
2111 | 610 |
// If the OS doesn't support SSE, we can't use this feature even if the HW does |
611 |
if (!os::supports_sse()) |
|
35148 | 612 |
_features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); |
2111 | 613 |
|
614 |
if (UseSSE < 4) { |
|
35148 | 615 |
_features &= ~CPU_SSE4_1; |
616 |
_features &= ~CPU_SSE4_2; |
|
2111 | 617 |
} |
618 |
||
619 |
if (UseSSE < 3) { |
|
35148 | 620 |
_features &= ~CPU_SSE3; |
621 |
_features &= ~CPU_SSSE3; |
|
622 |
_features &= ~CPU_SSE4A; |
|
2111 | 623 |
} |
624 |
||
625 |
if (UseSSE < 2) |
|
35148 | 626 |
_features &= ~CPU_SSE2; |
2111 | 627 |
|
628 |
if (UseSSE < 1) |
|
35148 | 629 |
_features &= ~CPU_SSE; |
2111 | 630 |
|
48489
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
631 |
//since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0. |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
632 |
if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
633 |
UseAVX = 0; |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
634 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
635 |
|
30624 | 636 |
// first try initial setting and detect what we can support |
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
637 |
int use_avx_limit = 0; |
30624 | 638 |
if (UseAVX > 0) { |
639 |
if (UseAVX > 2 && supports_evex()) { |
|
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
640 |
use_avx_limit = 3; |
30624 | 641 |
} else if (UseAVX > 1 && supports_avx2()) { |
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
642 |
use_avx_limit = 2; |
30624 | 643 |
} else if (UseAVX > 0 && supports_avx()) { |
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
644 |
use_avx_limit = 1; |
30624 | 645 |
} else { |
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
646 |
use_avx_limit = 0; |
30624 | 647 |
} |
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
648 |
} |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
649 |
if (FLAG_IS_DEFAULT(UseAVX)) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
650 |
FLAG_SET_DEFAULT(UseAVX, use_avx_limit); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
651 |
} else if (UseAVX > use_avx_limit) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
652 |
warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
653 |
FLAG_SET_DEFAULT(UseAVX, use_avx_limit); |
30624 | 654 |
} else if (UseAVX < 0) { |
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
655 |
warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
656 |
FLAG_SET_DEFAULT(UseAVX, 0); |
30624 | 657 |
} |
658 |
||
659 |
if (UseAVX < 3) { |
|
35148 | 660 |
_features &= ~CPU_AVX512F; |
661 |
_features &= ~CPU_AVX512DQ; |
|
662 |
_features &= ~CPU_AVX512CD; |
|
663 |
_features &= ~CPU_AVX512BW; |
|
664 |
_features &= ~CPU_AVX512VL; |
|
49384 | 665 |
_features &= ~CPU_AVX512_VPOPCNTDQ; |
49614
3b1570be8557
8200067: Add support for vpclmulqdq for crc32
srukmannagar
parents:
49384
diff
changeset
|
666 |
_features &= ~CPU_VPCLMULQDQ; |
50699
cc7fc46cc8c1
8205398: AES-CBC decryption algorithm using AVX512 instructions
kvn
parents:
50534
diff
changeset
|
667 |
_features &= ~CPU_VAES; |
30624 | 668 |
} |
669 |
||
11427 | 670 |
if (UseAVX < 2) |
35148 | 671 |
_features &= ~CPU_AVX2; |
11427 | 672 |
|
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
673 |
if (UseAVX < 1) { |
35148 | 674 |
_features &= ~CPU_AVX; |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
675 |
_features &= ~CPU_VZEROUPPER; |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
676 |
} |
11427 | 677 |
|
2111 | 678 |
if (logical_processors_per_package() == 1) { |
679 |
// HT processor could be installed on a system which doesn't support HT. |
|
35148 | 680 |
_features &= ~CPU_HT; |
2111 | 681 |
} |
682 |
||
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
683 |
if( is_intel() ) { // Intel cpus specific settings |
46563
cfca8fbb4051
8182138: Disable generating INC and DEC instructions on Xeon Phi and ATOM CPUs
kvn
parents:
46560
diff
changeset
|
684 |
if (is_knights_family()) { |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
685 |
_features &= ~CPU_VZEROUPPER; |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
686 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
687 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
688 |
|
2111 | 689 |
char buf[256]; |
41323 | 690 |
jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
2111 | 691 |
cores_per_cpu(), threads_per_core(), |
692 |
cpu_family(), _model, _stepping, |
|
693 |
(supports_cmov() ? ", cmov" : ""), |
|
694 |
(supports_cmpxchg8() ? ", cx8" : ""), |
|
695 |
(supports_fxsr() ? ", fxsr" : ""), |
|
696 |
(supports_mmx() ? ", mmx" : ""), |
|
697 |
(supports_sse() ? ", sse" : ""), |
|
698 |
(supports_sse2() ? ", sse2" : ""), |
|
699 |
(supports_sse3() ? ", sse3" : ""), |
|
700 |
(supports_ssse3()? ", ssse3": ""), |
|
701 |
(supports_sse4_1() ? ", sse4.1" : ""), |
|
702 |
(supports_sse4_2() ? ", sse4.2" : ""), |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
703 |
(supports_popcnt() ? ", popcnt" : ""), |
11427 | 704 |
(supports_avx() ? ", avx" : ""), |
705 |
(supports_avx2() ? ", avx2" : ""), |
|
14132 | 706 |
(supports_aes() ? ", aes" : ""), |
23491 | 707 |
(supports_clmul() ? ", clmul" : ""), |
15114
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
708 |
(supports_erms() ? ", erms" : ""), |
23491 | 709 |
(supports_rtm() ? ", rtm" : ""), |
2111 | 710 |
(supports_mmx_ext() ? ", mmxext" : ""), |
9135 | 711 |
(supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
712 |
(supports_lzcnt() ? ", lzcnt": ""), |
2111 | 713 |
(supports_sse4a() ? ", sse4a": ""), |
11417
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
714 |
(supports_ht() ? ", ht": ""), |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
715 |
(supports_tsc() ? ", tsc": ""), |
4ecc3253bec4
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
phh
parents:
10565
diff
changeset
|
716 |
(supports_tscinv_bit() ? ", tscinvbit": ""), |
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
717 |
(supports_tscinv() ? ", tscinv": ""), |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
718 |
(supports_bmi1() ? ", bmi1" : ""), |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
719 |
(supports_bmi2() ? ", bmi2" : ""), |
30624 | 720 |
(supports_adx() ? ", adx" : ""), |
36555 | 721 |
(supports_evex() ? ", evex" : ""), |
41323 | 722 |
(supports_sha() ? ", sha" : ""), |
723 |
(supports_fma() ? ", fma" : "")); |
|
35148 | 724 |
_features_string = os::strdup(buf); |
2111 | 725 |
|
726 |
// UseSSE is set to the smaller of what hardware supports and what |
|
727 |
// the command line requires. I.e., you cannot set UseSSE to 2 on |
|
728 |
// older Pentiums which do not support it. |
|
48195
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
729 |
int use_sse_limit = 0; |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
730 |
if (UseSSE > 0) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
731 |
if (UseSSE > 3 && supports_sse4_1()) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
732 |
use_sse_limit = 4; |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
733 |
} else if (UseSSE > 2 && supports_sse3()) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
734 |
use_sse_limit = 3; |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
735 |
} else if (UseSSE > 1 && supports_sse2()) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
736 |
use_sse_limit = 2; |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
737 |
} else if (UseSSE > 0 && supports_sse()) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
738 |
use_sse_limit = 1; |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
739 |
} else { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
740 |
use_sse_limit = 0; |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
741 |
} |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
742 |
} |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
743 |
if (FLAG_IS_DEFAULT(UseSSE)) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
744 |
FLAG_SET_DEFAULT(UseSSE, use_sse_limit); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
745 |
} else if (UseSSE > use_sse_limit) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
746 |
warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
747 |
FLAG_SET_DEFAULT(UseSSE, use_sse_limit); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
748 |
} else if (UseSSE < 0) { |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
749 |
warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
750 |
FLAG_SET_DEFAULT(UseSSE, 0); |
255407049d98
8170244: Update UseAVX after cpu feature detection to use more default mapping
vdeshpande
parents:
47799
diff
changeset
|
751 |
} |
2111 | 752 |
|
14132 | 753 |
// Use AES instructions if available. |
754 |
if (supports_aes()) { |
|
755 |
if (FLAG_IS_DEFAULT(UseAES)) { |
|
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
756 |
FLAG_SET_DEFAULT(UseAES, true); |
14132 | 757 |
} |
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
758 |
if (!UseAES) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
759 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
760 |
warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
761 |
} |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
762 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
763 |
} else { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
764 |
if (UseSSE > 2) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
765 |
if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
766 |
FLAG_SET_DEFAULT(UseAESIntrinsics, true); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
767 |
} |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
768 |
} else { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
769 |
// The AES intrinsic stubs require AES instruction support (of course) |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
770 |
// but also require sse3 mode or higher for instructions it use. |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
771 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
772 |
warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled."); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
773 |
} |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
774 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
775 |
} |
35154 | 776 |
|
777 |
// --AES-CTR begins-- |
|
778 |
if (!UseAESIntrinsics) { |
|
779 |
if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { |
|
780 |
warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled."); |
|
781 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); |
|
782 |
} |
|
783 |
} else { |
|
39256
ac12f57c6d9c
8158214: Crash with "assert(VM_Version::supports_sse4_1()) failed" if UseSSE < 4 is set
thartmann
parents:
38135
diff
changeset
|
784 |
if(supports_sse4_1()) { |
35154 | 785 |
if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { |
786 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true); |
|
787 |
} |
|
788 |
} else { |
|
789 |
// The AES-CTR intrinsic stubs require AES instruction support (of course) |
|
790 |
// but also require sse4.1 mode or higher for instructions it use. |
|
791 |
if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { |
|
792 |
warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled."); |
|
793 |
} |
|
794 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); |
|
795 |
} |
|
796 |
} |
|
797 |
// --AES-CTR ends-- |
|
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
798 |
} |
35537
bed5e2dc57a1
8146581: Minor corrections to the patch submitted for earlier bug id - 8143925
kvn
parents:
35154
diff
changeset
|
799 |
} else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) { |
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
800 |
if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { |
23491 | 801 |
warning("AES instructions are not available on this CPU"); |
34176
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
802 |
FLAG_SET_DEFAULT(UseAES, false); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
803 |
} |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
804 |
if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
805 |
warning("AES intrinsics are not available on this CPU"); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
806 |
FLAG_SET_DEFAULT(UseAESIntrinsics, false); |
c1b52e665b47
8131778: java disables UseAES flag when using VIS=2 on sparc
kshefov
parents:
34162
diff
changeset
|
807 |
} |
35154 | 808 |
if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { |
809 |
warning("AES-CTR intrinsics are not available on this CPU"); |
|
810 |
FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); |
|
811 |
} |
|
14132 | 812 |
} |
813 |
||
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
814 |
// Use CLMUL instructions if available. |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
815 |
if (supports_clmul()) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
816 |
if (FLAG_IS_DEFAULT(UseCLMUL)) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
817 |
UseCLMUL = true; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
818 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
819 |
} else if (UseCLMUL) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
820 |
if (!FLAG_IS_DEFAULT(UseCLMUL)) |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
821 |
warning("CLMUL instructions not available on this CPU (AVX may also be required)"); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
822 |
FLAG_SET_DEFAULT(UseCLMUL, false); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
823 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
824 |
|
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
825 |
if (UseCLMUL && (UseSSE > 2)) { |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
826 |
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
827 |
UseCRC32Intrinsics = true; |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
828 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
829 |
} else if (UseCRC32Intrinsics) { |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
830 |
if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
831 |
warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)"); |
18507
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
832 |
FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
833 |
} |
61bfc8995bb3
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
15243
diff
changeset
|
834 |
|
44737
d090627aedb8
8178723: Workaround for failure of CRC32C intrinsic on x86 machines without CLMUL support (JDK-8178720)
zmajo
parents:
43936
diff
changeset
|
835 |
if (supports_sse4_2() && supports_clmul()) { |
33066 | 836 |
if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { |
837 |
UseCRC32CIntrinsics = true; |
|
838 |
} |
|
44737
d090627aedb8
8178723: Workaround for failure of CRC32C intrinsic on x86 machines without CLMUL support (JDK-8178720)
zmajo
parents:
43936
diff
changeset
|
839 |
} else if (UseCRC32CIntrinsics) { |
33066 | 840 |
if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { |
841 |
warning("CRC32C intrinsics are not available on this CPU"); |
|
842 |
} |
|
843 |
FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); |
|
844 |
} |
|
845 |
||
31404
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
846 |
// GHASH/GCM intrinsics |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
847 |
if (UseCLMUL && (UseSSE > 2)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
848 |
if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
849 |
UseGHASHIntrinsics = true; |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
850 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
851 |
} else if (UseGHASHIntrinsics) { |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
852 |
if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
853 |
warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU"); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
854 |
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
855 |
} |
63e8fcd70bfc
8073108: Use x86 and SPARC CPU instructions for GHASH acceleration
ascarpino
parents:
31129
diff
changeset
|
856 |
|
50860
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
857 |
// Base64 Intrinsics (Check the condition for which the intrinsic will be active) |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
858 |
if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
859 |
if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
860 |
UseBASE64Intrinsics = true; |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
861 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
862 |
} else if (UseBASE64Intrinsics) { |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
863 |
if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics)) |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
864 |
warning("Base64 intrinsic requires EVEX instructions on this CPU"); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
865 |
FLAG_SET_DEFAULT(UseBASE64Intrinsics, false); |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
866 |
} |
480a96a43b62
8205528: Base64 encoding algorithm using AVX512 instructions
kvn
parents:
50699
diff
changeset
|
867 |
|
46546 | 868 |
if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions |
41323 | 869 |
if (FLAG_IS_DEFAULT(UseFMA)) { |
870 |
UseFMA = true; |
|
871 |
} |
|
872 |
} else if (UseFMA) { |
|
873 |
warning("FMA instructions are not available on this CPU"); |
|
874 |
FLAG_SET_DEFAULT(UseFMA, false); |
|
875 |
} |
|
876 |
||
38135
e06e2d071465
8154495: SHA256 AVX2 intrinsic (when no supports_sha() available)
jcivlin
parents:
37430
diff
changeset
|
877 |
if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) { |
36555 | 878 |
if (FLAG_IS_DEFAULT(UseSHA)) { |
879 |
UseSHA = true; |
|
880 |
} |
|
881 |
} else if (UseSHA) { |
|
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
882 |
warning("SHA instructions are not available on this CPU"); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
883 |
FLAG_SET_DEFAULT(UseSHA, false); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
884 |
} |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
885 |
|
51868
92960b0e6191
8211061: Tests fail with assert(VM_Version::supports_sse4_1()) on ThreadRipper CPU
rkennke
parents:
51857
diff
changeset
|
886 |
if (supports_sha() && supports_sse4_1() && UseSHA) { |
36555 | 887 |
if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { |
888 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); |
|
889 |
} |
|
890 |
} else if (UseSHA1Intrinsics) { |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
891 |
warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
892 |
FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
893 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
894 |
|
51868
92960b0e6191
8211061: Tests fail with assert(VM_Version::supports_sse4_1()) on ThreadRipper CPU
rkennke
parents:
51857
diff
changeset
|
895 |
if (supports_sse4_1() && UseSHA) { |
36555 | 896 |
if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { |
897 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); |
|
898 |
} |
|
899 |
} else if (UseSHA256Intrinsics) { |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
900 |
warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
901 |
FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); |
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
902 |
} |
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
903 |
|
48444
a97a26eb896f
8194494: SHA-512 stub uses AVX 2 instructions on non-supporting CPUs
thartmann
parents:
48195
diff
changeset
|
904 |
if (UseSHA && supports_avx2() && supports_bmi2()) { |
42039 | 905 |
if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { |
906 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); |
|
907 |
} |
|
908 |
} else if (UseSHA512Intrinsics) { |
|
31588
2a864a4a414c
8130120: Handling of SHA intrinsics inconsistent across platforms
zmajo
parents:
31584
diff
changeset
|
909 |
warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
910 |
FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
911 |
} |
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24424
diff
changeset
|
912 |
|
36555 | 913 |
if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { |
914 |
FLAG_SET_DEFAULT(UseSHA, false); |
|
915 |
} |
|
916 |
||
32581 | 917 |
if (UseAdler32Intrinsics) { |
918 |
warning("Adler32Intrinsics not available on this CPU."); |
|
919 |
FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); |
|
920 |
} |
|
921 |
||
23491 | 922 |
if (!supports_rtm() && UseRTMLocking) { |
923 |
// Can't continue because UseRTMLocking affects UseBiasedLocking flag |
|
924 |
// setting during arguments processing. See use_biased_locking(). |
|
925 |
// VM_Version_init() is executed after UseBiasedLocking is used |
|
926 |
// in Thread::allocate(). |
|
927 |
vm_exit_during_initialization("RTM instructions are not available on this CPU"); |
|
928 |
} |
|
929 |
||
930 |
#if INCLUDE_RTM_OPT |
|
931 |
if (UseRTMLocking) { |
|
43936
093cd5bea2e2
8173679: Disable ProfileTrap code and UseRTMLocking in emulated client Win32
jcm
parents:
42586
diff
changeset
|
932 |
if (is_client_compilation_mode_vm()) { |
093cd5bea2e2
8173679: Disable ProfileTrap code and UseRTMLocking in emulated client Win32
jcm
parents:
42586
diff
changeset
|
933 |
// Only C2 does RTM locking optimization. |
093cd5bea2e2
8173679: Disable ProfileTrap code and UseRTMLocking in emulated client Win32
jcm
parents:
42586
diff
changeset
|
934 |
// Can't continue because UseRTMLocking affects UseBiasedLocking flag |
093cd5bea2e2
8173679: Disable ProfileTrap code and UseRTMLocking in emulated client Win32
jcm
parents:
42586
diff
changeset
|
935 |
// setting during arguments processing. See use_biased_locking(). |
50261
3fd701692627
8184030: TestUseRTMLockingOptionOnUnsupportedVM - RTM locking optimization not supported is missing
jcm
parents:
49614
diff
changeset
|
936 |
vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); |
43936
093cd5bea2e2
8173679: Disable ProfileTrap code and UseRTMLocking in emulated client Win32
jcm
parents:
42586
diff
changeset
|
937 |
} |
26306
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
938 |
if (is_intel_family_core()) { |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
939 |
if ((_model == CPU_MODEL_HASWELL_E3) || |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
940 |
(_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) || |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
941 |
(_model == CPU_MODEL_BROADWELL && _stepping < 4)) { |
30624 | 942 |
// currently a collision between SKL and HSW_E3 |
943 |
if (!UnlockExperimentalVMOptions && UseAVX < 3) { |
|
46698
fa625dca9270
8184800: Streamline RTM flag validity testing with generic flag testing support
goetz
parents:
46630
diff
changeset
|
944 |
vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this " |
fa625dca9270
8184800: Streamline RTM flag validity testing with generic flag testing support
goetz
parents:
46630
diff
changeset
|
945 |
"platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); |
26306
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
946 |
} else { |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
947 |
warning("UseRTMLocking is only available as experimental option on this platform."); |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
948 |
} |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
949 |
} |
2b4cf8eb3de7
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
kvn
parents:
25949
diff
changeset
|
950 |
} |
23491 | 951 |
if (!FLAG_IS_CMDLINE(UseRTMLocking)) { |
952 |
// RTM locking should be used only for applications with |
|
953 |
// high lock contention. For now we do not use it by default. |
|
954 |
vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); |
|
955 |
} |
|
956 |
} else { // !UseRTMLocking |
|
957 |
if (UseRTMForStackLocks) { |
|
958 |
if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { |
|
959 |
warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); |
|
960 |
} |
|
961 |
FLAG_SET_DEFAULT(UseRTMForStackLocks, false); |
|
962 |
} |
|
963 |
if (UseRTMDeopt) { |
|
964 |
FLAG_SET_DEFAULT(UseRTMDeopt, false); |
|
965 |
} |
|
966 |
if (PrintPreciseRTMLockingStatistics) { |
|
967 |
FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); |
|
968 |
} |
|
969 |
} |
|
970 |
#else |
|
971 |
if (UseRTMLocking) { |
|
972 |
// Only C2 does RTM locking optimization. |
|
973 |
// Can't continue because UseRTMLocking affects UseBiasedLocking flag |
|
974 |
// setting during arguments processing. See use_biased_locking(). |
|
975 |
vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); |
|
976 |
} |
|
977 |
#endif |
|
978 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
979 |
#ifdef COMPILER2 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
980 |
if (UseFPUForSpilling) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
981 |
if (UseSSE < 2) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
982 |
// Only supported with SSE2+ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
983 |
FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
984 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
985 |
} |
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33066
diff
changeset
|
986 |
#endif |
47799 | 987 |
#if COMPILER2_OR_JVMCI |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
988 |
if (MaxVectorSize > 0) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
989 |
if (!is_power_of_2(MaxVectorSize)) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
990 |
warning("MaxVectorSize must be a power of 2"); |
30624 | 991 |
FLAG_SET_DEFAULT(MaxVectorSize, 64); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
992 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
993 |
if (UseSSE < 2) { |
23487
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
994 |
// Vectors (in XMM) are only supported with SSE2+ |
46440
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
995 |
if (MaxVectorSize > 0) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
996 |
if (!FLAG_IS_DEFAULT(MaxVectorSize)) |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
997 |
warning("MaxVectorSize must be 0"); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
998 |
FLAG_SET_DEFAULT(MaxVectorSize, 0); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
999 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1000 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1001 |
else if (UseAVX == 0 || !os_supports_avx_vectors()) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1002 |
// 32 bytes vectors (in YMM) are only supported with AVX+ |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1003 |
if (MaxVectorSize > 16) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1004 |
if (!FLAG_IS_DEFAULT(MaxVectorSize)) |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1005 |
warning("MaxVectorSize must be <= 16"); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1006 |
FLAG_SET_DEFAULT(MaxVectorSize, 16); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1007 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1008 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1009 |
else if (UseAVX == 1 || UseAVX == 2) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1010 |
// 64 bytes vectors (in ZMM) are only supported with AVX 3 |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1011 |
if (MaxVectorSize > 32) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1012 |
if (!FLAG_IS_DEFAULT(MaxVectorSize)) |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1013 |
warning("MaxVectorSize must be <= 32"); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1014 |
FLAG_SET_DEFAULT(MaxVectorSize, 32); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1015 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1016 |
} |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1017 |
else if (UseAVX > 2 ) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1018 |
if (MaxVectorSize > 64) { |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1019 |
if (!FLAG_IS_DEFAULT(MaxVectorSize)) |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1020 |
warning("MaxVectorSize must be <= 64"); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1021 |
FLAG_SET_DEFAULT(MaxVectorSize, 64); |
61025eecb743
8178811: Minimize the AVX <-> SSE transition penalty through generation of vzeroupper instruction on x86
vdeshpande
parents:
43936
diff
changeset
|
1022 |
} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1023 |
} |
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33066
diff
changeset
|
1024 |
#if defined(COMPILER2) && defined(ASSERT) |
23487
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1025 |
if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1026 |
tty->print_cr("State of YMM registers after signal handle:"); |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1027 |
int nreg = 2 LP64_ONLY(+2); |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1028 |
const char* ymm_name[4] = {"0", "7", "8", "15"}; |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1029 |
for (int i = 0; i < nreg; i++) { |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1030 |
tty->print("YMM%s:", ymm_name[i]); |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1031 |
for (int j = 7; j >=0; j--) { |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1032 |
tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1033 |
} |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1034 |
tty->cr(); |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1035 |
} |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1036 |
} |
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33066
diff
changeset
|
1037 |
#endif // COMPILER2 && ASSERT |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1038 |
} |
47799 | 1039 |
#endif // COMPILER2_OR_JVMCI |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1040 |
|
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
33066
diff
changeset
|
1041 |
#ifdef COMPILER2 |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1042 |
#ifdef _LP64 |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1043 |
if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1044 |
UseMultiplyToLenIntrinsic = true; |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1045 |
} |
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1046 |
if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1047 |
UseSquareToLenIntrinsic = true; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1048 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1049 |
if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1050 |
UseMulAddIntrinsic = true; |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1051 |
} |
31583
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1052 |
if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1053 |
UseMontgomeryMultiplyIntrinsic = true; |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1054 |
} |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1055 |
if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1056 |
UseMontgomerySquareIntrinsic = true; |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1057 |
} |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1058 |
#else |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1059 |
if (UseMultiplyToLenIntrinsic) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1060 |
if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1061 |
warning("multiplyToLen intrinsic is not available in 32-bit VM"); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1062 |
} |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1063 |
FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1064 |
} |
31583
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1065 |
if (UseMontgomeryMultiplyIntrinsic) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1066 |
if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1067 |
warning("montgomeryMultiply intrinsic is not available in 32-bit VM"); |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1068 |
} |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1069 |
FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false); |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1070 |
} |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1071 |
if (UseMontgomerySquareIntrinsic) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1072 |
if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1073 |
warning("montgomerySquare intrinsic is not available in 32-bit VM"); |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1074 |
} |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1075 |
FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false); |
eb5bea7b4835
8130150: Implement BigInteger.montgomeryMultiply intrinsic
aph
parents:
31129
diff
changeset
|
1076 |
} |
31129
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1077 |
if (UseSquareToLenIntrinsic) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1078 |
if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1079 |
warning("squareToLen intrinsic is not available in 32-bit VM"); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1080 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1081 |
FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1082 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1083 |
if (UseMulAddIntrinsic) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1084 |
if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1085 |
warning("mulAdd intrinsic is not available in 32-bit VM"); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1086 |
} |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1087 |
FLAG_SET_DEFAULT(UseMulAddIntrinsic, false); |
02ee7609f0e1
8081778: Use Intel x64 CPU instructions for RSA acceleration
kvn
parents:
30624
diff
changeset
|
1088 |
} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1089 |
#endif |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1090 |
#endif // COMPILER2 |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1091 |
|
2111 | 1092 |
// On new cpus instructions which update whole XMM register should be used |
1093 |
// to prevent partial register stall due to dependencies on high half. |
|
1094 |
// |
|
1095 |
// UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) |
|
1096 |
// UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) |
|
1097 |
// UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). |
|
1098 |
// UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). |
|
1099 |
||
48489
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1100 |
|
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1101 |
if (is_zx()) { // ZX cpus specific settings |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1102 |
if (FLAG_IS_DEFAULT(UseStoreImmI16)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1103 |
UseStoreImmI16 = false; // don't use it on ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1104 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1105 |
if ((cpu_family() == 6) || (cpu_family() == 7)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1106 |
if (FLAG_IS_DEFAULT(UseAddressNop)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1107 |
// Use it on all ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1108 |
UseAddressNop = true; |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1109 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1110 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1111 |
if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1112 |
UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1113 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1114 |
if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1115 |
if (supports_sse3()) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1116 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1117 |
} else { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1118 |
UseXmmRegToRegMoveAll = false; |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1119 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1120 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1121 |
if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1122 |
#ifdef COMPILER2 |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1123 |
if (FLAG_IS_DEFAULT(MaxLoopPad)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1124 |
// For new ZX cpus do the next optimization: |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1125 |
// don't align the beginning of a loop if there are enough instructions |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1126 |
// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1127 |
// in current fetch line (OptoLoopAlignment) or the padding |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1128 |
// is big (> MaxLoopPad). |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1129 |
// Set MaxLoopPad to 11 for new ZX cpus to reduce number of |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1130 |
// generated NOP instructions. 11 is the largest size of one |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1131 |
// address NOP instruction '0F 1F' (see Assembler::nop(i)). |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1132 |
MaxLoopPad = 11; |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1133 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1134 |
#endif // COMPILER2 |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1135 |
if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1136 |
UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1137 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1138 |
if (supports_sse4_2()) { // new ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1139 |
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1140 |
UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1141 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1142 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1143 |
if (supports_sse4_2()) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1144 |
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1145 |
FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1146 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1147 |
} else { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1148 |
if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1149 |
warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1150 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1151 |
FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1152 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1153 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1154 |
|
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1155 |
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1156 |
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1157 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1158 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1159 |
|
2111 | 1160 |
if( is_amd() ) { // AMD cpus specific settings |
1161 |
if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { |
|
1162 |
// Use it on new AMD cpus starting from Opteron. |
|
1163 |
UseAddressNop = true; |
|
1164 |
} |
|
1165 |
if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { |
|
1166 |
// Use it on new AMD cpus starting from Opteron. |
|
1167 |
UseNewLongLShift = true; |
|
1168 |
} |
|
1169 |
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
34162 | 1170 |
if (supports_sse4a()) { |
2111 | 1171 |
UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron |
1172 |
} else { |
|
1173 |
UseXmmLoadAndClearUpper = false; |
|
1174 |
} |
|
1175 |
} |
|
1176 |
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
1177 |
if( supports_sse4a() ) { |
|
1178 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' |
|
1179 |
} else { |
|
1180 |
UseXmmRegToRegMoveAll = false; |
|
1181 |
} |
|
1182 |
} |
|
1183 |
if( FLAG_IS_DEFAULT(UseXmmI2F) ) { |
|
1184 |
if( supports_sse4a() ) { |
|
1185 |
UseXmmI2F = true; |
|
1186 |
} else { |
|
1187 |
UseXmmI2F = false; |
|
1188 |
} |
|
1189 |
} |
|
1190 |
if( FLAG_IS_DEFAULT(UseXmmI2D) ) { |
|
1191 |
if( supports_sse4a() ) { |
|
1192 |
UseXmmI2D = true; |
|
1193 |
} else { |
|
1194 |
UseXmmI2D = false; |
|
1195 |
} |
|
1196 |
} |
|
39256
ac12f57c6d9c
8158214: Crash with "assert(VM_Version::supports_sse4_1()) failed" if UseSSE < 4 is set
thartmann
parents:
38135
diff
changeset
|
1197 |
if (supports_sse4_2()) { |
34207
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1198 |
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1199 |
FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); |
8873 | 1200 |
} |
34207
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1201 |
} else { |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1202 |
if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1203 |
warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1204 |
} |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1205 |
FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); |
8873 | 1206 |
} |
2862
fad636edf18f
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
2348
diff
changeset
|
1207 |
|
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1208 |
// some defaults for AMD family 15h |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1209 |
if ( cpu_family() == 0x15 ) { |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1210 |
// On family 15h processors default is no sw prefetch |
8677 | 1211 |
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1212 |
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0); |
8677 | 1213 |
} |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1214 |
// Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1215 |
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1216 |
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1217 |
} |
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1218 |
// On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
13885 | 1219 |
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1220 |
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true); |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1221 |
} |
13885 | 1222 |
if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1223 |
FLAG_SET_DEFAULT(UseUnalignedLoadStores, true); |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1224 |
} |
8677 | 1225 |
} |
9325
2b95b2b2b60f
7037812: few more defaults changes for new AMD processors
kvn
parents:
9135
diff
changeset
|
1226 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1227 |
#ifdef COMPILER2 |
47582
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1228 |
if (cpu_family() < 0x17 && MaxVectorSize > 16) { |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1229 |
// Limit vectors size to 16 bytes on AMD cpus < 17h. |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1230 |
FLAG_SET_DEFAULT(MaxVectorSize, 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1231 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11881
diff
changeset
|
1232 |
#endif // COMPILER2 |
47582
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1233 |
|
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1234 |
// Some defaults for AMD family 17h |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1235 |
if ( cpu_family() == 0x17 ) { |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1236 |
// On family 17h processors use XMM and UnalignedLoadStores for Array Copy |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1237 |
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1238 |
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true); |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1239 |
} |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1240 |
if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1241 |
FLAG_SET_DEFAULT(UseUnalignedLoadStores, true); |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1242 |
} |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1243 |
#ifdef COMPILER2 |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1244 |
if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1245 |
FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1246 |
} |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1247 |
#endif |
fde01e0fccb4
8187219: Newer AMD 17h (EPYC) Processor family defaults
kvn
parents:
47216
diff
changeset
|
1248 |
} |
2111 | 1249 |
} |
1250 |
||
1251 |
if( is_intel() ) { // Intel cpus specific settings |
|
1252 |
if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { |
|
1253 |
UseStoreImmI16 = false; // don't use it on Intel cpus |
|
1254 |
} |
|
1255 |
if( cpu_family() == 6 || cpu_family() == 15 ) { |
|
1256 |
if( FLAG_IS_DEFAULT(UseAddressNop) ) { |
|
1257 |
// Use it on all Intel cpus starting from PentiumPro |
|
1258 |
UseAddressNop = true; |
|
1259 |
} |
|
1260 |
} |
|
1261 |
if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { |
|
1262 |
UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus |
|
1263 |
} |
|
1264 |
if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { |
|
1265 |
if( supports_sse3() ) { |
|
1266 |
UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus |
|
1267 |
} else { |
|
1268 |
UseXmmRegToRegMoveAll = false; |
|
1269 |
} |
|
1270 |
} |
|
1271 |
if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus |
|
1272 |
#ifdef COMPILER2 |
|
1273 |
if( FLAG_IS_DEFAULT(MaxLoopPad) ) { |
|
1274 |
// For new Intel cpus do the next optimization: |
|
1275 |
// don't align the beginning of a loop if there are enough instructions |
|
1276 |
// left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) |
|
1277 |
// in current fetch line (OptoLoopAlignment) or the padding |
|
1278 |
// is big (> MaxLoopPad). |
|
1279 |
// Set MaxLoopPad to 11 for new Intel cpus to reduce number of |
|
1280 |
// generated NOP instructions. 11 is the largest size of one |
|
1281 |
// address NOP instruction '0F 1F' (see Assembler::nop(i)). |
|
1282 |
MaxLoopPad = 11; |
|
1283 |
} |
|
1284 |
#endif // COMPILER2 |
|
13885 | 1285 |
if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { |
2111 | 1286 |
UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus |
1287 |
} |
|
13885 | 1288 |
if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus |
1289 |
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
|
2111 | 1290 |
UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
1291 |
} |
|
1292 |
} |
|
39256
ac12f57c6d9c
8158214: Crash with "assert(VM_Version::supports_sse4_1()) failed" if UseSSE < 4 is set
thartmann
parents:
38135
diff
changeset
|
1293 |
if (supports_sse4_2()) { |
13885 | 1294 |
if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { |
34207
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1295 |
FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); |
2348 | 1296 |
} |
34207
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1297 |
} else { |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1298 |
if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1299 |
warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1300 |
} |
a5f1c458b56e
8143208: compiler/c1/6855215/Test6855215.java supports_sse2() failed
zmajo
parents:
34176
diff
changeset
|
1301 |
FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); |
2348 | 1302 |
} |
2111 | 1303 |
} |
46563
cfca8fbb4051
8182138: Disable generating INC and DEC instructions on Xeon Phi and ATOM CPUs
kvn
parents:
46560
diff
changeset
|
1304 |
if (is_atom_family() || is_knights_family()) { |
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1305 |
#ifdef COMPILER2 |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1306 |
if (FLAG_IS_DEFAULT(OptoScheduling)) { |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1307 |
OptoScheduling = true; |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1308 |
} |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1309 |
#endif |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1310 |
if (supports_sse4_2()) { // Silvermont |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1311 |
if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1312 |
UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1313 |
} |
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1314 |
} |
46563
cfca8fbb4051
8182138: Disable generating INC and DEC instructions on Xeon Phi and ATOM CPUs
kvn
parents:
46560
diff
changeset
|
1315 |
if (FLAG_IS_DEFAULT(UseIncDec)) { |
cfca8fbb4051
8182138: Disable generating INC and DEC instructions on Xeon Phi and ATOM CPUs
kvn
parents:
46560
diff
changeset
|
1316 |
FLAG_SET_DEFAULT(UseIncDec, false); |
cfca8fbb4051
8182138: Disable generating INC and DEC instructions on Xeon Phi and ATOM CPUs
kvn
parents:
46560
diff
changeset
|
1317 |
} |
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1318 |
} |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1319 |
if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1320 |
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1321 |
} |
2111 | 1322 |
} |
1323 |
||
35110
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1324 |
#ifdef _LP64 |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1325 |
if (UseSSE42Intrinsics) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1326 |
if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1327 |
UseVectorizedMismatchIntrinsic = true; |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1328 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1329 |
} else if (UseVectorizedMismatchIntrinsic) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1330 |
if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1331 |
warning("vectorizedMismatch intrinsics are not available on this CPU"); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1332 |
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1333 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1334 |
#else |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1335 |
if (UseVectorizedMismatchIntrinsic) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1336 |
if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) { |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1337 |
warning("vectorizedMismatch intrinsic is not available in 32-bit VM"); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1338 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1339 |
FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1340 |
} |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1341 |
#endif // _LP64 |
f19bcdf40799
8143355: Update for addition of vectorizedMismatch intrinsic for x86
kvn
parents:
34207
diff
changeset
|
1342 |
|
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1343 |
// Use count leading zeros count instruction if available. |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1344 |
if (supports_lzcnt()) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1345 |
if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1346 |
UseCountLeadingZerosInstruction = true; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1347 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1348 |
} else if (UseCountLeadingZerosInstruction) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1349 |
warning("lzcnt instruction is not available on this CPU"); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1350 |
FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1351 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1352 |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1353 |
// Use count trailing zeros instruction if available |
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1354 |
if (supports_bmi1()) { |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1355 |
// tzcnt does not require VEX prefix |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1356 |
if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { |
27414
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1357 |
if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1358 |
// Don't use tzcnt if BMI1 is switched off on command line. |
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1359 |
UseCountTrailingZerosInstruction = false; |
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1360 |
} else { |
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1361 |
UseCountTrailingZerosInstruction = true; |
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1362 |
} |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1363 |
} |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1364 |
} else if (UseCountTrailingZerosInstruction) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1365 |
warning("tzcnt instruction is not available on this CPU"); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1366 |
FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1367 |
} |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1368 |
|
27414
39d976b80fb4
8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
kvn
parents:
26434
diff
changeset
|
1369 |
// BMI instructions (except tzcnt) use an encoding with VEX prefix. |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1370 |
// VEX prefix is generated only when AVX > 0. |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1371 |
if (supports_bmi1() && supports_avx()) { |
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1372 |
if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1373 |
UseBMI1Instructions = true; |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1374 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1375 |
} else if (UseBMI1Instructions) { |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1376 |
warning("BMI1 instructions are not available on this CPU (AVX is also required)"); |
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1377 |
FLAG_SET_DEFAULT(UseBMI1Instructions, false); |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1378 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1379 |
|
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1380 |
if (supports_bmi2() && supports_avx()) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1381 |
if (FLAG_IS_DEFAULT(UseBMI2Instructions)) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1382 |
UseBMI2Instructions = true; |
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1383 |
} |
26434
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1384 |
} else if (UseBMI2Instructions) { |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1385 |
warning("BMI2 instructions are not available on this CPU (AVX is also required)"); |
09ad55e5f486
8055494: Add C2 x86 intrinsic for BigInteger::multiplyToLen() method
kvn
parents:
26306
diff
changeset
|
1386 |
FLAG_SET_DEFAULT(UseBMI2Instructions, false); |
23220
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1387 |
} |
fc827339dc37
8031321: Support Intel bit manipulation instructions
iveresov
parents:
18507
diff
changeset
|
1388 |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1389 |
// Use population count instruction if available. |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1390 |
if (supports_popcnt()) { |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1391 |
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1392 |
UsePopCountInstruction = true; |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1393 |
} |
11427 | 1394 |
} else if (UsePopCountInstruction) { |
1395 |
warning("POPCNT instruction is not available on this CPU"); |
|
1396 |
FLAG_SET_DEFAULT(UsePopCountInstruction, false); |
|
2255
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1397 |
} |
54abdf3e1055
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
2111
diff
changeset
|
1398 |
|
15114
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1399 |
// Use fast-string operations if available. |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1400 |
if (supports_erms()) { |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1401 |
if (FLAG_IS_DEFAULT(UseFastStosb)) { |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1402 |
UseFastStosb = true; |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1403 |
} |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1404 |
} else if (UseFastStosb) { |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1405 |
warning("fast-string operations are not available on this CPU"); |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1406 |
FLAG_SET_DEFAULT(UseFastStosb, false); |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1407 |
} |
4074553c678b
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
14834
diff
changeset
|
1408 |
|
50534 | 1409 |
// Use XMM/YMM MOVDQU instruction for Object Initialization |
1410 |
if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) { |
|
1411 |
if (FLAG_IS_DEFAULT(UseXMMForObjInit)) { |
|
1412 |
UseXMMForObjInit = true; |
|
1413 |
} |
|
1414 |
} else if (UseXMMForObjInit) { |
|
1415 |
warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off."); |
|
1416 |
FLAG_SET_DEFAULT(UseXMMForObjInit, false); |
|
1417 |
} |
|
1418 |
||
13885 | 1419 |
#ifdef COMPILER2 |
1420 |
if (FLAG_IS_DEFAULT(AlignVector)) { |
|
1421 |
// Modern processors allow misaligned memory operations for vectors. |
|
1422 |
AlignVector = !UseUnalignedLoadStores; |
|
1423 |
} |
|
1424 |
#endif // COMPILER2 |
|
1425 |
||
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1426 |
if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1427 |
if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1428 |
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1429 |
} else if (!supports_sse() && supports_3dnow_prefetch()) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1430 |
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1431 |
} |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1432 |
} |
2111 | 1433 |
|
1434 |
// Allocation prefetch settings |
|
10267 | 1435 |
intx cache_line_size = prefetch_data_size(); |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1436 |
if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) && |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1437 |
(cache_line_size > AllocatePrefetchStepSize)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1438 |
FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1439 |
} |
10267 | 1440 |
|
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1441 |
if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1442 |
assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0"); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1443 |
if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1444 |
warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag."); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1445 |
} |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1446 |
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1447 |
} |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1448 |
|
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1449 |
if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1450 |
bool use_watermark_prefetch = (AllocatePrefetchStyle == 2); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1451 |
FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch)); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1452 |
} |
2111 | 1453 |
|
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1454 |
if (is_intel() && cpu_family() == 6 && supports_sse3()) { |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1455 |
if (FLAG_IS_DEFAULT(AllocatePrefetchLines) && |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1456 |
supports_sse4_2() && supports_ht()) { // Nehalem based cpus |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1457 |
FLAG_SET_DEFAULT(AllocatePrefetchLines, 4); |
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1458 |
} |
6272
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
1459 |
#ifdef COMPILER2 |
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1460 |
if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1461 |
FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
25932
15d133edd8f6
8052081: Optimize generated by C2 code for Intel's Atom processor
kvn
parents:
25633
diff
changeset
|
1462 |
} |
6272
94a20ad0e9de
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
5902
diff
changeset
|
1463 |
#endif |
2111 | 1464 |
} |
1465 |
||
48489
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1466 |
if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1467 |
#ifdef COMPILER2 |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1468 |
if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1469 |
FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1470 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1471 |
#endif |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1472 |
} |
a5548cf24286
8194279: support zhaoxin x86 cpu vendor ids CentaurHauls and Shanghai
dholmes
parents:
48195
diff
changeset
|
1473 |
|
2111 | 1474 |
#ifdef _LP64 |
1475 |
// Prefetch settings |
|
46547
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1476 |
|
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1477 |
// Prefetch interval for gc copy/scan == 9 dcache lines. Derived from |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1478 |
// 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1479 |
// Tested intervals from 128 to 2048 in increments of 64 == one cache line. |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1480 |
// 256 bytes (4 dcache lines) was the nearest runner-up to 576. |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1481 |
|
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1482 |
// gc copy/scan is disabled if prefetchw isn't supported, because |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1483 |
// Prefetch::write emits an inlined prefetchw on Linux. |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1484 |
// Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1485 |
// The used prefetcht0 instruction works for both amd64 and em64t. |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1486 |
|
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1487 |
if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1488 |
FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1489 |
} |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1490 |
if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1491 |
FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1492 |
} |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1493 |
if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) { |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1494 |
FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1); |
e1b926a0b23f
8016470: AllocatePrefetchDistance is not changed by command line
rraghavan
parents:
46546
diff
changeset
|
1495 |
} |
2111 | 1496 |
#endif |
1497 |
||
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14834
diff
changeset
|
1498 |
if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14834
diff
changeset
|
1499 |
(cache_line_size > ContendedPaddingWidth)) |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14834
diff
changeset
|
1500 |
ContendedPaddingWidth = cache_line_size; |
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14834
diff
changeset
|
1501 |
|
30209
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
28954
diff
changeset
|
1502 |
// This machine allows unaligned memory accesses |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
28954
diff
changeset
|
1503 |
if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
28954
diff
changeset
|
1504 |
FLAG_SET_DEFAULT(UseUnalignedAccesses, true); |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
28954
diff
changeset
|
1505 |
} |
8ea30dc99369
8026049: (bf) Intrinsify ByteBuffer.put{Int, Double, Float, ...} methods
aph
parents:
28954
diff
changeset
|
1506 |
|
2111 | 1507 |
#ifndef PRODUCT |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1508 |
if (log_is_enabled(Info, os, cpu)) { |
46701
f559541c0daa
8181917: Refactor UL LogStreams to avoid using resource area
stuefe
parents:
46698
diff
changeset
|
1509 |
LogStream ls(Log(os, cpu)::info()); |
f559541c0daa
8181917: Refactor UL LogStreams to avoid using resource area
stuefe
parents:
46698
diff
changeset
|
1510 |
outputStream* log = &ls; |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1511 |
log->print_cr("Logical CPUs per core: %u", |
2111 | 1512 |
logical_processors_per_package()); |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1513 |
log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1514 |
log->print("UseSSE=%d", (int) UseSSE); |
11427 | 1515 |
if (UseAVX > 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1516 |
log->print(" UseAVX=%d", (int) UseAVX); |
11427 | 1517 |
} |
14132 | 1518 |
if (UseAES) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1519 |
log->print(" UseAES=1"); |
14132 | 1520 |
} |
23487
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1521 |
#ifdef COMPILER2 |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1522 |
if (MaxVectorSize > 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1523 |
log->print(" MaxVectorSize=%d", (int) MaxVectorSize); |
23487
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1524 |
} |
0f7e268cd9e3
8037226: compiler/7196199/Test7196199.java fails on 32-bit linux with MaxVectorSize > 16
kvn
parents:
23220
diff
changeset
|
1525 |
#endif |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1526 |
log->cr(); |
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1527 |
log->print("Allocation"); |
46630
75aa3e39d02c
8182299: Enable disabled clang warnings, build on OSX 10 + Xcode 8
jwilhelm
parents:
46563
diff
changeset
|
1528 |
if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1529 |
log->print_cr(": no prefetching"); |
2111 | 1530 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1531 |
log->print(" prefetching: "); |
9135 | 1532 |
if (UseSSE == 0 && supports_3dnow_prefetch()) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1533 |
log->print("PREFETCHW"); |
2111 | 1534 |
} else if (UseSSE >= 1) { |
1535 |
if (AllocatePrefetchInstr == 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1536 |
log->print("PREFETCHNTA"); |
2111 | 1537 |
} else if (AllocatePrefetchInstr == 1) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1538 |
log->print("PREFETCHT0"); |
2111 | 1539 |
} else if (AllocatePrefetchInstr == 2) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1540 |
log->print("PREFETCHT2"); |
2111 | 1541 |
} else if (AllocatePrefetchInstr == 3) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1542 |
log->print("PREFETCHW"); |
2111 | 1543 |
} |
1544 |
} |
|
1545 |
if (AllocatePrefetchLines > 1) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1546 |
log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); |
2111 | 1547 |
} else { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1548 |
log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); |
2111 | 1549 |
} |
1550 |
} |
|
1551 |
||
1552 |
if (PrefetchCopyIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1553 |
log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); |
2111 | 1554 |
} |
1555 |
if (PrefetchScanIntervalInBytes > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1556 |
log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); |
2111 | 1557 |
} |
1558 |
if (PrefetchFieldsAhead > 0) { |
|
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1559 |
log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); |
2111 | 1560 |
} |
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14834
diff
changeset
|
1561 |
if (ContendedPaddingWidth > 0) { |
37430
fd743dadef12
8151939: VM_Version_init() print buffer is too small
coleenp
parents:
36561
diff
changeset
|
1562 |
log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); |
15193
8e6b5694267f
8003985: Support @Contended Annotation - JEP 142
jwilhelm
parents:
14834
diff
changeset
|
1563 |
} |
2111 | 1564 |
} |
1565 |
#endif // !PRODUCT |
|
1566 |
} |
|
1567 |
||
23491 | 1568 |
bool VM_Version::use_biased_locking() { |
1569 |
#if INCLUDE_RTM_OPT |
|
1570 |
// RTM locking is most useful when there is high lock contention and |
|
1571 |
// low data contention. With high lock contention the lock is usually |
|
1572 |
// inflated and biased locking is not suitable for that case. |
|
1573 |
// RTM locking code requires that biased locking is off. |
|
1574 |
// Note: we can't switch off UseBiasedLocking in get_processor_features() |
|
1575 |
// because it is used by Thread::allocate() which is called before |
|
1576 |
// VM_Version::initialize(). |
|
1577 |
if (UseRTMLocking && UseBiasedLocking) { |
|
1578 |
if (FLAG_IS_DEFAULT(UseBiasedLocking)) { |
|
1579 |
FLAG_SET_DEFAULT(UseBiasedLocking, false); |
|
1580 |
} else { |
|
1581 |
warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); |
|
1582 |
UseBiasedLocking = false; |
|
1583 |
} |
|
1584 |
} |
|
1585 |
#endif |
|
1586 |
return UseBiasedLocking; |
|
1587 |
} |
|
1588 |
||
2111 | 1589 |
void VM_Version::initialize() { |
1590 |
ResourceMark rm; |
|
1591 |
// Making this stub must be FIRST use of assembler |
|
1592 |
||
23527
397b6816032d
8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents:
23491
diff
changeset
|
1593 |
stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); |
2111 | 1594 |
if (stub_blob == NULL) { |
23527
397b6816032d
8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents:
23491
diff
changeset
|
1595 |
vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); |
2111 | 1596 |
} |
6418 | 1597 |
CodeBuffer c(stub_blob); |
2111 | 1598 |
VM_Version_StubGenerator g(&c); |
23527
397b6816032d
8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents:
23491
diff
changeset
|
1599 |
get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, |
397b6816032d
8038633: crash in VM_Version::get_processor_features() on startup
kvn
parents:
23491
diff
changeset
|
1600 |
g.generate_get_cpu_info()); |
2111 | 1601 |
|
1602 |
get_processor_features(); |
|
1603 |
} |