author | mcberg |
Tue, 23 Jun 2015 12:45:08 -0700 | |
changeset 31410 | 2a222ae1205f |
parent 30624 | 2e1803c8a26d |
child 32082 | 2a3323e25de1 |
permissions | -rw-r--r-- |
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// |
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// Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved. |
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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// |
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// This code is free software; you can redistribute it and/or modify it |
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// under the terms of the GNU General Public License version 2 only, as |
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// published by the Free Software Foundation. |
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// |
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// This code is distributed in the hope that it will be useful, but WITHOUT |
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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// version 2 for more details (a copy is included in the LICENSE file that |
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// accompanied this code). |
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// |
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// You should have received a copy of the GNU General Public License version |
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// 2 along with this work; if not, write to the Free Software Foundation, |
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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// |
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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// or visit www.oracle.com if you need additional information or have any |
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// questions. |
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// |
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// |
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||
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// X86 Common Architecture Description File |
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||
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//----------REGISTER DEFINITION BLOCK------------------------------------------ |
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// This information is used by the matcher and the register allocator to |
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// describe individual registers and classes of registers within the target |
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// archtecture. |
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register %{ |
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//----------Architecture Description Register Definitions---------------------- |
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// General Registers |
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// "reg_def" name ( register save type, C convention save type, |
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// ideal register type, encoding ); |
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// Register Save Types: |
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// |
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// NS = No-Save: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, & |
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// that they do not need to be saved at call sites. |
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// |
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// SOC = Save-On-Call: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, |
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// but that they must be saved at call sites. |
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// |
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// SOE = Save-On-Entry: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, but they do not need to be saved at call |
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// sites. |
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// |
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// AS = Always-Save: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, & that they must be saved at call sites. |
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// |
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// Ideal Register Type is used to determine how to save & restore a |
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// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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// |
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// The encoding number is the actual bit-pattern placed into the opcodes. |
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// XMM registers. 512-bit registers or 8 words each, labeled (a)-p. |
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// Word a in each register holds a Float, words ab hold a Double. |
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// The whole registers are used in SSE4.2 version intrinsics, |
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// array copy stubs and superword operations (see UseSSE42Intrinsics, |
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// UseXMMForArrayCopy and UseSuperword flags). |
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// For pre EVEX enabled architectures: |
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// XMM8-XMM15 must be encoded with REX (VEX for UseAVX) |
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// For EVEX enabled architectures: |
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// XMM8-XMM31 must be encoded with REX (EVEX for UseAVX). |
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// |
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// Linux ABI: No register preserved across function calls |
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// XMM0-XMM7 might hold parameters |
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// Windows ABI: XMM6-XMM31 preserved across function calls |
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// XMM0-XMM3 might hold parameters |
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reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); |
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reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(1)); |
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reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(2)); |
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reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(3)); |
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reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(4)); |
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reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(5)); |
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reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(6)); |
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reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(7)); |
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reg_def XMM0i( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(8)); |
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reg_def XMM0j( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(9)); |
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reg_def XMM0k( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(10)); |
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reg_def XMM0l( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(11)); |
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reg_def XMM0m( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(12)); |
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reg_def XMM0n( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(13)); |
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reg_def XMM0o( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(14)); |
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reg_def XMM0p( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(15)); |
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reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); |
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reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(1)); |
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reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(2)); |
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reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(3)); |
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reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(4)); |
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reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(5)); |
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reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(6)); |
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reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(7)); |
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reg_def XMM1i( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(8)); |
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reg_def XMM1j( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(9)); |
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reg_def XMM1k( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(10)); |
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reg_def XMM1l( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(11)); |
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reg_def XMM1m( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(12)); |
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reg_def XMM1n( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(13)); |
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reg_def XMM1o( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(14)); |
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reg_def XMM1p( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(15)); |
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reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); |
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reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(1)); |
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reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(2)); |
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reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(3)); |
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reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(4)); |
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reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(5)); |
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reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(6)); |
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reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(7)); |
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reg_def XMM2i( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(8)); |
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reg_def XMM2j( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(9)); |
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reg_def XMM2k( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(10)); |
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reg_def XMM2l( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(11)); |
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reg_def XMM2m( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(12)); |
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reg_def XMM2n( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(13)); |
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reg_def XMM2o( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(14)); |
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reg_def XMM2p( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(15)); |
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reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); |
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reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(1)); |
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reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(2)); |
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reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(3)); |
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reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(4)); |
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reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(5)); |
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reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(6)); |
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reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(7)); |
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reg_def XMM3i( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(8)); |
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reg_def XMM3j( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(9)); |
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reg_def XMM3k( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(10)); |
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reg_def XMM3l( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(11)); |
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reg_def XMM3m( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(12)); |
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reg_def XMM3n( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(13)); |
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reg_def XMM3o( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(14)); |
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reg_def XMM3p( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(15)); |
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reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); |
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reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(1)); |
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reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(2)); |
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reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(3)); |
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reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(4)); |
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reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(5)); |
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reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(6)); |
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reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(7)); |
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reg_def XMM4i( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(8)); |
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reg_def XMM4j( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(9)); |
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reg_def XMM4k( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(10)); |
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reg_def XMM4l( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(11)); |
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reg_def XMM4m( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(12)); |
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reg_def XMM4n( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(13)); |
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reg_def XMM4o( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(14)); |
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reg_def XMM4p( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(15)); |
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reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); |
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reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(1)); |
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reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(2)); |
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reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(3)); |
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reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(4)); |
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reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(5)); |
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reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(6)); |
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reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(7)); |
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reg_def XMM5i( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(8)); |
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reg_def XMM5j( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(9)); |
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reg_def XMM5k( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(10)); |
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reg_def XMM5l( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(11)); |
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reg_def XMM5m( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(12)); |
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reg_def XMM5n( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(13)); |
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reg_def XMM5o( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(14)); |
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reg_def XMM5p( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(15)); |
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#ifdef _WIN64 |
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reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); |
13294 | 182 |
reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(1)); |
183 |
reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(2)); |
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184 |
reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(3)); |
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185 |
reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(4)); |
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186 |
reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(5)); |
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187 |
reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(6)); |
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188 |
reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(7)); |
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30624 | 189 |
reg_def XMM6i( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(8)); |
190 |
reg_def XMM6j( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(9)); |
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191 |
reg_def XMM6k( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(10)); |
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192 |
reg_def XMM6l( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(11)); |
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193 |
reg_def XMM6m( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(12)); |
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194 |
reg_def XMM6n( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(13)); |
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195 |
reg_def XMM6o( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(14)); |
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196 |
reg_def XMM6p( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(15)); |
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reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); |
13294 | 199 |
reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(1)); |
200 |
reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(2)); |
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201 |
reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(3)); |
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202 |
reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(4)); |
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203 |
reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(5)); |
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204 |
reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(6)); |
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205 |
reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(7)); |
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30624 | 206 |
reg_def XMM7i( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(8)); |
207 |
reg_def XMM7j( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(9)); |
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208 |
reg_def XMM7k( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(10)); |
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209 |
reg_def XMM7l( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(11)); |
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210 |
reg_def XMM7m( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(12)); |
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211 |
reg_def XMM7n( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(13)); |
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212 |
reg_def XMM7o( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(14)); |
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213 |
reg_def XMM7p( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(15)); |
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reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); |
13294 | 216 |
reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(1)); |
217 |
reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(2)); |
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218 |
reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(3)); |
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219 |
reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(4)); |
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220 |
reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(5)); |
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221 |
reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(6)); |
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222 |
reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(7)); |
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30624 | 223 |
reg_def XMM8i( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(8)); |
224 |
reg_def XMM8j( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(9)); |
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225 |
reg_def XMM8k( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(10)); |
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226 |
reg_def XMM8l( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(11)); |
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227 |
reg_def XMM8m( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(12)); |
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228 |
reg_def XMM8n( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(13)); |
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229 |
reg_def XMM8o( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(14)); |
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230 |
reg_def XMM8p( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(15)); |
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reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); |
13294 | 233 |
reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(1)); |
234 |
reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(2)); |
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235 |
reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(3)); |
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236 |
reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(4)); |
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237 |
reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(5)); |
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238 |
reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(6)); |
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239 |
reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(7)); |
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30624 | 240 |
reg_def XMM9i( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(8)); |
241 |
reg_def XMM9j( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(9)); |
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242 |
reg_def XMM9k( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(10)); |
|
243 |
reg_def XMM9l( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(11)); |
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244 |
reg_def XMM9m( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(12)); |
|
245 |
reg_def XMM9n( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(13)); |
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246 |
reg_def XMM9o( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(14)); |
|
247 |
reg_def XMM9p( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(15)); |
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reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); |
13294 | 250 |
reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(1)); |
251 |
reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(2)); |
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252 |
reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(3)); |
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253 |
reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(4)); |
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254 |
reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(5)); |
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255 |
reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(6)); |
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256 |
reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(7)); |
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30624 | 257 |
reg_def XMM10i( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(8)); |
258 |
reg_def XMM10j( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(9)); |
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259 |
reg_def XMM10k( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(10)); |
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260 |
reg_def XMM10l( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(11)); |
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261 |
reg_def XMM10m( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(12)); |
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262 |
reg_def XMM10n( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(13)); |
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263 |
reg_def XMM10o( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(14)); |
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264 |
reg_def XMM10p( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(15)); |
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reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); |
13294 | 267 |
reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(1)); |
268 |
reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(2)); |
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269 |
reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(3)); |
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270 |
reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(4)); |
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271 |
reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(5)); |
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272 |
reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(6)); |
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273 |
reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(7)); |
|
30624 | 274 |
reg_def XMM11i( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(8)); |
275 |
reg_def XMM11j( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(9)); |
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276 |
reg_def XMM11k( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(10)); |
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277 |
reg_def XMM11l( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(11)); |
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278 |
reg_def XMM11m( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(12)); |
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279 |
reg_def XMM11n( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(13)); |
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280 |
reg_def XMM11o( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(14)); |
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281 |
reg_def XMM11p( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(15)); |
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reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); |
13294 | 284 |
reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(1)); |
285 |
reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(2)); |
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286 |
reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(3)); |
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287 |
reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(4)); |
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288 |
reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(5)); |
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289 |
reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(6)); |
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290 |
reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(7)); |
|
30624 | 291 |
reg_def XMM12i( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(8)); |
292 |
reg_def XMM12j( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(9)); |
|
293 |
reg_def XMM12k( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(10)); |
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294 |
reg_def XMM12l( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(11)); |
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295 |
reg_def XMM12m( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(12)); |
|
296 |
reg_def XMM12n( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(13)); |
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297 |
reg_def XMM12o( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(14)); |
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298 |
reg_def XMM12p( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(15)); |
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300 |
reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); |
13294 | 301 |
reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(1)); |
302 |
reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(2)); |
|
303 |
reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(3)); |
|
304 |
reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(4)); |
|
305 |
reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(5)); |
|
306 |
reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(6)); |
|
307 |
reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(7)); |
|
30624 | 308 |
reg_def XMM13i( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(8)); |
309 |
reg_def XMM13j( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(9)); |
|
310 |
reg_def XMM13k( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(10)); |
|
311 |
reg_def XMM13l( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(11)); |
|
312 |
reg_def XMM13m( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(12)); |
|
313 |
reg_def XMM13n( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(13)); |
|
314 |
reg_def XMM13o( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(14)); |
|
315 |
reg_def XMM13p( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(15)); |
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reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); |
13294 | 318 |
reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(1)); |
319 |
reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(2)); |
|
320 |
reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(3)); |
|
321 |
reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(4)); |
|
322 |
reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(5)); |
|
323 |
reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(6)); |
|
324 |
reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(7)); |
|
30624 | 325 |
reg_def XMM14i( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(8)); |
326 |
reg_def XMM14j( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(9)); |
|
327 |
reg_def XMM14k( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(10)); |
|
328 |
reg_def XMM14l( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(11)); |
|
329 |
reg_def XMM14m( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(12)); |
|
330 |
reg_def XMM14n( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(13)); |
|
331 |
reg_def XMM14o( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(14)); |
|
332 |
reg_def XMM14p( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(15)); |
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334 |
reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); |
13294 | 335 |
reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(1)); |
336 |
reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(2)); |
|
337 |
reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(3)); |
|
338 |
reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(4)); |
|
339 |
reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(5)); |
|
340 |
reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(6)); |
|
341 |
reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(7)); |
|
30624 | 342 |
reg_def XMM15i( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(8)); |
343 |
reg_def XMM15j( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(9)); |
|
344 |
reg_def XMM15k( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(10)); |
|
345 |
reg_def XMM15l( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(11)); |
|
346 |
reg_def XMM15m( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(12)); |
|
347 |
reg_def XMM15n( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(13)); |
|
348 |
reg_def XMM15o( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(14)); |
|
349 |
reg_def XMM15p( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(15)); |
|
350 |
||
351 |
reg_def XMM16 ( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()); |
|
352 |
reg_def XMM16b( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(1)); |
|
353 |
reg_def XMM16c( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(2)); |
|
354 |
reg_def XMM16d( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(3)); |
|
355 |
reg_def XMM16e( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(4)); |
|
356 |
reg_def XMM16f( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(5)); |
|
357 |
reg_def XMM16g( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(6)); |
|
358 |
reg_def XMM16h( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(7)); |
|
359 |
reg_def XMM16i( SOC, SOE, Op_RegF, 16, xmm15->as_VMReg()->next(8)); |
|
360 |
reg_def XMM16j( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(9)); |
|
361 |
reg_def XMM16k( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(10)); |
|
362 |
reg_def XMM16l( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(11)); |
|
363 |
reg_def XMM16m( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(12)); |
|
364 |
reg_def XMM16n( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(13)); |
|
365 |
reg_def XMM16o( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(14)); |
|
366 |
reg_def XMM16p( SOC, SOE, Op_RegF, 16, xmm16->as_VMReg()->next(15)); |
|
367 |
||
368 |
reg_def XMM17 ( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()); |
|
369 |
reg_def XMM17b( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(1)); |
|
370 |
reg_def XMM17c( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(2)); |
|
371 |
reg_def XMM17d( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(3)); |
|
372 |
reg_def XMM17e( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(4)); |
|
373 |
reg_def XMM17f( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(5)); |
|
374 |
reg_def XMM17g( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(6)); |
|
375 |
reg_def XMM17h( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(7)); |
|
376 |
reg_def XMM17i( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(8)); |
|
377 |
reg_def XMM17j( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(9)); |
|
378 |
reg_def XMM17k( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(10)); |
|
379 |
reg_def XMM17l( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(11)); |
|
380 |
reg_def XMM17m( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(12)); |
|
381 |
reg_def XMM17n( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(13)); |
|
382 |
reg_def XMM17o( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(14)); |
|
383 |
reg_def XMM17p( SOC, SOE, Op_RegF, 17, xmm17->as_VMReg()->next(15)); |
|
384 |
||
385 |
reg_def XMM18 ( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()); |
|
386 |
reg_def XMM18b( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(1)); |
|
387 |
reg_def XMM18c( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(2)); |
|
388 |
reg_def XMM18d( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(3)); |
|
389 |
reg_def XMM18e( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(4)); |
|
390 |
reg_def XMM18f( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(5)); |
|
391 |
reg_def XMM18g( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(6)); |
|
392 |
reg_def XMM18h( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(7)); |
|
393 |
reg_def XMM18i( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(8)); |
|
394 |
reg_def XMM18j( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(9)); |
|
395 |
reg_def XMM18k( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(10)); |
|
396 |
reg_def XMM18l( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(11)); |
|
397 |
reg_def XMM18m( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(12)); |
|
398 |
reg_def XMM18n( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(13)); |
|
399 |
reg_def XMM18o( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(14)); |
|
400 |
reg_def XMM18p( SOC, SOE, Op_RegF, 18, xmm18->as_VMReg()->next(15)); |
|
401 |
||
402 |
reg_def XMM19 ( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()); |
|
403 |
reg_def XMM19b( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(1)); |
|
404 |
reg_def XMM19c( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(2)); |
|
405 |
reg_def XMM19d( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(3)); |
|
406 |
reg_def XMM19e( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(4)); |
|
407 |
reg_def XMM19f( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(5)); |
|
408 |
reg_def XMM19g( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(6)); |
|
409 |
reg_def XMM19h( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(7)); |
|
410 |
reg_def XMM19i( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(8)); |
|
411 |
reg_def XMM19j( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(9)); |
|
412 |
reg_def XMM19k( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(10)); |
|
413 |
reg_def XMM19l( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(11)); |
|
414 |
reg_def XMM19m( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(12)); |
|
415 |
reg_def XMM19n( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(13)); |
|
416 |
reg_def XMM19o( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(14)); |
|
417 |
reg_def XMM19p( SOC, SOE, Op_RegF, 19, xmm19->as_VMReg()->next(15)); |
|
418 |
||
419 |
reg_def XMM20 ( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()); |
|
420 |
reg_def XMM20b( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(1)); |
|
421 |
reg_def XMM20c( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(2)); |
|
422 |
reg_def XMM20d( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(3)); |
|
423 |
reg_def XMM20e( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(4)); |
|
424 |
reg_def XMM20f( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(5)); |
|
425 |
reg_def XMM20g( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(6)); |
|
426 |
reg_def XMM20h( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(7)); |
|
427 |
reg_def XMM20i( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(8)); |
|
428 |
reg_def XMM20j( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(9)); |
|
429 |
reg_def XMM20k( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(10)); |
|
430 |
reg_def XMM20l( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(11)); |
|
431 |
reg_def XMM20m( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(12)); |
|
432 |
reg_def XMM20n( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(13)); |
|
433 |
reg_def XMM20o( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(14)); |
|
434 |
reg_def XMM20p( SOC, SOE, Op_RegF, 20, xmm20->as_VMReg()->next(15)); |
|
435 |
||
436 |
reg_def XMM21 ( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()); |
|
437 |
reg_def XMM21b( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(1)); |
|
438 |
reg_def XMM21c( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(2)); |
|
439 |
reg_def XMM21d( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(3)); |
|
440 |
reg_def XMM21e( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(4)); |
|
441 |
reg_def XMM21f( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(5)); |
|
442 |
reg_def XMM21g( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(6)); |
|
443 |
reg_def XMM21h( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(7)); |
|
444 |
reg_def XMM21i( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(8)); |
|
445 |
reg_def XMM21j( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(9)); |
|
446 |
reg_def XMM21k( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(10)); |
|
447 |
reg_def XMM21l( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(11)); |
|
448 |
reg_def XMM21m( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(12)); |
|
449 |
reg_def XMM21n( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(13)); |
|
450 |
reg_def XMM21o( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(14)); |
|
451 |
reg_def XMM21p( SOC, SOE, Op_RegF, 21, xmm21->as_VMReg()->next(15)); |
|
452 |
||
453 |
reg_def XMM22 ( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()); |
|
454 |
reg_def XMM22b( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(1)); |
|
455 |
reg_def XMM22c( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(2)); |
|
456 |
reg_def XMM22d( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(3)); |
|
457 |
reg_def XMM22e( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(4)); |
|
458 |
reg_def XMM22f( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(5)); |
|
459 |
reg_def XMM22g( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(6)); |
|
460 |
reg_def XMM22h( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(7)); |
|
461 |
reg_def XMM22i( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(8)); |
|
462 |
reg_def XMM22j( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(9)); |
|
463 |
reg_def XMM22k( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(10)); |
|
464 |
reg_def XMM22l( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(11)); |
|
465 |
reg_def XMM22m( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(12)); |
|
466 |
reg_def XMM22n( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(13)); |
|
467 |
reg_def XMM22o( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(14)); |
|
468 |
reg_def XMM22p( SOC, SOE, Op_RegF, 22, xmm22->as_VMReg()->next(15)); |
|
469 |
||
470 |
reg_def XMM23 ( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()); |
|
471 |
reg_def XMM23b( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(1)); |
|
472 |
reg_def XMM23c( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(2)); |
|
473 |
reg_def XMM23d( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(3)); |
|
474 |
reg_def XMM23e( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(4)); |
|
475 |
reg_def XMM23f( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(5)); |
|
476 |
reg_def XMM23g( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(6)); |
|
477 |
reg_def XMM23h( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(7)); |
|
478 |
reg_def XMM23i( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(8)); |
|
479 |
reg_def XMM23j( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(9)); |
|
480 |
reg_def XMM23k( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(10)); |
|
481 |
reg_def XMM23l( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(11)); |
|
482 |
reg_def XMM23m( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(12)); |
|
483 |
reg_def XMM23n( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(13)); |
|
484 |
reg_def XMM23o( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(14)); |
|
485 |
reg_def XMM23p( SOC, SOE, Op_RegF, 23, xmm23->as_VMReg()->next(15)); |
|
486 |
||
487 |
reg_def XMM24 ( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()); |
|
488 |
reg_def XMM24b( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(1)); |
|
489 |
reg_def XMM24c( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(2)); |
|
490 |
reg_def XMM24d( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(3)); |
|
491 |
reg_def XMM24e( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(4)); |
|
492 |
reg_def XMM24f( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(5)); |
|
493 |
reg_def XMM24g( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(6)); |
|
494 |
reg_def XMM24h( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(7)); |
|
495 |
reg_def XMM24i( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(8)); |
|
496 |
reg_def XMM24j( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(9)); |
|
497 |
reg_def XMM24k( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(10)); |
|
498 |
reg_def XMM24l( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(11)); |
|
499 |
reg_def XMM24m( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(12)); |
|
500 |
reg_def XMM24n( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(13)); |
|
501 |
reg_def XMM24o( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(14)); |
|
502 |
reg_def XMM24p( SOC, SOE, Op_RegF, 24, xmm24->as_VMReg()->next(15)); |
|
503 |
||
504 |
reg_def XMM25 ( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()); |
|
505 |
reg_def XMM25b( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(1)); |
|
506 |
reg_def XMM25c( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(2)); |
|
507 |
reg_def XMM25d( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(3)); |
|
508 |
reg_def XMM25e( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(4)); |
|
509 |
reg_def XMM25f( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(5)); |
|
510 |
reg_def XMM25g( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(6)); |
|
511 |
reg_def XMM25h( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(7)); |
|
512 |
reg_def XMM25i( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(8)); |
|
513 |
reg_def XMM25j( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(9)); |
|
514 |
reg_def XMM25k( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(10)); |
|
515 |
reg_def XMM25l( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(11)); |
|
516 |
reg_def XMM25m( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(12)); |
|
517 |
reg_def XMM25n( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(13)); |
|
518 |
reg_def XMM25o( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(14)); |
|
519 |
reg_def XMM25p( SOC, SOE, Op_RegF, 25, xmm25->as_VMReg()->next(15)); |
|
520 |
||
521 |
reg_def XMM26 ( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()); |
|
522 |
reg_def XMM26b( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(1)); |
|
523 |
reg_def XMM26c( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(2)); |
|
524 |
reg_def XMM26d( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(3)); |
|
525 |
reg_def XMM26e( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(4)); |
|
526 |
reg_def XMM26f( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(5)); |
|
527 |
reg_def XMM26g( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(6)); |
|
528 |
reg_def XMM26h( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(7)); |
|
529 |
reg_def XMM26i( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(8)); |
|
530 |
reg_def XMM26j( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(9)); |
|
531 |
reg_def XMM26k( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(10)); |
|
532 |
reg_def XMM26l( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(11)); |
|
533 |
reg_def XMM26m( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(12)); |
|
534 |
reg_def XMM26n( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(13)); |
|
535 |
reg_def XMM26o( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(14)); |
|
536 |
reg_def XMM26p( SOC, SOE, Op_RegF, 26, xmm26->as_VMReg()->next(15)); |
|
537 |
||
538 |
reg_def XMM27g( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(1)); |
|
539 |
reg_def XMM27c( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(2)); |
|
540 |
reg_def XMM27d( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(3)); |
|
541 |
reg_def XMM27e( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(4)); |
|
542 |
reg_def XMM27f( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(5)); |
|
543 |
reg_def XMM27g( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(6)); |
|
544 |
reg_def XMM27h( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(7)); |
|
545 |
reg_def XMM27i( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(8)); |
|
546 |
reg_def XMM27j( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(9)); |
|
547 |
reg_def XMM27k( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(10)); |
|
548 |
reg_def XMM27l( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(11)); |
|
549 |
reg_def XMM27m( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(12)); |
|
550 |
reg_def XMM27n( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(13)); |
|
551 |
reg_def XMM27o( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(14)); |
|
552 |
reg_def XMM27p( SOC, SOE, Op_RegF, 27, xmm27->as_VMReg()->next(15)); |
|
553 |
||
554 |
reg_def XMM28 ( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()); |
|
555 |
reg_def XMM28b( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(1)); |
|
556 |
reg_def XMM28c( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(2)); |
|
557 |
reg_def XMM28d( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(3)); |
|
558 |
reg_def XMM28e( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(4)); |
|
559 |
reg_def XMM28f( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(5)); |
|
560 |
reg_def XMM28g( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(6)); |
|
561 |
reg_def XMM28h( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(7)); |
|
562 |
reg_def XMM28i( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(8)); |
|
563 |
reg_def XMM28j( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(9)); |
|
564 |
reg_def XMM28k( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(10)); |
|
565 |
reg_def XMM28l( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(11)); |
|
566 |
reg_def XMM28m( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(12)); |
|
567 |
reg_def XMM28n( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(13)); |
|
568 |
reg_def XMM28o( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(14)); |
|
569 |
reg_def XMM28p( SOC, SOE, Op_RegF, 28, xmm28->as_VMReg()->next(15)); |
|
570 |
||
571 |
reg_def XMM29 ( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()); |
|
572 |
reg_def XMM29b( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(1)); |
|
573 |
reg_def XMM29c( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(2)); |
|
574 |
reg_def XMM29d( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(3)); |
|
575 |
reg_def XMM29e( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(4)); |
|
576 |
reg_def XMM29f( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(5)); |
|
577 |
reg_def XMM29g( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(6)); |
|
578 |
reg_def XMM29h( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(7)); |
|
579 |
reg_def XMM29i( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(8)); |
|
580 |
reg_def XMM29j( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(9)); |
|
581 |
reg_def XMM29k( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(10)); |
|
582 |
reg_def XMM29l( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(11)); |
|
583 |
reg_def XMM29m( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(12)); |
|
584 |
reg_def XMM29n( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(13)); |
|
585 |
reg_def XMM29o( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(14)); |
|
586 |
reg_def XMM29p( SOC, SOE, Op_RegF, 29, xmm29->as_VMReg()->next(15)); |
|
587 |
||
588 |
reg_def XMM30 ( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()); |
|
589 |
reg_def XMM30b( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(1)); |
|
590 |
reg_def XMM30c( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(2)); |
|
591 |
reg_def XMM30d( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(3)); |
|
592 |
reg_def XMM30e( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(4)); |
|
593 |
reg_def XMM30f( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(5)); |
|
594 |
reg_def XMM30g( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(6)); |
|
595 |
reg_def XMM30h( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(7)); |
|
596 |
reg_def XMM30i( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(8)); |
|
597 |
reg_def XMM30j( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(9)); |
|
598 |
reg_def XMM30k( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(10)); |
|
599 |
reg_def XMM30l( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(11)); |
|
600 |
reg_def XMM30m( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(12)); |
|
601 |
reg_def XMM30n( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(13)); |
|
602 |
reg_def XMM30o( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(14)); |
|
603 |
reg_def XMM30p( SOC, SOE, Op_RegF, 30, xmm30->as_VMReg()->next(15)); |
|
604 |
||
605 |
reg_def XMM31 ( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()); |
|
606 |
reg_def XMM31b( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(1)); |
|
607 |
reg_def XMM31c( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(2)); |
|
608 |
reg_def XMM31d( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(3)); |
|
609 |
reg_def XMM31e( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(4)); |
|
610 |
reg_def XMM31f( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(5)); |
|
611 |
reg_def XMM31g( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(6)); |
|
612 |
reg_def XMM31h( SOC, SOE, Op_RegF, 31, xmm31>-as_VMReg()->next(7)); |
|
613 |
reg_def XMM31i( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(8)); |
|
614 |
reg_def XMM31j( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(9)); |
|
615 |
reg_def XMM31k( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(10)); |
|
616 |
reg_def XMM31l( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(11)); |
|
617 |
reg_def XMM31m( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(12)); |
|
618 |
reg_def XMM31n( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(13)); |
|
619 |
reg_def XMM31o( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(14)); |
|
620 |
reg_def XMM31p( SOC, SOE, Op_RegF, 31, xmm31->as_VMReg()->next(15)); |
|
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|
621 |
|
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|
622 |
#else // _WIN64 |
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7119644: Increase superword's vector size up to 256 bits
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|
623 |
|
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|
624 |
reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); |
13294 | 625 |
reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(1)); |
626 |
reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(2)); |
|
627 |
reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(3)); |
|
628 |
reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(4)); |
|
629 |
reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(5)); |
|
630 |
reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(6)); |
|
631 |
reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(7)); |
|
30624 | 632 |
reg_def XMM6i( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(8)); |
633 |
reg_def XMM6j( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(9)); |
|
634 |
reg_def XMM6k( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(10)); |
|
635 |
reg_def XMM6l( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(11)); |
|
636 |
reg_def XMM6m( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(12)); |
|
637 |
reg_def XMM6n( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(13)); |
|
638 |
reg_def XMM6o( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(14)); |
|
639 |
reg_def XMM6p( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(15)); |
|
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|
640 |
|
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|
641 |
reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); |
13294 | 642 |
reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(1)); |
643 |
reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(2)); |
|
644 |
reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(3)); |
|
645 |
reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(4)); |
|
646 |
reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(5)); |
|
647 |
reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(6)); |
|
648 |
reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(7)); |
|
30624 | 649 |
reg_def XMM7i( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(8)); |
650 |
reg_def XMM7j( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(9)); |
|
651 |
reg_def XMM7k( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(10)); |
|
652 |
reg_def XMM7l( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(11)); |
|
653 |
reg_def XMM7m( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(12)); |
|
654 |
reg_def XMM7n( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(13)); |
|
655 |
reg_def XMM7o( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(14)); |
|
656 |
reg_def XMM7p( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(15)); |
|
13104
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|
657 |
|
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7119644: Increase superword's vector size up to 256 bits
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diff
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|
658 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
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parents:
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diff
changeset
|
659 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
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diff
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|
660 |
reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); |
13294 | 661 |
reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(1)); |
662 |
reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(2)); |
|
663 |
reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(3)); |
|
664 |
reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(4)); |
|
665 |
reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(5)); |
|
666 |
reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(6)); |
|
667 |
reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(7)); |
|
30624 | 668 |
reg_def XMM8i( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(8)); |
669 |
reg_def XMM8j( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(9)); |
|
670 |
reg_def XMM8k( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(10)); |
|
671 |
reg_def XMM8l( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(11)); |
|
672 |
reg_def XMM8m( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(12)); |
|
673 |
reg_def XMM8n( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(13)); |
|
674 |
reg_def XMM8o( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(14)); |
|
675 |
reg_def XMM8p( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(15)); |
|
13104
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11794
diff
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|
676 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
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|
677 |
reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); |
13294 | 678 |
reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(1)); |
679 |
reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(2)); |
|
680 |
reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(3)); |
|
681 |
reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(4)); |
|
682 |
reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(5)); |
|
683 |
reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(6)); |
|
684 |
reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(7)); |
|
30624 | 685 |
reg_def XMM9i( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(8)); |
686 |
reg_def XMM9j( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(9)); |
|
687 |
reg_def XMM9k( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(10)); |
|
688 |
reg_def XMM9l( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(11)); |
|
689 |
reg_def XMM9m( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(12)); |
|
690 |
reg_def XMM9n( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(13)); |
|
691 |
reg_def XMM9o( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(14)); |
|
692 |
reg_def XMM9p( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(15)); |
|
13104
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parents:
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diff
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|
693 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
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parents:
11794
diff
changeset
|
694 |
reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); |
13294 | 695 |
reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(1)); |
696 |
reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(2)); |
|
697 |
reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(3)); |
|
698 |
reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(4)); |
|
699 |
reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(5)); |
|
700 |
reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(6)); |
|
701 |
reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(7)); |
|
30624 | 702 |
reg_def XMM10i( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(8)); |
703 |
reg_def XMM10j( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(9)); |
|
704 |
reg_def XMM10k( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(10)); |
|
705 |
reg_def XMM10l( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(11)); |
|
706 |
reg_def XMM10m( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(12)); |
|
707 |
reg_def XMM10n( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(13)); |
|
708 |
reg_def XMM10o( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(14)); |
|
709 |
reg_def XMM10p( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(15)); |
|
13104
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|
710 |
|
657b387034fb
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|
711 |
reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); |
13294 | 712 |
reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(1)); |
713 |
reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(2)); |
|
714 |
reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(3)); |
|
715 |
reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(4)); |
|
716 |
reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(5)); |
|
717 |
reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(6)); |
|
718 |
reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(7)); |
|
30624 | 719 |
reg_def XMM11i( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(8)); |
720 |
reg_def XMM11j( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(9)); |
|
721 |
reg_def XMM11k( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(10)); |
|
722 |
reg_def XMM11l( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(11)); |
|
723 |
reg_def XMM11m( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(12)); |
|
724 |
reg_def XMM11n( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(13)); |
|
725 |
reg_def XMM11o( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(14)); |
|
726 |
reg_def XMM11p( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(15)); |
|
13104
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diff
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|
727 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
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parents:
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diff
changeset
|
728 |
reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); |
13294 | 729 |
reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(1)); |
730 |
reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(2)); |
|
731 |
reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(3)); |
|
732 |
reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(4)); |
|
733 |
reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(5)); |
|
734 |
reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(6)); |
|
735 |
reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(7)); |
|
30624 | 736 |
reg_def XMM12i( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(8)); |
737 |
reg_def XMM12j( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(9)); |
|
738 |
reg_def XMM12k( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(10)); |
|
739 |
reg_def XMM12l( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(11)); |
|
740 |
reg_def XMM12m( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(12)); |
|
741 |
reg_def XMM12n( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(13)); |
|
742 |
reg_def XMM12o( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(14)); |
|
743 |
reg_def XMM12p( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(15)); |
|
13104
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diff
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|
744 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
745 |
reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); |
13294 | 746 |
reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(1)); |
747 |
reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(2)); |
|
748 |
reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(3)); |
|
749 |
reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(4)); |
|
750 |
reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(5)); |
|
751 |
reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(6)); |
|
752 |
reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(7)); |
|
30624 | 753 |
reg_def XMM13i( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(8)); |
754 |
reg_def XMM13j( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(9)); |
|
755 |
reg_def XMM13k( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(10)); |
|
756 |
reg_def XMM13l( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(11)); |
|
757 |
reg_def XMM13m( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(12)); |
|
758 |
reg_def XMM13n( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(13)); |
|
759 |
reg_def XMM13o( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(14)); |
|
760 |
reg_def XMM13p( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(15)); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
761 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
762 |
reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); |
13294 | 763 |
reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(1)); |
764 |
reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(2)); |
|
765 |
reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(3)); |
|
766 |
reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(4)); |
|
767 |
reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(5)); |
|
768 |
reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(6)); |
|
769 |
reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(7)); |
|
30624 | 770 |
reg_def XMM14i( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(8)); |
771 |
reg_def XMM14j( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(9)); |
|
772 |
reg_def XMM14k( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(10)); |
|
773 |
reg_def XMM14l( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(11)); |
|
774 |
reg_def XMM14m( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(12)); |
|
775 |
reg_def XMM14n( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(13)); |
|
776 |
reg_def XMM14o( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(14)); |
|
777 |
reg_def XMM14p( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(15)); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
778 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
779 |
reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); |
13294 | 780 |
reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(1)); |
781 |
reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(2)); |
|
782 |
reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(3)); |
|
783 |
reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(4)); |
|
784 |
reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(5)); |
|
785 |
reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(6)); |
|
786 |
reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(7)); |
|
30624 | 787 |
reg_def XMM15i( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(8)); |
788 |
reg_def XMM15j( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(9)); |
|
789 |
reg_def XMM15k( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(10)); |
|
790 |
reg_def XMM15l( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(11)); |
|
791 |
reg_def XMM15m( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(12)); |
|
792 |
reg_def XMM15n( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(13)); |
|
793 |
reg_def XMM15o( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(14)); |
|
794 |
reg_def XMM15p( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(15)); |
|
795 |
||
796 |
reg_def XMM16 ( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()); |
|
797 |
reg_def XMM16b( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(1)); |
|
798 |
reg_def XMM16c( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(2)); |
|
799 |
reg_def XMM16d( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(3)); |
|
800 |
reg_def XMM16e( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(4)); |
|
801 |
reg_def XMM16f( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(5)); |
|
802 |
reg_def XMM16g( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(6)); |
|
803 |
reg_def XMM16h( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(7)); |
|
804 |
reg_def XMM16i( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(8)); |
|
805 |
reg_def XMM16j( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(9)); |
|
806 |
reg_def XMM16k( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(10)); |
|
807 |
reg_def XMM16l( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(11)); |
|
808 |
reg_def XMM16m( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(12)); |
|
809 |
reg_def XMM16n( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(13)); |
|
810 |
reg_def XMM16o( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(14)); |
|
811 |
reg_def XMM16p( SOC, SOC, Op_RegF, 16, xmm16->as_VMReg()->next(15)); |
|
812 |
||
813 |
reg_def XMM17 ( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()); |
|
814 |
reg_def XMM17b( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(1)); |
|
815 |
reg_def XMM17c( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(2)); |
|
816 |
reg_def XMM17d( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(3)); |
|
817 |
reg_def XMM17e( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(4)); |
|
818 |
reg_def XMM17f( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(5)); |
|
819 |
reg_def XMM17g( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(6)); |
|
820 |
reg_def XMM17h( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(7)); |
|
821 |
reg_def XMM17i( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(8)); |
|
822 |
reg_def XMM17j( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(9)); |
|
823 |
reg_def XMM17k( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(10)); |
|
824 |
reg_def XMM17l( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(11)); |
|
825 |
reg_def XMM17m( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(12)); |
|
826 |
reg_def XMM17n( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(13)); |
|
827 |
reg_def XMM17o( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(14)); |
|
828 |
reg_def XMM17p( SOC, SOC, Op_RegF, 17, xmm17->as_VMReg()->next(15)); |
|
829 |
||
830 |
reg_def XMM18 ( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()); |
|
831 |
reg_def XMM18b( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(1)); |
|
832 |
reg_def XMM18c( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(2)); |
|
833 |
reg_def XMM18d( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(3)); |
|
834 |
reg_def XMM18e( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(4)); |
|
835 |
reg_def XMM18f( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(5)); |
|
836 |
reg_def XMM18g( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(6)); |
|
837 |
reg_def XMM18h( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(7)); |
|
838 |
reg_def XMM18i( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(8)); |
|
839 |
reg_def XMM18j( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(9)); |
|
840 |
reg_def XMM18k( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(10)); |
|
841 |
reg_def XMM18l( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(11)); |
|
842 |
reg_def XMM18m( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(12)); |
|
843 |
reg_def XMM18n( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(13)); |
|
844 |
reg_def XMM18o( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(14)); |
|
845 |
reg_def XMM18p( SOC, SOC, Op_RegF, 18, xmm18->as_VMReg()->next(15)); |
|
846 |
||
847 |
reg_def XMM19 ( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()); |
|
848 |
reg_def XMM19b( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(1)); |
|
849 |
reg_def XMM19c( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(2)); |
|
850 |
reg_def XMM19d( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(3)); |
|
851 |
reg_def XMM19e( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(4)); |
|
852 |
reg_def XMM19f( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(5)); |
|
853 |
reg_def XMM19g( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(6)); |
|
854 |
reg_def XMM19h( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(7)); |
|
855 |
reg_def XMM19i( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(8)); |
|
856 |
reg_def XMM19j( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(9)); |
|
857 |
reg_def XMM19k( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(10)); |
|
858 |
reg_def XMM19l( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(11)); |
|
859 |
reg_def XMM19m( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(12)); |
|
860 |
reg_def XMM19n( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(13)); |
|
861 |
reg_def XMM19o( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(14)); |
|
862 |
reg_def XMM19p( SOC, SOC, Op_RegF, 19, xmm19->as_VMReg()->next(15)); |
|
863 |
||
864 |
reg_def XMM20 ( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()); |
|
865 |
reg_def XMM20b( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(1)); |
|
866 |
reg_def XMM20c( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(2)); |
|
867 |
reg_def XMM20d( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(3)); |
|
868 |
reg_def XMM20e( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(4)); |
|
869 |
reg_def XMM20f( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(5)); |
|
870 |
reg_def XMM20g( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(6)); |
|
871 |
reg_def XMM20h( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(7)); |
|
872 |
reg_def XMM20i( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(8)); |
|
873 |
reg_def XMM20j( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(9)); |
|
874 |
reg_def XMM20k( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(10)); |
|
875 |
reg_def XMM20l( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(11)); |
|
876 |
reg_def XMM20m( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(12)); |
|
877 |
reg_def XMM20n( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(13)); |
|
878 |
reg_def XMM20o( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(14)); |
|
879 |
reg_def XMM20p( SOC, SOC, Op_RegF, 20, xmm20->as_VMReg()->next(15)); |
|
880 |
||
881 |
reg_def XMM21 ( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()); |
|
882 |
reg_def XMM21b( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(1)); |
|
883 |
reg_def XMM21c( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(2)); |
|
884 |
reg_def XMM21d( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(3)); |
|
885 |
reg_def XMM21e( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(4)); |
|
886 |
reg_def XMM21f( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(5)); |
|
887 |
reg_def XMM21g( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(6)); |
|
888 |
reg_def XMM21h( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(7)); |
|
889 |
reg_def XMM21i( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(8)); |
|
890 |
reg_def XMM21j( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(9)); |
|
891 |
reg_def XMM21k( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(10)); |
|
892 |
reg_def XMM21l( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(11)); |
|
893 |
reg_def XMM21m( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(12)); |
|
894 |
reg_def XMM21n( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(13)); |
|
895 |
reg_def XMM21o( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(14)); |
|
896 |
reg_def XMM21p( SOC, SOC, Op_RegF, 21, xmm21->as_VMReg()->next(15)); |
|
897 |
||
898 |
reg_def XMM22 ( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()); |
|
899 |
reg_def XMM22b( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(1)); |
|
900 |
reg_def XMM22c( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(2)); |
|
901 |
reg_def XMM22d( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(3)); |
|
902 |
reg_def XMM22e( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(4)); |
|
903 |
reg_def XMM22f( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(5)); |
|
904 |
reg_def XMM22g( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(6)); |
|
905 |
reg_def XMM22h( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(7)); |
|
906 |
reg_def XMM22i( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(8)); |
|
907 |
reg_def XMM22j( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(9)); |
|
908 |
reg_def XMM22k( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(10)); |
|
909 |
reg_def XMM22l( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(11)); |
|
910 |
reg_def XMM22m( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(12)); |
|
911 |
reg_def XMM22n( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(13)); |
|
912 |
reg_def XMM22o( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(14)); |
|
913 |
reg_def XMM22p( SOC, SOC, Op_RegF, 22, xmm22->as_VMReg()->next(15)); |
|
914 |
||
915 |
reg_def XMM23 ( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()); |
|
916 |
reg_def XMM23b( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(1)); |
|
917 |
reg_def XMM23c( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(2)); |
|
918 |
reg_def XMM23d( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(3)); |
|
919 |
reg_def XMM23e( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(4)); |
|
920 |
reg_def XMM23f( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(5)); |
|
921 |
reg_def XMM23g( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(6)); |
|
922 |
reg_def XMM23h( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(7)); |
|
923 |
reg_def XMM23i( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(8)); |
|
924 |
reg_def XMM23j( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(9)); |
|
925 |
reg_def XMM23k( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(10)); |
|
926 |
reg_def XMM23l( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(11)); |
|
927 |
reg_def XMM23m( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(12)); |
|
928 |
reg_def XMM23n( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(13)); |
|
929 |
reg_def XMM23o( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(14)); |
|
930 |
reg_def XMM23p( SOC, SOC, Op_RegF, 23, xmm23->as_VMReg()->next(15)); |
|
931 |
||
932 |
reg_def XMM24 ( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()); |
|
933 |
reg_def XMM24b( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(1)); |
|
934 |
reg_def XMM24c( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(2)); |
|
935 |
reg_def XMM24d( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(3)); |
|
936 |
reg_def XMM24e( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(4)); |
|
937 |
reg_def XMM24f( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(5)); |
|
938 |
reg_def XMM24g( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(6)); |
|
939 |
reg_def XMM24h( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(7)); |
|
940 |
reg_def XMM24i( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(8)); |
|
941 |
reg_def XMM24j( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(9)); |
|
942 |
reg_def XMM24k( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(10)); |
|
943 |
reg_def XMM24l( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(11)); |
|
944 |
reg_def XMM24m( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(12)); |
|
945 |
reg_def XMM24n( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(13)); |
|
946 |
reg_def XMM24o( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(14)); |
|
947 |
reg_def XMM24p( SOC, SOC, Op_RegF, 24, xmm24->as_VMReg()->next(15)); |
|
948 |
||
949 |
reg_def XMM25 ( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()); |
|
950 |
reg_def XMM25b( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(1)); |
|
951 |
reg_def XMM25c( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(2)); |
|
952 |
reg_def XMM25d( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(3)); |
|
953 |
reg_def XMM25e( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(4)); |
|
954 |
reg_def XMM25f( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(5)); |
|
955 |
reg_def XMM25g( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(6)); |
|
956 |
reg_def XMM25h( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(7)); |
|
957 |
reg_def XMM25i( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(8)); |
|
958 |
reg_def XMM25j( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(9)); |
|
959 |
reg_def XMM25k( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(10)); |
|
960 |
reg_def XMM25l( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(11)); |
|
961 |
reg_def XMM25m( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(12)); |
|
962 |
reg_def XMM25n( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(13)); |
|
963 |
reg_def XMM25o( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(14)); |
|
964 |
reg_def XMM25p( SOC, SOC, Op_RegF, 25, xmm25->as_VMReg()->next(15)); |
|
965 |
||
966 |
reg_def XMM26 ( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()); |
|
967 |
reg_def XMM26b( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(1)); |
|
968 |
reg_def XMM26c( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(2)); |
|
969 |
reg_def XMM26d( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(3)); |
|
970 |
reg_def XMM26e( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(4)); |
|
971 |
reg_def XMM26f( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(5)); |
|
972 |
reg_def XMM26g( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(6)); |
|
973 |
reg_def XMM26h( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(7)); |
|
974 |
reg_def XMM26i( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(8)); |
|
975 |
reg_def XMM26j( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(9)); |
|
976 |
reg_def XMM26k( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(10)); |
|
977 |
reg_def XMM26l( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(11)); |
|
978 |
reg_def XMM26m( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(12)); |
|
979 |
reg_def XMM26n( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(13)); |
|
980 |
reg_def XMM26o( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(14)); |
|
981 |
reg_def XMM26p( SOC, SOC, Op_RegF, 26, xmm26->as_VMReg()->next(15)); |
|
982 |
||
983 |
reg_def XMM27 ( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()); |
|
984 |
reg_def XMM27b( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(1)); |
|
985 |
reg_def XMM27c( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(2)); |
|
986 |
reg_def XMM27d( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(3)); |
|
987 |
reg_def XMM27e( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(4)); |
|
988 |
reg_def XMM27f( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(5)); |
|
989 |
reg_def XMM27g( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(6)); |
|
990 |
reg_def XMM27h( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(7)); |
|
991 |
reg_def XMM27i( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(8)); |
|
992 |
reg_def XMM27j( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(9)); |
|
993 |
reg_def XMM27k( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(10)); |
|
994 |
reg_def XMM27l( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(11)); |
|
995 |
reg_def XMM27m( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(12)); |
|
996 |
reg_def XMM27n( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(13)); |
|
997 |
reg_def XMM27o( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(14)); |
|
998 |
reg_def XMM27p( SOC, SOC, Op_RegF, 27, xmm27->as_VMReg()->next(15)); |
|
999 |
||
1000 |
reg_def XMM28 ( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()); |
|
1001 |
reg_def XMM28b( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(1)); |
|
1002 |
reg_def XMM28c( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(2)); |
|
1003 |
reg_def XMM28d( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(3)); |
|
1004 |
reg_def XMM28e( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(4)); |
|
1005 |
reg_def XMM28f( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(5)); |
|
1006 |
reg_def XMM28g( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(6)); |
|
1007 |
reg_def XMM28h( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(7)); |
|
1008 |
reg_def XMM28i( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(8)); |
|
1009 |
reg_def XMM28j( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(9)); |
|
1010 |
reg_def XMM28k( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(10)); |
|
1011 |
reg_def XMM28l( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(11)); |
|
1012 |
reg_def XMM28m( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(12)); |
|
1013 |
reg_def XMM28n( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(13)); |
|
1014 |
reg_def XMM28o( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(14)); |
|
1015 |
reg_def XMM28p( SOC, SOC, Op_RegF, 28, xmm28->as_VMReg()->next(15)); |
|
1016 |
||
1017 |
reg_def XMM29 ( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()); |
|
1018 |
reg_def XMM29b( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(1)); |
|
1019 |
reg_def XMM29c( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(2)); |
|
1020 |
reg_def XMM29d( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(3)); |
|
1021 |
reg_def XMM29e( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(4)); |
|
1022 |
reg_def XMM29f( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(5)); |
|
1023 |
reg_def XMM29g( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(6)); |
|
1024 |
reg_def XMM29h( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(7)); |
|
1025 |
reg_def XMM29i( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(8)); |
|
1026 |
reg_def XMM29j( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(9)); |
|
1027 |
reg_def XMM29k( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(10)); |
|
1028 |
reg_def XMM29l( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(11)); |
|
1029 |
reg_def XMM29m( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(12)); |
|
1030 |
reg_def XMM29n( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(13)); |
|
1031 |
reg_def XMM29o( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(14)); |
|
1032 |
reg_def XMM29p( SOC, SOC, Op_RegF, 29, xmm29->as_VMReg()->next(15)); |
|
1033 |
||
1034 |
reg_def XMM30 ( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()); |
|
1035 |
reg_def XMM30b( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(1)); |
|
1036 |
reg_def XMM30c( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(2)); |
|
1037 |
reg_def XMM30d( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(3)); |
|
1038 |
reg_def XMM30e( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(4)); |
|
1039 |
reg_def XMM30f( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(5)); |
|
1040 |
reg_def XMM30g( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(6)); |
|
1041 |
reg_def XMM30h( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(7)); |
|
1042 |
reg_def XMM30i( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(8)); |
|
1043 |
reg_def XMM30j( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(9)); |
|
1044 |
reg_def XMM30k( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(10)); |
|
1045 |
reg_def XMM30l( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(11)); |
|
1046 |
reg_def XMM30m( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(12)); |
|
1047 |
reg_def XMM30n( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(13)); |
|
1048 |
reg_def XMM30o( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(14)); |
|
1049 |
reg_def XMM30p( SOC, SOC, Op_RegF, 30, xmm30->as_VMReg()->next(15)); |
|
1050 |
||
1051 |
reg_def XMM31 ( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()); |
|
1052 |
reg_def XMM31b( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(1)); |
|
1053 |
reg_def XMM31c( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(2)); |
|
1054 |
reg_def XMM31d( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(3)); |
|
1055 |
reg_def XMM31e( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(4)); |
|
1056 |
reg_def XMM31f( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(5)); |
|
1057 |
reg_def XMM31g( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(6)); |
|
1058 |
reg_def XMM31h( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(7)); |
|
1059 |
reg_def XMM31i( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(8)); |
|
1060 |
reg_def XMM31j( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(9)); |
|
1061 |
reg_def XMM31k( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(10)); |
|
1062 |
reg_def XMM31l( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(11)); |
|
1063 |
reg_def XMM31m( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(12)); |
|
1064 |
reg_def XMM31n( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(13)); |
|
1065 |
reg_def XMM31o( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(14)); |
|
1066 |
reg_def XMM31p( SOC, SOC, Op_RegF, 31, xmm31->as_VMReg()->next(15)); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1067 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1068 |
#endif // _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1069 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1070 |
#endif // _WIN64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1071 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1072 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1073 |
reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1074 |
#else |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1075 |
reg_def RFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1076 |
#endif // _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1077 |
|
30624 | 1078 |
alloc_class chunk1(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, XMM0i, XMM0j, XMM0k, XMM0l, XMM0m, XMM0n, XMM0o, XMM0p, |
1079 |
XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, XMM1i, XMM1j, XMM1k, XMM1l, XMM1m, XMM1n, XMM1o, XMM1p, |
|
1080 |
XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, XMM2i, XMM2j, XMM2k, XMM2l, XMM2m, XMM2n, XMM2o, XMM2p, |
|
1081 |
XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, XMM3i, XMM3j, XMM3k, XMM3l, XMM3m, XMM3n, XMM3o, XMM3p, |
|
1082 |
XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, XMM4i, XMM4j, XMM4k, XMM4l, XMM4m, XMM4n, XMM4o, XMM4p, |
|
1083 |
XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, XMM5i, XMM5j, XMM5k, XMM5l, XMM5m, XMM5n, XMM5o, XMM5p, |
|
1084 |
XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, XMM6i, XMM6j, XMM6k, XMM6l, XMM6m, XMM6n, XMM6o, XMM6p, |
|
1085 |
XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h, XMM7i, XMM7j, XMM7k, XMM7l, XMM7m, XMM7n, XMM7o, XMM7p |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1086 |
#ifdef _LP64 |
30624 | 1087 |
,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, XMM8i, XMM8j, XMM8k, XMM8l, XMM8m, XMM8n, XMM8o, XMM8p, |
1088 |
XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, XMM9i, XMM9j, XMM9k, XMM9l, XMM9m, XMM9n, XMM9o, XMM9p, |
|
1089 |
XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, XMM10i, XMM10j, XMM10k, XMM10l, XMM10m, XMM10n, XMM10o, XMM10p, |
|
1090 |
XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, XMM11i, XMM11j, XMM11k, XMM11l, XMM11m, XMM11n, XMM11o, XMM11p, |
|
1091 |
XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, XMM12i, XMM12j, XMM12k, XMM12l, XMM12m, XMM12n, XMM12o, XMM12p, |
|
1092 |
XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, XMM13i, XMM13j, XMM13k, XMM13l, XMM13m, XMM13n, XMM13o, XMM13p, |
|
1093 |
XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, XMM14i, XMM14j, XMM14k, XMM14l, XMM14m, XMM14n, XMM14o, XMM14p, |
|
1094 |
XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h, XMM15i, XMM15j, XMM15k, XMM15l, XMM15m, XMM15n, XMM15o, XMM15p |
|
1095 |
,XMM16, XMM16b, XMM16c, XMM16d, XMM16e, XMM16f, XMM16g, XMM16h, XMM16i, XMM16j, XMM16k, XMM16l, XMM16m, XMM16n, XMM16o, XMM16p, |
|
1096 |
XMM17, XMM17b, XMM17c, XMM17d, XMM17e, XMM17f, XMM17g, XMM17h, XMM17i, XMM17j, XMM17k, XMM17l, XMM17m, XMM17n, XMM17o, XMM17p, |
|
1097 |
XMM18, XMM18b, XMM18c, XMM18d, XMM18e, XMM18f, XMM18g, XMM18h, XMM18i, XMM18j, XMM18k, XMM18l, XMM18m, XMM18n, XMM18o, XMM18p, |
|
1098 |
XMM19, XMM19b, XMM19c, XMM19d, XMM19e, XMM19f, XMM19g, XMM19h, XMM19i, XMM19j, XMM19k, XMM19l, XMM19m, XMM19n, XMM19o, XMM19p, |
|
1099 |
XMM20, XMM20b, XMM20c, XMM20d, XMM20e, XMM20f, XMM20g, XMM20h, XMM20i, XMM20j, XMM20k, XMM20l, XMM20m, XMM20n, XMM20o, XMM20p, |
|
1100 |
XMM21, XMM21b, XMM21c, XMM21d, XMM21e, XMM21f, XMM21g, XMM21h, XMM21i, XMM21j, XMM21k, XMM21l, XMM21m, XMM21n, XMM21o, XMM21p, |
|
1101 |
XMM22, XMM22b, XMM22c, XMM22d, XMM22e, XMM22f, XMM22g, XMM22h, XMM22i, XMM22j, XMM22k, XMM22l, XMM22m, XMM22n, XMM22o, XMM22p, |
|
1102 |
XMM23, XMM23b, XMM23c, XMM23d, XMM23e, XMM23f, XMM23g, XMM23h, XMM23i, XMM23j, XMM23k, XMM23l, XMM23m, XMM23n, XMM23o, XMM23p, |
|
1103 |
XMM24, XMM24b, XMM24c, XMM24d, XMM24e, XMM24f, XMM24g, XMM24h, XMM24i, XMM24j, XMM24k, XMM24l, XMM24m, XMM24n, XMM24o, XMM24p, |
|
1104 |
XMM25, XMM25b, XMM25c, XMM25d, XMM25e, XMM25f, XMM25g, XMM25h, XMM25i, XMM25j, XMM25k, XMM25l, XMM25m, XMM25n, XMM25o, XMM25p, |
|
1105 |
XMM26, XMM26b, XMM26c, XMM26d, XMM26e, XMM26f, XMM26g, XMM26h, XMM26i, XMM26j, XMM26k, XMM26l, XMM26m, XMM26n, XMM26o, XMM26p, |
|
1106 |
XMM27, XMM27b, XMM27c, XMM27d, XMM27e, XMM27f, XMM27g, XMM27h, XMM27i, XMM27j, XMM27k, XMM27l, XMM27m, XMM27n, XMM27o, XMM27p, |
|
1107 |
XMM28, XMM28b, XMM28c, XMM28d, XMM28e, XMM28f, XMM28g, XMM28h, XMM28i, XMM28j, XMM28k, XMM28l, XMM28m, XMM28n, XMM28o, XMM28p, |
|
1108 |
XMM29, XMM29b, XMM29c, XMM29d, XMM29e, XMM29f, XMM29g, XMM29h, XMM29i, XMM29j, XMM29k, XMM29l, XMM29m, XMM29n, XMM29o, XMM29p, |
|
1109 |
XMM30, XMM30b, XMM30c, XMM30d, XMM30e, XMM30f, XMM30g, XMM30h, XMM30i, XMM30j, XMM30k, XMM30l, XMM30m, XMM30n, XMM30o, XMM30p, |
|
1110 |
XMM31, XMM31b, XMM31c, XMM31d, XMM31e, XMM31f, XMM31g, XMM31h, XMM31i, XMM31j, XMM31k, XMM31l, XMM31m, XMM31n, XMM31o, XMM31p |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1111 |
#endif |
30624 | 1112 |
); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1113 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1114 |
// flags allocation class should be last. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1115 |
alloc_class chunk2(RFLAGS); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1116 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1117 |
// Singleton class for condition codes |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1118 |
reg_class int_flags(RFLAGS); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1119 |
|
30624 | 1120 |
// Class for pre evex float registers |
1121 |
reg_class float_reg_legacy(XMM0, |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1122 |
XMM1, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1123 |
XMM2, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1124 |
XMM3, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1125 |
XMM4, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1126 |
XMM5, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1127 |
XMM6, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1128 |
XMM7 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1129 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1130 |
,XMM8, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1131 |
XMM9, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1132 |
XMM10, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1133 |
XMM11, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1134 |
XMM12, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1135 |
XMM13, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1136 |
XMM14, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1137 |
XMM15 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1138 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1139 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1140 |
|
30624 | 1141 |
// Class for evex float registers |
1142 |
reg_class float_reg_evex(XMM0, |
|
1143 |
XMM1, |
|
1144 |
XMM2, |
|
1145 |
XMM3, |
|
1146 |
XMM4, |
|
1147 |
XMM5, |
|
1148 |
XMM6, |
|
1149 |
XMM7 |
|
1150 |
#ifdef _LP64 |
|
1151 |
,XMM8, |
|
1152 |
XMM9, |
|
1153 |
XMM10, |
|
1154 |
XMM11, |
|
1155 |
XMM12, |
|
1156 |
XMM13, |
|
1157 |
XMM14, |
|
1158 |
XMM15, |
|
1159 |
XMM16, |
|
1160 |
XMM17, |
|
1161 |
XMM18, |
|
1162 |
XMM19, |
|
1163 |
XMM20, |
|
1164 |
XMM21, |
|
1165 |
XMM22, |
|
1166 |
XMM23, |
|
1167 |
XMM24, |
|
1168 |
XMM25, |
|
1169 |
XMM26, |
|
1170 |
XMM27, |
|
1171 |
XMM28, |
|
1172 |
XMM29, |
|
1173 |
XMM30, |
|
1174 |
XMM31 |
|
1175 |
#endif |
|
1176 |
); |
|
1177 |
||
1178 |
reg_class_dynamic float_reg(float_reg_evex, float_reg_legacy, %{ VM_Version::supports_evex() %} ); |
|
1179 |
||
1180 |
// Class for pre evex double registers |
|
1181 |
reg_class double_reg_legacy(XMM0, XMM0b, |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1182 |
XMM1, XMM1b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1183 |
XMM2, XMM2b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1184 |
XMM3, XMM3b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1185 |
XMM4, XMM4b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1186 |
XMM5, XMM5b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1187 |
XMM6, XMM6b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1188 |
XMM7, XMM7b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1189 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1190 |
,XMM8, XMM8b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1191 |
XMM9, XMM9b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1192 |
XMM10, XMM10b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1193 |
XMM11, XMM11b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1194 |
XMM12, XMM12b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1195 |
XMM13, XMM13b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1196 |
XMM14, XMM14b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1197 |
XMM15, XMM15b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1198 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1199 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1200 |
|
30624 | 1201 |
// Class for evex double registers |
1202 |
reg_class double_reg_evex(XMM0, XMM0b, |
|
1203 |
XMM1, XMM1b, |
|
1204 |
XMM2, XMM2b, |
|
1205 |
XMM3, XMM3b, |
|
1206 |
XMM4, XMM4b, |
|
1207 |
XMM5, XMM5b, |
|
1208 |
XMM6, XMM6b, |
|
1209 |
XMM7, XMM7b |
|
1210 |
#ifdef _LP64 |
|
1211 |
,XMM8, XMM8b, |
|
1212 |
XMM9, XMM9b, |
|
1213 |
XMM10, XMM10b, |
|
1214 |
XMM11, XMM11b, |
|
1215 |
XMM12, XMM12b, |
|
1216 |
XMM13, XMM13b, |
|
1217 |
XMM14, XMM14b, |
|
1218 |
XMM15, XMM15b, |
|
1219 |
XMM16, XMM16b, |
|
1220 |
XMM17, XMM17b, |
|
1221 |
XMM18, XMM18b, |
|
1222 |
XMM19, XMM19b, |
|
1223 |
XMM20, XMM20b, |
|
1224 |
XMM21, XMM21b, |
|
1225 |
XMM22, XMM22b, |
|
1226 |
XMM23, XMM23b, |
|
1227 |
XMM24, XMM24b, |
|
1228 |
XMM25, XMM25b, |
|
1229 |
XMM26, XMM26b, |
|
1230 |
XMM27, XMM27b, |
|
1231 |
XMM28, XMM28b, |
|
1232 |
XMM29, XMM29b, |
|
1233 |
XMM30, XMM30b, |
|
1234 |
XMM31, XMM31b |
|
1235 |
#endif |
|
1236 |
); |
|
1237 |
||
1238 |
reg_class_dynamic double_reg(double_reg_evex, double_reg_legacy, %{ VM_Version::supports_evex() %} ); |
|
1239 |
||
1240 |
// Class for pre evex 32bit vector registers |
|
1241 |
reg_class vectors_reg_legacy(XMM0, |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1242 |
XMM1, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1243 |
XMM2, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1244 |
XMM3, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1245 |
XMM4, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1246 |
XMM5, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1247 |
XMM6, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1248 |
XMM7 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1249 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1250 |
,XMM8, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1251 |
XMM9, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1252 |
XMM10, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1253 |
XMM11, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1254 |
XMM12, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1255 |
XMM13, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1256 |
XMM14, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1257 |
XMM15 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1258 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1259 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1260 |
|
30624 | 1261 |
// Class for evex 32bit vector registers |
1262 |
reg_class vectors_reg_evex(XMM0, |
|
1263 |
XMM1, |
|
1264 |
XMM2, |
|
1265 |
XMM3, |
|
1266 |
XMM4, |
|
1267 |
XMM5, |
|
1268 |
XMM6, |
|
1269 |
XMM7 |
|
1270 |
#ifdef _LP64 |
|
1271 |
,XMM8, |
|
1272 |
XMM9, |
|
1273 |
XMM10, |
|
1274 |
XMM11, |
|
1275 |
XMM12, |
|
1276 |
XMM13, |
|
1277 |
XMM14, |
|
1278 |
XMM15, |
|
1279 |
XMM16, |
|
1280 |
XMM17, |
|
1281 |
XMM18, |
|
1282 |
XMM19, |
|
1283 |
XMM20, |
|
1284 |
XMM21, |
|
1285 |
XMM22, |
|
1286 |
XMM23, |
|
1287 |
XMM24, |
|
1288 |
XMM25, |
|
1289 |
XMM26, |
|
1290 |
XMM27, |
|
1291 |
XMM28, |
|
1292 |
XMM29, |
|
1293 |
XMM30, |
|
1294 |
XMM31 |
|
1295 |
#endif |
|
1296 |
); |
|
1297 |
||
1298 |
reg_class_dynamic vectors_reg(vectors_reg_evex, vectors_reg_legacy, %{ VM_Version::supports_evex() %} ); |
|
1299 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1300 |
// Class for all 64bit vector registers |
30624 | 1301 |
reg_class vectord_reg_legacy(XMM0, XMM0b, |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1302 |
XMM1, XMM1b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1303 |
XMM2, XMM2b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1304 |
XMM3, XMM3b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1305 |
XMM4, XMM4b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1306 |
XMM5, XMM5b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1307 |
XMM6, XMM6b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1308 |
XMM7, XMM7b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1309 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1310 |
,XMM8, XMM8b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1311 |
XMM9, XMM9b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1312 |
XMM10, XMM10b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1313 |
XMM11, XMM11b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1314 |
XMM12, XMM12b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1315 |
XMM13, XMM13b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1316 |
XMM14, XMM14b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1317 |
XMM15, XMM15b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1318 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1319 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1320 |
|
30624 | 1321 |
// Class for all 64bit vector registers |
1322 |
reg_class vectord_reg_evex(XMM0, XMM0b, |
|
1323 |
XMM1, XMM1b, |
|
1324 |
XMM2, XMM2b, |
|
1325 |
XMM3, XMM3b, |
|
1326 |
XMM4, XMM4b, |
|
1327 |
XMM5, XMM5b, |
|
1328 |
XMM6, XMM6b, |
|
1329 |
XMM7, XMM7b |
|
1330 |
#ifdef _LP64 |
|
1331 |
,XMM8, XMM8b, |
|
1332 |
XMM9, XMM9b, |
|
1333 |
XMM10, XMM10b, |
|
1334 |
XMM11, XMM11b, |
|
1335 |
XMM12, XMM12b, |
|
1336 |
XMM13, XMM13b, |
|
1337 |
XMM14, XMM14b, |
|
1338 |
XMM15, XMM15b, |
|
1339 |
XMM16, XMM16b, |
|
1340 |
XMM17, XMM17b, |
|
1341 |
XMM18, XMM18b, |
|
1342 |
XMM19, XMM19b, |
|
1343 |
XMM20, XMM20b, |
|
1344 |
XMM21, XMM21b, |
|
1345 |
XMM22, XMM22b, |
|
1346 |
XMM23, XMM23b, |
|
1347 |
XMM24, XMM24b, |
|
1348 |
XMM25, XMM25b, |
|
1349 |
XMM26, XMM26b, |
|
1350 |
XMM27, XMM27b, |
|
1351 |
XMM28, XMM28b, |
|
1352 |
XMM29, XMM29b, |
|
1353 |
XMM30, XMM30b, |
|
1354 |
XMM31, XMM31b |
|
1355 |
#endif |
|
1356 |
); |
|
1357 |
||
1358 |
reg_class_dynamic vectord_reg(vectord_reg_evex, vectord_reg_legacy, %{ VM_Version::supports_evex() %} ); |
|
1359 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1360 |
// Class for all 128bit vector registers |
30624 | 1361 |
reg_class vectorx_reg_legacy(XMM0, XMM0b, XMM0c, XMM0d, |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1362 |
XMM1, XMM1b, XMM1c, XMM1d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1363 |
XMM2, XMM2b, XMM2c, XMM2d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1364 |
XMM3, XMM3b, XMM3c, XMM3d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1365 |
XMM4, XMM4b, XMM4c, XMM4d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1366 |
XMM5, XMM5b, XMM5c, XMM5d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1367 |
XMM6, XMM6b, XMM6c, XMM6d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1368 |
XMM7, XMM7b, XMM7c, XMM7d |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1369 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1370 |
,XMM8, XMM8b, XMM8c, XMM8d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1371 |
XMM9, XMM9b, XMM9c, XMM9d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1372 |
XMM10, XMM10b, XMM10c, XMM10d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1373 |
XMM11, XMM11b, XMM11c, XMM11d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1374 |
XMM12, XMM12b, XMM12c, XMM12d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1375 |
XMM13, XMM13b, XMM13c, XMM13d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1376 |
XMM14, XMM14b, XMM14c, XMM14d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1377 |
XMM15, XMM15b, XMM15c, XMM15d |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1378 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1379 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1380 |
|
30624 | 1381 |
// Class for all 128bit vector registers |
1382 |
reg_class vectorx_reg_evex(XMM0, XMM0b, XMM0c, XMM0d, |
|
1383 |
XMM1, XMM1b, XMM1c, XMM1d, |
|
1384 |
XMM2, XMM2b, XMM2c, XMM2d, |
|
1385 |
XMM3, XMM3b, XMM3c, XMM3d, |
|
1386 |
XMM4, XMM4b, XMM4c, XMM4d, |
|
1387 |
XMM5, XMM5b, XMM5c, XMM5d, |
|
1388 |
XMM6, XMM6b, XMM6c, XMM6d, |
|
1389 |
XMM7, XMM7b, XMM7c, XMM7d |
|
1390 |
#ifdef _LP64 |
|
1391 |
,XMM8, XMM8b, XMM8c, XMM8d, |
|
1392 |
XMM9, XMM9b, XMM9c, XMM9d, |
|
1393 |
XMM10, XMM10b, XMM10c, XMM10d, |
|
1394 |
XMM11, XMM11b, XMM11c, XMM11d, |
|
1395 |
XMM12, XMM12b, XMM12c, XMM12d, |
|
1396 |
XMM13, XMM13b, XMM13c, XMM13d, |
|
1397 |
XMM14, XMM14b, XMM14c, XMM14d, |
|
1398 |
XMM15, XMM15b, XMM15c, XMM15d, |
|
1399 |
XMM16, XMM16b, XMM16c, XMM16d, |
|
1400 |
XMM17, XMM17b, XMM17c, XMM17d, |
|
1401 |
XMM18, XMM18b, XMM18c, XMM18d, |
|
1402 |
XMM19, XMM19b, XMM19c, XMM19d, |
|
1403 |
XMM20, XMM20b, XMM20c, XMM20d, |
|
1404 |
XMM21, XMM21b, XMM21c, XMM21d, |
|
1405 |
XMM22, XMM22b, XMM22c, XMM22d, |
|
1406 |
XMM23, XMM23b, XMM23c, XMM23d, |
|
1407 |
XMM24, XMM24b, XMM24c, XMM24d, |
|
1408 |
XMM25, XMM25b, XMM25c, XMM25d, |
|
1409 |
XMM26, XMM26b, XMM26c, XMM26d, |
|
1410 |
XMM27, XMM27b, XMM27c, XMM27d, |
|
1411 |
XMM28, XMM28b, XMM28c, XMM28d, |
|
1412 |
XMM29, XMM29b, XMM29c, XMM29d, |
|
1413 |
XMM30, XMM30b, XMM30c, XMM30d, |
|
1414 |
XMM31, XMM31b, XMM31c, XMM31d |
|
1415 |
#endif |
|
1416 |
); |
|
1417 |
||
1418 |
reg_class_dynamic vectorx_reg(vectorx_reg_evex, vectorx_reg_legacy, %{ VM_Version::supports_evex() %} ); |
|
1419 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1420 |
// Class for all 256bit vector registers |
30624 | 1421 |
reg_class vectory_reg_legacy(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1422 |
XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1423 |
XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1424 |
XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1425 |
XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1426 |
XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1427 |
XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1428 |
XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1429 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1430 |
,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1431 |
XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1432 |
XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1433 |
XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1434 |
XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1435 |
XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1436 |
XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1437 |
XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1438 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1439 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1440 |
|
30624 | 1441 |
// Class for all 256bit vector registers |
1442 |
reg_class vectory_reg_evex(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
|
1443 |
XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
|
1444 |
XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
|
1445 |
XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
|
1446 |
XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
|
1447 |
XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
|
1448 |
XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
|
1449 |
XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
|
1450 |
#ifdef _LP64 |
|
1451 |
,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
|
1452 |
XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
|
1453 |
XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
|
1454 |
XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
|
1455 |
XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
|
1456 |
XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
|
1457 |
XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
|
1458 |
XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h, |
|
1459 |
XMM16, XMM16b, XMM16c, XMM16d, XMM16e, XMM16f, XMM16g, XMM16h, |
|
1460 |
XMM17, XMM17b, XMM17c, XMM17d, XMM17e, XMM17f, XMM17g, XMM17h, |
|
1461 |
XMM18, XMM18b, XMM18c, XMM18d, XMM18e, XMM18f, XMM18g, XMM18h, |
|
1462 |
XMM19, XMM19b, XMM19c, XMM19d, XMM19e, XMM19f, XMM19g, XMM19h, |
|
1463 |
XMM20, XMM20b, XMM20c, XMM20d, XMM20e, XMM20f, XMM20g, XMM20h, |
|
1464 |
XMM21, XMM21b, XMM21c, XMM21d, XMM21e, XMM21f, XMM21g, XMM21h, |
|
1465 |
XMM22, XMM22b, XMM22c, XMM22d, XMM22e, XMM22f, XMM22g, XMM22h, |
|
1466 |
XMM23, XMM23b, XMM23c, XMM23d, XMM23e, XMM23f, XMM23g, XMM23h, |
|
1467 |
XMM24, XMM24b, XMM24c, XMM24d, XMM24e, XMM24f, XMM24g, XMM24h, |
|
1468 |
XMM25, XMM25b, XMM25c, XMM25d, XMM25e, XMM25f, XMM25g, XMM25h, |
|
1469 |
XMM26, XMM26b, XMM26c, XMM26d, XMM26e, XMM26f, XMM26g, XMM26h, |
|
1470 |
XMM27, XMM27b, XMM27c, XMM27d, XMM27e, XMM27f, XMM27g, XMM27h, |
|
1471 |
XMM28, XMM28b, XMM28c, XMM28d, XMM28e, XMM28f, XMM28g, XMM28h, |
|
1472 |
XMM29, XMM29b, XMM29c, XMM29d, XMM29e, XMM29f, XMM29g, XMM29h, |
|
1473 |
XMM30, XMM30b, XMM30c, XMM30d, XMM30e, XMM30f, XMM30g, XMM30h, |
|
1474 |
XMM31, XMM31b, XMM31c, XMM31d, XMM31e, XMM31f, XMM31g, XMM31h |
|
1475 |
#endif |
|
1476 |
); |
|
1477 |
||
1478 |
reg_class_dynamic vectory_reg(vectory_reg_evex, vectory_reg_legacy, %{ VM_Version::supports_evex() %} ); |
|
1479 |
||
1480 |
// Class for all 512bit vector registers |
|
1481 |
reg_class vectorz_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, XMM0i, XMM0j, XMM0k, XMM0l, XMM0m, XMM0n, XMM0o, XMM0p, |
|
1482 |
XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, XMM1i, XMM1j, XMM1k, XMM1l, XMM1m, XMM1n, XMM1o, XMM1p, |
|
1483 |
XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, XMM2i, XMM2j, XMM2k, XMM2l, XMM2m, XMM2n, XMM2o, XMM2p, |
|
1484 |
XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, XMM3i, XMM3j, XMM3k, XMM3l, XMM3m, XMM3n, XMM3o, XMM3p, |
|
1485 |
XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, XMM4i, XMM4j, XMM4k, XMM4l, XMM4m, XMM4n, XMM4o, XMM4p, |
|
1486 |
XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, XMM5i, XMM5j, XMM5k, XMM5l, XMM5m, XMM5n, XMM5o, XMM5p, |
|
1487 |
XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, XMM6i, XMM6j, XMM6k, XMM6l, XMM6m, XMM6n, XMM6o, XMM6p, |
|
1488 |
XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h, XMM7i, XMM7j, XMM7k, XMM7l, XMM7m, XMM7n, XMM7o, XMM7p |
|
1489 |
#ifdef _LP64 |
|
1490 |
,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, XMM8i, XMM8j, XMM8k, XMM8l, XMM8m, XMM8n, XMM8o, XMM8p, |
|
1491 |
XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, XMM9i, XMM9j, XMM9k, XMM9l, XMM9m, XMM9n, XMM9o, XMM9p, |
|
1492 |
XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, XMM10i, XMM10j, XMM10k, XMM10l, XMM10m, XMM10n, XMM10o, XMM10p, |
|
1493 |
XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, XMM11i, XMM11j, XMM11k, XMM11l, XMM11m, XMM11n, XMM11o, XMM11p, |
|
1494 |
XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, XMM12i, XMM12j, XMM12k, XMM12l, XMM12m, XMM12n, XMM12o, XMM12p, |
|
1495 |
XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, XMM13i, XMM13j, XMM13k, XMM13l, XMM13m, XMM13n, XMM13o, XMM13p, |
|
1496 |
XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, XMM14i, XMM14j, XMM14k, XMM14l, XMM14m, XMM14n, XMM14o, XMM14p, |
|
1497 |
XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h, XMM15i, XMM15j, XMM15k, XMM15l, XMM15m, XMM15n, XMM15o, XMM15p |
|
1498 |
,XMM16, XMM16b, XMM16c, XMM16d, XMM16e, XMM16f, XMM16g, XMM16h, XMM16i, XMM16j, XMM16k, XMM16l, XMM16m, XMM16n, XMM16o, XMM16p, |
|
1499 |
XMM17, XMM17b, XMM17c, XMM17d, XMM17e, XMM17f, XMM17g, XMM17h, XMM17i, XMM17j, XMM17k, XMM17l, XMM17m, XMM17n, XMM17o, XMM17p, |
|
1500 |
XMM18, XMM18b, XMM18c, XMM18d, XMM18e, XMM18f, XMM18g, XMM18h, XMM18i, XMM18j, XMM18k, XMM18l, XMM18m, XMM18n, XMM18o, XMM18p, |
|
1501 |
XMM19, XMM19b, XMM19c, XMM19d, XMM19e, XMM19f, XMM19g, XMM19h, XMM19i, XMM19j, XMM19k, XMM19l, XMM19m, XMM19n, XMM19o, XMM19p, |
|
1502 |
XMM20, XMM20b, XMM20c, XMM20d, XMM20e, XMM20f, XMM20g, XMM20h, XMM20i, XMM20j, XMM20k, XMM20l, XMM20m, XMM20n, XMM20o, XMM20p, |
|
1503 |
XMM21, XMM21b, XMM21c, XMM21d, XMM21e, XMM21f, XMM21g, XMM21h, XMM21i, XMM21j, XMM21k, XMM21l, XMM21m, XMM21n, XMM21o, XMM21p, |
|
1504 |
XMM22, XMM22b, XMM22c, XMM22d, XMM22e, XMM22f, XMM22g, XMM22h, XMM22i, XMM22j, XMM22k, XMM22l, XMM22m, XMM22n, XMM22o, XMM22p, |
|
1505 |
XMM23, XMM23b, XMM23c, XMM23d, XMM23e, XMM23f, XMM23g, XMM23h, XMM23i, XMM23j, XMM23k, XMM23l, XMM23m, XMM23n, XMM23o, XMM23p, |
|
1506 |
XMM24, XMM24b, XMM24c, XMM24d, XMM24e, XMM24f, XMM24g, XMM24h, XMM24i, XMM24j, XMM24k, XMM24l, XMM24m, XMM24n, XMM24o, XMM24p, |
|
1507 |
XMM25, XMM25b, XMM25c, XMM25d, XMM25e, XMM25f, XMM25g, XMM25h, XMM25i, XMM25j, XMM25k, XMM25l, XMM25m, XMM25n, XMM25o, XMM25p, |
|
1508 |
XMM26, XMM26b, XMM26c, XMM26d, XMM26e, XMM26f, XMM26g, XMM26h, XMM26i, XMM26j, XMM26k, XMM26l, XMM26m, XMM26n, XMM26o, XMM26p, |
|
1509 |
XMM27, XMM27b, XMM27c, XMM27d, XMM27e, XMM27f, XMM27g, XMM27h, XMM27i, XMM27j, XMM27k, XMM27l, XMM27m, XMM27n, XMM27o, XMM27p, |
|
1510 |
XMM28, XMM28b, XMM28c, XMM28d, XMM28e, XMM28f, XMM28g, XMM28h, XMM28i, XMM28j, XMM28k, XMM28l, XMM28m, XMM28n, XMM28o, XMM28p, |
|
1511 |
XMM29, XMM29b, XMM29c, XMM29d, XMM29e, XMM29f, XMM29g, XMM29h, XMM29i, XMM29j, XMM29k, XMM29l, XMM29m, XMM29n, XMM29o, XMM29p, |
|
1512 |
XMM30, XMM30b, XMM30c, XMM30d, XMM30e, XMM30f, XMM30g, XMM30h, XMM30i, XMM30j, XMM30k, XMM30l, XMM30m, XMM30n, XMM30o, XMM30p, |
|
1513 |
XMM31, XMM31b, XMM31c, XMM31d, XMM31e, XMM31f, XMM31g, XMM31h, XMM31i, XMM31j, XMM31k, XMM31l, XMM31m, XMM31n, XMM31o, XMM31p |
|
1514 |
#endif |
|
1515 |
); |
|
1516 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1517 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1518 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1519 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1520 |
//----------SOURCE BLOCK------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1521 |
// This is a block of C++ code which provides values, functions, and |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1522 |
// definitions necessary in the rest of the architecture description |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1523 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1524 |
source_hpp %{ |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1525 |
// Header information of the source block. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1526 |
// Method declarations/definitions which are used outside |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1527 |
// the ad-scope can conveniently be defined here. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1528 |
// |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1529 |
// To keep related declarations/definitions/uses close together, |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1530 |
// we switch between source %{ }% and source_hpp %{ }% freely as needed. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1531 |
|
25715
d5a8dbdc5150
8049325: Introduce and clean up umbrella headers for the files in the cpu subdirectories.
goetz
parents:
23498
diff
changeset
|
1532 |
class NativeJump; |
d5a8dbdc5150
8049325: Introduce and clean up umbrella headers for the files in the cpu subdirectories.
goetz
parents:
23498
diff
changeset
|
1533 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1534 |
class CallStubImpl { |
30211 | 1535 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1536 |
//-------------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1537 |
//---< Used for optimization in Compile::shorten_branches >--- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1538 |
//-------------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1539 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1540 |
public: |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1541 |
// Size of call trampoline stub. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1542 |
static uint size_call_trampoline() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1543 |
return 0; // no call trampolines on this platform |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1544 |
} |
30211 | 1545 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1546 |
// number of relocations needed by a call trampoline stub |
30211 | 1547 |
static uint reloc_call_trampoline() { |
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1548 |
return 0; // no call trampolines on this platform |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1549 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1550 |
}; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1551 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1552 |
class HandlerImpl { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1553 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1554 |
public: |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1555 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1556 |
static int emit_exception_handler(CodeBuffer &cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1557 |
static int emit_deopt_handler(CodeBuffer& cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1558 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1559 |
static uint size_exception_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1560 |
// NativeCall instruction size is the same as NativeJump. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1561 |
// exception handler starts out as jump and can be patched to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1562 |
// a call be deoptimization. (4932387) |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1563 |
// Note that this value is also credited (in output.cpp) to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1564 |
// the size of the code section. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1565 |
return NativeJump::instruction_size; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1566 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1567 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1568 |
#ifdef _LP64 |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1569 |
static uint size_deopt_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1570 |
// three 5 byte instructions |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1571 |
return 15; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1572 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1573 |
#else |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1574 |
static uint size_deopt_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1575 |
// NativeCall instruction size is the same as NativeJump. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1576 |
// exception handler starts out as jump and can be patched to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1577 |
// a call be deoptimization. (4932387) |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1578 |
// Note that this value is also credited (in output.cpp) to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1579 |
// the size of the code section. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1580 |
return 5 + NativeJump::instruction_size; // pushl(); jmp; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1581 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1582 |
#endif |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1583 |
}; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1584 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1585 |
%} // end source_hpp |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1586 |
|
11429 | 1587 |
source %{ |
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1588 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1589 |
// Emit exception handler code. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1590 |
// Stuff framesize into a register and call a VM stub routine. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1591 |
int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1592 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1593 |
// Note that the code buffer's insts_mark is always relative to insts. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1594 |
// That's why we must use the macroassembler to generate a handler. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1595 |
MacroAssembler _masm(&cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1596 |
address base = __ start_a_stub(size_exception_handler()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1597 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1598 |
int offset = __ offset(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1599 |
__ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1600 |
assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1601 |
__ end_a_stub(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1602 |
return offset; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1603 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1604 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1605 |
// Emit deopt handler code. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1606 |
int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1607 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1608 |
// Note that the code buffer's insts_mark is always relative to insts. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1609 |
// That's why we must use the macroassembler to generate a handler. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1610 |
MacroAssembler _masm(&cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1611 |
address base = __ start_a_stub(size_deopt_handler()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1612 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1613 |
int offset = __ offset(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1614 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1615 |
#ifdef _LP64 |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1616 |
address the_pc = (address) __ pc(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1617 |
Label next; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1618 |
// push a "the_pc" on the stack without destroying any registers |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1619 |
// as they all may be live. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1620 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1621 |
// push address of "next" |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1622 |
__ call(next, relocInfo::none); // reloc none is fine since it is a disp32 |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1623 |
__ bind(next); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1624 |
// adjust it so it matches "the_pc" |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1625 |
__ subptr(Address(rsp, 0), __ offset() - offset); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1626 |
#else |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1627 |
InternalAddress here(__ pc()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1628 |
__ pushptr(here.addr()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1629 |
#endif |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1630 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1631 |
__ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1632 |
assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1633 |
__ end_a_stub(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1634 |
return offset; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1635 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1636 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1637 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1638 |
//============================================================================= |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
1639 |
|
11429 | 1640 |
// Float masks come from different places depending on platform. |
1641 |
#ifdef _LP64 |
|
1642 |
static address float_signmask() { return StubRoutines::x86::float_sign_mask(); } |
|
1643 |
static address float_signflip() { return StubRoutines::x86::float_sign_flip(); } |
|
1644 |
static address double_signmask() { return StubRoutines::x86::double_sign_mask(); } |
|
1645 |
static address double_signflip() { return StubRoutines::x86::double_sign_flip(); } |
|
1646 |
#else |
|
1647 |
static address float_signmask() { return (address)float_signmask_pool; } |
|
1648 |
static address float_signflip() { return (address)float_signflip_pool; } |
|
1649 |
static address double_signmask() { return (address)double_signmask_pool; } |
|
1650 |
static address double_signflip() { return (address)double_signflip_pool; } |
|
1651 |
#endif |
|
11794 | 1652 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1653 |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1654 |
const bool Matcher::match_rule_supported(int opcode) { |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1655 |
if (!has_match_rule(opcode)) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1656 |
return false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1657 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1658 |
switch (opcode) { |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1659 |
case Op_PopCountI: |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1660 |
case Op_PopCountL: |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1661 |
if (!UsePopCountInstruction) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1662 |
return false; |
13883
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13728
diff
changeset
|
1663 |
break; |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1664 |
case Op_MulVI: |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1665 |
if ((UseSSE < 4) && (UseAVX < 1)) // only with SSE4_1 or AVX |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1666 |
return false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1667 |
break; |
30624 | 1668 |
case Op_MulVL: |
1669 |
case Op_MulReductionVL: |
|
1670 |
if (VM_Version::supports_avx512dq() == false) |
|
1671 |
return false; |
|
30211 | 1672 |
case Op_AddReductionVL: |
1673 |
if (UseAVX < 3) // only EVEX : vector connectivity becomes an issue here |
|
1674 |
return false; |
|
1675 |
case Op_AddReductionVI: |
|
1676 |
if (UseSSE < 3) // requires at least SSE3 |
|
1677 |
return false; |
|
1678 |
case Op_MulReductionVI: |
|
1679 |
if (UseSSE < 4) // requires at least SSE4 |
|
1680 |
return false; |
|
1681 |
case Op_AddReductionVF: |
|
1682 |
case Op_AddReductionVD: |
|
1683 |
case Op_MulReductionVF: |
|
1684 |
case Op_MulReductionVD: |
|
1685 |
if (UseSSE < 1) // requires at least SSE |
|
1686 |
return false; |
|
1687 |
break; |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1688 |
case Op_CompareAndSwapL: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1689 |
#ifdef _LP64 |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1690 |
case Op_CompareAndSwapP: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1691 |
#endif |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1692 |
if (!VM_Version::supports_cx8()) |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1693 |
return false; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
1694 |
break; |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1695 |
} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1696 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1697 |
return true; // Per default match rules are supported. |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1698 |
} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1699 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1700 |
// Max vector size in bytes. 0 if not supported. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1701 |
const int Matcher::vector_width_in_bytes(BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1702 |
assert(is_java_primitive(bt), "only primitive type vectors"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1703 |
if (UseSSE < 2) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1704 |
// SSE2 supports 128bit vectors for all types. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1705 |
// AVX2 supports 256bit vectors for all types. |
30624 | 1706 |
// AVX2/EVEX supports 512bit vectors for all types. |
1707 |
int size = (UseAVX > 1) ? (1 << UseAVX) * 8 : 16; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1708 |
// AVX1 supports 256bit vectors only for FLOAT and DOUBLE. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1709 |
if (UseAVX > 0 && (bt == T_FLOAT || bt == T_DOUBLE)) |
30624 | 1710 |
size = (UseAVX > 2) ? 64 : 32; |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1711 |
// Use flag to limit vector size. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1712 |
size = MIN2(size,(int)MaxVectorSize); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1713 |
// Minimum 2 values in vector (or 4 for bytes). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1714 |
switch (bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1715 |
case T_DOUBLE: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1716 |
case T_LONG: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1717 |
if (size < 16) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1718 |
case T_FLOAT: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1719 |
case T_INT: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1720 |
if (size < 8) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1721 |
case T_BOOLEAN: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1722 |
case T_BYTE: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1723 |
case T_CHAR: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1724 |
case T_SHORT: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1725 |
if (size < 4) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1726 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1727 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1728 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1729 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1730 |
return size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1731 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1732 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1733 |
// Limits on vector size (number of elements) loaded into vector. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1734 |
const int Matcher::max_vector_size(const BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1735 |
return vector_width_in_bytes(bt)/type2aelembytes(bt); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1736 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1737 |
const int Matcher::min_vector_size(const BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1738 |
int max_size = max_vector_size(bt); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1739 |
// Min size which can be loaded into vector is 4 bytes. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1740 |
int size = (type2aelembytes(bt) == 1) ? 4 : 2; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1741 |
return MIN2(size,max_size); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1742 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1743 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1744 |
// Vector ideal reg corresponding to specidied size in bytes |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1745 |
const int Matcher::vector_ideal_reg(int size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1746 |
assert(MaxVectorSize >= size, ""); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1747 |
switch(size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1748 |
case 4: return Op_VecS; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1749 |
case 8: return Op_VecD; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1750 |
case 16: return Op_VecX; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1751 |
case 32: return Op_VecY; |
30624 | 1752 |
case 64: return Op_VecZ; |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1753 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1754 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1755 |
return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1756 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1757 |
|
13930 | 1758 |
// Only lowest bits of xmm reg are used for vector shift count. |
1759 |
const int Matcher::vector_shift_count_ideal_reg(int size) { |
|
1760 |
return Op_VecS; |
|
1761 |
} |
|
1762 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1763 |
// x86 supports misaligned vectors store/load. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1764 |
const bool Matcher::misaligned_vectors_ok() { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1765 |
return !AlignVector; // can be changed by flag |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1766 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1767 |
|
22505 | 1768 |
// x86 AES instructions are compatible with SunJCE expanded |
1769 |
// keys, hence we do not need to pass the original key to stubs |
|
1770 |
const bool Matcher::pass_original_key_for_aes() { |
|
1771 |
return false; |
|
1772 |
} |
|
1773 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1774 |
// Helper methods for MachSpillCopyNode::implementation(). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1775 |
static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1776 |
int src_hi, int dst_hi, uint ireg, outputStream* st) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1777 |
// In 64-bit VM size calculation is very complex. Emitting instructions |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1778 |
// into scratch buffer is used to get size in 64-bit VM. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1779 |
LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1780 |
assert(ireg == Op_VecS || // 32bit vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1781 |
(src_lo & 1) == 0 && (src_lo + 1) == src_hi && |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1782 |
(dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1783 |
"no non-adjacent vector moves" ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1784 |
if (cbuf) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1785 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1786 |
int offset = __ offset(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1787 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1788 |
case Op_VecS: // copy whole register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1789 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1790 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1791 |
__ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1792 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1793 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1794 |
__ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1795 |
break; |
30624 | 1796 |
case Op_VecZ: |
1797 |
__ evmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 2); |
|
1798 |
break; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1799 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1800 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1801 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1802 |
int size = __ offset() - offset; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1803 |
#ifdef ASSERT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1804 |
// VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1805 |
assert(!do_size || size == 4, "incorrect size calculattion"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1806 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1807 |
return size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1808 |
#ifndef PRODUCT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1809 |
} else if (!do_size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1810 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1811 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1812 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1813 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1814 |
st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1815 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1816 |
case Op_VecY: |
30624 | 1817 |
case Op_VecZ: |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1818 |
st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1819 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1820 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1821 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1822 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1823 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1824 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1825 |
// VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
30624 | 1826 |
return (UseAVX > 2) ? 6 : 4; |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1827 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1828 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1829 |
static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1830 |
int stack_offset, int reg, uint ireg, outputStream* st) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1831 |
// In 64-bit VM size calculation is very complex. Emitting instructions |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1832 |
// into scratch buffer is used to get size in 64-bit VM. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1833 |
LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1834 |
if (cbuf) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1835 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1836 |
int offset = __ offset(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1837 |
if (is_load) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1838 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1839 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1840 |
__ movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1841 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1842 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1843 |
__ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1844 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1845 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1846 |
__ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1847 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1848 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1849 |
__ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1850 |
break; |
30624 | 1851 |
case Op_VecZ: |
1852 |
__ evmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset), 2); |
|
1853 |
break; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1854 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1855 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1856 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1857 |
} else { // store |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1858 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1859 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1860 |
__ movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1861 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1862 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1863 |
__ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1864 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1865 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1866 |
__ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1867 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1868 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1869 |
__ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1870 |
break; |
30624 | 1871 |
case Op_VecZ: |
1872 |
__ evmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 2); |
|
1873 |
break; |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1874 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1875 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1876 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1877 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1878 |
int size = __ offset() - offset; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1879 |
#ifdef ASSERT |
30624 | 1880 |
int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : (UseAVX > 2) ? 6 : 4); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1881 |
// VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1882 |
assert(!do_size || size == (5+offset_size), "incorrect size calculattion"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1883 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1884 |
return size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1885 |
#ifndef PRODUCT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1886 |
} else if (!do_size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1887 |
if (is_load) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1888 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1889 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1890 |
st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1891 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1892 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1893 |
st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1894 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1895 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1896 |
st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1897 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1898 |
case Op_VecY: |
30624 | 1899 |
case Op_VecZ: |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1900 |
st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1901 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1902 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1903 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1904 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1905 |
} else { // store |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1906 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1907 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1908 |
st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1909 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1910 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1911 |
st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1912 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1913 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1914 |
st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1915 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1916 |
case Op_VecY: |
30624 | 1917 |
case Op_VecZ: |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1918 |
st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1919 |
break; |
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diff
changeset
|
1920 |
default: |
657b387034fb
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parents:
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diff
changeset
|
1921 |
ShouldNotReachHere(); |
657b387034fb
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kvn
parents:
11794
diff
changeset
|
1922 |
} |
657b387034fb
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parents:
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diff
changeset
|
1923 |
} |
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parents:
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diff
changeset
|
1924 |
#endif |
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parents:
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diff
changeset
|
1925 |
} |
30624 | 1926 |
int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : (UseAVX > 2) ? 6 : 4); |
13104
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diff
changeset
|
1927 |
// VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
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diff
changeset
|
1928 |
return 5+offset_size; |
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parents:
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diff
changeset
|
1929 |
} |
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parents:
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diff
changeset
|
1930 |
|
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diff
changeset
|
1931 |
static inline jfloat replicate4_imm(int con, int width) { |
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changeset
|
1932 |
// Load a constant of "width" (in bytes) and replicate it to fill 32bit. |
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|
1933 |
assert(width == 1 || width == 2, "only byte or short types here"); |
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diff
changeset
|
1934 |
int bit_width = width * 8; |
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parents:
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diff
changeset
|
1935 |
jint val = con; |
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diff
changeset
|
1936 |
val &= (1 << bit_width) - 1; // mask off sign bits |
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diff
changeset
|
1937 |
while(bit_width < 32) { |
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parents:
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diff
changeset
|
1938 |
val |= (val << bit_width); |
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parents:
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diff
changeset
|
1939 |
bit_width <<= 1; |
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parents:
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diff
changeset
|
1940 |
} |
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diff
changeset
|
1941 |
jfloat fval = *((jfloat*) &val); // coerce to float type |
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parents:
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diff
changeset
|
1942 |
return fval; |
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parents:
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diff
changeset
|
1943 |
} |
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parents:
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diff
changeset
|
1944 |
|
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parents:
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diff
changeset
|
1945 |
static inline jdouble replicate8_imm(int con, int width) { |
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parents:
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diff
changeset
|
1946 |
// Load a constant of "width" (in bytes) and replicate it to fill 64bit. |
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diff
changeset
|
1947 |
assert(width == 1 || width == 2 || width == 4, "only byte, short or int types here"); |
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parents:
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diff
changeset
|
1948 |
int bit_width = width * 8; |
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parents:
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diff
changeset
|
1949 |
jlong val = con; |
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diff
changeset
|
1950 |
val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
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parents:
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diff
changeset
|
1951 |
while(bit_width < 64) { |
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parents:
11794
diff
changeset
|
1952 |
val |= (val << bit_width); |
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parents:
11794
diff
changeset
|
1953 |
bit_width <<= 1; |
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kvn
parents:
11794
diff
changeset
|
1954 |
} |
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parents:
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diff
changeset
|
1955 |
jdouble dval = *((jdouble*) &val); // coerce to double type |
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parents:
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diff
changeset
|
1956 |
return dval; |
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parents:
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diff
changeset
|
1957 |
} |
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parents:
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diff
changeset
|
1958 |
|
11794 | 1959 |
#ifndef PRODUCT |
1960 |
void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const { |
|
1961 |
st->print("nop \t# %d bytes pad for loops and calls", _count); |
|
1962 |
} |
|
1963 |
#endif |
|
1964 |
||
1965 |
void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const { |
|
1966 |
MacroAssembler _masm(&cbuf); |
|
1967 |
__ nop(_count); |
|
1968 |
} |
|
1969 |
||
1970 |
uint MachNopNode::size(PhaseRegAlloc*) const { |
|
1971 |
return _count; |
|
1972 |
} |
|
1973 |
||
1974 |
#ifndef PRODUCT |
|
1975 |
void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const { |
|
1976 |
st->print("# breakpoint"); |
|
1977 |
} |
|
1978 |
#endif |
|
1979 |
||
1980 |
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const { |
|
1981 |
MacroAssembler _masm(&cbuf); |
|
1982 |
__ int3(); |
|
1983 |
} |
|
1984 |
||
1985 |
uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { |
|
1986 |
return MachNode::size(ra_); |
|
1987 |
} |
|
1988 |
||
1989 |
%} |
|
1990 |
||
1991 |
encode %{ |
|
1992 |
||
1993 |
enc_class call_epilog %{ |
|
1994 |
if (VerifyStackAtCalls) { |
|
1995 |
// Check that stack depth is unchanged: find majik cookie on stack |
|
1996 |
int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word)); |
|
1997 |
MacroAssembler _masm(&cbuf); |
|
1998 |
Label L; |
|
1999 |
__ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d); |
|
2000 |
__ jccb(Assembler::equal, L); |
|
2001 |
// Die if stack mismatch |
|
2002 |
__ int3(); |
|
2003 |
__ bind(L); |
|
2004 |
} |
|
2005 |
%} |
|
2006 |
||
11429 | 2007 |
%} |
2008 |
||
13104
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parents:
11794
diff
changeset
|
2009 |
|
657b387034fb
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kvn
parents:
11794
diff
changeset
|
2010 |
//----------OPERANDS----------------------------------------------------------- |
657b387034fb
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kvn
parents:
11794
diff
changeset
|
2011 |
// Operand definitions must precede instruction definitions for correct parsing |
657b387034fb
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kvn
parents:
11794
diff
changeset
|
2012 |
// in the ADLC because operands constitute user defined types which are used in |
657b387034fb
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kvn
parents:
11794
diff
changeset
|
2013 |
// instruction definitions. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2014 |
|
30624 | 2015 |
// This one generically applies only for evex, so only one version |
2016 |
operand vecZ() %{ |
|
2017 |
constraint(ALLOC_IN_RC(vectorz_reg)); |
|
2018 |
match(VecZ); |
|
13104
657b387034fb
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kvn
parents:
11794
diff
changeset
|
2019 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2020 |
format %{ %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2021 |
interface(REG_INTER); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2022 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2023 |
|
11429 | 2024 |
// INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit) |
2025 |
||
11794 | 2026 |
// ============================================================================ |
2027 |
||
2028 |
instruct ShouldNotReachHere() %{ |
|
2029 |
match(Halt); |
|
2030 |
format %{ "int3\t# ShouldNotReachHere" %} |
|
2031 |
ins_encode %{ |
|
2032 |
__ int3(); |
|
2033 |
%} |
|
2034 |
ins_pipe(pipe_slow); |
|
2035 |
%} |
|
2036 |
||
2037 |
// ============================================================================ |
|
2038 |
||
11429 | 2039 |
instruct addF_reg(regF dst, regF src) %{ |
2040 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2041 |
match(Set dst (AddF dst src)); |
|
2042 |
||
2043 |
format %{ "addss $dst, $src" %} |
|
2044 |
ins_cost(150); |
|
2045 |
ins_encode %{ |
|
2046 |
__ addss($dst$$XMMRegister, $src$$XMMRegister); |
|
2047 |
%} |
|
2048 |
ins_pipe(pipe_slow); |
|
2049 |
%} |
|
2050 |
||
2051 |
instruct addF_mem(regF dst, memory src) %{ |
|
2052 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2053 |
match(Set dst (AddF dst (LoadF src))); |
|
2054 |
||
2055 |
format %{ "addss $dst, $src" %} |
|
2056 |
ins_cost(150); |
|
2057 |
ins_encode %{ |
|
2058 |
__ addss($dst$$XMMRegister, $src$$Address); |
|
2059 |
%} |
|
2060 |
ins_pipe(pipe_slow); |
|
2061 |
%} |
|
2062 |
||
2063 |
instruct addF_imm(regF dst, immF con) %{ |
|
2064 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2065 |
match(Set dst (AddF dst con)); |
|
2066 |
format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2067 |
ins_cost(150); |
|
2068 |
ins_encode %{ |
|
2069 |
__ addss($dst$$XMMRegister, $constantaddress($con)); |
|
2070 |
%} |
|
2071 |
ins_pipe(pipe_slow); |
|
2072 |
%} |
|
2073 |
||
13294 | 2074 |
instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 2075 |
predicate(UseAVX > 0); |
2076 |
match(Set dst (AddF src1 src2)); |
|
2077 |
||
2078 |
format %{ "vaddss $dst, $src1, $src2" %} |
|
2079 |
ins_cost(150); |
|
2080 |
ins_encode %{ |
|
2081 |
__ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2082 |
%} |
|
2083 |
ins_pipe(pipe_slow); |
|
2084 |
%} |
|
2085 |
||
13294 | 2086 |
instruct addF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 2087 |
predicate(UseAVX > 0); |
2088 |
match(Set dst (AddF src1 (LoadF src2))); |
|
2089 |
||
2090 |
format %{ "vaddss $dst, $src1, $src2" %} |
|
2091 |
ins_cost(150); |
|
2092 |
ins_encode %{ |
|
2093 |
__ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2094 |
%} |
|
2095 |
ins_pipe(pipe_slow); |
|
2096 |
%} |
|
2097 |
||
13294 | 2098 |
instruct addF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 2099 |
predicate(UseAVX > 0); |
2100 |
match(Set dst (AddF src con)); |
|
2101 |
||
2102 |
format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2103 |
ins_cost(150); |
|
2104 |
ins_encode %{ |
|
2105 |
__ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2106 |
%} |
|
2107 |
ins_pipe(pipe_slow); |
|
2108 |
%} |
|
2109 |
||
2110 |
instruct addD_reg(regD dst, regD src) %{ |
|
2111 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2112 |
match(Set dst (AddD dst src)); |
|
2113 |
||
2114 |
format %{ "addsd $dst, $src" %} |
|
2115 |
ins_cost(150); |
|
2116 |
ins_encode %{ |
|
2117 |
__ addsd($dst$$XMMRegister, $src$$XMMRegister); |
|
2118 |
%} |
|
2119 |
ins_pipe(pipe_slow); |
|
2120 |
%} |
|
2121 |
||
2122 |
instruct addD_mem(regD dst, memory src) %{ |
|
2123 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2124 |
match(Set dst (AddD dst (LoadD src))); |
|
2125 |
||
2126 |
format %{ "addsd $dst, $src" %} |
|
2127 |
ins_cost(150); |
|
2128 |
ins_encode %{ |
|
2129 |
__ addsd($dst$$XMMRegister, $src$$Address); |
|
2130 |
%} |
|
2131 |
ins_pipe(pipe_slow); |
|
2132 |
%} |
|
2133 |
||
2134 |
instruct addD_imm(regD dst, immD con) %{ |
|
2135 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2136 |
match(Set dst (AddD dst con)); |
|
2137 |
format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2138 |
ins_cost(150); |
|
2139 |
ins_encode %{ |
|
2140 |
__ addsd($dst$$XMMRegister, $constantaddress($con)); |
|
2141 |
%} |
|
2142 |
ins_pipe(pipe_slow); |
|
2143 |
%} |
|
2144 |
||
13294 | 2145 |
instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 2146 |
predicate(UseAVX > 0); |
2147 |
match(Set dst (AddD src1 src2)); |
|
2148 |
||
2149 |
format %{ "vaddsd $dst, $src1, $src2" %} |
|
2150 |
ins_cost(150); |
|
2151 |
ins_encode %{ |
|
2152 |
__ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2153 |
%} |
|
2154 |
ins_pipe(pipe_slow); |
|
2155 |
%} |
|
2156 |
||
13294 | 2157 |
instruct addD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 2158 |
predicate(UseAVX > 0); |
2159 |
match(Set dst (AddD src1 (LoadD src2))); |
|
2160 |
||
2161 |
format %{ "vaddsd $dst, $src1, $src2" %} |
|
2162 |
ins_cost(150); |
|
2163 |
ins_encode %{ |
|
2164 |
__ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2165 |
%} |
|
2166 |
ins_pipe(pipe_slow); |
|
2167 |
%} |
|
2168 |
||
13294 | 2169 |
instruct addD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 2170 |
predicate(UseAVX > 0); |
2171 |
match(Set dst (AddD src con)); |
|
2172 |
||
2173 |
format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2174 |
ins_cost(150); |
|
2175 |
ins_encode %{ |
|
2176 |
__ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2177 |
%} |
|
2178 |
ins_pipe(pipe_slow); |
|
2179 |
%} |
|
2180 |
||
2181 |
instruct subF_reg(regF dst, regF src) %{ |
|
2182 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2183 |
match(Set dst (SubF dst src)); |
|
2184 |
||
2185 |
format %{ "subss $dst, $src" %} |
|
2186 |
ins_cost(150); |
|
2187 |
ins_encode %{ |
|
2188 |
__ subss($dst$$XMMRegister, $src$$XMMRegister); |
|
2189 |
%} |
|
2190 |
ins_pipe(pipe_slow); |
|
2191 |
%} |
|
2192 |
||
2193 |
instruct subF_mem(regF dst, memory src) %{ |
|
2194 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2195 |
match(Set dst (SubF dst (LoadF src))); |
|
2196 |
||
2197 |
format %{ "subss $dst, $src" %} |
|
2198 |
ins_cost(150); |
|
2199 |
ins_encode %{ |
|
2200 |
__ subss($dst$$XMMRegister, $src$$Address); |
|
2201 |
%} |
|
2202 |
ins_pipe(pipe_slow); |
|
2203 |
%} |
|
2204 |
||
2205 |
instruct subF_imm(regF dst, immF con) %{ |
|
2206 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2207 |
match(Set dst (SubF dst con)); |
|
2208 |
format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2209 |
ins_cost(150); |
|
2210 |
ins_encode %{ |
|
2211 |
__ subss($dst$$XMMRegister, $constantaddress($con)); |
|
2212 |
%} |
|
2213 |
ins_pipe(pipe_slow); |
|
2214 |
%} |
|
2215 |
||
13294 | 2216 |
instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 2217 |
predicate(UseAVX > 0); |
2218 |
match(Set dst (SubF src1 src2)); |
|
2219 |
||
2220 |
format %{ "vsubss $dst, $src1, $src2" %} |
|
2221 |
ins_cost(150); |
|
2222 |
ins_encode %{ |
|
2223 |
__ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2224 |
%} |
|
2225 |
ins_pipe(pipe_slow); |
|
2226 |
%} |
|
2227 |
||
13294 | 2228 |
instruct subF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 2229 |
predicate(UseAVX > 0); |
2230 |
match(Set dst (SubF src1 (LoadF src2))); |
|
2231 |
||
2232 |
format %{ "vsubss $dst, $src1, $src2" %} |
|
2233 |
ins_cost(150); |
|
2234 |
ins_encode %{ |
|
2235 |
__ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2236 |
%} |
|
2237 |
ins_pipe(pipe_slow); |
|
2238 |
%} |
|
2239 |
||
13294 | 2240 |
instruct subF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 2241 |
predicate(UseAVX > 0); |
2242 |
match(Set dst (SubF src con)); |
|
2243 |
||
2244 |
format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2245 |
ins_cost(150); |
|
2246 |
ins_encode %{ |
|
2247 |
__ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2248 |
%} |
|
2249 |
ins_pipe(pipe_slow); |
|
2250 |
%} |
|
2251 |
||
2252 |
instruct subD_reg(regD dst, regD src) %{ |
|
2253 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2254 |
match(Set dst (SubD dst src)); |
|
2255 |
||
2256 |
format %{ "subsd $dst, $src" %} |
|
2257 |
ins_cost(150); |
|
2258 |
ins_encode %{ |
|
2259 |
__ subsd($dst$$XMMRegister, $src$$XMMRegister); |
|
2260 |
%} |
|
2261 |
ins_pipe(pipe_slow); |
|
2262 |
%} |
|
2263 |
||
2264 |
instruct subD_mem(regD dst, memory src) %{ |
|
2265 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2266 |
match(Set dst (SubD dst (LoadD src))); |
|
2267 |
||
2268 |
format %{ "subsd $dst, $src" %} |
|
2269 |
ins_cost(150); |
|
2270 |
ins_encode %{ |
|
2271 |
__ subsd($dst$$XMMRegister, $src$$Address); |
|
2272 |
%} |
|
2273 |
ins_pipe(pipe_slow); |
|
2274 |
%} |
|
2275 |
||
2276 |
instruct subD_imm(regD dst, immD con) %{ |
|
2277 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2278 |
match(Set dst (SubD dst con)); |
|
2279 |
format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2280 |
ins_cost(150); |
|
2281 |
ins_encode %{ |
|
2282 |
__ subsd($dst$$XMMRegister, $constantaddress($con)); |
|
2283 |
%} |
|
2284 |
ins_pipe(pipe_slow); |
|
2285 |
%} |
|
2286 |
||
13294 | 2287 |
instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 2288 |
predicate(UseAVX > 0); |
2289 |
match(Set dst (SubD src1 src2)); |
|
2290 |
||
2291 |
format %{ "vsubsd $dst, $src1, $src2" %} |
|
2292 |
ins_cost(150); |
|
2293 |
ins_encode %{ |
|
2294 |
__ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2295 |
%} |
|
2296 |
ins_pipe(pipe_slow); |
|
2297 |
%} |
|
2298 |
||
13294 | 2299 |
instruct subD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 2300 |
predicate(UseAVX > 0); |
2301 |
match(Set dst (SubD src1 (LoadD src2))); |
|
2302 |
||
2303 |
format %{ "vsubsd $dst, $src1, $src2" %} |
|
2304 |
ins_cost(150); |
|
2305 |
ins_encode %{ |
|
2306 |
__ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2307 |
%} |
|
2308 |
ins_pipe(pipe_slow); |
|
2309 |
%} |
|
2310 |
||
13294 | 2311 |
instruct subD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 2312 |
predicate(UseAVX > 0); |
2313 |
match(Set dst (SubD src con)); |
|
2314 |
||
2315 |
format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2316 |
ins_cost(150); |
|
2317 |
ins_encode %{ |
|
2318 |
__ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2319 |
%} |
|
2320 |
ins_pipe(pipe_slow); |
|
2321 |
%} |
|
2322 |
||
2323 |
instruct mulF_reg(regF dst, regF src) %{ |
|
2324 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2325 |
match(Set dst (MulF dst src)); |
|
2326 |
||
2327 |
format %{ "mulss $dst, $src" %} |
|
2328 |
ins_cost(150); |
|
2329 |
ins_encode %{ |
|
2330 |
__ mulss($dst$$XMMRegister, $src$$XMMRegister); |
|
2331 |
%} |
|
2332 |
ins_pipe(pipe_slow); |
|
2333 |
%} |
|
2334 |
||
2335 |
instruct mulF_mem(regF dst, memory src) %{ |
|
2336 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2337 |
match(Set dst (MulF dst (LoadF src))); |
|
2338 |
||
2339 |
format %{ "mulss $dst, $src" %} |
|
2340 |
ins_cost(150); |
|
2341 |
ins_encode %{ |
|
2342 |
__ mulss($dst$$XMMRegister, $src$$Address); |
|
2343 |
%} |
|
2344 |
ins_pipe(pipe_slow); |
|
2345 |
%} |
|
2346 |
||
2347 |
instruct mulF_imm(regF dst, immF con) %{ |
|
2348 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2349 |
match(Set dst (MulF dst con)); |
|
2350 |
format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2351 |
ins_cost(150); |
|
2352 |
ins_encode %{ |
|
2353 |
__ mulss($dst$$XMMRegister, $constantaddress($con)); |
|
2354 |
%} |
|
2355 |
ins_pipe(pipe_slow); |
|
2356 |
%} |
|
2357 |
||
13294 | 2358 |
instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 2359 |
predicate(UseAVX > 0); |
2360 |
match(Set dst (MulF src1 src2)); |
|
2361 |
||
2362 |
format %{ "vmulss $dst, $src1, $src2" %} |
|
2363 |
ins_cost(150); |
|
2364 |
ins_encode %{ |
|
2365 |
__ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2366 |
%} |
|
2367 |
ins_pipe(pipe_slow); |
|
2368 |
%} |
|
2369 |
||
13294 | 2370 |
instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 2371 |
predicate(UseAVX > 0); |
2372 |
match(Set dst (MulF src1 (LoadF src2))); |
|
2373 |
||
2374 |
format %{ "vmulss $dst, $src1, $src2" %} |
|
2375 |
ins_cost(150); |
|
2376 |
ins_encode %{ |
|
2377 |
__ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2378 |
%} |
|
2379 |
ins_pipe(pipe_slow); |
|
2380 |
%} |
|
2381 |
||
13294 | 2382 |
instruct mulF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 2383 |
predicate(UseAVX > 0); |
2384 |
match(Set dst (MulF src con)); |
|
2385 |
||
2386 |
format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2387 |
ins_cost(150); |
|
2388 |
ins_encode %{ |
|
2389 |
__ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2390 |
%} |
|
2391 |
ins_pipe(pipe_slow); |
|
2392 |
%} |
|
2393 |
||
2394 |
instruct mulD_reg(regD dst, regD src) %{ |
|
2395 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2396 |
match(Set dst (MulD dst src)); |
|
2397 |
||
2398 |
format %{ "mulsd $dst, $src" %} |
|
2399 |
ins_cost(150); |
|
2400 |
ins_encode %{ |
|
2401 |
__ mulsd($dst$$XMMRegister, $src$$XMMRegister); |
|
2402 |
%} |
|
2403 |
ins_pipe(pipe_slow); |
|
2404 |
%} |
|
2405 |
||
2406 |
instruct mulD_mem(regD dst, memory src) %{ |
|
2407 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2408 |
match(Set dst (MulD dst (LoadD src))); |
|
2409 |
||
2410 |
format %{ "mulsd $dst, $src" %} |
|
2411 |
ins_cost(150); |
|
2412 |
ins_encode %{ |
|
2413 |
__ mulsd($dst$$XMMRegister, $src$$Address); |
|
2414 |
%} |
|
2415 |
ins_pipe(pipe_slow); |
|
2416 |
%} |
|
2417 |
||
2418 |
instruct mulD_imm(regD dst, immD con) %{ |
|
2419 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2420 |
match(Set dst (MulD dst con)); |
|
2421 |
format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2422 |
ins_cost(150); |
|
2423 |
ins_encode %{ |
|
2424 |
__ mulsd($dst$$XMMRegister, $constantaddress($con)); |
|
2425 |
%} |
|
2426 |
ins_pipe(pipe_slow); |
|
2427 |
%} |
|
2428 |
||
13294 | 2429 |
instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 2430 |
predicate(UseAVX > 0); |
2431 |
match(Set dst (MulD src1 src2)); |
|
2432 |
||
2433 |
format %{ "vmulsd $dst, $src1, $src2" %} |
|
2434 |
ins_cost(150); |
|
2435 |
ins_encode %{ |
|
2436 |
__ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2437 |
%} |
|
2438 |
ins_pipe(pipe_slow); |
|
2439 |
%} |
|
2440 |
||
13294 | 2441 |
instruct mulD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 2442 |
predicate(UseAVX > 0); |
2443 |
match(Set dst (MulD src1 (LoadD src2))); |
|
2444 |
||
2445 |
format %{ "vmulsd $dst, $src1, $src2" %} |
|
2446 |
ins_cost(150); |
|
2447 |
ins_encode %{ |
|
2448 |
__ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2449 |
%} |
|
2450 |
ins_pipe(pipe_slow); |
|
2451 |
%} |
|
2452 |
||
13294 | 2453 |
instruct mulD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 2454 |
predicate(UseAVX > 0); |
2455 |
match(Set dst (MulD src con)); |
|
2456 |
||
2457 |
format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2458 |
ins_cost(150); |
|
2459 |
ins_encode %{ |
|
2460 |
__ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2461 |
%} |
|
2462 |
ins_pipe(pipe_slow); |
|
2463 |
%} |
|
2464 |
||
2465 |
instruct divF_reg(regF dst, regF src) %{ |
|
2466 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2467 |
match(Set dst (DivF dst src)); |
|
2468 |
||
2469 |
format %{ "divss $dst, $src" %} |
|
2470 |
ins_cost(150); |
|
2471 |
ins_encode %{ |
|
2472 |
__ divss($dst$$XMMRegister, $src$$XMMRegister); |
|
2473 |
%} |
|
2474 |
ins_pipe(pipe_slow); |
|
2475 |
%} |
|
2476 |
||
2477 |
instruct divF_mem(regF dst, memory src) %{ |
|
2478 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2479 |
match(Set dst (DivF dst (LoadF src))); |
|
2480 |
||
2481 |
format %{ "divss $dst, $src" %} |
|
2482 |
ins_cost(150); |
|
2483 |
ins_encode %{ |
|
2484 |
__ divss($dst$$XMMRegister, $src$$Address); |
|
2485 |
%} |
|
2486 |
ins_pipe(pipe_slow); |
|
2487 |
%} |
|
2488 |
||
2489 |
instruct divF_imm(regF dst, immF con) %{ |
|
2490 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2491 |
match(Set dst (DivF dst con)); |
|
2492 |
format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2493 |
ins_cost(150); |
|
2494 |
ins_encode %{ |
|
2495 |
__ divss($dst$$XMMRegister, $constantaddress($con)); |
|
2496 |
%} |
|
2497 |
ins_pipe(pipe_slow); |
|
2498 |
%} |
|
2499 |
||
13294 | 2500 |
instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 2501 |
predicate(UseAVX > 0); |
2502 |
match(Set dst (DivF src1 src2)); |
|
2503 |
||
2504 |
format %{ "vdivss $dst, $src1, $src2" %} |
|
2505 |
ins_cost(150); |
|
2506 |
ins_encode %{ |
|
2507 |
__ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2508 |
%} |
|
2509 |
ins_pipe(pipe_slow); |
|
2510 |
%} |
|
2511 |
||
13294 | 2512 |
instruct divF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 2513 |
predicate(UseAVX > 0); |
2514 |
match(Set dst (DivF src1 (LoadF src2))); |
|
2515 |
||
2516 |
format %{ "vdivss $dst, $src1, $src2" %} |
|
2517 |
ins_cost(150); |
|
2518 |
ins_encode %{ |
|
2519 |
__ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2520 |
%} |
|
2521 |
ins_pipe(pipe_slow); |
|
2522 |
%} |
|
2523 |
||
13294 | 2524 |
instruct divF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 2525 |
predicate(UseAVX > 0); |
2526 |
match(Set dst (DivF src con)); |
|
2527 |
||
2528 |
format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2529 |
ins_cost(150); |
|
2530 |
ins_encode %{ |
|
2531 |
__ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2532 |
%} |
|
2533 |
ins_pipe(pipe_slow); |
|
2534 |
%} |
|
2535 |
||
2536 |
instruct divD_reg(regD dst, regD src) %{ |
|
2537 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2538 |
match(Set dst (DivD dst src)); |
|
2539 |
||
2540 |
format %{ "divsd $dst, $src" %} |
|
2541 |
ins_cost(150); |
|
2542 |
ins_encode %{ |
|
2543 |
__ divsd($dst$$XMMRegister, $src$$XMMRegister); |
|
2544 |
%} |
|
2545 |
ins_pipe(pipe_slow); |
|
2546 |
%} |
|
2547 |
||
2548 |
instruct divD_mem(regD dst, memory src) %{ |
|
2549 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2550 |
match(Set dst (DivD dst (LoadD src))); |
|
2551 |
||
2552 |
format %{ "divsd $dst, $src" %} |
|
2553 |
ins_cost(150); |
|
2554 |
ins_encode %{ |
|
2555 |
__ divsd($dst$$XMMRegister, $src$$Address); |
|
2556 |
%} |
|
2557 |
ins_pipe(pipe_slow); |
|
2558 |
%} |
|
2559 |
||
2560 |
instruct divD_imm(regD dst, immD con) %{ |
|
2561 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2562 |
match(Set dst (DivD dst con)); |
|
2563 |
format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2564 |
ins_cost(150); |
|
2565 |
ins_encode %{ |
|
2566 |
__ divsd($dst$$XMMRegister, $constantaddress($con)); |
|
2567 |
%} |
|
2568 |
ins_pipe(pipe_slow); |
|
2569 |
%} |
|
2570 |
||
13294 | 2571 |
instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 2572 |
predicate(UseAVX > 0); |
2573 |
match(Set dst (DivD src1 src2)); |
|
2574 |
||
2575 |
format %{ "vdivsd $dst, $src1, $src2" %} |
|
2576 |
ins_cost(150); |
|
2577 |
ins_encode %{ |
|
2578 |
__ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2579 |
%} |
|
2580 |
ins_pipe(pipe_slow); |
|
2581 |
%} |
|
2582 |
||
13294 | 2583 |
instruct divD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 2584 |
predicate(UseAVX > 0); |
2585 |
match(Set dst (DivD src1 (LoadD src2))); |
|
2586 |
||
2587 |
format %{ "vdivsd $dst, $src1, $src2" %} |
|
2588 |
ins_cost(150); |
|
2589 |
ins_encode %{ |
|
2590 |
__ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
2591 |
%} |
|
2592 |
ins_pipe(pipe_slow); |
|
2593 |
%} |
|
2594 |
||
13294 | 2595 |
instruct divD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 2596 |
predicate(UseAVX > 0); |
2597 |
match(Set dst (DivD src con)); |
|
2598 |
||
2599 |
format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2600 |
ins_cost(150); |
|
2601 |
ins_encode %{ |
|
2602 |
__ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
2603 |
%} |
|
2604 |
ins_pipe(pipe_slow); |
|
2605 |
%} |
|
2606 |
||
2607 |
instruct absF_reg(regF dst) %{ |
|
2608 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2609 |
match(Set dst (AbsF dst)); |
|
2610 |
ins_cost(150); |
|
2611 |
format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} |
|
2612 |
ins_encode %{ |
|
2613 |
__ andps($dst$$XMMRegister, ExternalAddress(float_signmask())); |
|
2614 |
%} |
|
2615 |
ins_pipe(pipe_slow); |
|
2616 |
%} |
|
2617 |
||
13294 | 2618 |
instruct absF_reg_reg(regF dst, regF src) %{ |
11429 | 2619 |
predicate(UseAVX > 0); |
2620 |
match(Set dst (AbsF src)); |
|
2621 |
ins_cost(150); |
|
2622 |
format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %} |
|
2623 |
ins_encode %{ |
|
30624 | 2624 |
int vector_len = 0; |
11429 | 2625 |
__ vandps($dst$$XMMRegister, $src$$XMMRegister, |
30624 | 2626 |
ExternalAddress(float_signmask()), vector_len); |
11429 | 2627 |
%} |
2628 |
ins_pipe(pipe_slow); |
|
2629 |
%} |
|
2630 |
||
2631 |
instruct absD_reg(regD dst) %{ |
|
2632 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2633 |
match(Set dst (AbsD dst)); |
|
2634 |
ins_cost(150); |
|
2635 |
format %{ "andpd $dst, [0x7fffffffffffffff]\t" |
|
2636 |
"# abs double by sign masking" %} |
|
2637 |
ins_encode %{ |
|
2638 |
__ andpd($dst$$XMMRegister, ExternalAddress(double_signmask())); |
|
2639 |
%} |
|
2640 |
ins_pipe(pipe_slow); |
|
2641 |
%} |
|
2642 |
||
13294 | 2643 |
instruct absD_reg_reg(regD dst, regD src) %{ |
11429 | 2644 |
predicate(UseAVX > 0); |
2645 |
match(Set dst (AbsD src)); |
|
2646 |
ins_cost(150); |
|
2647 |
format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t" |
|
2648 |
"# abs double by sign masking" %} |
|
2649 |
ins_encode %{ |
|
30624 | 2650 |
int vector_len = 0; |
11429 | 2651 |
__ vandpd($dst$$XMMRegister, $src$$XMMRegister, |
30624 | 2652 |
ExternalAddress(double_signmask()), vector_len); |
11429 | 2653 |
%} |
2654 |
ins_pipe(pipe_slow); |
|
2655 |
%} |
|
2656 |
||
2657 |
instruct negF_reg(regF dst) %{ |
|
2658 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
2659 |
match(Set dst (NegF dst)); |
|
2660 |
ins_cost(150); |
|
2661 |
format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} |
|
2662 |
ins_encode %{ |
|
2663 |
__ xorps($dst$$XMMRegister, ExternalAddress(float_signflip())); |
|
2664 |
%} |
|
2665 |
ins_pipe(pipe_slow); |
|
2666 |
%} |
|
2667 |
||
13294 | 2668 |
instruct negF_reg_reg(regF dst, regF src) %{ |
11429 | 2669 |
predicate(UseAVX > 0); |
2670 |
match(Set dst (NegF src)); |
|
2671 |
ins_cost(150); |
|
2672 |
format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %} |
|
2673 |
ins_encode %{ |
|
30624 | 2674 |
int vector_len = 0; |
11429 | 2675 |
__ vxorps($dst$$XMMRegister, $src$$XMMRegister, |
30624 | 2676 |
ExternalAddress(float_signflip()), vector_len); |
11429 | 2677 |
%} |
2678 |
ins_pipe(pipe_slow); |
|
2679 |
%} |
|
2680 |
||
2681 |
instruct negD_reg(regD dst) %{ |
|
2682 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
2683 |
match(Set dst (NegD dst)); |
|
2684 |
ins_cost(150); |
|
2685 |
format %{ "xorpd $dst, [0x8000000000000000]\t" |
|
2686 |
"# neg double by sign flipping" %} |
|
2687 |
ins_encode %{ |
|
2688 |
__ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip())); |
|
2689 |
%} |
|
2690 |
ins_pipe(pipe_slow); |
|
2691 |
%} |
|
2692 |
||
13294 | 2693 |
instruct negD_reg_reg(regD dst, regD src) %{ |
11429 | 2694 |
predicate(UseAVX > 0); |
2695 |
match(Set dst (NegD src)); |
|
2696 |
ins_cost(150); |
|
2697 |
format %{ "vxorpd $dst, $src, [0x8000000000000000]\t" |
|
2698 |
"# neg double by sign flipping" %} |
|
2699 |
ins_encode %{ |
|
30624 | 2700 |
int vector_len = 0; |
11429 | 2701 |
__ vxorpd($dst$$XMMRegister, $src$$XMMRegister, |
30624 | 2702 |
ExternalAddress(double_signflip()), vector_len); |
11429 | 2703 |
%} |
2704 |
ins_pipe(pipe_slow); |
|
2705 |
%} |
|
2706 |
||
2707 |
instruct sqrtF_reg(regF dst, regF src) %{ |
|
2708 |
predicate(UseSSE>=1); |
|
2709 |
match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
2710 |
||
2711 |
format %{ "sqrtss $dst, $src" %} |
|
2712 |
ins_cost(150); |
|
2713 |
ins_encode %{ |
|
2714 |
__ sqrtss($dst$$XMMRegister, $src$$XMMRegister); |
|
2715 |
%} |
|
2716 |
ins_pipe(pipe_slow); |
|
2717 |
%} |
|
2718 |
||
2719 |
instruct sqrtF_mem(regF dst, memory src) %{ |
|
2720 |
predicate(UseSSE>=1); |
|
2721 |
match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); |
|
2722 |
||
2723 |
format %{ "sqrtss $dst, $src" %} |
|
2724 |
ins_cost(150); |
|
2725 |
ins_encode %{ |
|
2726 |
__ sqrtss($dst$$XMMRegister, $src$$Address); |
|
2727 |
%} |
|
2728 |
ins_pipe(pipe_slow); |
|
2729 |
%} |
|
2730 |
||
2731 |
instruct sqrtF_imm(regF dst, immF con) %{ |
|
2732 |
predicate(UseSSE>=1); |
|
2733 |
match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); |
|
2734 |
format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
2735 |
ins_cost(150); |
|
2736 |
ins_encode %{ |
|
2737 |
__ sqrtss($dst$$XMMRegister, $constantaddress($con)); |
|
2738 |
%} |
|
2739 |
ins_pipe(pipe_slow); |
|
2740 |
%} |
|
2741 |
||
2742 |
instruct sqrtD_reg(regD dst, regD src) %{ |
|
2743 |
predicate(UseSSE>=2); |
|
2744 |
match(Set dst (SqrtD src)); |
|
2745 |
||
2746 |
format %{ "sqrtsd $dst, $src" %} |
|
2747 |
ins_cost(150); |
|
2748 |
ins_encode %{ |
|
2749 |
__ sqrtsd($dst$$XMMRegister, $src$$XMMRegister); |
|
2750 |
%} |
|
2751 |
ins_pipe(pipe_slow); |
|
2752 |
%} |
|
2753 |
||
2754 |
instruct sqrtD_mem(regD dst, memory src) %{ |
|
2755 |
predicate(UseSSE>=2); |
|
2756 |
match(Set dst (SqrtD (LoadD src))); |
|
2757 |
||
2758 |
format %{ "sqrtsd $dst, $src" %} |
|
2759 |
ins_cost(150); |
|
2760 |
ins_encode %{ |
|
2761 |
__ sqrtsd($dst$$XMMRegister, $src$$Address); |
|
2762 |
%} |
|
2763 |
ins_pipe(pipe_slow); |
|
2764 |
%} |
|
2765 |
||
2766 |
instruct sqrtD_imm(regD dst, immD con) %{ |
|
2767 |
predicate(UseSSE>=2); |
|
2768 |
match(Set dst (SqrtD con)); |
|
2769 |
format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
2770 |
ins_cost(150); |
|
2771 |
ins_encode %{ |
|
2772 |
__ sqrtsd($dst$$XMMRegister, $constantaddress($con)); |
|
2773 |
%} |
|
2774 |
ins_pipe(pipe_slow); |
|
2775 |
%} |
|
2776 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2777 |
// ====================VECTOR INSTRUCTIONS===================================== |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2778 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2779 |
// Load vectors (4 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2780 |
instruct loadV4(vecS dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2781 |
predicate(n->as_LoadVector()->memory_size() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2782 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2783 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2784 |
format %{ "movd $dst,$mem\t! load vector (4 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2785 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2786 |
__ movdl($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2787 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2788 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2789 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2790 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2791 |
// Load vectors (8 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2792 |
instruct loadV8(vecD dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2793 |
predicate(n->as_LoadVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2794 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2795 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2796 |
format %{ "movq $dst,$mem\t! load vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2797 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2798 |
__ movq($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2799 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2800 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2801 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2802 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2803 |
// Load vectors (16 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2804 |
instruct loadV16(vecX dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2805 |
predicate(n->as_LoadVector()->memory_size() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2806 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2807 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2808 |
format %{ "movdqu $dst,$mem\t! load vector (16 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2809 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2810 |
__ movdqu($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2811 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2812 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2813 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2814 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2815 |
// Load vectors (32 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2816 |
instruct loadV32(vecY dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2817 |
predicate(n->as_LoadVector()->memory_size() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2818 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2819 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2820 |
format %{ "vmovdqu $dst,$mem\t! load vector (32 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2821 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2822 |
__ vmovdqu($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2823 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2824 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2825 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2826 |
|
30624 | 2827 |
// Load vectors (64 bytes long) |
2828 |
instruct loadV64(vecZ dst, memory mem) %{ |
|
2829 |
predicate(n->as_LoadVector()->memory_size() == 64); |
|
2830 |
match(Set dst (LoadVector mem)); |
|
2831 |
ins_cost(125); |
|
2832 |
format %{ "vmovdqu $dst k0,$mem\t! load vector (64 bytes)" %} |
|
2833 |
ins_encode %{ |
|
2834 |
int vector_len = 2; |
|
2835 |
__ evmovdqu($dst$$XMMRegister, $mem$$Address, vector_len); |
|
2836 |
%} |
|
2837 |
ins_pipe( pipe_slow ); |
|
2838 |
%} |
|
2839 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2840 |
// Store vectors |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2841 |
instruct storeV4(memory mem, vecS src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2842 |
predicate(n->as_StoreVector()->memory_size() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2843 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2844 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2845 |
format %{ "movd $mem,$src\t! store vector (4 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2846 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2847 |
__ movdl($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2848 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2849 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2850 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2851 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2852 |
instruct storeV8(memory mem, vecD src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2853 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2854 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2855 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2856 |
format %{ "movq $mem,$src\t! store vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2857 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2858 |
__ movq($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2859 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2860 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2861 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2862 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2863 |
instruct storeV16(memory mem, vecX src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2864 |
predicate(n->as_StoreVector()->memory_size() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2865 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2866 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2867 |
format %{ "movdqu $mem,$src\t! store vector (16 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2868 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2869 |
__ movdqu($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2870 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2871 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2872 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2873 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2874 |
instruct storeV32(memory mem, vecY src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2875 |
predicate(n->as_StoreVector()->memory_size() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2876 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2877 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2878 |
format %{ "vmovdqu $mem,$src\t! store vector (32 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2879 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2880 |
__ vmovdqu($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2881 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2882 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2883 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2884 |
|
30624 | 2885 |
instruct storeV64(memory mem, vecZ src) %{ |
2886 |
predicate(n->as_StoreVector()->memory_size() == 64); |
|
2887 |
match(Set mem (StoreVector mem src)); |
|
2888 |
ins_cost(145); |
|
2889 |
format %{ "vmovdqu $mem k0,$src\t! store vector (64 bytes)" %} |
|
2890 |
ins_encode %{ |
|
2891 |
int vector_len = 2; |
|
2892 |
__ evmovdqu($mem$$Address, $src$$XMMRegister, vector_len); |
|
2893 |
%} |
|
2894 |
ins_pipe( pipe_slow ); |
|
2895 |
%} |
|
2896 |
||
31410 | 2897 |
// ====================LEGACY REPLICATE======================================= |
2898 |
||
2899 |
instruct Repl4B_mem(vecS dst, memory mem) %{ |
|
2900 |
predicate(n->as_Vector()->length() == 4 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); |
|
2901 |
match(Set dst (ReplicateB (LoadB mem))); |
|
2902 |
format %{ "punpcklbw $dst,$mem\n\t" |
|
2903 |
"pshuflw $dst,$dst,0x00\t! replicate4B" %} |
|
2904 |
ins_encode %{ |
|
2905 |
__ punpcklbw($dst$$XMMRegister, $mem$$Address); |
|
2906 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
2907 |
%} |
|
2908 |
ins_pipe( pipe_slow ); |
|
2909 |
%} |
|
2910 |
||
2911 |
instruct Repl8B_mem(vecD dst, memory mem) %{ |
|
2912 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); |
|
2913 |
match(Set dst (ReplicateB (LoadB mem))); |
|
2914 |
format %{ "punpcklbw $dst,$mem\n\t" |
|
2915 |
"pshuflw $dst,$dst,0x00\t! replicate8B" %} |
|
2916 |
ins_encode %{ |
|
2917 |
__ punpcklbw($dst$$XMMRegister, $mem$$Address); |
|
2918 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
2919 |
%} |
|
2920 |
ins_pipe( pipe_slow ); |
|
2921 |
%} |
|
2922 |
||
2923 |
instruct Repl16B(vecX dst, rRegI src) %{ |
|
2924 |
predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); |
|
2925 |
match(Set dst (ReplicateB src)); |
|
2926 |
format %{ "movd $dst,$src\n\t" |
|
2927 |
"punpcklbw $dst,$dst\n\t" |
|
2928 |
"pshuflw $dst,$dst,0x00\n\t" |
|
2929 |
"punpcklqdq $dst,$dst\t! replicate16B" %} |
|
2930 |
ins_encode %{ |
|
2931 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
2932 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
|
2933 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
2934 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2935 |
%} |
|
2936 |
ins_pipe( pipe_slow ); |
|
2937 |
%} |
|
2938 |
||
2939 |
instruct Repl16B_mem(vecX dst, memory mem) %{ |
|
2940 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); |
|
2941 |
match(Set dst (ReplicateB (LoadB mem))); |
|
2942 |
format %{ "punpcklbw $dst,$mem\n\t" |
|
2943 |
"pshuflw $dst,$dst,0x00\n\t" |
|
2944 |
"punpcklqdq $dst,$dst\t! replicate16B" %} |
|
2945 |
ins_encode %{ |
|
2946 |
__ punpcklbw($dst$$XMMRegister, $mem$$Address); |
|
2947 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
2948 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2949 |
%} |
|
2950 |
ins_pipe( pipe_slow ); |
|
2951 |
%} |
|
2952 |
||
2953 |
instruct Repl32B(vecY dst, rRegI src) %{ |
|
2954 |
predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512vlbw()); |
|
2955 |
match(Set dst (ReplicateB src)); |
|
2956 |
format %{ "movd $dst,$src\n\t" |
|
2957 |
"punpcklbw $dst,$dst\n\t" |
|
2958 |
"pshuflw $dst,$dst,0x00\n\t" |
|
2959 |
"punpcklqdq $dst,$dst\n\t" |
|
2960 |
"vinserti128h $dst,$dst,$dst\t! replicate32B" %} |
|
2961 |
ins_encode %{ |
|
2962 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
2963 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
|
2964 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
2965 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2966 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
2967 |
%} |
|
2968 |
ins_pipe( pipe_slow ); |
|
2969 |
%} |
|
2970 |
||
2971 |
instruct Repl32B_mem(vecY dst, memory mem) %{ |
|
2972 |
predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512vlbw()); |
|
2973 |
match(Set dst (ReplicateB (LoadB mem))); |
|
2974 |
format %{ "punpcklbw $dst,$mem\n\t" |
|
2975 |
"pshuflw $dst,$dst,0x00\n\t" |
|
2976 |
"punpcklqdq $dst,$dst\n\t" |
|
2977 |
"vinserti128h $dst,$dst,$dst\t! replicate32B" %} |
|
2978 |
ins_encode %{ |
|
2979 |
__ punpcklbw($dst$$XMMRegister, $mem$$Address); |
|
2980 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
2981 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2982 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
2983 |
%} |
|
2984 |
ins_pipe( pipe_slow ); |
|
2985 |
%} |
|
2986 |
||
2987 |
instruct Repl16B_imm(vecX dst, immI con) %{ |
|
2988 |
predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); |
|
2989 |
match(Set dst (ReplicateB con)); |
|
2990 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
2991 |
"punpcklqdq $dst,$dst\t! replicate16B($con)" %} |
|
2992 |
ins_encode %{ |
|
2993 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
|
2994 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2995 |
%} |
|
2996 |
ins_pipe( pipe_slow ); |
|
2997 |
%} |
|
2998 |
||
2999 |
instruct Repl32B_imm(vecY dst, immI con) %{ |
|
3000 |
predicate(n->as_Vector()->length() == 32 && !VM_Version::supports_avx512vlbw()); |
|
3001 |
match(Set dst (ReplicateB con)); |
|
3002 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3003 |
"punpcklqdq $dst,$dst\n\t" |
|
3004 |
"vinserti128h $dst,$dst,$dst\t! lreplicate32B($con)" %} |
|
3005 |
ins_encode %{ |
|
3006 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
|
3007 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3008 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3009 |
%} |
|
3010 |
ins_pipe( pipe_slow ); |
|
3011 |
%} |
|
3012 |
||
3013 |
instruct Repl4S(vecD dst, rRegI src) %{ |
|
3014 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vlbw()); |
|
3015 |
match(Set dst (ReplicateS src)); |
|
3016 |
format %{ "movd $dst,$src\n\t" |
|
3017 |
"pshuflw $dst,$dst,0x00\t! replicate4S" %} |
|
3018 |
ins_encode %{ |
|
3019 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
3020 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
3021 |
%} |
|
3022 |
ins_pipe( pipe_slow ); |
|
3023 |
%} |
|
3024 |
||
3025 |
instruct Repl4S_mem(vecD dst, memory mem) %{ |
|
3026 |
predicate(n->as_Vector()->length() == 4 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); |
|
3027 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3028 |
format %{ "pshuflw $dst,$mem,0x00\t! replicate4S" %} |
|
3029 |
ins_encode %{ |
|
3030 |
__ pshuflw($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3031 |
%} |
|
3032 |
ins_pipe( pipe_slow ); |
|
3033 |
%} |
|
3034 |
||
3035 |
instruct Repl8S(vecX dst, rRegI src) %{ |
|
3036 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vlbw()); |
|
3037 |
match(Set dst (ReplicateS src)); |
|
3038 |
format %{ "movd $dst,$src\n\t" |
|
3039 |
"pshuflw $dst,$dst,0x00\n\t" |
|
3040 |
"punpcklqdq $dst,$dst\t! replicate8S" %} |
|
3041 |
ins_encode %{ |
|
3042 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
3043 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
3044 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3045 |
%} |
|
3046 |
ins_pipe( pipe_slow ); |
|
3047 |
%} |
|
3048 |
||
3049 |
instruct Repl8S_mem(vecX dst, memory mem) %{ |
|
3050 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 0 && !VM_Version::supports_avx512vlbw()); |
|
3051 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3052 |
format %{ "pshuflw $dst,$mem,0x00\n\t" |
|
3053 |
"punpcklqdq $dst,$dst\t! replicate8S" %} |
|
3054 |
ins_encode %{ |
|
3055 |
__ pshuflw($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3056 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3057 |
%} |
|
3058 |
ins_pipe( pipe_slow ); |
|
3059 |
%} |
|
3060 |
||
3061 |
instruct Repl8S_imm(vecX dst, immI con) %{ |
|
3062 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vlbw()); |
|
3063 |
match(Set dst (ReplicateS con)); |
|
3064 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3065 |
"punpcklqdq $dst,$dst\t! replicate8S($con)" %} |
|
3066 |
ins_encode %{ |
|
3067 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
|
3068 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3069 |
%} |
|
3070 |
ins_pipe( pipe_slow ); |
|
3071 |
%} |
|
3072 |
||
3073 |
instruct Repl16S(vecY dst, rRegI src) %{ |
|
3074 |
predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); |
|
3075 |
match(Set dst (ReplicateS src)); |
|
3076 |
format %{ "movd $dst,$src\n\t" |
|
3077 |
"pshuflw $dst,$dst,0x00\n\t" |
|
3078 |
"punpcklqdq $dst,$dst\n\t" |
|
3079 |
"vinserti128h $dst,$dst,$dst\t! replicate16S" %} |
|
3080 |
ins_encode %{ |
|
3081 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
3082 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
3083 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3084 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3085 |
%} |
|
3086 |
ins_pipe( pipe_slow ); |
|
3087 |
%} |
|
3088 |
||
3089 |
instruct Repl16S_mem(vecY dst, memory mem) %{ |
|
3090 |
predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); |
|
3091 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3092 |
format %{ "pshuflw $dst,$mem,0x00\n\t" |
|
3093 |
"punpcklqdq $dst,$dst\n\t" |
|
3094 |
"vinserti128h $dst,$dst,$dst\t! replicate16S" %} |
|
3095 |
ins_encode %{ |
|
3096 |
__ pshuflw($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3097 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3098 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3099 |
%} |
|
3100 |
ins_pipe( pipe_slow ); |
|
3101 |
%} |
|
3102 |
||
3103 |
instruct Repl16S_imm(vecY dst, immI con) %{ |
|
3104 |
predicate(n->as_Vector()->length() == 16 && !VM_Version::supports_avx512vlbw()); |
|
3105 |
match(Set dst (ReplicateS con)); |
|
3106 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3107 |
"punpcklqdq $dst,$dst\n\t" |
|
3108 |
"vinserti128h $dst,$dst,$dst\t! replicate16S($con)" %} |
|
3109 |
ins_encode %{ |
|
3110 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
|
3111 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3112 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3113 |
%} |
|
3114 |
ins_pipe( pipe_slow ); |
|
3115 |
%} |
|
3116 |
||
3117 |
instruct Repl4I(vecX dst, rRegI src) %{ |
|
3118 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3119 |
match(Set dst (ReplicateI src)); |
|
3120 |
format %{ "movd $dst,$src\n\t" |
|
3121 |
"pshufd $dst,$dst,0x00\t! replicate4I" %} |
|
3122 |
ins_encode %{ |
|
3123 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
3124 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
3125 |
%} |
|
3126 |
ins_pipe( pipe_slow ); |
|
3127 |
%} |
|
3128 |
||
3129 |
instruct Repl4I_mem(vecX dst, memory mem) %{ |
|
3130 |
predicate(n->as_Vector()->length() == 4 && UseAVX > 0 && !VM_Version::supports_avx512vl()); |
|
3131 |
match(Set dst (ReplicateI (LoadI mem))); |
|
3132 |
format %{ "pshufd $dst,$mem,0x00\t! replicate4I" %} |
|
3133 |
ins_encode %{ |
|
3134 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3135 |
%} |
|
3136 |
ins_pipe( pipe_slow ); |
|
3137 |
%} |
|
3138 |
||
3139 |
instruct Repl8I(vecY dst, rRegI src) %{ |
|
3140 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vl()); |
|
3141 |
match(Set dst (ReplicateI src)); |
|
3142 |
format %{ "movd $dst,$src\n\t" |
|
3143 |
"pshufd $dst,$dst,0x00\n\t" |
|
3144 |
"vinserti128h $dst,$dst,$dst\t! replicate8I" %} |
|
3145 |
ins_encode %{ |
|
3146 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
3147 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
|
3148 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3149 |
%} |
|
3150 |
ins_pipe( pipe_slow ); |
|
3151 |
%} |
|
3152 |
||
3153 |
instruct Repl8I_mem(vecY dst, memory mem) %{ |
|
3154 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vl()); |
|
3155 |
match(Set dst (ReplicateI (LoadI mem))); |
|
3156 |
format %{ "pshufd $dst,$mem,0x00\n\t" |
|
3157 |
"vinserti128h $dst,$dst,$dst\t! replicate8I" %} |
|
3158 |
ins_encode %{ |
|
3159 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3160 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3161 |
%} |
|
3162 |
ins_pipe( pipe_slow ); |
|
3163 |
%} |
|
3164 |
||
3165 |
instruct Repl4I_imm(vecX dst, immI con) %{ |
|
3166 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3167 |
match(Set dst (ReplicateI con)); |
|
3168 |
format %{ "movq $dst,[$constantaddress]\t! replicate4I($con)\n\t" |
|
3169 |
"punpcklqdq $dst,$dst" %} |
|
3170 |
ins_encode %{ |
|
3171 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
|
3172 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3173 |
%} |
|
3174 |
ins_pipe( pipe_slow ); |
|
3175 |
%} |
|
3176 |
||
3177 |
instruct Repl8I_imm(vecY dst, immI con) %{ |
|
3178 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vl()); |
|
3179 |
match(Set dst (ReplicateI con)); |
|
3180 |
format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t" |
|
3181 |
"punpcklqdq $dst,$dst\n\t" |
|
3182 |
"vinserti128h $dst,$dst,$dst" %} |
|
3183 |
ins_encode %{ |
|
3184 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
|
3185 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3186 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3187 |
%} |
|
3188 |
ins_pipe( pipe_slow ); |
|
3189 |
%} |
|
3190 |
||
3191 |
// Long could be loaded into xmm register directly from memory. |
|
3192 |
instruct Repl2L_mem(vecX dst, memory mem) %{ |
|
3193 |
predicate(n->as_Vector()->length() == 2 && !VM_Version::supports_avx512vlbw()); |
|
3194 |
match(Set dst (ReplicateL (LoadL mem))); |
|
3195 |
format %{ "movq $dst,$mem\n\t" |
|
3196 |
"punpcklqdq $dst,$dst\t! replicate2L" %} |
|
3197 |
ins_encode %{ |
|
3198 |
__ movq($dst$$XMMRegister, $mem$$Address); |
|
3199 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3200 |
%} |
|
3201 |
ins_pipe( pipe_slow ); |
|
3202 |
%} |
|
3203 |
||
3204 |
// Replicate long (8 byte) scalar to be vector |
|
3205 |
#ifdef _LP64 |
|
3206 |
instruct Repl4L(vecY dst, rRegL src) %{ |
|
3207 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3208 |
match(Set dst (ReplicateL src)); |
|
3209 |
format %{ "movdq $dst,$src\n\t" |
|
3210 |
"punpcklqdq $dst,$dst\n\t" |
|
3211 |
"vinserti128h $dst,$dst,$dst\t! replicate4L" %} |
|
3212 |
ins_encode %{ |
|
3213 |
__ movdq($dst$$XMMRegister, $src$$Register); |
|
3214 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3215 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3216 |
%} |
|
3217 |
ins_pipe( pipe_slow ); |
|
3218 |
%} |
|
3219 |
#else // _LP64 |
|
3220 |
instruct Repl4L(vecY dst, eRegL src, regD tmp) %{ |
|
3221 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3222 |
match(Set dst (ReplicateL src)); |
|
3223 |
effect(TEMP dst, USE src, TEMP tmp); |
|
3224 |
format %{ "movdl $dst,$src.lo\n\t" |
|
3225 |
"movdl $tmp,$src.hi\n\t" |
|
3226 |
"punpckldq $dst,$tmp\n\t" |
|
3227 |
"punpcklqdq $dst,$dst\n\t" |
|
3228 |
"vinserti128h $dst,$dst,$dst\t! replicate4L" %} |
|
3229 |
ins_encode %{ |
|
3230 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
3231 |
__ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
|
3232 |
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
|
3233 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3234 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3235 |
%} |
|
3236 |
ins_pipe( pipe_slow ); |
|
3237 |
%} |
|
3238 |
#endif // _LP64 |
|
3239 |
||
3240 |
instruct Repl4L_imm(vecY dst, immL con) %{ |
|
3241 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3242 |
match(Set dst (ReplicateL con)); |
|
3243 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3244 |
"punpcklqdq $dst,$dst\n\t" |
|
3245 |
"vinserti128h $dst,$dst,$dst\t! replicate4L($con)" %} |
|
3246 |
ins_encode %{ |
|
3247 |
__ movq($dst$$XMMRegister, $constantaddress($con)); |
|
3248 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3249 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3250 |
%} |
|
3251 |
ins_pipe( pipe_slow ); |
|
3252 |
%} |
|
3253 |
||
3254 |
instruct Repl4L_mem(vecY dst, memory mem) %{ |
|
3255 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3256 |
match(Set dst (ReplicateL (LoadL mem))); |
|
3257 |
format %{ "movq $dst,$mem\n\t" |
|
3258 |
"punpcklqdq $dst,$dst\n\t" |
|
3259 |
"vinserti128h $dst,$dst,$dst\t! replicate4L" %} |
|
3260 |
ins_encode %{ |
|
3261 |
__ movq($dst$$XMMRegister, $mem$$Address); |
|
3262 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
3263 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3264 |
%} |
|
3265 |
ins_pipe( pipe_slow ); |
|
3266 |
%} |
|
3267 |
||
3268 |
instruct Repl2F_mem(vecD dst, memory mem) %{ |
|
3269 |
predicate(n->as_Vector()->length() == 2 && UseAVX > 0 && !VM_Version::supports_avx512vl()); |
|
3270 |
match(Set dst (ReplicateF (LoadF mem))); |
|
3271 |
format %{ "pshufd $dst,$mem,0x00\t! replicate2F" %} |
|
3272 |
ins_encode %{ |
|
3273 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3274 |
%} |
|
3275 |
ins_pipe( pipe_slow ); |
|
3276 |
%} |
|
3277 |
||
3278 |
instruct Repl4F_mem(vecX dst, memory mem) %{ |
|
3279 |
predicate(n->as_Vector()->length() == 4 && UseAVX > 0 && !VM_Version::supports_avx512vl()); |
|
3280 |
match(Set dst (ReplicateF (LoadF mem))); |
|
3281 |
format %{ "pshufd $dst,$mem,0x00\t! replicate4F" %} |
|
3282 |
ins_encode %{ |
|
3283 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3284 |
%} |
|
3285 |
ins_pipe( pipe_slow ); |
|
3286 |
%} |
|
3287 |
||
3288 |
instruct Repl8F(vecY dst, regF src) %{ |
|
3289 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vl()); |
|
3290 |
match(Set dst (ReplicateF src)); |
|
3291 |
format %{ "pshufd $dst,$src,0x00\n\t" |
|
3292 |
"vinsertf128h $dst,$dst,$dst\t! replicate8F" %} |
|
3293 |
ins_encode %{ |
|
3294 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
|
3295 |
__ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3296 |
%} |
|
3297 |
ins_pipe( pipe_slow ); |
|
3298 |
%} |
|
3299 |
||
3300 |
instruct Repl8F_mem(vecY dst, memory mem) %{ |
|
3301 |
predicate(n->as_Vector()->length() == 8 && !VM_Version::supports_avx512vl()); |
|
3302 |
match(Set dst (ReplicateF (LoadF mem))); |
|
3303 |
format %{ "pshufd $dst,$mem,0x00\n\t" |
|
3304 |
"vinsertf128h $dst,$dst,$dst\t! replicate8F" %} |
|
3305 |
ins_encode %{ |
|
3306 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x00); |
|
3307 |
__ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3308 |
%} |
|
3309 |
ins_pipe( pipe_slow ); |
|
3310 |
%} |
|
3311 |
||
3312 |
instruct Repl2D_mem(vecX dst, memory mem) %{ |
|
3313 |
predicate(n->as_Vector()->length() == 2 && UseAVX > 0 && !VM_Version::supports_avx512vl()); |
|
3314 |
match(Set dst (ReplicateD (LoadD mem))); |
|
3315 |
format %{ "pshufd $dst,$mem,0x44\t! replicate2D" %} |
|
3316 |
ins_encode %{ |
|
3317 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x44); |
|
3318 |
%} |
|
3319 |
ins_pipe( pipe_slow ); |
|
3320 |
%} |
|
3321 |
||
3322 |
instruct Repl4D(vecY dst, regD src) %{ |
|
3323 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3324 |
match(Set dst (ReplicateD src)); |
|
3325 |
format %{ "pshufd $dst,$src,0x44\n\t" |
|
3326 |
"vinsertf128h $dst,$dst,$dst\t! replicate4D" %} |
|
3327 |
ins_encode %{ |
|
3328 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
|
3329 |
__ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3330 |
%} |
|
3331 |
ins_pipe( pipe_slow ); |
|
3332 |
%} |
|
3333 |
||
3334 |
instruct Repl4D_mem(vecY dst, memory mem) %{ |
|
3335 |
predicate(n->as_Vector()->length() == 4 && !VM_Version::supports_avx512vl()); |
|
3336 |
match(Set dst (ReplicateD (LoadD mem))); |
|
3337 |
format %{ "pshufd $dst,$mem,0x44\n\t" |
|
3338 |
"vinsertf128h $dst,$dst,$dst\t! replicate4D" %} |
|
3339 |
ins_encode %{ |
|
3340 |
__ pshufd($dst$$XMMRegister, $mem$$Address, 0x44); |
|
3341 |
__ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
3342 |
%} |
|
3343 |
ins_pipe( pipe_slow ); |
|
3344 |
%} |
|
3345 |
||
3346 |
// ====================GENERIC REPLICATE========================================== |
|
3347 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3348 |
// Replicate byte scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3349 |
instruct Repl4B(vecS dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3350 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3351 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3352 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3353 |
"punpcklbw $dst,$dst\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3354 |
"pshuflw $dst,$dst,0x00\t! replicate4B" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3355 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3356 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3357 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3358 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3359 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3360 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3361 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3362 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3363 |
instruct Repl8B(vecD dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3364 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3365 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3366 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3367 |
"punpcklbw $dst,$dst\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3368 |
"pshuflw $dst,$dst,0x00\t! replicate8B" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3369 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3370 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3371 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3372 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3373 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3374 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3375 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3376 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3377 |
// Replicate byte scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3378 |
instruct Repl4B_imm(vecS dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3379 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3380 |
match(Set dst (ReplicateB con)); |
13294 | 3381 |
format %{ "movdl $dst,[$constantaddress]\t! replicate4B($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3382 |
ins_encode %{ |
13294 | 3383 |
__ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3384 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3385 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3386 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3387 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3388 |
instruct Repl8B_imm(vecD dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3389 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3390 |
match(Set dst (ReplicateB con)); |
13294 | 3391 |
format %{ "movq $dst,[$constantaddress]\t! replicate8B($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3392 |
ins_encode %{ |
13294 | 3393 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3394 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3395 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3396 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3397 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3398 |
// Replicate byte scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3399 |
instruct Repl4B_zero(vecS dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3400 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3401 |
match(Set dst (ReplicateB zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3402 |
format %{ "pxor $dst,$dst\t! replicate4B zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3403 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3404 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3405 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3406 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3407 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3408 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3409 |
instruct Repl8B_zero(vecD dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3410 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3411 |
match(Set dst (ReplicateB zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3412 |
format %{ "pxor $dst,$dst\t! replicate8B zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3413 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3414 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3415 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3416 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3417 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3418 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3419 |
instruct Repl16B_zero(vecX dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3420 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3421 |
match(Set dst (ReplicateB zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3422 |
format %{ "pxor $dst,$dst\t! replicate16B zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3423 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3424 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3425 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3426 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3427 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3428 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3429 |
instruct Repl32B_zero(vecY dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3430 |
predicate(n->as_Vector()->length() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3431 |
match(Set dst (ReplicateB zero)); |
13294 | 3432 |
format %{ "vpxor $dst,$dst,$dst\t! replicate32B zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3433 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3434 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
30624 | 3435 |
int vector_len = 1; |
3436 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3437 |
%} |
|
3438 |
ins_pipe( fpu_reg_reg ); |
|
3439 |
%} |
|
3440 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3441 |
// Replicate char/short (2 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3442 |
instruct Repl2S(vecS dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3443 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3444 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3445 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3446 |
"pshuflw $dst,$dst,0x00\t! replicate2S" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3447 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3448 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3449 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3450 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3451 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3452 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3453 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3454 |
// Replicate char/short (2 byte) scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3455 |
instruct Repl2S_imm(vecS dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3456 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3457 |
match(Set dst (ReplicateS con)); |
13294 | 3458 |
format %{ "movdl $dst,[$constantaddress]\t! replicate2S($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3459 |
ins_encode %{ |
13294 | 3460 |
__ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3461 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3462 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3463 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3464 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3465 |
instruct Repl4S_imm(vecD dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3466 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3467 |
match(Set dst (ReplicateS con)); |
13294 | 3468 |
format %{ "movq $dst,[$constantaddress]\t! replicate4S($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3469 |
ins_encode %{ |
13294 | 3470 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3471 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3472 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3473 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3474 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3475 |
// Replicate char/short (2 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3476 |
instruct Repl2S_zero(vecS dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3477 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3478 |
match(Set dst (ReplicateS zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3479 |
format %{ "pxor $dst,$dst\t! replicate2S zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3480 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3481 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3482 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3483 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3484 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3485 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3486 |
instruct Repl4S_zero(vecD dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3487 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3488 |
match(Set dst (ReplicateS zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3489 |
format %{ "pxor $dst,$dst\t! replicate4S zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3490 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3491 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3492 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3493 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3494 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3495 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3496 |
instruct Repl8S_zero(vecX dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3497 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3498 |
match(Set dst (ReplicateS zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3499 |
format %{ "pxor $dst,$dst\t! replicate8S zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3500 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3501 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3502 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3503 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3504 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3505 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3506 |
instruct Repl16S_zero(vecY dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3507 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3508 |
match(Set dst (ReplicateS zero)); |
13294 | 3509 |
format %{ "vpxor $dst,$dst,$dst\t! replicate16S zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3510 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3511 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
30624 | 3512 |
int vector_len = 1; |
3513 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3514 |
%} |
|
3515 |
ins_pipe( fpu_reg_reg ); |
|
3516 |
%} |
|
3517 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3518 |
// Replicate integer (4 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3519 |
instruct Repl2I(vecD dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3520 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3521 |
match(Set dst (ReplicateI src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3522 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3523 |
"pshufd $dst,$dst,0x00\t! replicate2I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3524 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3525 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3526 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3527 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3528 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3529 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3530 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3531 |
// Integer could be loaded into xmm register directly from memory. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3532 |
instruct Repl2I_mem(vecD dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3533 |
predicate(n->as_Vector()->length() == 2); |
13294 | 3534 |
match(Set dst (ReplicateI (LoadI mem))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3535 |
format %{ "movd $dst,$mem\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3536 |
"pshufd $dst,$dst,0x00\t! replicate2I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3537 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3538 |
__ movdl($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3539 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3540 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3541 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3542 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3543 |
|
31410 | 3544 |
// Replicate integer (4 byte) scalar immediate to be vector by loading from const table. |
3545 |
instruct Repl2I_imm(vecD dst, immI con) %{ |
|
3546 |
predicate(n->as_Vector()->length() == 2); |
|
3547 |
match(Set dst (ReplicateI con)); |
|
3548 |
format %{ "movq $dst,[$constantaddress]\t! replicate2I($con)" %} |
|
3549 |
ins_encode %{ |
|
3550 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
|
3551 |
%} |
|
3552 |
ins_pipe( fpu_reg_reg ); |
|
30624 | 3553 |
%} |
3554 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3555 |
// Replicate integer (4 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3556 |
instruct Repl2I_zero(vecD dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3557 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3558 |
match(Set dst (ReplicateI zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3559 |
format %{ "pxor $dst,$dst\t! replicate2I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3560 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3561 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3562 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3563 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3564 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3565 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3566 |
instruct Repl4I_zero(vecX dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3567 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3568 |
match(Set dst (ReplicateI zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3569 |
format %{ "pxor $dst,$dst\t! replicate4I zero)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3570 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3571 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3572 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3573 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3574 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3575 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3576 |
instruct Repl8I_zero(vecY dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3577 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3578 |
match(Set dst (ReplicateI zero)); |
13294 | 3579 |
format %{ "vpxor $dst,$dst,$dst\t! replicate8I zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3580 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3581 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
30624 | 3582 |
int vector_len = 1; |
3583 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3584 |
%} |
|
3585 |
ins_pipe( fpu_reg_reg ); |
|
3586 |
%} |
|
3587 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3588 |
// Replicate long (8 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3589 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3590 |
instruct Repl2L(vecX dst, rRegL src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3591 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3592 |
match(Set dst (ReplicateL src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3593 |
format %{ "movdq $dst,$src\n\t" |
13294 | 3594 |
"punpcklqdq $dst,$dst\t! replicate2L" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3595 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3596 |
__ movdq($dst$$XMMRegister, $src$$Register); |
13294 | 3597 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3598 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3599 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3600 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3601 |
#else // _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3602 |
instruct Repl2L(vecX dst, eRegL src, regD tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3603 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3604 |
match(Set dst (ReplicateL src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3605 |
effect(TEMP dst, USE src, TEMP tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3606 |
format %{ "movdl $dst,$src.lo\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3607 |
"movdl $tmp,$src.hi\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3608 |
"punpckldq $dst,$tmp\n\t" |
13294 | 3609 |
"punpcklqdq $dst,$dst\t! replicate2L"%} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3610 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3611 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3612 |
__ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3613 |
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
13294 | 3614 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3615 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3616 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3617 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3618 |
#endif // _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3619 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3620 |
// Replicate long (8 byte) scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3621 |
instruct Repl2L_imm(vecX dst, immL con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3622 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3623 |
match(Set dst (ReplicateL con)); |
13294 | 3624 |
format %{ "movq $dst,[$constantaddress]\n\t" |
3625 |
"punpcklqdq $dst,$dst\t! replicate2L($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3626 |
ins_encode %{ |
13294 | 3627 |
__ movq($dst$$XMMRegister, $constantaddress($con)); |
3628 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3629 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3630 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3631 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3632 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3633 |
// Replicate long (8 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3634 |
instruct Repl2L_zero(vecX dst, immL0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3635 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3636 |
match(Set dst (ReplicateL zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3637 |
format %{ "pxor $dst,$dst\t! replicate2L zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3638 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3639 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3640 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3641 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3642 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3643 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3644 |
instruct Repl4L_zero(vecY dst, immL0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3645 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3646 |
match(Set dst (ReplicateL zero)); |
13294 | 3647 |
format %{ "vpxor $dst,$dst,$dst\t! replicate4L zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3648 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3649 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
30624 | 3650 |
int vector_len = 1; |
3651 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3652 |
%} |
|
3653 |
ins_pipe( fpu_reg_reg ); |
|
3654 |
%} |
|
3655 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3656 |
// Replicate float (4 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3657 |
instruct Repl2F(vecD dst, regF src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3658 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3659 |
match(Set dst (ReplicateF src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3660 |
format %{ "pshufd $dst,$dst,0x00\t! replicate2F" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3661 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3662 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3663 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3664 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3665 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3666 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3667 |
instruct Repl4F(vecX dst, regF src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3668 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3669 |
match(Set dst (ReplicateF src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3670 |
format %{ "pshufd $dst,$dst,0x00\t! replicate4F" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3671 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3672 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3673 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3674 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3675 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3676 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3677 |
// Replicate float (4 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3678 |
instruct Repl2F_zero(vecD dst, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3679 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3680 |
match(Set dst (ReplicateF zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3681 |
format %{ "xorps $dst,$dst\t! replicate2F zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3682 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3683 |
__ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3684 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3685 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3686 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3687 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3688 |
instruct Repl4F_zero(vecX dst, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3689 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3690 |
match(Set dst (ReplicateF zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3691 |
format %{ "xorps $dst,$dst\t! replicate4F zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3692 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3693 |
__ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3694 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3695 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3696 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3697 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3698 |
instruct Repl8F_zero(vecY dst, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3699 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3700 |
match(Set dst (ReplicateF zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3701 |
format %{ "vxorps $dst,$dst,$dst\t! replicate8F zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3702 |
ins_encode %{ |
30624 | 3703 |
int vector_len = 1; |
3704 |
__ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3705 |
%} |
|
3706 |
ins_pipe( fpu_reg_reg ); |
|
3707 |
%} |
|
3708 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3709 |
// Replicate double (8 bytes) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3710 |
instruct Repl2D(vecX dst, regD src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3711 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3712 |
match(Set dst (ReplicateD src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3713 |
format %{ "pshufd $dst,$src,0x44\t! replicate2D" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3714 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3715 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3716 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3717 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3718 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3719 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3720 |
// Replicate double (8 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3721 |
instruct Repl2D_zero(vecX dst, immD0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3722 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3723 |
match(Set dst (ReplicateD zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3724 |
format %{ "xorpd $dst,$dst\t! replicate2D zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3725 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3726 |
__ xorpd($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3727 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3728 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3729 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3730 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3731 |
instruct Repl4D_zero(vecY dst, immD0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3732 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3733 |
match(Set dst (ReplicateD zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3734 |
format %{ "vxorpd $dst,$dst,$dst,vect256\t! replicate4D zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
3735 |
ins_encode %{ |
30624 | 3736 |
int vector_len = 1; |
3737 |
__ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3738 |
%} |
|
3739 |
ins_pipe( fpu_reg_reg ); |
|
3740 |
%} |
|
3741 |
||
31410 | 3742 |
// ====================EVEX REPLICATE============================================= |
3743 |
||
3744 |
instruct Repl4B_mem_evex(vecS dst, memory mem) %{ |
|
3745 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vlbw()); |
|
3746 |
match(Set dst (ReplicateB (LoadB mem))); |
|
3747 |
format %{ "vpbroadcastb $dst,$mem\t! replicate4B" %} |
|
3748 |
ins_encode %{ |
|
3749 |
int vector_len = 0; |
|
3750 |
__ evpbroadcastb($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3751 |
%} |
|
3752 |
ins_pipe( pipe_slow ); |
|
3753 |
%} |
|
3754 |
||
3755 |
instruct Repl8B_mem_evex(vecD dst, memory mem) %{ |
|
3756 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vlbw()); |
|
3757 |
match(Set dst (ReplicateB (LoadB mem))); |
|
3758 |
format %{ "vpbroadcastb $dst,$mem\t! replicate8B" %} |
|
3759 |
ins_encode %{ |
|
3760 |
int vector_len = 0; |
|
3761 |
__ evpbroadcastb($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3762 |
%} |
|
3763 |
ins_pipe( pipe_slow ); |
|
3764 |
%} |
|
3765 |
||
3766 |
instruct Repl16B_evex(vecX dst, rRegI src) %{ |
|
3767 |
predicate(n->as_Vector()->length() == 16 && VM_Version::supports_avx512vlbw()); |
|
3768 |
match(Set dst (ReplicateB src)); |
|
3769 |
format %{ "vpbroadcastb $dst,$src\t! replicate16B" %} |
|
3770 |
ins_encode %{ |
|
3771 |
int vector_len = 0; |
|
3772 |
__ evpbroadcastb($dst$$XMMRegister, $src$$Register, vector_len); |
|
3773 |
%} |
|
3774 |
ins_pipe( pipe_slow ); |
|
3775 |
%} |
|
3776 |
||
3777 |
instruct Repl16B_mem_evex(vecX dst, memory mem) %{ |
|
3778 |
predicate(n->as_Vector()->length() == 16 && VM_Version::supports_avx512vlbw()); |
|
3779 |
match(Set dst (ReplicateB (LoadB mem))); |
|
3780 |
format %{ "vpbroadcastb $dst,$mem\t! replicate16B" %} |
|
3781 |
ins_encode %{ |
|
3782 |
int vector_len = 0; |
|
3783 |
__ evpbroadcastb($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3784 |
%} |
|
3785 |
ins_pipe( pipe_slow ); |
|
3786 |
%} |
|
3787 |
||
3788 |
instruct Repl32B_evex(vecY dst, rRegI src) %{ |
|
3789 |
predicate(n->as_Vector()->length() == 32 && VM_Version::supports_avx512vlbw()); |
|
3790 |
match(Set dst (ReplicateB src)); |
|
3791 |
format %{ "vpbroadcastb $dst,$src\t! replicate32B" %} |
|
3792 |
ins_encode %{ |
|
3793 |
int vector_len = 1; |
|
3794 |
__ evpbroadcastb($dst$$XMMRegister, $src$$Register, vector_len); |
|
3795 |
%} |
|
3796 |
ins_pipe( pipe_slow ); |
|
3797 |
%} |
|
3798 |
||
3799 |
instruct Repl32B_mem_evex(vecY dst, memory mem) %{ |
|
3800 |
predicate(n->as_Vector()->length() == 32 && VM_Version::supports_avx512vlbw()); |
|
3801 |
match(Set dst (ReplicateB (LoadB mem))); |
|
3802 |
format %{ "vpbroadcastb $dst,$mem\t! replicate32B" %} |
|
3803 |
ins_encode %{ |
|
3804 |
int vector_len = 1; |
|
3805 |
__ evpbroadcastb($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3806 |
%} |
|
3807 |
ins_pipe( pipe_slow ); |
|
3808 |
%} |
|
3809 |
||
3810 |
instruct Repl64B_evex(vecZ dst, rRegI src) %{ |
|
3811 |
predicate(n->as_Vector()->length() == 64 && UseAVX > 2); |
|
3812 |
match(Set dst (ReplicateB src)); |
|
3813 |
format %{ "vpbroadcastb $dst,$src\t! upper replicate64B" %} |
|
3814 |
ins_encode %{ |
|
3815 |
int vector_len = 2; |
|
3816 |
__ evpbroadcastb($dst$$XMMRegister, $src$$Register, vector_len); |
|
3817 |
%} |
|
3818 |
ins_pipe( pipe_slow ); |
|
3819 |
%} |
|
3820 |
||
3821 |
instruct Repl64B_mem_evex(vecZ dst, memory mem) %{ |
|
3822 |
predicate(n->as_Vector()->length() == 64 && VM_Version::supports_avx512vlbw()); |
|
3823 |
match(Set dst (ReplicateB (LoadB mem))); |
|
3824 |
format %{ "vpbroadcastb $dst,$mem\t! replicate64B" %} |
|
3825 |
ins_encode %{ |
|
3826 |
int vector_len = 2; |
|
3827 |
__ evpbroadcastb($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3828 |
%} |
|
3829 |
ins_pipe( pipe_slow ); |
|
3830 |
%} |
|
3831 |
||
3832 |
instruct Repl16B_imm_evex(vecX dst, immI con) %{ |
|
3833 |
predicate(n->as_Vector()->length() == 16 && VM_Version::supports_avx512vlbw()); |
|
3834 |
match(Set dst (ReplicateB con)); |
|
3835 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3836 |
"vpbroadcastb $dst,$dst\t! replicate16B" %} |
|
3837 |
ins_encode %{ |
|
3838 |
int vector_len = 0; |
|
3839 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
|
3840 |
__ evpbroadcastb($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3841 |
%} |
|
3842 |
ins_pipe( pipe_slow ); |
|
3843 |
%} |
|
3844 |
||
3845 |
instruct Repl32B_imm_evex(vecY dst, immI con) %{ |
|
3846 |
predicate(n->as_Vector()->length() == 32 && VM_Version::supports_avx512vlbw()); |
|
3847 |
match(Set dst (ReplicateB con)); |
|
3848 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3849 |
"vpbroadcastb $dst,$dst\t! replicate32B" %} |
|
3850 |
ins_encode %{ |
|
3851 |
int vector_len = 1; |
|
3852 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
|
3853 |
__ evpbroadcastb($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3854 |
%} |
|
3855 |
ins_pipe( pipe_slow ); |
|
3856 |
%} |
|
3857 |
||
3858 |
instruct Repl64B_imm_evex(vecZ dst, immI con) %{ |
|
3859 |
predicate(n->as_Vector()->length() == 64 && UseAVX > 2); |
|
3860 |
match(Set dst (ReplicateB con)); |
|
3861 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3862 |
"vpbroadcastb $dst,$dst\t! upper replicate64B" %} |
|
3863 |
ins_encode %{ |
|
3864 |
int vector_len = 2; |
|
3865 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
|
3866 |
__ evpbroadcastb($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3867 |
%} |
|
3868 |
ins_pipe( pipe_slow ); |
|
3869 |
%} |
|
3870 |
||
3871 |
instruct Repl64B_zero_evex(vecZ dst, immI0 zero) %{ |
|
3872 |
predicate(n->as_Vector()->length() == 64 && UseAVX > 2); |
|
3873 |
match(Set dst (ReplicateB zero)); |
|
3874 |
format %{ "vpxor $dst k0,$dst,$dst\t! replicate64B zero" %} |
|
3875 |
ins_encode %{ |
|
3876 |
// Use vxorpd since AVX does not have vpxor for 512-bit (EVEX will have it). |
|
3877 |
int vector_len = 2; |
|
3878 |
__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3879 |
%} |
|
3880 |
ins_pipe( fpu_reg_reg ); |
|
3881 |
%} |
|
3882 |
||
3883 |
instruct Repl4S_evex(vecD dst, rRegI src) %{ |
|
3884 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vlbw()); |
|
3885 |
match(Set dst (ReplicateS src)); |
|
3886 |
format %{ "vpbroadcastw $dst,$src\t! replicate4S" %} |
|
3887 |
ins_encode %{ |
|
3888 |
int vector_len = 0; |
|
3889 |
__ evpbroadcastw($dst$$XMMRegister, $src$$Register, vector_len); |
|
3890 |
%} |
|
3891 |
ins_pipe( pipe_slow ); |
|
3892 |
%} |
|
3893 |
||
3894 |
instruct Repl4S_mem_evex(vecD dst, memory mem) %{ |
|
3895 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vlbw()); |
|
3896 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3897 |
format %{ "vpbroadcastw $dst,$mem\t! replicate4S" %} |
|
3898 |
ins_encode %{ |
|
3899 |
int vector_len = 0; |
|
3900 |
__ evpbroadcastw($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3901 |
%} |
|
3902 |
ins_pipe( pipe_slow ); |
|
3903 |
%} |
|
3904 |
||
3905 |
instruct Repl8S_evex(vecX dst, rRegI src) %{ |
|
3906 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vlbw()); |
|
3907 |
match(Set dst (ReplicateS src)); |
|
3908 |
format %{ "vpbroadcastw $dst,$src\t! replicate8S" %} |
|
3909 |
ins_encode %{ |
|
3910 |
int vector_len = 0; |
|
3911 |
__ evpbroadcastw($dst$$XMMRegister, $src$$Register, vector_len); |
|
3912 |
%} |
|
3913 |
ins_pipe( pipe_slow ); |
|
3914 |
%} |
|
3915 |
||
3916 |
instruct Repl8S_mem_evex(vecX dst, memory mem) %{ |
|
3917 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vlbw()); |
|
3918 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3919 |
format %{ "vpbroadcastw $dst,$mem\t! replicate8S" %} |
|
3920 |
ins_encode %{ |
|
3921 |
int vector_len = 0; |
|
3922 |
__ evpbroadcastw($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3923 |
%} |
|
3924 |
ins_pipe( pipe_slow ); |
|
3925 |
%} |
|
3926 |
||
3927 |
instruct Repl16S_evex(vecY dst, rRegI src) %{ |
|
3928 |
predicate(n->as_Vector()->length() == 16 && VM_Version::supports_avx512vlbw()); |
|
3929 |
match(Set dst (ReplicateS src)); |
|
3930 |
format %{ "vpbroadcastw $dst,$src\t! replicate16S" %} |
|
3931 |
ins_encode %{ |
|
3932 |
int vector_len = 1; |
|
3933 |
__ evpbroadcastw($dst$$XMMRegister, $src$$Register, vector_len); |
|
3934 |
%} |
|
3935 |
ins_pipe( pipe_slow ); |
|
3936 |
%} |
|
3937 |
||
3938 |
instruct Repl16S_mem_evex(vecY dst, memory mem) %{ |
|
3939 |
predicate(n->as_Vector()->length() == 16 && VM_Version::supports_avx512vlbw()); |
|
3940 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3941 |
format %{ "vpbroadcastw $dst,$mem\t! replicate16S" %} |
|
3942 |
ins_encode %{ |
|
3943 |
int vector_len = 1; |
|
3944 |
__ evpbroadcastw($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3945 |
%} |
|
3946 |
ins_pipe( pipe_slow ); |
|
3947 |
%} |
|
3948 |
||
3949 |
instruct Repl32S_evex(vecZ dst, rRegI src) %{ |
|
3950 |
predicate(n->as_Vector()->length() == 32 && UseAVX > 2); |
|
3951 |
match(Set dst (ReplicateS src)); |
|
3952 |
format %{ "vpbroadcastw $dst,$src\t! replicate32S" %} |
|
3953 |
ins_encode %{ |
|
3954 |
int vector_len = 2; |
|
3955 |
__ evpbroadcastw($dst$$XMMRegister, $src$$Register, vector_len); |
|
3956 |
%} |
|
3957 |
ins_pipe( pipe_slow ); |
|
3958 |
%} |
|
3959 |
||
3960 |
instruct Repl32S_mem_evex(vecZ dst, memory mem) %{ |
|
3961 |
predicate(n->as_Vector()->length() == 32 && UseAVX > 2); |
|
3962 |
match(Set dst (ReplicateS (LoadS mem))); |
|
3963 |
format %{ "vpbroadcastw $dst,$mem\t! replicate32S" %} |
|
3964 |
ins_encode %{ |
|
3965 |
int vector_len = 2; |
|
3966 |
__ evpbroadcastw($dst$$XMMRegister, $mem$$Address, vector_len); |
|
3967 |
%} |
|
3968 |
ins_pipe( pipe_slow ); |
|
3969 |
%} |
|
3970 |
||
3971 |
instruct Repl8S_imm_evex(vecX dst, immI con) %{ |
|
3972 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vlbw()); |
|
3973 |
match(Set dst (ReplicateS con)); |
|
3974 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3975 |
"vpbroadcastw $dst,$dst\t! replicate8S" %} |
|
3976 |
ins_encode %{ |
|
3977 |
int vector_len = 0; |
|
3978 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
|
3979 |
__ evpbroadcastw($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3980 |
%} |
|
3981 |
ins_pipe( pipe_slow ); |
|
3982 |
%} |
|
3983 |
||
3984 |
instruct Repl16S_imm_evex(vecY dst, immI con) %{ |
|
3985 |
predicate(n->as_Vector()->length() == 16 && VM_Version::supports_avx512vlbw()); |
|
3986 |
match(Set dst (ReplicateS con)); |
|
3987 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
3988 |
"vpbroadcastw $dst,$dst\t! replicate16S" %} |
|
3989 |
ins_encode %{ |
|
3990 |
int vector_len = 1; |
|
3991 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
|
3992 |
__ evpbroadcastw($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
3993 |
%} |
|
3994 |
ins_pipe( pipe_slow ); |
|
3995 |
%} |
|
3996 |
||
3997 |
instruct Repl32S_imm_evex(vecZ dst, immI con) %{ |
|
3998 |
predicate(n->as_Vector()->length() == 32 && UseAVX > 2); |
|
3999 |
match(Set dst (ReplicateS con)); |
|
4000 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
4001 |
"vpbroadcastw $dst,$dst\t! replicate32S" %} |
|
4002 |
ins_encode %{ |
|
4003 |
int vector_len = 2; |
|
4004 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
|
4005 |
__ evpbroadcastw($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4006 |
%} |
|
4007 |
ins_pipe( pipe_slow ); |
|
4008 |
%} |
|
4009 |
||
4010 |
instruct Repl32S_zero_evex(vecZ dst, immI0 zero) %{ |
|
4011 |
predicate(n->as_Vector()->length() == 32 && UseAVX > 2); |
|
4012 |
match(Set dst (ReplicateS zero)); |
|
4013 |
format %{ "vpxor $dst k0,$dst,$dst\t! replicate32S zero" %} |
|
4014 |
ins_encode %{ |
|
4015 |
// Use vxorpd since AVX does not have vpxor for 512-bit (EVEX will have it). |
|
4016 |
int vector_len = 2; |
|
4017 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4018 |
%} |
|
4019 |
ins_pipe( fpu_reg_reg ); |
|
4020 |
%} |
|
4021 |
||
4022 |
instruct Repl4I_evex(vecX dst, rRegI src) %{ |
|
4023 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4024 |
match(Set dst (ReplicateI src)); |
|
4025 |
format %{ "vpbroadcastd $dst,$src\t! replicate4I" %} |
|
4026 |
ins_encode %{ |
|
4027 |
int vector_len = 0; |
|
4028 |
__ evpbroadcastd($dst$$XMMRegister, $src$$Register, vector_len); |
|
4029 |
%} |
|
4030 |
ins_pipe( pipe_slow ); |
|
4031 |
%} |
|
4032 |
||
4033 |
instruct Repl4I_mem_evex(vecX dst, memory mem) %{ |
|
4034 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4035 |
match(Set dst (ReplicateI (LoadI mem))); |
|
4036 |
format %{ "vpbroadcastd $dst,$mem\t! replicate4I" %} |
|
4037 |
ins_encode %{ |
|
4038 |
int vector_len = 0; |
|
4039 |
__ evpbroadcastd($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4040 |
%} |
|
4041 |
ins_pipe( pipe_slow ); |
|
4042 |
%} |
|
4043 |
||
4044 |
instruct Repl8I_evex(vecY dst, rRegI src) %{ |
|
4045 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vl()); |
|
4046 |
match(Set dst (ReplicateI src)); |
|
4047 |
format %{ "vpbroadcastd $dst,$src\t! replicate8I" %} |
|
4048 |
ins_encode %{ |
|
4049 |
int vector_len = 1; |
|
4050 |
__ evpbroadcastd($dst$$XMMRegister, $src$$Register, vector_len); |
|
4051 |
%} |
|
4052 |
ins_pipe( pipe_slow ); |
|
4053 |
%} |
|
4054 |
||
4055 |
instruct Repl8I_mem_evex(vecY dst, memory mem) %{ |
|
4056 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vl()); |
|
4057 |
match(Set dst (ReplicateI (LoadI mem))); |
|
4058 |
format %{ "vpbroadcastd $dst,$mem\t! replicate8I" %} |
|
4059 |
ins_encode %{ |
|
4060 |
int vector_len = 1; |
|
4061 |
__ evpbroadcastd($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4062 |
%} |
|
4063 |
ins_pipe( pipe_slow ); |
|
4064 |
%} |
|
4065 |
||
4066 |
instruct Repl16I_evex(vecZ dst, rRegI src) %{ |
|
4067 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4068 |
match(Set dst (ReplicateI src)); |
|
4069 |
format %{ "vpbroadcastd $dst,$src\t! replicate16I" %} |
|
4070 |
ins_encode %{ |
|
4071 |
int vector_len = 2; |
|
4072 |
__ evpbroadcastd($dst$$XMMRegister, $src$$Register, vector_len); |
|
4073 |
%} |
|
4074 |
ins_pipe( pipe_slow ); |
|
4075 |
%} |
|
4076 |
||
4077 |
instruct Repl16I_mem_evex(vecZ dst, memory mem) %{ |
|
4078 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4079 |
match(Set dst (ReplicateI (LoadI mem))); |
|
4080 |
format %{ "vpbroadcastd $dst,$mem\t! replicate16I" %} |
|
4081 |
ins_encode %{ |
|
4082 |
int vector_len = 2; |
|
4083 |
__ evpbroadcastd($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4084 |
%} |
|
4085 |
ins_pipe( pipe_slow ); |
|
4086 |
%} |
|
4087 |
||
4088 |
instruct Repl4I_imm_evex(vecX dst, immI con) %{ |
|
4089 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4090 |
match(Set dst (ReplicateI con)); |
|
4091 |
format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t" |
|
4092 |
"vpbroadcastd $dst,$dst\t! replicate4I" %} |
|
4093 |
ins_encode %{ |
|
4094 |
int vector_len = 0; |
|
4095 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
|
4096 |
__ evpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4097 |
%} |
|
4098 |
ins_pipe( pipe_slow ); |
|
4099 |
%} |
|
4100 |
||
4101 |
instruct Repl8I_imm_evex(vecY dst, immI con) %{ |
|
4102 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vl()); |
|
4103 |
match(Set dst (ReplicateI con)); |
|
4104 |
format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t" |
|
4105 |
"vpbroadcastd $dst,$dst\t! replicate8I" %} |
|
4106 |
ins_encode %{ |
|
4107 |
int vector_len = 1; |
|
4108 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
|
4109 |
__ evpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4110 |
%} |
|
4111 |
ins_pipe( pipe_slow ); |
|
4112 |
%} |
|
4113 |
||
4114 |
instruct Repl16I_imm_evex(vecZ dst, immI con) %{ |
|
4115 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4116 |
match(Set dst (ReplicateI con)); |
|
4117 |
format %{ "movq $dst,[$constantaddress]\t! replicate16I($con)\n\t" |
|
4118 |
"vpbroadcastd $dst,$dst\t! replicate16I" %} |
|
4119 |
ins_encode %{ |
|
4120 |
int vector_len = 2; |
|
4121 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
|
4122 |
__ evpbroadcastd($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4123 |
%} |
|
4124 |
ins_pipe( pipe_slow ); |
|
4125 |
%} |
|
4126 |
||
4127 |
instruct Repl16I_zero_evex(vecZ dst, immI0 zero) %{ |
|
4128 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4129 |
match(Set dst (ReplicateI zero)); |
|
4130 |
format %{ "vpxor $dst k0,$dst,$dst\t! replicate16I zero" %} |
|
4131 |
ins_encode %{ |
|
4132 |
// Use vxorpd since AVX does not have vpxor for 512-bit (AVX2 will have it). |
|
4133 |
int vector_len = 2; |
|
4134 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4135 |
%} |
|
4136 |
ins_pipe( fpu_reg_reg ); |
|
4137 |
%} |
|
4138 |
||
4139 |
// Replicate long (8 byte) scalar to be vector |
|
4140 |
#ifdef _LP64 |
|
4141 |
instruct Repl4L_evex(vecY dst, rRegL src) %{ |
|
4142 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4143 |
match(Set dst (ReplicateL src)); |
|
4144 |
format %{ "vpbroadcastq $dst,$src\t! replicate4L" %} |
|
4145 |
ins_encode %{ |
|
4146 |
int vector_len = 1; |
|
4147 |
__ evpbroadcastq($dst$$XMMRegister, $src$$Register, vector_len); |
|
4148 |
%} |
|
4149 |
ins_pipe( pipe_slow ); |
|
4150 |
%} |
|
4151 |
||
4152 |
instruct Repl8L_evex(vecZ dst, rRegL src) %{ |
|
4153 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4154 |
match(Set dst (ReplicateL src)); |
|
4155 |
format %{ "vpbroadcastq $dst,$src\t! replicate8L" %} |
|
4156 |
ins_encode %{ |
|
4157 |
int vector_len = 2; |
|
4158 |
__ evpbroadcastq($dst$$XMMRegister, $src$$Register, vector_len); |
|
4159 |
%} |
|
4160 |
ins_pipe( pipe_slow ); |
|
4161 |
%} |
|
4162 |
#else // _LP64 |
|
4163 |
instruct Repl4L_evex(vecY dst, eRegL src, regD tmp) %{ |
|
4164 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4165 |
match(Set dst (ReplicateL src)); |
|
4166 |
effect(TEMP dst, USE src, TEMP tmp); |
|
4167 |
format %{ "movdl $dst,$src.lo\n\t" |
|
4168 |
"movdl $tmp,$src.hi\n\t" |
|
4169 |
"punpckldq $dst,$tmp\n\t" |
|
4170 |
"vpbroadcastq $dst,$dst\t! replicate4L" %} |
|
4171 |
ins_encode %{ |
|
4172 |
int vector_len = 1; |
|
4173 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
4174 |
__ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
|
4175 |
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
|
4176 |
__ evpbroadcastq($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4177 |
%} |
|
4178 |
ins_pipe( pipe_slow ); |
|
4179 |
%} |
|
4180 |
||
4181 |
instruct Repl8L_evex(vecZ dst, eRegL src, regD tmp) %{ |
|
4182 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4183 |
match(Set dst (ReplicateL src)); |
|
4184 |
effect(TEMP dst, USE src, TEMP tmp); |
|
4185 |
format %{ "movdl $dst,$src.lo\n\t" |
|
4186 |
"movdl $tmp,$src.hi\n\t" |
|
4187 |
"punpckldq $dst,$tmp\n\t" |
|
4188 |
"vpbroadcastq $dst,$dst\t! replicate8L" %} |
|
4189 |
ins_encode %{ |
|
4190 |
int vector_len = 2; |
|
4191 |
__ movdl($dst$$XMMRegister, $src$$Register); |
|
4192 |
__ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
|
4193 |
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
|
4194 |
__ evpbroadcastq($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4195 |
%} |
|
4196 |
ins_pipe( pipe_slow ); |
|
4197 |
%} |
|
4198 |
#endif // _LP64 |
|
4199 |
||
4200 |
instruct Repl4L_imm_evex(vecY dst, immL con) %{ |
|
4201 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4202 |
match(Set dst (ReplicateL con)); |
|
4203 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
4204 |
"vpbroadcastq $dst,$dst\t! replicate4L" %} |
|
4205 |
ins_encode %{ |
|
4206 |
int vector_len = 1; |
|
4207 |
__ movq($dst$$XMMRegister, $constantaddress($con)); |
|
4208 |
__ evpbroadcastq($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4209 |
%} |
|
4210 |
ins_pipe( pipe_slow ); |
|
4211 |
%} |
|
4212 |
||
4213 |
instruct Repl8L_imm_evex(vecZ dst, immL con) %{ |
|
4214 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4215 |
match(Set dst (ReplicateL con)); |
|
4216 |
format %{ "movq $dst,[$constantaddress]\n\t" |
|
4217 |
"vpbroadcastq $dst,$dst\t! replicate8L" %} |
|
4218 |
ins_encode %{ |
|
4219 |
int vector_len = 2; |
|
4220 |
__ movq($dst$$XMMRegister, $constantaddress($con)); |
|
4221 |
__ evpbroadcastq($dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4222 |
%} |
|
4223 |
ins_pipe( pipe_slow ); |
|
4224 |
%} |
|
4225 |
||
4226 |
instruct Repl2L_mem_evex(vecX dst, memory mem) %{ |
|
4227 |
predicate(n->as_Vector()->length() == 2 && VM_Version::supports_avx512vl()); |
|
4228 |
match(Set dst (ReplicateL (LoadL mem))); |
|
4229 |
format %{ "vpbroadcastd $dst,$mem\t! replicate2L" %} |
|
4230 |
ins_encode %{ |
|
4231 |
int vector_len = 0; |
|
4232 |
__ evpbroadcastq($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4233 |
%} |
|
4234 |
ins_pipe( pipe_slow ); |
|
4235 |
%} |
|
4236 |
||
4237 |
instruct Repl4L_mem_evex(vecY dst, memory mem) %{ |
|
4238 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4239 |
match(Set dst (ReplicateL (LoadL mem))); |
|
4240 |
format %{ "vpbroadcastd $dst,$mem\t! replicate4L" %} |
|
4241 |
ins_encode %{ |
|
4242 |
int vector_len = 1; |
|
4243 |
__ evpbroadcastq($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4244 |
%} |
|
4245 |
ins_pipe( pipe_slow ); |
|
4246 |
%} |
|
4247 |
||
4248 |
instruct Repl8L_mem_evex(vecZ dst, memory mem) %{ |
|
4249 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4250 |
match(Set dst (ReplicateL (LoadL mem))); |
|
4251 |
format %{ "vpbroadcastd $dst,$mem\t! replicate8L" %} |
|
4252 |
ins_encode %{ |
|
4253 |
int vector_len = 2; |
|
4254 |
__ evpbroadcastq($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4255 |
%} |
|
4256 |
ins_pipe( pipe_slow ); |
|
4257 |
%} |
|
4258 |
||
4259 |
instruct Repl8L_zero_evex(vecZ dst, immL0 zero) %{ |
|
4260 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4261 |
match(Set dst (ReplicateL zero)); |
|
4262 |
format %{ "vpxor $dst k0,$dst,$dst\t! replicate8L zero" %} |
|
4263 |
ins_encode %{ |
|
4264 |
// Use vxorpd since AVX does not have vpxor for 512-bit (EVEX will have it). |
|
4265 |
int vector_len = 2; |
|
4266 |
__ vpxor($dst$$XMMRegister,$dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4267 |
%} |
|
4268 |
ins_pipe( fpu_reg_reg ); |
|
4269 |
%} |
|
4270 |
||
4271 |
instruct Repl8F_evex(vecY dst, regF src) %{ |
|
4272 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vl()); |
|
4273 |
match(Set dst (ReplicateF src)); |
|
4274 |
format %{ "vbroadcastss $dst,$src\t! replicate8F" %} |
|
4275 |
ins_encode %{ |
|
4276 |
int vector_len = 1; |
|
4277 |
__ evpbroadcastss($dst$$XMMRegister, $src$$XMMRegister, vector_len); |
|
4278 |
%} |
|
4279 |
ins_pipe( pipe_slow ); |
|
4280 |
%} |
|
4281 |
||
4282 |
instruct Repl8F_mem_evex(vecY dst, memory mem) %{ |
|
4283 |
predicate(n->as_Vector()->length() == 8 && VM_Version::supports_avx512vl()); |
|
4284 |
match(Set dst (ReplicateF (LoadF mem))); |
|
4285 |
format %{ "vbroadcastss $dst,$mem\t! replicate8F" %} |
|
4286 |
ins_encode %{ |
|
4287 |
int vector_len = 1; |
|
4288 |
__ evpbroadcastss($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4289 |
%} |
|
4290 |
ins_pipe( pipe_slow ); |
|
4291 |
%} |
|
4292 |
||
4293 |
instruct Repl16F_evex(vecZ dst, regF src) %{ |
|
4294 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4295 |
match(Set dst (ReplicateF src)); |
|
4296 |
format %{ "vbroadcastss $dst,$src\t! replicate16F" %} |
|
4297 |
ins_encode %{ |
|
4298 |
int vector_len = 2; |
|
4299 |
__ evpbroadcastss($dst$$XMMRegister, $src$$XMMRegister, vector_len); |
|
4300 |
%} |
|
4301 |
ins_pipe( pipe_slow ); |
|
4302 |
%} |
|
4303 |
||
4304 |
instruct Repl16F_mem_evex(vecZ dst, memory mem) %{ |
|
4305 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4306 |
match(Set dst (ReplicateF (LoadF mem))); |
|
4307 |
format %{ "vbroadcastss $dst,$mem\t! replicate16F" %} |
|
4308 |
ins_encode %{ |
|
4309 |
int vector_len = 2; |
|
4310 |
__ evpbroadcastss($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4311 |
%} |
|
4312 |
ins_pipe( pipe_slow ); |
|
4313 |
%} |
|
4314 |
||
4315 |
instruct Repl16F_zero_evex(vecZ dst, immF0 zero) %{ |
|
4316 |
predicate(n->as_Vector()->length() == 16 && UseAVX > 2); |
|
4317 |
match(Set dst (ReplicateF zero)); |
|
4318 |
format %{ "vxorps $dst k0,$dst,$dst\t! replicate16F zero" %} |
|
4319 |
ins_encode %{ |
|
4320 |
int vector_len = 2; |
|
4321 |
__ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
4322 |
%} |
|
4323 |
ins_pipe( fpu_reg_reg ); |
|
4324 |
%} |
|
4325 |
||
4326 |
instruct Repl4D_evex(vecY dst, regD src) %{ |
|
4327 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4328 |
match(Set dst (ReplicateD src)); |
|
4329 |
format %{ "vbroadcastsd $dst,$src\t! replicate4D" %} |
|
4330 |
ins_encode %{ |
|
4331 |
int vector_len = 1; |
|
4332 |
__ evpbroadcastsd($dst$$XMMRegister, $src$$XMMRegister, vector_len); |
|
4333 |
%} |
|
4334 |
ins_pipe( pipe_slow ); |
|
4335 |
%} |
|
4336 |
||
4337 |
instruct Repl4D_mem_evex(vecY dst, memory mem) %{ |
|
4338 |
predicate(n->as_Vector()->length() == 4 && VM_Version::supports_avx512vl()); |
|
4339 |
match(Set dst (ReplicateD (LoadD mem))); |
|
4340 |
format %{ "vbroadcastsd $dst,$mem\t! replicate4D" %} |
|
4341 |
ins_encode %{ |
|
4342 |
int vector_len = 1; |
|
4343 |
__ evpbroadcastsd($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4344 |
%} |
|
4345 |
ins_pipe( pipe_slow ); |
|
4346 |
%} |
|
4347 |
||
4348 |
instruct Repl8D_evex(vecZ dst, regD src) %{ |
|
4349 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4350 |
match(Set dst (ReplicateD src)); |
|
4351 |
format %{ "vbroadcastsd $dst,$src\t! replicate8D" %} |
|
4352 |
ins_encode %{ |
|
4353 |
int vector_len = 2; |
|
4354 |
__ evpbroadcastsd($dst$$XMMRegister, $src$$XMMRegister, vector_len); |
|
4355 |
%} |
|
4356 |
ins_pipe( pipe_slow ); |
|
4357 |
%} |
|
4358 |
||
4359 |
instruct Repl8D_mem_evex(vecZ dst, memory mem) %{ |
|
4360 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
4361 |
match(Set dst (ReplicateD (LoadD mem))); |
|
4362 |
format %{ "vbroadcastsd $dst,$mem\t! replicate8D" %} |
|
4363 |
ins_encode %{ |
|
4364 |
int vector_len = 2; |
|
4365 |
__ evpbroadcastsd($dst$$XMMRegister, $mem$$Address, vector_len); |
|
4366 |
%} |
|
4367 |
ins_pipe( pipe_slow ); |
|
4368 |
%} |
|
4369 |
||
4370 |
instruct Repl8D_zero_evex(vecZ dst, immD0 zero) %{ |
|
4371 |
predicate(n->as_Vector()->length() == 8 && UseAVX > 2); |
|
30624 | 4372 |
match(Set dst (ReplicateD zero)); |
4373 |
format %{ "vxorpd $dst k0,$dst,$dst,vect512\t! replicate8D zero" %} |
|
4374 |
ins_encode %{ |
|
4375 |
int vector_len = 2; |
|
4376 |
__ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector_len); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
4377 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
4378 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
4379 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
4380 |
|
30211 | 4381 |
// ====================REDUCTION ARITHMETIC======================================= |
4382 |
||
4383 |
instruct rsadd2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
4384 |
predicate(UseSSE > 2 && UseAVX == 0); |
|
4385 |
match(Set dst (AddReductionVI src1 src2)); |
|
4386 |
effect(TEMP tmp2, TEMP tmp); |
|
4387 |
format %{ "movdqu $tmp2,$src2\n\t" |
|
4388 |
"phaddd $tmp2,$tmp2\n\t" |
|
4389 |
"movd $tmp,$src1\n\t" |
|
4390 |
"paddd $tmp,$tmp2\n\t" |
|
4391 |
"movd $dst,$tmp\t! add reduction2I" %} |
|
4392 |
ins_encode %{ |
|
4393 |
__ movdqu($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
4394 |
__ phaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister); |
|
4395 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
4396 |
__ paddd($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4397 |
__ movdl($dst$$Register, $tmp$$XMMRegister); |
|
4398 |
%} |
|
4399 |
ins_pipe( pipe_slow ); |
|
4400 |
%} |
|
4401 |
||
4402 |
instruct rvadd2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
30624 | 4403 |
predicate(UseAVX > 0 && UseAVX < 3); |
30211 | 4404 |
match(Set dst (AddReductionVI src1 src2)); |
4405 |
effect(TEMP tmp, TEMP tmp2); |
|
30624 | 4406 |
format %{ "vphaddd $tmp,$src2,$src2\n\t" |
4407 |
"movd $tmp2,$src1\n\t" |
|
4408 |
"vpaddd $tmp2,$tmp2,$tmp\n\t" |
|
4409 |
"movd $dst,$tmp2\t! add reduction2I" %} |
|
4410 |
ins_encode %{ |
|
4411 |
int vector_len = 0; |
|
4412 |
__ vphaddd($tmp$$XMMRegister, $src2$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
4413 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
4414 |
__ vpaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, vector_len); |
|
4415 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
4416 |
%} |
|
4417 |
ins_pipe( pipe_slow ); |
|
4418 |
%} |
|
4419 |
||
4420 |
instruct rvadd2I_reduction_reg_evex(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
4421 |
predicate(UseAVX > 2); |
|
4422 |
match(Set dst (AddReductionVI src1 src2)); |
|
4423 |
effect(TEMP tmp, TEMP tmp2); |
|
4424 |
format %{ "pshufd $tmp2,$src2,0x1\n\t" |
|
4425 |
"vpaddd $tmp,$src2,$tmp2\n\t" |
|
30211 | 4426 |
"movd $tmp2,$src1\n\t" |
30624 | 4427 |
"vpaddd $tmp2,$tmp,$tmp2\n\t" |
30211 | 4428 |
"movd $dst,$tmp2\t! add reduction2I" %} |
4429 |
ins_encode %{ |
|
30624 | 4430 |
int vector_len = 0; |
4431 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
4432 |
__ vpaddd($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
30211 | 4433 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
30624 | 4434 |
__ vpaddd($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 4435 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
4436 |
%} |
|
4437 |
ins_pipe( pipe_slow ); |
|
4438 |
%} |
|
4439 |
||
4440 |
instruct rsadd4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
4441 |
predicate(UseSSE > 2 && UseAVX == 0); |
|
4442 |
match(Set dst (AddReductionVI src1 src2)); |
|
4443 |
effect(TEMP tmp2, TEMP tmp); |
|
4444 |
format %{ "movdqu $tmp2,$src2\n\t" |
|
4445 |
"phaddd $tmp2,$tmp2\n\t" |
|
4446 |
"phaddd $tmp2,$tmp2\n\t" |
|
4447 |
"movd $tmp,$src1\n\t" |
|
4448 |
"paddd $tmp,$tmp2\n\t" |
|
4449 |
"movd $dst,$tmp\t! add reduction4I" %} |
|
4450 |
ins_encode %{ |
|
4451 |
__ movdqu($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
4452 |
__ phaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister); |
|
4453 |
__ phaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister); |
|
4454 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
4455 |
__ paddd($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4456 |
__ movdl($dst$$Register, $tmp$$XMMRegister); |
|
4457 |
%} |
|
4458 |
ins_pipe( pipe_slow ); |
|
4459 |
%} |
|
4460 |
||
4461 |
instruct rvadd4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
30624 | 4462 |
predicate(UseAVX > 0 && UseAVX < 3); |
30211 | 4463 |
match(Set dst (AddReductionVI src1 src2)); |
4464 |
effect(TEMP tmp, TEMP tmp2); |
|
30624 | 4465 |
format %{ "vphaddd $tmp,$src2,$src2\n\t" |
4466 |
"vphaddd $tmp,$tmp,$tmp2\n\t" |
|
4467 |
"movd $tmp2,$src1\n\t" |
|
4468 |
"vpaddd $tmp2,$tmp2,$tmp\n\t" |
|
4469 |
"movd $dst,$tmp2\t! add reduction4I" %} |
|
4470 |
ins_encode %{ |
|
4471 |
int vector_len = 0; |
|
4472 |
__ vphaddd($tmp$$XMMRegister, $src2$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
4473 |
__ vphaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
4474 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
4475 |
__ vpaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, vector_len); |
|
4476 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
4477 |
%} |
|
4478 |
ins_pipe( pipe_slow ); |
|
4479 |
%} |
|
4480 |
||
4481 |
instruct rvadd4I_reduction_reg_evex(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
4482 |
predicate(UseAVX > 2); |
|
4483 |
match(Set dst (AddReductionVI src1 src2)); |
|
4484 |
effect(TEMP tmp, TEMP tmp2); |
|
4485 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
|
4486 |
"vpaddd $tmp,$src2,$tmp2\n\t" |
|
4487 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
4488 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
|
30211 | 4489 |
"movd $tmp2,$src1\n\t" |
30624 | 4490 |
"vpaddd $tmp2,$tmp,$tmp2\n\t" |
30211 | 4491 |
"movd $dst,$tmp2\t! add reduction4I" %} |
4492 |
ins_encode %{ |
|
30624 | 4493 |
int vector_len = 0; |
4494 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4495 |
__ vpaddd($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
4496 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
|
4497 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
30211 | 4498 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
30624 | 4499 |
__ vpaddd($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 4500 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
4501 |
%} |
|
4502 |
ins_pipe( pipe_slow ); |
|
4503 |
%} |
|
4504 |
||
4505 |
instruct rvadd8I_reduction_reg(rRegI dst, rRegI src1, vecY src2, regF tmp, regF tmp2) %{ |
|
30624 | 4506 |
predicate(UseAVX > 0 && UseAVX < 3); |
4507 |
match(Set dst (AddReductionVI src1 src2)); |
|
4508 |
effect(TEMP tmp, TEMP tmp2); |
|
4509 |
format %{ "vphaddd $tmp,$src2,$src2\n\t" |
|
4510 |
"vphaddd $tmp,$tmp,$tmp2\n\t" |
|
4511 |
"vextracti128 $tmp2,$tmp\n\t" |
|
4512 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
|
4513 |
"movd $tmp2,$src1\n\t" |
|
4514 |
"vpaddd $tmp2,$tmp2,$tmp\n\t" |
|
4515 |
"movd $dst,$tmp2\t! add reduction8I" %} |
|
4516 |
ins_encode %{ |
|
4517 |
int vector_len = 1; |
|
4518 |
__ vphaddd($tmp$$XMMRegister, $src2$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
4519 |
__ vphaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
4520 |
__ vextracti128h($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4521 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
4522 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
4523 |
__ vpaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
4524 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
4525 |
%} |
|
4526 |
ins_pipe( pipe_slow ); |
|
4527 |
%} |
|
4528 |
||
4529 |
instruct rvadd8I_reduction_reg_evex(rRegI dst, rRegI src1, vecY src2, regF tmp, regF tmp2) %{ |
|
4530 |
predicate(UseAVX > 2); |
|
30211 | 4531 |
match(Set dst (AddReductionVI src1 src2)); |
4532 |
effect(TEMP tmp, TEMP tmp2); |
|
30624 | 4533 |
format %{ "vextracti128 $tmp,$src2\n\t" |
4534 |
"vpaddd $tmp,$tmp,$src2\n\t" |
|
4535 |
"pshufd $tmp2,$tmp,0xE\n\t" |
|
4536 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
|
4537 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
4538 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
|
4539 |
"movd $tmp2,$src1\n\t" |
|
4540 |
"vpaddd $tmp2,$tmp,$tmp2\n\t" |
|
4541 |
"movd $dst,$tmp2\t! add reduction8I" %} |
|
4542 |
ins_encode %{ |
|
4543 |
int vector_len = 0; |
|
4544 |
__ vextracti128h($tmp$$XMMRegister, $src2$$XMMRegister); |
|
4545 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
4546 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0xE); |
|
4547 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
4548 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
|
4549 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
4550 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
4551 |
__ vpaddd($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
4552 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
4553 |
%} |
|
4554 |
ins_pipe( pipe_slow ); |
|
4555 |
%} |
|
4556 |
||
4557 |
instruct rvadd16I_reduction_reg_evex(rRegI dst, rRegI src1, vecZ src2, regF tmp, regF tmp2, regF tmp3) %{ |
|
4558 |
predicate(UseAVX > 2); |
|
4559 |
match(Set dst (AddReductionVI src1 src2)); |
|
4560 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
4561 |
format %{ "vextracti64x4 $tmp3,$src2\n\t" |
|
4562 |
"vpaddd $tmp3,$tmp3,$src2\n\t" |
|
4563 |
"vextracti128 $tmp,$tmp3\n\t" |
|
4564 |
"vpaddd $tmp,$tmp,$tmp3\n\t" |
|
4565 |
"pshufd $tmp2,$tmp,0xE\n\t" |
|
4566 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
|
4567 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
30211 | 4568 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
4569 |
"movd $tmp2,$src1\n\t" |
|
30624 | 4570 |
"vpaddd $tmp2,$tmp,$tmp2\n\t" |
4571 |
"movd $dst,$tmp2\t! mul reduction16I" %} |
|
4572 |
ins_encode %{ |
|
4573 |
__ vextracti64x4h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
4574 |
__ vpaddd($tmp3$$XMMRegister, $tmp3$$XMMRegister, $src2$$XMMRegister, 1); |
|
4575 |
__ vextracti128h($tmp$$XMMRegister, $tmp3$$XMMRegister); |
|
4576 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp3$$XMMRegister, 0); |
|
4577 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0xE); |
|
4578 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
4579 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
|
4580 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
30211 | 4581 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
30624 | 4582 |
__ vpaddd($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
30211 | 4583 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
4584 |
%} |
|
4585 |
ins_pipe( pipe_slow ); |
|
4586 |
%} |
|
4587 |
||
30624 | 4588 |
#ifdef _LP64 |
4589 |
instruct rvadd2L_reduction_reg(rRegL dst, rRegL src1, vecX src2, regF tmp, regF tmp2) %{ |
|
4590 |
predicate(UseAVX > 2); |
|
4591 |
match(Set dst (AddReductionVL src1 src2)); |
|
4592 |
effect(TEMP tmp, TEMP tmp2); |
|
4593 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
|
4594 |
"vpaddq $tmp,$src2,$tmp2\n\t" |
|
4595 |
"movdq $tmp2,$src1\n\t" |
|
4596 |
"vpaddq $tmp2,$tmp,$tmp2\n\t" |
|
4597 |
"movdq $dst,$tmp2\t! add reduction2L" %} |
|
4598 |
ins_encode %{ |
|
4599 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4600 |
__ vpaddq($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
4601 |
__ movdq($tmp2$$XMMRegister, $src1$$Register); |
|
4602 |
__ vpaddq($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
4603 |
__ movdq($dst$$Register, $tmp2$$XMMRegister); |
|
4604 |
%} |
|
4605 |
ins_pipe( pipe_slow ); |
|
4606 |
%} |
|
4607 |
||
4608 |
instruct rvadd4L_reduction_reg(rRegL dst, rRegL src1, vecY src2, regF tmp, regF tmp2) %{ |
|
4609 |
predicate(UseAVX > 2); |
|
4610 |
match(Set dst (AddReductionVL src1 src2)); |
|
4611 |
effect(TEMP tmp, TEMP tmp2); |
|
4612 |
format %{ "vextracti64x2 $tmp,$src2, 0x1\n\t" |
|
4613 |
"vpaddq $tmp2,$tmp,$src2\n\t" |
|
4614 |
"pshufd $tmp,$tmp2,0xE\n\t" |
|
4615 |
"vpaddq $tmp2,$tmp2,$tmp\n\t" |
|
4616 |
"movdq $tmp,$src1\n\t" |
|
4617 |
"vpaddq $tmp2,$tmp2,$tmp\n\t" |
|
4618 |
"movdq $dst,$tmp2\t! add reduction4L" %} |
|
4619 |
ins_encode %{ |
|
4620 |
__ vextracti64x2h($tmp$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
4621 |
__ vpaddq($tmp2$$XMMRegister, $tmp$$XMMRegister, $src2$$XMMRegister, 0); |
|
4622 |
__ pshufd($tmp$$XMMRegister, $tmp2$$XMMRegister, 0xE); |
|
4623 |
__ vpaddq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
4624 |
__ movdq($tmp$$XMMRegister, $src1$$Register); |
|
4625 |
__ vpaddq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
4626 |
__ movdq($dst$$Register, $tmp2$$XMMRegister); |
|
4627 |
%} |
|
4628 |
ins_pipe( pipe_slow ); |
|
4629 |
%} |
|
4630 |
||
4631 |
instruct rvadd8L_reduction_reg(rRegL dst, rRegL src1, vecZ src2, regF tmp, regF tmp2) %{ |
|
4632 |
predicate(UseAVX > 2); |
|
4633 |
match(Set dst (AddReductionVL src1 src2)); |
|
4634 |
effect(TEMP tmp, TEMP tmp2); |
|
4635 |
format %{ "vextracti64x4 $tmp2,$src2\n\t" |
|
4636 |
"vpaddq $tmp2,$tmp2,$src2\n\t" |
|
4637 |
"vextracti128 $tmp,$tmp2\n\t" |
|
4638 |
"vpaddq $tmp2,$tmp2,$tmp\n\t" |
|
4639 |
"pshufd $tmp,$tmp2,0xE\n\t" |
|
4640 |
"vpaddq $tmp2,$tmp2,$tmp\n\t" |
|
4641 |
"movdq $tmp,$src1\n\t" |
|
4642 |
"vpaddq $tmp2,$tmp2,$tmp\n\t" |
|
4643 |
"movdq $dst,$tmp2\t! add reduction8L" %} |
|
4644 |
ins_encode %{ |
|
4645 |
__ vextracti64x4h($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
4646 |
__ vpaddq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $src2$$XMMRegister, 1); |
|
4647 |
__ vextracti128h($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4648 |
__ vpaddq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
4649 |
__ pshufd($tmp$$XMMRegister, $tmp2$$XMMRegister, 0xE); |
|
4650 |
__ vpaddq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
4651 |
__ movdq($tmp$$XMMRegister, $src1$$Register); |
|
4652 |
__ vpaddq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
4653 |
__ movdq($dst$$Register, $tmp2$$XMMRegister); |
|
4654 |
%} |
|
4655 |
ins_pipe( pipe_slow ); |
|
4656 |
%} |
|
4657 |
#endif |
|
4658 |
||
30211 | 4659 |
instruct rsadd2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
4660 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
4661 |
match(Set dst (AddReductionVF src1 src2)); |
|
4662 |
effect(TEMP tmp, TEMP tmp2); |
|
4663 |
format %{ "movdqu $tmp,$src1\n\t" |
|
4664 |
"addss $tmp,$src2\n\t" |
|
4665 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
4666 |
"addss $tmp,$tmp2\n\t" |
|
4667 |
"movdqu $dst,$tmp\t! add reduction2F" %} |
|
4668 |
ins_encode %{ |
|
4669 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
4670 |
__ addss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
4671 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
4672 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4673 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
4674 |
%} |
|
4675 |
ins_pipe( pipe_slow ); |
|
4676 |
%} |
|
4677 |
||
4678 |
instruct rvadd2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
4679 |
predicate(UseAVX > 0); |
|
4680 |
match(Set dst (AddReductionVF src1 src2)); |
|
4681 |
effect(TEMP tmp2, TEMP tmp); |
|
4682 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
4683 |
"pshufd $tmp,$src2,0x01\n\t" |
|
4684 |
"vaddss $dst,$tmp2,$tmp\t! add reduction2F" %} |
|
4685 |
ins_encode %{ |
|
4686 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4687 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
4688 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4689 |
%} |
|
4690 |
ins_pipe( pipe_slow ); |
|
4691 |
%} |
|
4692 |
||
4693 |
instruct rsadd4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
4694 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
4695 |
match(Set dst (AddReductionVF src1 src2)); |
|
4696 |
effect(TEMP tmp, TEMP tmp2); |
|
4697 |
format %{ "movdqu $tmp,$src1\n\t" |
|
4698 |
"addss $tmp,$src2\n\t" |
|
4699 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
4700 |
"addss $tmp,$tmp2\n\t" |
|
4701 |
"pshufd $tmp2,$src2,0x02\n\t" |
|
4702 |
"addss $tmp,$tmp2\n\t" |
|
4703 |
"pshufd $tmp2,$src2,0x03\n\t" |
|
4704 |
"addss $tmp,$tmp2\n\t" |
|
4705 |
"movdqu $dst,$tmp\t! add reduction4F" %} |
|
4706 |
ins_encode %{ |
|
4707 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
4708 |
__ addss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
4709 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
4710 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4711 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
4712 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4713 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
4714 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
4715 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
4716 |
%} |
|
4717 |
ins_pipe( pipe_slow ); |
|
4718 |
%} |
|
4719 |
||
4720 |
instruct rvadd4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
4721 |
predicate(UseAVX > 0); |
|
4722 |
match(Set dst (AddReductionVF src1 src2)); |
|
4723 |
effect(TEMP tmp, TEMP tmp2); |
|
4724 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
4725 |
"pshufd $tmp,$src2,0x01\n\t" |
|
4726 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4727 |
"pshufd $tmp,$src2,0x02\n\t" |
|
4728 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4729 |
"pshufd $tmp,$src2,0x03\n\t" |
|
4730 |
"vaddss $dst,$tmp2,$tmp\t! add reduction4F" %} |
|
4731 |
ins_encode %{ |
|
4732 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4733 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
4734 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4735 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
4736 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4737 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
4738 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4739 |
%} |
|
4740 |
ins_pipe( pipe_slow ); |
|
4741 |
%} |
|
4742 |
||
4743 |
instruct radd8F_reduction_reg(regF dst, regF src1, vecY src2, regF tmp, regF tmp2, regF tmp3) %{ |
|
4744 |
predicate(UseAVX > 0); |
|
4745 |
match(Set dst (AddReductionVF src1 src2)); |
|
4746 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
4747 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
4748 |
"pshufd $tmp,$src2,0x01\n\t" |
|
4749 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4750 |
"pshufd $tmp,$src2,0x02\n\t" |
|
4751 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4752 |
"pshufd $tmp,$src2,0x03\n\t" |
|
4753 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4754 |
"vextractf128 $tmp3,$src2\n\t" |
|
4755 |
"vaddss $tmp2,$tmp2,$tmp3\n\t" |
|
4756 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
4757 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4758 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
4759 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4760 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
4761 |
"vaddss $dst,$tmp2,$tmp\t! add reduction8F" %} |
|
4762 |
ins_encode %{ |
|
4763 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4764 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
4765 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4766 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
4767 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4768 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
4769 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4770 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
4771 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4772 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
4773 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4774 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
4775 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4776 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
4777 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4778 |
%} |
|
4779 |
ins_pipe( pipe_slow ); |
|
4780 |
%} |
|
4781 |
||
30624 | 4782 |
instruct radd16F_reduction_reg(regF dst, regF src1, vecZ src2, regF tmp, regF tmp2, regF tmp3) %{ |
4783 |
predicate(UseAVX > 2); |
|
4784 |
match(Set dst (AddReductionVF src1 src2)); |
|
4785 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
4786 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
4787 |
"pshufd $tmp,$src2,0x01\n\t" |
|
4788 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4789 |
"pshufd $tmp,$src2,0x02\n\t" |
|
4790 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4791 |
"pshufd $tmp,$src2,0x03\n\t" |
|
4792 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4793 |
"vextractf64x2 $tmp3,$src2, 0x1\n\t" |
|
4794 |
"vaddss $tmp2,$tmp2,$tmp3\n\t" |
|
4795 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
4796 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4797 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
4798 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4799 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
4800 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4801 |
"vextractf64x2 $tmp3,$src2, 0x2\n\t" |
|
4802 |
"vaddss $tmp2,$tmp2,$tmp3\n\t" |
|
4803 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
4804 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4805 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
4806 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4807 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
4808 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4809 |
"vextractf64x2 $tmp3,$src2, 0x3\n\t" |
|
4810 |
"vaddss $tmp2,$tmp2,$tmp3\n\t" |
|
4811 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
4812 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4813 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
4814 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
4815 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
4816 |
"vaddss $dst,$tmp2,$tmp\t! add reduction16F" %} |
|
4817 |
ins_encode %{ |
|
4818 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4819 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
4820 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4821 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
4822 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4823 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
4824 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4825 |
__ vextractf32x4h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
4826 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4827 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
4828 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4829 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
4830 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4831 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
4832 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4833 |
__ vextractf32x4h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x2); |
|
4834 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4835 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
4836 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4837 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
4838 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4839 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
4840 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4841 |
__ vextractf32x4h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x3); |
|
4842 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4843 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
4844 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4845 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
4846 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4847 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
4848 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4849 |
%} |
|
4850 |
ins_pipe( pipe_slow ); |
|
4851 |
%} |
|
4852 |
||
30211 | 4853 |
instruct rsadd2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp) %{ |
4854 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
4855 |
match(Set dst (AddReductionVD src1 src2)); |
|
4856 |
effect(TEMP tmp, TEMP dst); |
|
4857 |
format %{ "movdqu $tmp,$src1\n\t" |
|
4858 |
"addsd $tmp,$src2\n\t" |
|
4859 |
"pshufd $dst,$src2,0xE\n\t" |
|
4860 |
"addsd $dst,$tmp\t! add reduction2D" %} |
|
4861 |
ins_encode %{ |
|
4862 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
4863 |
__ addsd($tmp$$XMMRegister, $src2$$XMMRegister); |
|
4864 |
__ pshufd($dst$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4865 |
__ addsd($dst$$XMMRegister, $tmp$$XMMRegister); |
|
4866 |
%} |
|
4867 |
ins_pipe( pipe_slow ); |
|
4868 |
%} |
|
4869 |
||
4870 |
instruct rvadd2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp, regD tmp2) %{ |
|
4871 |
predicate(UseAVX > 0); |
|
4872 |
match(Set dst (AddReductionVD src1 src2)); |
|
4873 |
effect(TEMP tmp, TEMP tmp2); |
|
4874 |
format %{ "vaddsd $tmp2,$src1,$src2\n\t" |
|
4875 |
"pshufd $tmp,$src2,0xE\n\t" |
|
4876 |
"vaddsd $dst,$tmp2,$tmp\t! add reduction2D" %} |
|
4877 |
ins_encode %{ |
|
4878 |
__ vaddsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4879 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4880 |
__ vaddsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4881 |
%} |
|
4882 |
ins_pipe( pipe_slow ); |
|
4883 |
%} |
|
4884 |
||
4885 |
instruct rvadd4D_reduction_reg(regD dst, regD src1, vecY src2, regD tmp, regD tmp2, regD tmp3) %{ |
|
4886 |
predicate(UseAVX > 0); |
|
4887 |
match(Set dst (AddReductionVD src1 src2)); |
|
4888 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
4889 |
format %{ "vaddsd $tmp2,$src1,$src2\n\t" |
|
4890 |
"pshufd $tmp,$src2,0xE\n\t" |
|
4891 |
"vaddsd $tmp2,$tmp2,$tmp\n\t" |
|
4892 |
"vextractf128 $tmp3,$src2\n\t" |
|
4893 |
"vaddsd $tmp2,$tmp2,$tmp3\n\t" |
|
4894 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
4895 |
"vaddsd $dst,$tmp2,$tmp\t! add reduction4D" %} |
|
4896 |
ins_encode %{ |
|
4897 |
__ vaddsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4898 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4899 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4900 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
4901 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4902 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
4903 |
__ vaddsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4904 |
%} |
|
4905 |
ins_pipe( pipe_slow ); |
|
4906 |
%} |
|
4907 |
||
30624 | 4908 |
instruct rvadd8D_reduction_reg(regD dst, regD src1, vecZ src2, regD tmp, regD tmp2, regD tmp3) %{ |
4909 |
predicate(UseAVX > 2); |
|
4910 |
match(Set dst (AddReductionVD src1 src2)); |
|
4911 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
4912 |
format %{ "vaddsd $tmp2,$src1,$src2\n\t" |
|
4913 |
"pshufd $tmp,$src2,0xE\n\t" |
|
4914 |
"vaddsd $tmp2,$tmp2,$tmp\n\t" |
|
4915 |
"vextractf64x2 $tmp3,$src2, 0x1\n\t" |
|
4916 |
"vaddsd $tmp2,$tmp2,$tmp3\n\t" |
|
4917 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
4918 |
"vaddsd $tmp2,$tmp2,$tmp\n\t" |
|
4919 |
"vextractf64x2 $tmp3,$src2, 0x2\n\t" |
|
4920 |
"vaddsd $tmp2,$tmp2,$tmp3\n\t" |
|
4921 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
4922 |
"vaddsd $tmp2,$tmp2,$tmp\n\t" |
|
4923 |
"vextractf64x2 $tmp3,$src2, 0x3\n\t" |
|
4924 |
"vaddsd $tmp2,$tmp2,$tmp3\n\t" |
|
4925 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
4926 |
"vaddsd $dst,$tmp2,$tmp\t! add reduction8D" %} |
|
4927 |
ins_encode %{ |
|
4928 |
__ vaddsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
4929 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4930 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4931 |
__ vextractf64x2h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
4932 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4933 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
4934 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4935 |
__ vextractf64x2h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x2); |
|
4936 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4937 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
4938 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4939 |
__ vextractf64x2h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x3); |
|
4940 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
4941 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
4942 |
__ vaddsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4943 |
%} |
|
4944 |
ins_pipe( pipe_slow ); |
|
4945 |
%} |
|
4946 |
||
30211 | 4947 |
instruct rsmul2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
4948 |
predicate(UseSSE > 3 && UseAVX == 0); |
|
4949 |
match(Set dst (MulReductionVI src1 src2)); |
|
4950 |
effect(TEMP tmp, TEMP tmp2); |
|
4951 |
format %{ "pshufd $tmp2,$src2,0x1\n\t" |
|
4952 |
"pmulld $tmp2,$src2\n\t" |
|
4953 |
"movd $tmp,$src1\n\t" |
|
4954 |
"pmulld $tmp2,$tmp\n\t" |
|
4955 |
"movd $dst,$tmp2\t! mul reduction2I" %} |
|
4956 |
ins_encode %{ |
|
4957 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
4958 |
__ pmulld($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
4959 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
4960 |
__ pmulld($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
4961 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
4962 |
%} |
|
4963 |
ins_pipe( pipe_slow ); |
|
4964 |
%} |
|
4965 |
||
4966 |
instruct rvmul2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
4967 |
predicate(UseAVX > 0); |
|
4968 |
match(Set dst (MulReductionVI src1 src2)); |
|
4969 |
effect(TEMP tmp, TEMP tmp2); |
|
30624 | 4970 |
format %{ "pshufd $tmp2,$src2,0x1\n\t" |
4971 |
"vpmulld $tmp,$src2,$tmp2\n\t" |
|
4972 |
"movd $tmp2,$src1\n\t" |
|
4973 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
4974 |
"movd $dst,$tmp2\t! mul reduction2I" %} |
|
4975 |
ins_encode %{ |
|
4976 |
int vector_len = 0; |
|
30211 | 4977 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x1); |
30624 | 4978 |
__ vpmulld($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 4979 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
30624 | 4980 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 4981 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
4982 |
%} |
|
4983 |
ins_pipe( pipe_slow ); |
|
4984 |
%} |
|
4985 |
||
4986 |
instruct rsmul4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
4987 |
predicate(UseSSE > 3 && UseAVX == 0); |
|
4988 |
match(Set dst (MulReductionVI src1 src2)); |
|
4989 |
effect(TEMP tmp, TEMP tmp2); |
|
4990 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
|
4991 |
"pmulld $tmp2,$src2\n\t" |
|
4992 |
"pshufd $tmp,$tmp2,0x1\n\t" |
|
4993 |
"pmulld $tmp2,$tmp\n\t" |
|
4994 |
"movd $tmp,$src1\n\t" |
|
4995 |
"pmulld $tmp2,$tmp\n\t" |
|
4996 |
"movd $dst,$tmp2\t! mul reduction4I" %} |
|
4997 |
ins_encode %{ |
|
4998 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
4999 |
__ pmulld($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
5000 |
__ pshufd($tmp$$XMMRegister, $tmp2$$XMMRegister, 0x1); |
|
5001 |
__ pmulld($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5002 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
5003 |
__ pmulld($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5004 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
5005 |
%} |
|
5006 |
ins_pipe( pipe_slow ); |
|
5007 |
%} |
|
5008 |
||
5009 |
instruct rvmul4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
5010 |
predicate(UseAVX > 0); |
|
5011 |
match(Set dst (MulReductionVI src1 src2)); |
|
5012 |
effect(TEMP tmp, TEMP tmp2); |
|
30624 | 5013 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
5014 |
"vpmulld $tmp,$src2,$tmp2\n\t" |
|
5015 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
5016 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
5017 |
"movd $tmp2,$src1\n\t" |
|
5018 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
5019 |
"movd $dst,$tmp2\t! mul reduction4I" %} |
|
5020 |
ins_encode %{ |
|
5021 |
int vector_len = 0; |
|
30211 | 5022 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
30624 | 5023 |
__ vpmulld($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 5024 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
30624 | 5025 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 5026 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
30624 | 5027 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
30211 | 5028 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
5029 |
%} |
|
5030 |
ins_pipe( pipe_slow ); |
|
5031 |
%} |
|
5032 |
||
5033 |
instruct rvmul8I_reduction_reg(rRegI dst, rRegI src1, vecY src2, regF tmp, regF tmp2) %{ |
|
5034 |
predicate(UseAVX > 0); |
|
5035 |
match(Set dst (MulReductionVI src1 src2)); |
|
5036 |
effect(TEMP tmp, TEMP tmp2); |
|
30624 | 5037 |
format %{ "vextracti128 $tmp,$src2\n\t" |
5038 |
"vpmulld $tmp,$tmp,$src2\n\t" |
|
5039 |
"pshufd $tmp2,$tmp,0xE\n\t" |
|
5040 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
5041 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
5042 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
5043 |
"movd $tmp2,$src1\n\t" |
|
5044 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
5045 |
"movd $dst,$tmp2\t! mul reduction8I" %} |
|
5046 |
ins_encode %{ |
|
5047 |
int vector_len = 0; |
|
5048 |
__ vextracti128h($tmp$$XMMRegister, $src2$$XMMRegister); |
|
5049 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
5050 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0xE); |
|
5051 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
5052 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
|
5053 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
5054 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
5055 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, vector_len); |
|
5056 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
5057 |
%} |
|
5058 |
ins_pipe( pipe_slow ); |
|
5059 |
%} |
|
5060 |
||
5061 |
instruct rvmul16I_reduction_reg(rRegI dst, rRegI src1, vecZ src2, regF tmp, regF tmp2, regF tmp3) %{ |
|
5062 |
predicate(UseAVX > 2); |
|
5063 |
match(Set dst (MulReductionVI src1 src2)); |
|
5064 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
5065 |
format %{ "vextracti64x4 $tmp3,$src2\n\t" |
|
5066 |
"vpmulld $tmp3,$tmp3,$src2\n\t" |
|
5067 |
"vextracti128 $tmp,$tmp3\n\t" |
|
5068 |
"vpmulld $tmp,$tmp,$src2\n\t" |
|
5069 |
"pshufd $tmp2,$tmp,0xE\n\t" |
|
5070 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
5071 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
5072 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
5073 |
"movd $tmp2,$src1\n\t" |
|
5074 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
5075 |
"movd $dst,$tmp2\t! mul reduction16I" %} |
|
5076 |
ins_encode %{ |
|
5077 |
__ vextracti64x4h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
5078 |
__ vpmulld($tmp3$$XMMRegister, $tmp3$$XMMRegister, $src2$$XMMRegister, 1); |
|
5079 |
__ vextracti128h($tmp$$XMMRegister, $tmp3$$XMMRegister); |
|
5080 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp3$$XMMRegister, 0); |
|
30211 | 5081 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0xE); |
30624 | 5082 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
30211 | 5083 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
30624 | 5084 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
30211 | 5085 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
30624 | 5086 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
30211 | 5087 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
5088 |
%} |
|
5089 |
ins_pipe( pipe_slow ); |
|
5090 |
%} |
|
5091 |
||
30624 | 5092 |
#ifdef _LP64 |
5093 |
instruct rvmul2L_reduction_reg(rRegL dst, rRegL src1, vecX src2, regF tmp, regF tmp2) %{ |
|
5094 |
predicate(UseAVX > 2 && VM_Version::supports_avx512dq()); |
|
5095 |
match(Set dst (MulReductionVL src1 src2)); |
|
5096 |
effect(TEMP tmp, TEMP tmp2); |
|
5097 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
|
5098 |
"vpmullq $tmp,$src2,$tmp2\n\t" |
|
5099 |
"movdq $tmp2,$src1\n\t" |
|
5100 |
"vpmullq $tmp2,$tmp,$tmp2\n\t" |
|
5101 |
"movdq $dst,$tmp2\t! mul reduction2L" %} |
|
5102 |
ins_encode %{ |
|
5103 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
5104 |
__ vpmullq($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
5105 |
__ movdq($tmp2$$XMMRegister, $src1$$Register); |
|
5106 |
__ vpmullq($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, 0); |
|
5107 |
__ movdq($dst$$Register, $tmp2$$XMMRegister); |
|
5108 |
%} |
|
5109 |
ins_pipe( pipe_slow ); |
|
5110 |
%} |
|
5111 |
||
5112 |
instruct rvmul4L_reduction_reg(rRegL dst, rRegL src1, vecY src2, regF tmp, regF tmp2) %{ |
|
5113 |
predicate(UseAVX > 2 && VM_Version::supports_avx512dq()); |
|
5114 |
match(Set dst (MulReductionVL src1 src2)); |
|
5115 |
effect(TEMP tmp, TEMP tmp2); |
|
5116 |
format %{ "vextracti64x2 $tmp,$src2, 0x1\n\t" |
|
5117 |
"vpmullq $tmp2,$tmp,$src2\n\t" |
|
5118 |
"pshufd $tmp,$tmp2,0xE\n\t" |
|
5119 |
"vpmullq $tmp2,$tmp2,$tmp\n\t" |
|
5120 |
"movdq $tmp,$src1\n\t" |
|
5121 |
"vpmullq $tmp2,$tmp2,$tmp\n\t" |
|
5122 |
"movdq $dst,$tmp2\t! mul reduction4L" %} |
|
5123 |
ins_encode %{ |
|
5124 |
__ vextracti64x2h($tmp$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
5125 |
__ vpmullq($tmp2$$XMMRegister, $tmp$$XMMRegister, $src2$$XMMRegister, 0); |
|
5126 |
__ pshufd($tmp$$XMMRegister, $tmp2$$XMMRegister, 0xE); |
|
5127 |
__ vpmullq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
5128 |
__ movdq($tmp$$XMMRegister, $src1$$Register); |
|
5129 |
__ vpmullq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
5130 |
__ movdq($dst$$Register, $tmp2$$XMMRegister); |
|
5131 |
%} |
|
5132 |
ins_pipe( pipe_slow ); |
|
5133 |
%} |
|
5134 |
||
5135 |
instruct rvmul8L_reduction_reg(rRegL dst, rRegL src1, vecZ src2, regF tmp, regF tmp2) %{ |
|
5136 |
predicate(UseAVX > 2 && VM_Version::supports_avx512dq()); |
|
5137 |
match(Set dst (MulReductionVL src1 src2)); |
|
5138 |
effect(TEMP tmp, TEMP tmp2); |
|
5139 |
format %{ "vextracti64x4 $tmp2,$src2\n\t" |
|
5140 |
"vpmullq $tmp2,$tmp2,$src2\n\t" |
|
5141 |
"vextracti128 $tmp,$tmp2\n\t" |
|
5142 |
"vpmullq $tmp2,$tmp2,$tmp\n\t" |
|
5143 |
"pshufd $tmp,$tmp2,0xE\n\t" |
|
5144 |
"vpmullq $tmp2,$tmp2,$tmp\n\t" |
|
5145 |
"movdq $tmp,$src1\n\t" |
|
5146 |
"vpmullq $tmp2,$tmp2,$tmp\n\t" |
|
5147 |
"movdq $dst,$tmp2\t! mul reduction8L" %} |
|
5148 |
ins_encode %{ |
|
5149 |
__ vextracti64x4h($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
5150 |
__ vpmullq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $src2$$XMMRegister, 1); |
|
5151 |
__ vextracti128h($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
5152 |
__ vpmullq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
5153 |
__ pshufd($tmp$$XMMRegister, $tmp2$$XMMRegister, 0xE); |
|
5154 |
__ vpmullq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
5155 |
__ movdq($tmp$$XMMRegister, $src1$$Register); |
|
5156 |
__ vpmullq($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, 0); |
|
5157 |
__ movdq($dst$$Register, $tmp2$$XMMRegister); |
|
5158 |
%} |
|
5159 |
ins_pipe( pipe_slow ); |
|
5160 |
%} |
|
5161 |
#endif |
|
5162 |
||
5163 |
instruct rsmul2F_reduction(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
30211 | 5164 |
predicate(UseSSE >= 1 && UseAVX == 0); |
5165 |
match(Set dst (MulReductionVF src1 src2)); |
|
5166 |
effect(TEMP tmp, TEMP tmp2); |
|
5167 |
format %{ "movdqu $tmp,$src1\n\t" |
|
5168 |
"mulss $tmp,$src2\n\t" |
|
5169 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
5170 |
"mulss $tmp,$tmp2\n\t" |
|
30624 | 5171 |
"movdqu $dst,$tmp\t! mul reduction2F" %} |
30211 | 5172 |
ins_encode %{ |
5173 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
5174 |
__ mulss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
5175 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
5176 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
5177 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
5178 |
%} |
|
5179 |
ins_pipe( pipe_slow ); |
|
5180 |
%} |
|
5181 |
||
5182 |
instruct rvmul2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
5183 |
predicate(UseAVX > 0); |
|
5184 |
match(Set dst (MulReductionVF src1 src2)); |
|
5185 |
effect(TEMP tmp, TEMP tmp2); |
|
5186 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
5187 |
"pshufd $tmp,$src2,0x01\n\t" |
|
30624 | 5188 |
"vmulss $dst,$tmp2,$tmp\t! mul reduction2F" %} |
30211 | 5189 |
ins_encode %{ |
5190 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5191 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
5192 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5193 |
%} |
|
5194 |
ins_pipe( pipe_slow ); |
|
5195 |
%} |
|
5196 |
||
5197 |
instruct rsmul4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
5198 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
5199 |
match(Set dst (MulReductionVF src1 src2)); |
|
5200 |
effect(TEMP tmp, TEMP tmp2); |
|
5201 |
format %{ "movdqu $tmp,$src1\n\t" |
|
5202 |
"mulss $tmp,$src2\n\t" |
|
5203 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
5204 |
"mulss $tmp,$tmp2\n\t" |
|
5205 |
"pshufd $tmp2,$src2,0x02\n\t" |
|
5206 |
"mulss $tmp,$tmp2\n\t" |
|
5207 |
"pshufd $tmp2,$src2,0x03\n\t" |
|
5208 |
"mulss $tmp,$tmp2\n\t" |
|
30624 | 5209 |
"movdqu $dst,$tmp\t! mul reduction4F" %} |
30211 | 5210 |
ins_encode %{ |
5211 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
5212 |
__ mulss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
5213 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
5214 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
5215 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
5216 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
5217 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
5218 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
5219 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
5220 |
%} |
|
5221 |
ins_pipe( pipe_slow ); |
|
5222 |
%} |
|
5223 |
||
5224 |
instruct rvmul4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
5225 |
predicate(UseAVX > 0); |
|
5226 |
match(Set dst (MulReductionVF src1 src2)); |
|
5227 |
effect(TEMP tmp, TEMP tmp2); |
|
5228 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
5229 |
"pshufd $tmp,$src2,0x01\n\t" |
|
5230 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5231 |
"pshufd $tmp,$src2,0x02\n\t" |
|
5232 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5233 |
"pshufd $tmp,$src2,0x03\n\t" |
|
30624 | 5234 |
"vmulss $dst,$tmp2,$tmp\t! mul reduction4F" %} |
30211 | 5235 |
ins_encode %{ |
5236 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5237 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
5238 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5239 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
5240 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5241 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
5242 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5243 |
%} |
|
5244 |
ins_pipe( pipe_slow ); |
|
5245 |
%} |
|
5246 |
||
5247 |
instruct rvmul8F_reduction_reg(regF dst, regF src1, vecY src2, regF tmp, regF tmp2, regF tmp3) %{ |
|
5248 |
predicate(UseAVX > 0); |
|
5249 |
match(Set dst (MulReductionVF src1 src2)); |
|
5250 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
5251 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
5252 |
"pshufd $tmp,$src2,0x01\n\t" |
|
5253 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5254 |
"pshufd $tmp,$src2,0x02\n\t" |
|
5255 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5256 |
"pshufd $tmp,$src2,0x03\n\t" |
|
5257 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5258 |
"vextractf128 $tmp3,$src2\n\t" |
|
5259 |
"vmulss $tmp2,$tmp2,$tmp3\n\t" |
|
5260 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
5261 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5262 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
5263 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5264 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
5265 |
"vmulss $dst,$tmp2,$tmp\t! mul reduction8F" %} |
|
5266 |
ins_encode %{ |
|
5267 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5268 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
5269 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5270 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
5271 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5272 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
5273 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5274 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
5275 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5276 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
5277 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5278 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
5279 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5280 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
5281 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5282 |
%} |
|
5283 |
ins_pipe( pipe_slow ); |
|
5284 |
%} |
|
5285 |
||
30624 | 5286 |
instruct rvmul16F_reduction_reg(regF dst, regF src1, vecZ src2, regF tmp, regF tmp2, regF tmp3) %{ |
5287 |
predicate(UseAVX > 2); |
|
5288 |
match(Set dst (MulReductionVF src1 src2)); |
|
5289 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
5290 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
5291 |
"pshufd $tmp,$src2,0x01\n\t" |
|
5292 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5293 |
"pshufd $tmp,$src2,0x02\n\t" |
|
5294 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5295 |
"pshufd $tmp,$src2,0x03\n\t" |
|
5296 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5297 |
"vextractf32x4 $tmp3,$src2, 0x1\n\t" |
|
5298 |
"vmulss $tmp2,$tmp2,$tmp3\n\t" |
|
5299 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
5300 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5301 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
5302 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5303 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
5304 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5305 |
"vextractf32x4 $tmp3,$src2, 0x2\n\t" |
|
5306 |
"vmulss $tmp2,$tmp2,$tmp3\n\t" |
|
5307 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
5308 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5309 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
5310 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5311 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
5312 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5313 |
"vextractf32x4 $tmp3,$src2, 0x3\n\t" |
|
5314 |
"vmulss $tmp2,$tmp2,$tmp3\n\t" |
|
5315 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
5316 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5317 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
5318 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
5319 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
5320 |
"vmulss $dst,$tmp2,$tmp\t! mul reduction16F" %} |
|
5321 |
ins_encode %{ |
|
5322 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5323 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
5324 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5325 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
5326 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5327 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
5328 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5329 |
__ vextractf32x4h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
5330 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5331 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
5332 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5333 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
5334 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5335 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
5336 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5337 |
__ vextractf32x4h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x2); |
|
5338 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5339 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
5340 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5341 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
5342 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5343 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
5344 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5345 |
__ vextractf32x4h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x3); |
|
5346 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5347 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
5348 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5349 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
5350 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5351 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
5352 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5353 |
%} |
|
5354 |
ins_pipe( pipe_slow ); |
|
5355 |
%} |
|
5356 |
||
30211 | 5357 |
instruct rsmul2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp) %{ |
5358 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
5359 |
match(Set dst (MulReductionVD src1 src2)); |
|
5360 |
effect(TEMP tmp, TEMP dst); |
|
5361 |
format %{ "movdqu $tmp,$src1\n\t" |
|
5362 |
"mulsd $tmp,$src2\n\t" |
|
5363 |
"pshufd $dst,$src2,0xE\n\t" |
|
30624 | 5364 |
"mulsd $dst,$tmp\t! mul reduction2D" %} |
30211 | 5365 |
ins_encode %{ |
5366 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
5367 |
__ mulsd($tmp$$XMMRegister, $src2$$XMMRegister); |
|
5368 |
__ pshufd($dst$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
5369 |
__ mulsd($dst$$XMMRegister, $tmp$$XMMRegister); |
|
5370 |
%} |
|
5371 |
ins_pipe( pipe_slow ); |
|
5372 |
%} |
|
5373 |
||
5374 |
instruct rvmul2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp, regD tmp2) %{ |
|
5375 |
predicate(UseAVX > 0); |
|
5376 |
match(Set dst (MulReductionVD src1 src2)); |
|
5377 |
effect(TEMP tmp, TEMP tmp2); |
|
5378 |
format %{ "vmulsd $tmp2,$src1,$src2\n\t" |
|
5379 |
"pshufd $tmp,$src2,0xE\n\t" |
|
5380 |
"vmulsd $dst,$tmp2,$tmp\t! mul reduction2D" %} |
|
5381 |
ins_encode %{ |
|
5382 |
__ vmulsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5383 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
5384 |
__ vmulsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5385 |
%} |
|
5386 |
ins_pipe( pipe_slow ); |
|
5387 |
%} |
|
5388 |
||
5389 |
instruct rvmul4D_reduction_reg(regD dst, regD src1, vecY src2, regD tmp, regD tmp2, regD tmp3) %{ |
|
5390 |
predicate(UseAVX > 0); |
|
5391 |
match(Set dst (MulReductionVD src1 src2)); |
|
5392 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
5393 |
format %{ "vmulsd $tmp2,$src1,$src2\n\t" |
|
5394 |
"pshufd $tmp,$src2,0xE\n\t" |
|
5395 |
"vmulsd $tmp2,$tmp2,$tmp\n\t" |
|
5396 |
"vextractf128 $tmp3,$src2\n\t" |
|
5397 |
"vmulsd $tmp2,$tmp2,$tmp3\n\t" |
|
5398 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
5399 |
"vmulsd $dst,$tmp2,$tmp\t! mul reduction4D" %} |
|
5400 |
ins_encode %{ |
|
5401 |
__ vmulsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5402 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
5403 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5404 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
5405 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5406 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
5407 |
__ vmulsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5408 |
%} |
|
5409 |
ins_pipe( pipe_slow ); |
|
5410 |
%} |
|
5411 |
||
30624 | 5412 |
instruct rvmul8D_reduction_reg(regD dst, regD src1, vecZ src2, regD tmp, regD tmp2, regD tmp3) %{ |
5413 |
predicate(UseAVX > 2); |
|
5414 |
match(Set dst (MulReductionVD src1 src2)); |
|
5415 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
5416 |
format %{ "vmulsd $tmp2,$src1,$src2\n\t" |
|
5417 |
"pshufd $tmp,$src2,0xE\n\t" |
|
5418 |
"vmulsd $tmp2,$tmp2,$tmp\n\t" |
|
5419 |
"vextractf64x2 $tmp3,$src2, 0x1\n\t" |
|
5420 |
"vmulsd $tmp2,$tmp2,$tmp3\n\t" |
|
5421 |
"pshufd $tmp,$src2,0xE\n\t" |
|
5422 |
"vmulsd $tmp2,$tmp2,$tmp\n\t" |
|
5423 |
"vextractf64x2 $tmp3,$src2, 0x2\n\t" |
|
5424 |
"vmulsd $tmp2,$tmp2,$tmp3\n\t" |
|
5425 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
5426 |
"vmulsd $tmp2,$tmp2,$tmp\n\t" |
|
5427 |
"vextractf64x2 $tmp3,$src2, 0x3\n\t" |
|
5428 |
"vmulsd $tmp2,$tmp2,$tmp3\n\t" |
|
5429 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
5430 |
"vmulsd $dst,$tmp2,$tmp\t! mul reduction8D" %} |
|
5431 |
ins_encode %{ |
|
5432 |
__ vmulsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
5433 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
5434 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5435 |
__ vextractf64x2h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
5436 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5437 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
5438 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5439 |
__ vextractf64x2h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x2); |
|
5440 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5441 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
5442 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5443 |
__ vextractf64x2h($tmp3$$XMMRegister, $src2$$XMMRegister, 0x3); |
|
5444 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
5445 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
5446 |
__ vmulsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
5447 |
%} |
|
5448 |
ins_pipe( pipe_slow ); |
|
5449 |
%} |
|
5450 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5451 |
// ====================VECTOR ARITHMETIC======================================= |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5452 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5453 |
// --------------------------------- ADD -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5454 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5455 |
// Bytes vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5456 |
instruct vadd4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5457 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5458 |
match(Set dst (AddVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5459 |
format %{ "paddb $dst,$src\t! add packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5460 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5461 |
__ paddb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5462 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5463 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5464 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5465 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5466 |
instruct vadd4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5467 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5468 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5469 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5470 |
ins_encode %{ |
30624 | 5471 |
int vector_len = 0; |
5472 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5473 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5474 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5475 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5476 |
|
31410 | 5477 |
instruct vadd4B_mem(vecS dst, vecS src, memory mem) %{ |
5478 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
|
5479 |
match(Set dst (AddVB src (LoadVector mem))); |
|
5480 |
format %{ "vpaddb $dst,$src,$mem\t! add packed4B" %} |
|
5481 |
ins_encode %{ |
|
5482 |
int vector_len = 0; |
|
5483 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5484 |
%} |
|
5485 |
ins_pipe( pipe_slow ); |
|
5486 |
%} |
|
5487 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5488 |
instruct vadd8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5489 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5490 |
match(Set dst (AddVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5491 |
format %{ "paddb $dst,$src\t! add packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5492 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5493 |
__ paddb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5494 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5495 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5496 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5497 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5498 |
instruct vadd8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5499 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5500 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5501 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5502 |
ins_encode %{ |
30624 | 5503 |
int vector_len = 0; |
5504 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5505 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5506 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5507 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5508 |
|
31410 | 5509 |
instruct vadd8B_mem(vecD dst, vecD src, memory mem) %{ |
5510 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
|
5511 |
match(Set dst (AddVB src (LoadVector mem))); |
|
5512 |
format %{ "vpaddb $dst,$src,$mem\t! add packed8B" %} |
|
5513 |
ins_encode %{ |
|
5514 |
int vector_len = 0; |
|
5515 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5516 |
%} |
|
5517 |
ins_pipe( pipe_slow ); |
|
5518 |
%} |
|
5519 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5520 |
instruct vadd16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5521 |
predicate(n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5522 |
match(Set dst (AddVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5523 |
format %{ "paddb $dst,$src\t! add packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5524 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5525 |
__ paddb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5526 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5527 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5528 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5529 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5530 |
instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5531 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5532 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5533 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5534 |
ins_encode %{ |
30624 | 5535 |
int vector_len = 0; |
5536 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5537 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5538 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5539 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5540 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5541 |
instruct vadd16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5542 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5543 |
match(Set dst (AddVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5544 |
format %{ "vpaddb $dst,$src,$mem\t! add packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5545 |
ins_encode %{ |
30624 | 5546 |
int vector_len = 0; |
5547 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5548 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5549 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5550 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5551 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5552 |
instruct vadd32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5553 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5554 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5555 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5556 |
ins_encode %{ |
30624 | 5557 |
int vector_len = 1; |
5558 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5559 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5560 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5561 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5562 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5563 |
instruct vadd32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5564 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5565 |
match(Set dst (AddVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5566 |
format %{ "vpaddb $dst,$src,$mem\t! add packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5567 |
ins_encode %{ |
30624 | 5568 |
int vector_len = 1; |
5569 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5570 |
%} |
|
5571 |
ins_pipe( pipe_slow ); |
|
5572 |
%} |
|
5573 |
||
5574 |
instruct vadd64B_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
5575 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 64); |
|
5576 |
match(Set dst (AddVB src1 src2)); |
|
5577 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed64B" %} |
|
5578 |
ins_encode %{ |
|
5579 |
int vector_len = 2; |
|
5580 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
5581 |
%} |
|
5582 |
ins_pipe( pipe_slow ); |
|
5583 |
%} |
|
5584 |
||
5585 |
instruct vadd64B_mem(vecZ dst, vecZ src, memory mem) %{ |
|
5586 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 64); |
|
5587 |
match(Set dst (AddVB src (LoadVector mem))); |
|
5588 |
format %{ "vpaddb $dst,$src,$mem\t! add packed64B" %} |
|
5589 |
ins_encode %{ |
|
5590 |
int vector_len = 2; |
|
5591 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5592 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5593 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5594 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5595 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5596 |
// Shorts/Chars vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5597 |
instruct vadd2S(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5598 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5599 |
match(Set dst (AddVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5600 |
format %{ "paddw $dst,$src\t! add packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5601 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5602 |
__ paddw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5603 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5604 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5605 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5606 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5607 |
instruct vadd2S_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5608 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5609 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5610 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5611 |
ins_encode %{ |
30624 | 5612 |
int vector_len = 0; |
5613 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5614 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5615 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5616 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5617 |
|
31410 | 5618 |
instruct vadd2S_mem(vecS dst, vecS src, memory mem) %{ |
5619 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
5620 |
match(Set dst (AddVS src (LoadVector mem))); |
|
5621 |
format %{ "vpaddw $dst,$src,$mem\t! add packed2S" %} |
|
5622 |
ins_encode %{ |
|
5623 |
int vector_len = 0; |
|
5624 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5625 |
%} |
|
5626 |
ins_pipe( pipe_slow ); |
|
5627 |
%} |
|
5628 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5629 |
instruct vadd4S(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5630 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5631 |
match(Set dst (AddVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5632 |
format %{ "paddw $dst,$src\t! add packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5633 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5634 |
__ paddw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5635 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5636 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5637 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5638 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5639 |
instruct vadd4S_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5640 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5641 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5642 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5643 |
ins_encode %{ |
30624 | 5644 |
int vector_len = 0; |
5645 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5646 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5647 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5648 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5649 |
|
31410 | 5650 |
instruct vadd4S_mem(vecD dst, vecD src, memory mem) %{ |
5651 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
|
5652 |
match(Set dst (AddVS src (LoadVector mem))); |
|
5653 |
format %{ "vpaddw $dst,$src,$mem\t! add packed4S" %} |
|
5654 |
ins_encode %{ |
|
5655 |
int vector_len = 0; |
|
5656 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5657 |
%} |
|
5658 |
ins_pipe( pipe_slow ); |
|
5659 |
%} |
|
5660 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5661 |
instruct vadd8S(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5662 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5663 |
match(Set dst (AddVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5664 |
format %{ "paddw $dst,$src\t! add packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5665 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5666 |
__ paddw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5667 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5668 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5669 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5670 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5671 |
instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5672 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5673 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5674 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5675 |
ins_encode %{ |
30624 | 5676 |
int vector_len = 0; |
5677 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5678 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5679 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5680 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5681 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5682 |
instruct vadd8S_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5683 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5684 |
match(Set dst (AddVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5685 |
format %{ "vpaddw $dst,$src,$mem\t! add packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5686 |
ins_encode %{ |
30624 | 5687 |
int vector_len = 0; |
5688 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5689 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5690 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5691 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5692 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5693 |
instruct vadd16S_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5694 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5695 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5696 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5697 |
ins_encode %{ |
30624 | 5698 |
int vector_len = 1; |
5699 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5700 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5701 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5702 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5703 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5704 |
instruct vadd16S_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5705 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5706 |
match(Set dst (AddVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5707 |
format %{ "vpaddw $dst,$src,$mem\t! add packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5708 |
ins_encode %{ |
30624 | 5709 |
int vector_len = 1; |
5710 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5711 |
%} |
|
5712 |
ins_pipe( pipe_slow ); |
|
5713 |
%} |
|
5714 |
||
5715 |
instruct vadd32S_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
5716 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
5717 |
match(Set dst (AddVS src1 src2)); |
|
5718 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed32S" %} |
|
5719 |
ins_encode %{ |
|
5720 |
int vector_len = 2; |
|
5721 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
5722 |
%} |
|
5723 |
ins_pipe( pipe_slow ); |
|
5724 |
%} |
|
5725 |
||
5726 |
instruct vadd32S_mem(vecZ dst, vecZ src, memory mem) %{ |
|
5727 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
5728 |
match(Set dst (AddVS src (LoadVector mem))); |
|
5729 |
format %{ "vpaddw $dst,$src,$mem\t! add packed32S" %} |
|
5730 |
ins_encode %{ |
|
5731 |
int vector_len = 2; |
|
5732 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5733 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5734 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5735 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5736 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5737 |
// Integers vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5738 |
instruct vadd2I(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5739 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5740 |
match(Set dst (AddVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5741 |
format %{ "paddd $dst,$src\t! add packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5742 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5743 |
__ paddd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5744 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5745 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5746 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5747 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5748 |
instruct vadd2I_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5749 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5750 |
match(Set dst (AddVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5751 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5752 |
ins_encode %{ |
30624 | 5753 |
int vector_len = 0; |
5754 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5755 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5756 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5757 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5758 |
|
31410 | 5759 |
instruct vadd2I_mem(vecD dst, vecD src, memory mem) %{ |
5760 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
5761 |
match(Set dst (AddVI src (LoadVector mem))); |
|
5762 |
format %{ "vpaddd $dst,$src,$mem\t! add packed2I" %} |
|
5763 |
ins_encode %{ |
|
5764 |
int vector_len = 0; |
|
5765 |
__ vpaddd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5766 |
%} |
|
5767 |
ins_pipe( pipe_slow ); |
|
5768 |
%} |
|
5769 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5770 |
instruct vadd4I(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5771 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5772 |
match(Set dst (AddVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5773 |
format %{ "paddd $dst,$src\t! add packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5774 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5775 |
__ paddd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5776 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5777 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5778 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5779 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5780 |
instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5781 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5782 |
match(Set dst (AddVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5783 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5784 |
ins_encode %{ |
30624 | 5785 |
int vector_len = 0; |
5786 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5787 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5788 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5789 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5790 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5791 |
instruct vadd4I_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5792 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5793 |
match(Set dst (AddVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5794 |
format %{ "vpaddd $dst,$src,$mem\t! add packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5795 |
ins_encode %{ |
30624 | 5796 |
int vector_len = 0; |
5797 |
__ vpaddd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5798 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5799 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5800 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5801 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5802 |
instruct vadd8I_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5803 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5804 |
match(Set dst (AddVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5805 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5806 |
ins_encode %{ |
30624 | 5807 |
int vector_len = 1; |
5808 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5809 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5810 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5811 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5812 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5813 |
instruct vadd8I_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5814 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5815 |
match(Set dst (AddVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5816 |
format %{ "vpaddd $dst,$src,$mem\t! add packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5817 |
ins_encode %{ |
30624 | 5818 |
int vector_len = 1; |
5819 |
__ vpaddd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5820 |
%} |
|
5821 |
ins_pipe( pipe_slow ); |
|
5822 |
%} |
|
5823 |
||
5824 |
instruct vadd16I_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
5825 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
5826 |
match(Set dst (AddVI src1 src2)); |
|
5827 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed16I" %} |
|
5828 |
ins_encode %{ |
|
5829 |
int vector_len = 2; |
|
5830 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
5831 |
%} |
|
5832 |
ins_pipe( pipe_slow ); |
|
5833 |
%} |
|
5834 |
||
5835 |
instruct vadd16I_mem(vecZ dst, vecZ src, memory mem) %{ |
|
5836 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
5837 |
match(Set dst (AddVI src (LoadVector mem))); |
|
5838 |
format %{ "vpaddd $dst,$src,$mem\t! add packed16I" %} |
|
5839 |
ins_encode %{ |
|
5840 |
int vector_len = 2; |
|
5841 |
__ vpaddd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5842 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5843 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5844 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5845 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5846 |
// Longs vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5847 |
instruct vadd2L(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5848 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5849 |
match(Set dst (AddVL dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5850 |
format %{ "paddq $dst,$src\t! add packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5851 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5852 |
__ paddq($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5853 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5854 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5855 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5856 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5857 |
instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5858 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5859 |
match(Set dst (AddVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5860 |
format %{ "vpaddq $dst,$src1,$src2\t! add packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5861 |
ins_encode %{ |
30624 | 5862 |
int vector_len = 0; |
5863 |
__ vpaddq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5864 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5865 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5866 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5867 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5868 |
instruct vadd2L_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5869 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5870 |
match(Set dst (AddVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5871 |
format %{ "vpaddq $dst,$src,$mem\t! add packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5872 |
ins_encode %{ |
30624 | 5873 |
int vector_len = 0; |
5874 |
__ vpaddq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5875 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5876 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5877 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5878 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5879 |
instruct vadd4L_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5880 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5881 |
match(Set dst (AddVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5882 |
format %{ "vpaddq $dst,$src1,$src2\t! add packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5883 |
ins_encode %{ |
30624 | 5884 |
int vector_len = 1; |
5885 |
__ vpaddq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5886 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5887 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5888 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5889 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5890 |
instruct vadd4L_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5891 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5892 |
match(Set dst (AddVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5893 |
format %{ "vpaddq $dst,$src,$mem\t! add packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5894 |
ins_encode %{ |
30624 | 5895 |
int vector_len = 1; |
5896 |
__ vpaddq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5897 |
%} |
|
5898 |
ins_pipe( pipe_slow ); |
|
5899 |
%} |
|
5900 |
||
5901 |
instruct vadd8L_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
5902 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
5903 |
match(Set dst (AddVL src1 src2)); |
|
5904 |
format %{ "vpaddq $dst,$src1,$src2\t! add packed8L" %} |
|
5905 |
ins_encode %{ |
|
5906 |
int vector_len = 2; |
|
5907 |
__ vpaddq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
5908 |
%} |
|
5909 |
ins_pipe( pipe_slow ); |
|
5910 |
%} |
|
5911 |
||
5912 |
instruct vadd8L_mem(vecZ dst, vecZ src, memory mem) %{ |
|
5913 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
5914 |
match(Set dst (AddVL src (LoadVector mem))); |
|
5915 |
format %{ "vpaddq $dst,$src,$mem\t! add packed8L" %} |
|
5916 |
ins_encode %{ |
|
5917 |
int vector_len = 2; |
|
5918 |
__ vpaddq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5919 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5920 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5921 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5922 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5923 |
// Floats vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5924 |
instruct vadd2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5925 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5926 |
match(Set dst (AddVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5927 |
format %{ "addps $dst,$src\t! add packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5928 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5929 |
__ addps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5930 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5931 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5932 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5933 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5934 |
instruct vadd2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5935 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5936 |
match(Set dst (AddVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5937 |
format %{ "vaddps $dst,$src1,$src2\t! add packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5938 |
ins_encode %{ |
30624 | 5939 |
int vector_len = 0; |
5940 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5941 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5942 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5943 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5944 |
|
31410 | 5945 |
instruct vadd2F_mem(vecD dst, vecD src, memory mem) %{ |
5946 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
5947 |
match(Set dst (AddVF src (LoadVector mem))); |
|
5948 |
format %{ "vaddps $dst,$src,$mem\t! add packed2F" %} |
|
5949 |
ins_encode %{ |
|
5950 |
int vector_len = 0; |
|
5951 |
__ vaddps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
5952 |
%} |
|
5953 |
ins_pipe( pipe_slow ); |
|
5954 |
%} |
|
5955 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5956 |
instruct vadd4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5957 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5958 |
match(Set dst (AddVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5959 |
format %{ "addps $dst,$src\t! add packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5960 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5961 |
__ addps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5962 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5963 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5964 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5965 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5966 |
instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5967 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5968 |
match(Set dst (AddVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5969 |
format %{ "vaddps $dst,$src1,$src2\t! add packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5970 |
ins_encode %{ |
30624 | 5971 |
int vector_len = 0; |
5972 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5973 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5974 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5975 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5976 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5977 |
instruct vadd4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5978 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5979 |
match(Set dst (AddVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5980 |
format %{ "vaddps $dst,$src,$mem\t! add packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5981 |
ins_encode %{ |
30624 | 5982 |
int vector_len = 0; |
5983 |
__ vaddps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5984 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5985 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5986 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5987 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5988 |
instruct vadd8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5989 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5990 |
match(Set dst (AddVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5991 |
format %{ "vaddps $dst,$src1,$src2\t! add packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5992 |
ins_encode %{ |
30624 | 5993 |
int vector_len = 1; |
5994 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5995 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5996 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5997 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5998 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5999 |
instruct vadd8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6000 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6001 |
match(Set dst (AddVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6002 |
format %{ "vaddps $dst,$src,$mem\t! add packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6003 |
ins_encode %{ |
30624 | 6004 |
int vector_len = 1; |
6005 |
__ vaddps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6006 |
%} |
|
6007 |
ins_pipe( pipe_slow ); |
|
6008 |
%} |
|
6009 |
||
6010 |
instruct vadd16F_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6011 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
6012 |
match(Set dst (AddVF src1 src2)); |
|
6013 |
format %{ "vaddps $dst,$src1,$src2\t! add packed16F" %} |
|
6014 |
ins_encode %{ |
|
6015 |
int vector_len = 2; |
|
6016 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6017 |
%} |
|
6018 |
ins_pipe( pipe_slow ); |
|
6019 |
%} |
|
6020 |
||
6021 |
instruct vadd16F_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6022 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
6023 |
match(Set dst (AddVF src (LoadVector mem))); |
|
6024 |
format %{ "vaddps $dst,$src,$mem\t! add packed16F" %} |
|
6025 |
ins_encode %{ |
|
6026 |
int vector_len = 2; |
|
6027 |
__ vaddps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6028 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6029 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6030 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6031 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6032 |
// Doubles vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6033 |
instruct vadd2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6034 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6035 |
match(Set dst (AddVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6036 |
format %{ "addpd $dst,$src\t! add packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6037 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6038 |
__ addpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6039 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6040 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6041 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6042 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6043 |
instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6044 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6045 |
match(Set dst (AddVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6046 |
format %{ "vaddpd $dst,$src1,$src2\t! add packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6047 |
ins_encode %{ |
30624 | 6048 |
int vector_len = 0; |
6049 |
__ vaddpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6050 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6051 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6052 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6053 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6054 |
instruct vadd2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6055 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6056 |
match(Set dst (AddVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6057 |
format %{ "vaddpd $dst,$src,$mem\t! add packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6058 |
ins_encode %{ |
30624 | 6059 |
int vector_len = 0; |
6060 |
__ vaddpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6061 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6062 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6063 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6064 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6065 |
instruct vadd4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6066 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6067 |
match(Set dst (AddVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6068 |
format %{ "vaddpd $dst,$src1,$src2\t! add packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6069 |
ins_encode %{ |
30624 | 6070 |
int vector_len = 1; |
6071 |
__ vaddpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6072 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6073 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6074 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6075 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6076 |
instruct vadd4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6077 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6078 |
match(Set dst (AddVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6079 |
format %{ "vaddpd $dst,$src,$mem\t! add packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6080 |
ins_encode %{ |
30624 | 6081 |
int vector_len = 1; |
6082 |
__ vaddpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6083 |
%} |
|
6084 |
ins_pipe( pipe_slow ); |
|
6085 |
%} |
|
6086 |
||
6087 |
instruct vadd8D_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6088 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
6089 |
match(Set dst (AddVD src1 src2)); |
|
6090 |
format %{ "vaddpd $dst,$src1,$src2\t! add packed8D" %} |
|
6091 |
ins_encode %{ |
|
6092 |
int vector_len = 2; |
|
6093 |
__ vaddpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6094 |
%} |
|
6095 |
ins_pipe( pipe_slow ); |
|
6096 |
%} |
|
6097 |
||
6098 |
instruct vadd8D_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6099 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
6100 |
match(Set dst (AddVD src (LoadVector mem))); |
|
6101 |
format %{ "vaddpd $dst,$src,$mem\t! add packed8D" %} |
|
6102 |
ins_encode %{ |
|
6103 |
int vector_len = 2; |
|
6104 |
__ vaddpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6105 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6106 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6107 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6108 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6109 |
// --------------------------------- SUB -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6110 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6111 |
// Bytes vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6112 |
instruct vsub4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6113 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6114 |
match(Set dst (SubVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6115 |
format %{ "psubb $dst,$src\t! sub packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6116 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6117 |
__ psubb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6118 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6119 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6120 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6121 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6122 |
instruct vsub4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6123 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6124 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6125 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6126 |
ins_encode %{ |
30624 | 6127 |
int vector_len = 0; |
6128 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6129 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6130 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6131 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6132 |
|
31410 | 6133 |
instruct vsub4B_mem(vecS dst, vecS src, memory mem) %{ |
6134 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
|
6135 |
match(Set dst (SubVB src (LoadVector mem))); |
|
6136 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed4B" %} |
|
6137 |
ins_encode %{ |
|
6138 |
int vector_len = 0; |
|
6139 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6140 |
%} |
|
6141 |
ins_pipe( pipe_slow ); |
|
6142 |
%} |
|
6143 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6144 |
instruct vsub8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6145 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6146 |
match(Set dst (SubVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6147 |
format %{ "psubb $dst,$src\t! sub packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6148 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6149 |
__ psubb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6150 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6151 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6152 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6153 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6154 |
instruct vsub8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6155 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6156 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6157 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6158 |
ins_encode %{ |
30624 | 6159 |
int vector_len = 0; |
6160 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6161 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6162 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6163 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6164 |
|
31410 | 6165 |
instruct vsub8B_mem(vecD dst, vecD src, memory mem) %{ |
6166 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
|
6167 |
match(Set dst (SubVB src (LoadVector mem))); |
|
6168 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed8B" %} |
|
6169 |
ins_encode %{ |
|
6170 |
int vector_len = 0; |
|
6171 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6172 |
%} |
|
6173 |
ins_pipe( pipe_slow ); |
|
6174 |
%} |
|
6175 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6176 |
instruct vsub16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6177 |
predicate(n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6178 |
match(Set dst (SubVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6179 |
format %{ "psubb $dst,$src\t! sub packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6180 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6181 |
__ psubb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6182 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6183 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6184 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6185 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6186 |
instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6187 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6188 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6189 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6190 |
ins_encode %{ |
30624 | 6191 |
int vector_len = 0; |
6192 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6193 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6194 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6195 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6196 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6197 |
instruct vsub16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6198 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6199 |
match(Set dst (SubVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6200 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6201 |
ins_encode %{ |
30624 | 6202 |
int vector_len = 0; |
6203 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6204 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6205 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6206 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6207 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6208 |
instruct vsub32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6209 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6210 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6211 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6212 |
ins_encode %{ |
30624 | 6213 |
int vector_len = 1; |
6214 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6215 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6216 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6217 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6218 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6219 |
instruct vsub32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6220 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6221 |
match(Set dst (SubVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6222 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6223 |
ins_encode %{ |
30624 | 6224 |
int vector_len = 1; |
6225 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6226 |
%} |
|
6227 |
ins_pipe( pipe_slow ); |
|
6228 |
%} |
|
6229 |
||
6230 |
instruct vsub64B_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6231 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 64); |
|
6232 |
match(Set dst (SubVB src1 src2)); |
|
6233 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed64B" %} |
|
6234 |
ins_encode %{ |
|
6235 |
int vector_len = 2; |
|
6236 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6237 |
%} |
|
6238 |
ins_pipe( pipe_slow ); |
|
6239 |
%} |
|
6240 |
||
6241 |
instruct vsub64B_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6242 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 64); |
|
6243 |
match(Set dst (SubVB src (LoadVector mem))); |
|
6244 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed64B" %} |
|
6245 |
ins_encode %{ |
|
6246 |
int vector_len = 2; |
|
6247 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6248 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6249 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6250 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6251 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6252 |
// Shorts/Chars vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6253 |
instruct vsub2S(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6254 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6255 |
match(Set dst (SubVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6256 |
format %{ "psubw $dst,$src\t! sub packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6257 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6258 |
__ psubw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6259 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6260 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6261 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6262 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6263 |
instruct vsub2S_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6264 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6265 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6266 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6267 |
ins_encode %{ |
30624 | 6268 |
int vector_len = 0; |
6269 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6270 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6271 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6272 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6273 |
|
31410 | 6274 |
instruct vsub2S_mem(vecS dst, vecS src, memory mem) %{ |
6275 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
6276 |
match(Set dst (SubVS src (LoadVector mem))); |
|
6277 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed2S" %} |
|
6278 |
ins_encode %{ |
|
6279 |
int vector_len = 0; |
|
6280 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6281 |
%} |
|
6282 |
ins_pipe( pipe_slow ); |
|
6283 |
%} |
|
6284 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6285 |
instruct vsub4S(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6286 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6287 |
match(Set dst (SubVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6288 |
format %{ "psubw $dst,$src\t! sub packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6289 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6290 |
__ psubw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6291 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6292 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6293 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6294 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6295 |
instruct vsub4S_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6296 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6297 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6298 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6299 |
ins_encode %{ |
30624 | 6300 |
int vector_len = 0; |
6301 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6302 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6303 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6304 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6305 |
|
31410 | 6306 |
instruct vsub4S_mem(vecD dst, vecD src, memory mem) %{ |
6307 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
|
6308 |
match(Set dst (SubVS src (LoadVector mem))); |
|
6309 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed4S" %} |
|
6310 |
ins_encode %{ |
|
6311 |
int vector_len = 0; |
|
6312 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6313 |
%} |
|
6314 |
ins_pipe( pipe_slow ); |
|
6315 |
%} |
|
6316 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6317 |
instruct vsub8S(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6318 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6319 |
match(Set dst (SubVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6320 |
format %{ "psubw $dst,$src\t! sub packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6321 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6322 |
__ psubw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6323 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6324 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6325 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6326 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6327 |
instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6328 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6329 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6330 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6331 |
ins_encode %{ |
30624 | 6332 |
int vector_len = 0; |
6333 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6334 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6335 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6336 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6337 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6338 |
instruct vsub8S_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6339 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6340 |
match(Set dst (SubVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6341 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6342 |
ins_encode %{ |
30624 | 6343 |
int vector_len = 0; |
6344 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6345 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6346 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6347 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6348 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6349 |
instruct vsub16S_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6350 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6351 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6352 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6353 |
ins_encode %{ |
30624 | 6354 |
int vector_len = 1; |
6355 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6356 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6357 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6358 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6359 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6360 |
instruct vsub16S_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6361 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6362 |
match(Set dst (SubVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6363 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6364 |
ins_encode %{ |
30624 | 6365 |
int vector_len = 1; |
6366 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6367 |
%} |
|
6368 |
ins_pipe( pipe_slow ); |
|
6369 |
%} |
|
6370 |
||
6371 |
instruct vsub32S_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6372 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
6373 |
match(Set dst (SubVS src1 src2)); |
|
6374 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed32S" %} |
|
6375 |
ins_encode %{ |
|
6376 |
int vector_len = 2; |
|
6377 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6378 |
%} |
|
6379 |
ins_pipe( pipe_slow ); |
|
6380 |
%} |
|
6381 |
||
6382 |
instruct vsub32S_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6383 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
6384 |
match(Set dst (SubVS src (LoadVector mem))); |
|
6385 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed32S" %} |
|
6386 |
ins_encode %{ |
|
6387 |
int vector_len = 2; |
|
6388 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6389 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6390 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6391 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6392 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6393 |
// Integers vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6394 |
instruct vsub2I(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6395 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6396 |
match(Set dst (SubVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6397 |
format %{ "psubd $dst,$src\t! sub packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6398 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6399 |
__ psubd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6400 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6401 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6402 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6403 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6404 |
instruct vsub2I_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6405 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6406 |
match(Set dst (SubVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6407 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6408 |
ins_encode %{ |
30624 | 6409 |
int vector_len = 0; |
6410 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6411 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6412 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6413 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6414 |
|
31410 | 6415 |
instruct vsub2I_mem(vecD dst, vecD src, memory mem) %{ |
6416 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
6417 |
match(Set dst (SubVI src (LoadVector mem))); |
|
6418 |
format %{ "vpsubd $dst,$src,$mem\t! sub packed2I" %} |
|
6419 |
ins_encode %{ |
|
6420 |
int vector_len = 0; |
|
6421 |
__ vpsubd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6422 |
%} |
|
6423 |
ins_pipe( pipe_slow ); |
|
6424 |
%} |
|
6425 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6426 |
instruct vsub4I(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6427 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6428 |
match(Set dst (SubVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6429 |
format %{ "psubd $dst,$src\t! sub packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6430 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6431 |
__ psubd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6432 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6433 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6434 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6435 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6436 |
instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6437 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6438 |
match(Set dst (SubVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6439 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6440 |
ins_encode %{ |
30624 | 6441 |
int vector_len = 0; |
6442 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6443 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6444 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6445 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6446 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6447 |
instruct vsub4I_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6448 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6449 |
match(Set dst (SubVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6450 |
format %{ "vpsubd $dst,$src,$mem\t! sub packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6451 |
ins_encode %{ |
30624 | 6452 |
int vector_len = 0; |
6453 |
__ vpsubd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6454 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6455 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6456 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6457 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6458 |
instruct vsub8I_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6459 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6460 |
match(Set dst (SubVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6461 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6462 |
ins_encode %{ |
30624 | 6463 |
int vector_len = 1; |
6464 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6465 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6466 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6467 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6468 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6469 |
instruct vsub8I_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6470 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6471 |
match(Set dst (SubVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6472 |
format %{ "vpsubd $dst,$src,$mem\t! sub packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6473 |
ins_encode %{ |
30624 | 6474 |
int vector_len = 1; |
6475 |
__ vpsubd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6476 |
%} |
|
6477 |
ins_pipe( pipe_slow ); |
|
6478 |
%} |
|
6479 |
||
6480 |
instruct vsub16I_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6481 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
6482 |
match(Set dst (SubVI src1 src2)); |
|
6483 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed16I" %} |
|
6484 |
ins_encode %{ |
|
6485 |
int vector_len = 2; |
|
6486 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6487 |
%} |
|
6488 |
ins_pipe( pipe_slow ); |
|
6489 |
%} |
|
6490 |
||
6491 |
instruct vsub16I_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6492 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
6493 |
match(Set dst (SubVI src (LoadVector mem))); |
|
6494 |
format %{ "vpsubd $dst,$src,$mem\t! sub packed16I" %} |
|
6495 |
ins_encode %{ |
|
6496 |
int vector_len = 2; |
|
6497 |
__ vpsubd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6498 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6499 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6500 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6501 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6502 |
// Longs vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6503 |
instruct vsub2L(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6504 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6505 |
match(Set dst (SubVL dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6506 |
format %{ "psubq $dst,$src\t! sub packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6507 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6508 |
__ psubq($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6509 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6510 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6511 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6512 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6513 |
instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6514 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6515 |
match(Set dst (SubVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6516 |
format %{ "vpsubq $dst,$src1,$src2\t! sub packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6517 |
ins_encode %{ |
30624 | 6518 |
int vector_len = 0; |
6519 |
__ vpsubq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6520 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6521 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6522 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6523 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6524 |
instruct vsub2L_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6525 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6526 |
match(Set dst (SubVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6527 |
format %{ "vpsubq $dst,$src,$mem\t! sub packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6528 |
ins_encode %{ |
30624 | 6529 |
int vector_len = 0; |
6530 |
__ vpsubq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6531 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6532 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6533 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6534 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6535 |
instruct vsub4L_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6536 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6537 |
match(Set dst (SubVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6538 |
format %{ "vpsubq $dst,$src1,$src2\t! sub packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6539 |
ins_encode %{ |
30624 | 6540 |
int vector_len = 1; |
6541 |
__ vpsubq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6542 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6543 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6544 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6545 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6546 |
instruct vsub4L_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6547 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6548 |
match(Set dst (SubVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6549 |
format %{ "vpsubq $dst,$src,$mem\t! sub packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6550 |
ins_encode %{ |
30624 | 6551 |
int vector_len = 1; |
6552 |
__ vpsubq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6553 |
%} |
|
6554 |
ins_pipe( pipe_slow ); |
|
6555 |
%} |
|
6556 |
||
6557 |
instruct vsub8L_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6558 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
6559 |
match(Set dst (SubVL src1 src2)); |
|
6560 |
format %{ "vpsubq $dst,$src1,$src2\t! sub packed8L" %} |
|
6561 |
ins_encode %{ |
|
6562 |
int vector_len = 2; |
|
6563 |
__ vpsubq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6564 |
%} |
|
6565 |
ins_pipe( pipe_slow ); |
|
6566 |
%} |
|
6567 |
||
6568 |
instruct vsub8L_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6569 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
6570 |
match(Set dst (SubVL src (LoadVector mem))); |
|
6571 |
format %{ "vpsubq $dst,$src,$mem\t! sub packed8L" %} |
|
6572 |
ins_encode %{ |
|
6573 |
int vector_len = 2; |
|
6574 |
__ vpsubq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6575 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6576 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6577 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6578 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6579 |
// Floats vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6580 |
instruct vsub2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6581 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6582 |
match(Set dst (SubVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6583 |
format %{ "subps $dst,$src\t! sub packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6584 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6585 |
__ subps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6586 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6587 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6588 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6589 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6590 |
instruct vsub2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6591 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6592 |
match(Set dst (SubVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6593 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6594 |
ins_encode %{ |
30624 | 6595 |
int vector_len = 0; |
6596 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6597 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6598 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6599 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6600 |
|
31410 | 6601 |
instruct vsub2F_mem(vecD dst, vecD src, memory mem) %{ |
6602 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
6603 |
match(Set dst (SubVF src (LoadVector mem))); |
|
6604 |
format %{ "vsubps $dst,$src,$mem\t! sub packed2F" %} |
|
6605 |
ins_encode %{ |
|
6606 |
int vector_len = 0; |
|
6607 |
__ vsubps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6608 |
%} |
|
6609 |
ins_pipe( pipe_slow ); |
|
6610 |
%} |
|
6611 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6612 |
instruct vsub4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6613 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6614 |
match(Set dst (SubVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6615 |
format %{ "subps $dst,$src\t! sub packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6616 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6617 |
__ subps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6618 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6619 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6620 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6621 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6622 |
instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6623 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6624 |
match(Set dst (SubVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6625 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6626 |
ins_encode %{ |
30624 | 6627 |
int vector_len = 0; |
6628 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6629 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6630 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6631 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6632 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6633 |
instruct vsub4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6634 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6635 |
match(Set dst (SubVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6636 |
format %{ "vsubps $dst,$src,$mem\t! sub packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6637 |
ins_encode %{ |
30624 | 6638 |
int vector_len = 0; |
6639 |
__ vsubps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6640 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6641 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6642 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6643 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6644 |
instruct vsub8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6645 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6646 |
match(Set dst (SubVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6647 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6648 |
ins_encode %{ |
30624 | 6649 |
int vector_len = 1; |
6650 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6651 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6652 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6653 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6654 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6655 |
instruct vsub8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6656 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6657 |
match(Set dst (SubVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6658 |
format %{ "vsubps $dst,$src,$mem\t! sub packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6659 |
ins_encode %{ |
30624 | 6660 |
int vector_len = 1; |
6661 |
__ vsubps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6662 |
%} |
|
6663 |
ins_pipe( pipe_slow ); |
|
6664 |
%} |
|
6665 |
||
6666 |
instruct vsub16F_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6667 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
6668 |
match(Set dst (SubVF src1 src2)); |
|
6669 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed16F" %} |
|
6670 |
ins_encode %{ |
|
6671 |
int vector_len = 2; |
|
6672 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6673 |
%} |
|
6674 |
ins_pipe( pipe_slow ); |
|
6675 |
%} |
|
6676 |
||
6677 |
instruct vsub16F_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6678 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
6679 |
match(Set dst (SubVF src (LoadVector mem))); |
|
6680 |
format %{ "vsubps $dst,$src,$mem\t! sub packed16F" %} |
|
6681 |
ins_encode %{ |
|
6682 |
int vector_len = 2; |
|
6683 |
__ vsubps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6684 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6685 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6686 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6687 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6688 |
// Doubles vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6689 |
instruct vsub2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6690 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6691 |
match(Set dst (SubVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6692 |
format %{ "subpd $dst,$src\t! sub packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6693 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6694 |
__ subpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6695 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6696 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6697 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6698 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6699 |
instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6700 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6701 |
match(Set dst (SubVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6702 |
format %{ "vsubpd $dst,$src1,$src2\t! sub packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6703 |
ins_encode %{ |
30624 | 6704 |
int vector_len = 0; |
6705 |
__ vsubpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6706 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6707 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6708 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6709 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6710 |
instruct vsub2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6711 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6712 |
match(Set dst (SubVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6713 |
format %{ "vsubpd $dst,$src,$mem\t! sub packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6714 |
ins_encode %{ |
30624 | 6715 |
int vector_len = 0; |
6716 |
__ vsubpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6717 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6718 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6719 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6720 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6721 |
instruct vsub4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6722 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6723 |
match(Set dst (SubVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6724 |
format %{ "vsubpd $dst,$src1,$src2\t! sub packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6725 |
ins_encode %{ |
30624 | 6726 |
int vector_len = 1; |
6727 |
__ vsubpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6728 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6729 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6730 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6731 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6732 |
instruct vsub4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6733 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6734 |
match(Set dst (SubVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6735 |
format %{ "vsubpd $dst,$src,$mem\t! sub packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6736 |
ins_encode %{ |
30624 | 6737 |
int vector_len = 1; |
6738 |
__ vsubpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6739 |
%} |
|
6740 |
ins_pipe( pipe_slow ); |
|
6741 |
%} |
|
6742 |
||
6743 |
instruct vsub8D_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6744 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
6745 |
match(Set dst (SubVD src1 src2)); |
|
6746 |
format %{ "vsubpd $dst,$src1,$src2\t! sub packed8D" %} |
|
6747 |
ins_encode %{ |
|
6748 |
int vector_len = 2; |
|
6749 |
__ vsubpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6750 |
%} |
|
6751 |
ins_pipe( pipe_slow ); |
|
6752 |
%} |
|
6753 |
||
6754 |
instruct vsub8D_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6755 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
6756 |
match(Set dst (SubVD src (LoadVector mem))); |
|
6757 |
format %{ "vsubpd $dst,$src,$mem\t! sub packed8D" %} |
|
6758 |
ins_encode %{ |
|
6759 |
int vector_len = 2; |
|
6760 |
__ vsubpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6761 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6762 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6763 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6764 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6765 |
// --------------------------------- MUL -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6766 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6767 |
// Shorts/Chars vector mul |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6768 |
instruct vmul2S(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6769 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6770 |
match(Set dst (MulVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6771 |
format %{ "pmullw $dst,$src\t! mul packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6772 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6773 |
__ pmullw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6774 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6775 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6776 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6777 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6778 |
instruct vmul2S_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6779 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6780 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6781 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6782 |
ins_encode %{ |
30624 | 6783 |
int vector_len = 0; |
6784 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6785 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6786 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6787 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6788 |
|
31410 | 6789 |
instruct vmul2S_mem(vecS dst, vecS src, memory mem) %{ |
6790 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
6791 |
match(Set dst (MulVS src (LoadVector mem))); |
|
6792 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed2S" %} |
|
6793 |
ins_encode %{ |
|
6794 |
int vector_len = 0; |
|
6795 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6796 |
%} |
|
6797 |
ins_pipe( pipe_slow ); |
|
6798 |
%} |
|
6799 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6800 |
instruct vmul4S(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6801 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6802 |
match(Set dst (MulVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6803 |
format %{ "pmullw $dst,$src\t! mul packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6804 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6805 |
__ pmullw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6806 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6807 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6808 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6809 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6810 |
instruct vmul4S_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6811 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6812 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6813 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6814 |
ins_encode %{ |
30624 | 6815 |
int vector_len = 0; |
6816 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6817 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6818 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6819 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6820 |
|
31410 | 6821 |
instruct vmul4S_mem(vecD dst, vecD src, memory mem) %{ |
6822 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
|
6823 |
match(Set dst (MulVS src (LoadVector mem))); |
|
6824 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed4S" %} |
|
6825 |
ins_encode %{ |
|
6826 |
int vector_len = 0; |
|
6827 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6828 |
%} |
|
6829 |
ins_pipe( pipe_slow ); |
|
6830 |
%} |
|
6831 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6832 |
instruct vmul8S(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6833 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6834 |
match(Set dst (MulVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6835 |
format %{ "pmullw $dst,$src\t! mul packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6836 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6837 |
__ pmullw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6838 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6839 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6840 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6841 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6842 |
instruct vmul8S_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6843 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6844 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6845 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6846 |
ins_encode %{ |
30624 | 6847 |
int vector_len = 0; |
6848 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6849 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6850 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6851 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6852 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6853 |
instruct vmul8S_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6854 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6855 |
match(Set dst (MulVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6856 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6857 |
ins_encode %{ |
30624 | 6858 |
int vector_len = 0; |
6859 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6860 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6861 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6862 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6863 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6864 |
instruct vmul16S_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6865 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6866 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6867 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6868 |
ins_encode %{ |
30624 | 6869 |
int vector_len = 1; |
6870 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6871 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6872 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6873 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6874 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6875 |
instruct vmul16S_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6876 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6877 |
match(Set dst (MulVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6878 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6879 |
ins_encode %{ |
30624 | 6880 |
int vector_len = 1; |
6881 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6882 |
%} |
|
6883 |
ins_pipe( pipe_slow ); |
|
6884 |
%} |
|
6885 |
||
6886 |
instruct vmul32S_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
6887 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
6888 |
match(Set dst (MulVS src1 src2)); |
|
6889 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed32S" %} |
|
6890 |
ins_encode %{ |
|
6891 |
int vector_len = 2; |
|
6892 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6893 |
%} |
|
6894 |
ins_pipe( pipe_slow ); |
|
6895 |
%} |
|
6896 |
||
6897 |
instruct vmul32S_mem(vecZ dst, vecZ src, memory mem) %{ |
|
6898 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
6899 |
match(Set dst (MulVS src (LoadVector mem))); |
|
6900 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed32S" %} |
|
6901 |
ins_encode %{ |
|
6902 |
int vector_len = 2; |
|
6903 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6904 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6905 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6906 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6907 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6908 |
// Integers vector mul (sse4_1) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6909 |
instruct vmul2I(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6910 |
predicate(UseSSE > 3 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6911 |
match(Set dst (MulVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6912 |
format %{ "pmulld $dst,$src\t! mul packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6913 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6914 |
__ pmulld($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6915 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6916 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6917 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6918 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6919 |
instruct vmul2I_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6920 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6921 |
match(Set dst (MulVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6922 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6923 |
ins_encode %{ |
30624 | 6924 |
int vector_len = 0; |
6925 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6926 |
%} |
|
6927 |
ins_pipe( pipe_slow ); |
|
6928 |
%} |
|
6929 |
||
31410 | 6930 |
instruct vmul2I_mem(vecD dst, vecD src, memory mem) %{ |
6931 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
6932 |
match(Set dst (MulVI src (LoadVector mem))); |
|
6933 |
format %{ "vpmulld $dst,$src,$mem\t! mul packed2I" %} |
|
6934 |
ins_encode %{ |
|
6935 |
int vector_len = 0; |
|
6936 |
__ vpmulld($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6937 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6938 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6939 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6940 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6941 |
instruct vmul4I(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6942 |
predicate(UseSSE > 3 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6943 |
match(Set dst (MulVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6944 |
format %{ "pmulld $dst,$src\t! mul packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6945 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6946 |
__ pmulld($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6947 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6948 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6949 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6950 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6951 |
instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6952 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6953 |
match(Set dst (MulVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6954 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6955 |
ins_encode %{ |
30624 | 6956 |
int vector_len = 0; |
6957 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6958 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6959 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6960 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6961 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6962 |
instruct vmul4I_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6963 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6964 |
match(Set dst (MulVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6965 |
format %{ "vpmulld $dst,$src,$mem\t! mul packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
6966 |
ins_encode %{ |
30624 | 6967 |
int vector_len = 0; |
6968 |
__ vpmulld($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6969 |
%} |
|
6970 |
ins_pipe( pipe_slow ); |
|
6971 |
%} |
|
6972 |
||
31410 | 6973 |
instruct vmul2L_reg(vecX dst, vecX src1, vecX src2) %{ |
6974 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 2 && VM_Version::supports_avx512dq()); |
|
6975 |
match(Set dst (MulVL src1 src2)); |
|
6976 |
format %{ "vpmullq $dst,$src1,$src2\t! mul packed2L" %} |
|
6977 |
ins_encode %{ |
|
6978 |
int vector_len = 0; |
|
6979 |
__ vpmullq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
6980 |
%} |
|
6981 |
ins_pipe( pipe_slow ); |
|
6982 |
%} |
|
6983 |
||
6984 |
instruct vmul2L_mem(vecX dst, vecX src, memory mem) %{ |
|
6985 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 2 && VM_Version::supports_avx512dq()); |
|
6986 |
match(Set dst (MulVL src (LoadVector mem))); |
|
6987 |
format %{ "vpmullq $dst,$src,$mem\t! mul packed2L" %} |
|
6988 |
ins_encode %{ |
|
6989 |
int vector_len = 0; |
|
6990 |
__ vpmullq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
6991 |
%} |
|
6992 |
ins_pipe( pipe_slow ); |
|
6993 |
%} |
|
6994 |
||
30624 | 6995 |
instruct vmul4L_reg(vecY dst, vecY src1, vecY src2) %{ |
6996 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 4 && VM_Version::supports_avx512dq()); |
|
6997 |
match(Set dst (MulVL src1 src2)); |
|
6998 |
format %{ "vpmullq $dst,$src1,$src2\t! mul packed4L" %} |
|
6999 |
ins_encode %{ |
|
7000 |
int vector_len = 1; |
|
7001 |
__ vpmullq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
7002 |
%} |
|
7003 |
ins_pipe( pipe_slow ); |
|
7004 |
%} |
|
7005 |
||
7006 |
instruct vmul4L_mem(vecY dst, vecY src, memory mem) %{ |
|
7007 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 4 && VM_Version::supports_avx512dq()); |
|
7008 |
match(Set dst (MulVL src (LoadVector mem))); |
|
7009 |
format %{ "vpmullq $dst,$src,$mem\t! mul packed4L" %} |
|
7010 |
ins_encode %{ |
|
7011 |
int vector_len = 1; |
|
7012 |
__ vpmullq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7013 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7014 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7015 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7016 |
|
30624 | 7017 |
instruct vmul8L_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
7018 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && VM_Version::supports_avx512dq()); |
|
7019 |
match(Set dst (MulVL src1 src2)); |
|
7020 |
format %{ "vpmullq $dst,$src1,$src2\t! mul packed8L" %} |
|
7021 |
ins_encode %{ |
|
7022 |
int vector_len = 2; |
|
7023 |
__ vpmullq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
7024 |
%} |
|
7025 |
ins_pipe( pipe_slow ); |
|
7026 |
%} |
|
7027 |
||
31410 | 7028 |
instruct vmul8L_mem(vecZ dst, vecZ src, memory mem) %{ |
7029 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && VM_Version::supports_avx512dq()); |
|
7030 |
match(Set dst (MulVL src (LoadVector mem))); |
|
7031 |
format %{ "vpmullq $dst,$src,$mem\t! mul packed8L" %} |
|
30624 | 7032 |
ins_encode %{ |
7033 |
int vector_len = 2; |
|
31410 | 7034 |
__ vpmullq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
7035 |
%} |
|
7036 |
ins_pipe( pipe_slow ); |
|
7037 |
%} |
|
7038 |
||
7039 |
instruct vmul8I_reg(vecY dst, vecY src1, vecY src2) %{ |
|
7040 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
|
7041 |
match(Set dst (MulVI src1 src2)); |
|
7042 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed8I" %} |
|
7043 |
ins_encode %{ |
|
7044 |
int vector_len = 1; |
|
30624 | 7045 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7046 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7047 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7048 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7049 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7050 |
instruct vmul8I_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7051 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7052 |
match(Set dst (MulVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7053 |
format %{ "vpmulld $dst,$src,$mem\t! mul packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7054 |
ins_encode %{ |
30624 | 7055 |
int vector_len = 1; |
7056 |
__ vpmulld($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7057 |
%} |
|
7058 |
ins_pipe( pipe_slow ); |
|
7059 |
%} |
|
7060 |
||
31410 | 7061 |
instruct vmul16I_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
7062 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
7063 |
match(Set dst (MulVI src1 src2)); |
|
7064 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed16I" %} |
|
30624 | 7065 |
ins_encode %{ |
7066 |
int vector_len = 2; |
|
31410 | 7067 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
30624 | 7068 |
%} |
7069 |
ins_pipe( pipe_slow ); |
|
7070 |
%} |
|
7071 |
||
7072 |
instruct vmul16I_mem(vecZ dst, vecZ src, memory mem) %{ |
|
7073 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
7074 |
match(Set dst (MulVI src (LoadVector mem))); |
|
7075 |
format %{ "vpmulld $dst,$src,$mem\t! mul packed16I" %} |
|
7076 |
ins_encode %{ |
|
7077 |
int vector_len = 2; |
|
7078 |
__ vpmulld($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7079 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7080 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7081 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7082 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7083 |
// Floats vector mul |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7084 |
instruct vmul2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7085 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7086 |
match(Set dst (MulVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7087 |
format %{ "mulps $dst,$src\t! mul packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7088 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7089 |
__ mulps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7090 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7091 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7092 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7093 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7094 |
instruct vmul2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7095 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7096 |
match(Set dst (MulVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7097 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7098 |
ins_encode %{ |
30624 | 7099 |
int vector_len = 0; |
7100 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7101 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7102 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7103 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7104 |
|
31410 | 7105 |
instruct vmul2F_mem(vecD dst, vecD src, memory mem) %{ |
7106 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
7107 |
match(Set dst (MulVF src (LoadVector mem))); |
|
7108 |
format %{ "vmulps $dst,$src,$mem\t! mul packed2F" %} |
|
7109 |
ins_encode %{ |
|
7110 |
int vector_len = 0; |
|
7111 |
__ vmulps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7112 |
%} |
|
7113 |
ins_pipe( pipe_slow ); |
|
7114 |
%} |
|
7115 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7116 |
instruct vmul4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7117 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7118 |
match(Set dst (MulVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7119 |
format %{ "mulps $dst,$src\t! mul packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7120 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7121 |
__ mulps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7122 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7123 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7124 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7125 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7126 |
instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7127 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7128 |
match(Set dst (MulVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7129 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7130 |
ins_encode %{ |
30624 | 7131 |
int vector_len = 0; |
7132 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7133 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7134 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7135 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7136 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7137 |
instruct vmul4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7138 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7139 |
match(Set dst (MulVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7140 |
format %{ "vmulps $dst,$src,$mem\t! mul packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7141 |
ins_encode %{ |
30624 | 7142 |
int vector_len = 0; |
7143 |
__ vmulps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7144 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7145 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7146 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7147 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7148 |
instruct vmul8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7149 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7150 |
match(Set dst (MulVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7151 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7152 |
ins_encode %{ |
30624 | 7153 |
int vector_len = 1; |
7154 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7155 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7156 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7157 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7158 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7159 |
instruct vmul8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7160 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7161 |
match(Set dst (MulVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7162 |
format %{ "vmulps $dst,$src,$mem\t! mul packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7163 |
ins_encode %{ |
30624 | 7164 |
int vector_len = 1; |
7165 |
__ vmulps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7166 |
%} |
|
7167 |
ins_pipe( pipe_slow ); |
|
7168 |
%} |
|
7169 |
||
7170 |
instruct vmul16F_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
7171 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
7172 |
match(Set dst (MulVF src1 src2)); |
|
7173 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed16F" %} |
|
7174 |
ins_encode %{ |
|
7175 |
int vector_len = 2; |
|
7176 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
7177 |
%} |
|
7178 |
ins_pipe( pipe_slow ); |
|
7179 |
%} |
|
7180 |
||
7181 |
instruct vmul16F_mem(vecZ dst, vecZ src, memory mem) %{ |
|
7182 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
7183 |
match(Set dst (MulVF src (LoadVector mem))); |
|
7184 |
format %{ "vmulps $dst,$src,$mem\t! mul packed16F" %} |
|
7185 |
ins_encode %{ |
|
7186 |
int vector_len = 2; |
|
7187 |
__ vmulps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7188 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7189 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7190 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7191 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7192 |
// Doubles vector mul |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7193 |
instruct vmul2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7194 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7195 |
match(Set dst (MulVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7196 |
format %{ "mulpd $dst,$src\t! mul packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7197 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7198 |
__ mulpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7199 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7200 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7201 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7202 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7203 |
instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7204 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7205 |
match(Set dst (MulVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7206 |
format %{ "vmulpd $dst,$src1,$src2\t! mul packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7207 |
ins_encode %{ |
30624 | 7208 |
int vector_len = 0; |
7209 |
__ vmulpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7210 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7211 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7212 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7213 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7214 |
instruct vmul2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7215 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7216 |
match(Set dst (MulVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7217 |
format %{ "vmulpd $dst,$src,$mem\t! mul packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7218 |
ins_encode %{ |
30624 | 7219 |
int vector_len = 0; |
7220 |
__ vmulpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7221 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7222 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7223 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7224 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7225 |
instruct vmul4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7226 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7227 |
match(Set dst (MulVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7228 |
format %{ "vmulpd $dst,$src1,$src2\t! mul packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7229 |
ins_encode %{ |
30624 | 7230 |
int vector_len = 1; |
7231 |
__ vmulpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7232 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7233 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7234 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7235 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7236 |
instruct vmul4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7237 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7238 |
match(Set dst (MulVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7239 |
format %{ "vmulpd $dst,$src,$mem\t! mul packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7240 |
ins_encode %{ |
30624 | 7241 |
int vector_len = 1; |
7242 |
__ vmulpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7243 |
%} |
|
7244 |
ins_pipe( pipe_slow ); |
|
7245 |
%} |
|
7246 |
||
7247 |
instruct vmul8D_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
7248 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
7249 |
match(Set dst (MulVD src1 src2)); |
|
7250 |
format %{ "vmulpd $dst k0,$src1,$src2\t! mul packed8D" %} |
|
7251 |
ins_encode %{ |
|
7252 |
int vector_len = 2; |
|
7253 |
__ vmulpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
7254 |
%} |
|
7255 |
ins_pipe( pipe_slow ); |
|
7256 |
%} |
|
7257 |
||
7258 |
instruct vmul8D_mem(vecZ dst, vecZ src, memory mem) %{ |
|
7259 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
7260 |
match(Set dst (MulVD src (LoadVector mem))); |
|
7261 |
format %{ "vmulpd $dst k0,$src,$mem\t! mul packed8D" %} |
|
7262 |
ins_encode %{ |
|
7263 |
int vector_len = 2; |
|
7264 |
__ vmulpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7265 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7266 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7267 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7268 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7269 |
// --------------------------------- DIV -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7270 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7271 |
// Floats vector div |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7272 |
instruct vdiv2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7273 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7274 |
match(Set dst (DivVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7275 |
format %{ "divps $dst,$src\t! div packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7276 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7277 |
__ divps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7278 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7279 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7280 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7281 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7282 |
instruct vdiv2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7283 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7284 |
match(Set dst (DivVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7285 |
format %{ "vdivps $dst,$src1,$src2\t! div packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7286 |
ins_encode %{ |
30624 | 7287 |
int vector_len = 0; |
7288 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7289 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7290 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7291 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7292 |
|
31410 | 7293 |
instruct vdiv2F_mem(vecD dst, vecD src, memory mem) %{ |
7294 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
|
7295 |
match(Set dst (DivVF src (LoadVector mem))); |
|
7296 |
format %{ "vdivps $dst,$src,$mem\t! div packed2F" %} |
|
7297 |
ins_encode %{ |
|
7298 |
int vector_len = 0; |
|
7299 |
__ vdivps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7300 |
%} |
|
7301 |
ins_pipe( pipe_slow ); |
|
7302 |
%} |
|
7303 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7304 |
instruct vdiv4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7305 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7306 |
match(Set dst (DivVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7307 |
format %{ "divps $dst,$src\t! div packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7308 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7309 |
__ divps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7310 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7311 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7312 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7313 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7314 |
instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7315 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7316 |
match(Set dst (DivVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7317 |
format %{ "vdivps $dst,$src1,$src2\t! div packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7318 |
ins_encode %{ |
30624 | 7319 |
int vector_len = 0; |
7320 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7321 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7322 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7323 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7324 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7325 |
instruct vdiv4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7326 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7327 |
match(Set dst (DivVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7328 |
format %{ "vdivps $dst,$src,$mem\t! div packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7329 |
ins_encode %{ |
30624 | 7330 |
int vector_len = 0; |
7331 |
__ vdivps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7332 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7333 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7334 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7335 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7336 |
instruct vdiv8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7337 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7338 |
match(Set dst (DivVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7339 |
format %{ "vdivps $dst,$src1,$src2\t! div packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7340 |
ins_encode %{ |
30624 | 7341 |
int vector_len = 1; |
7342 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7343 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7344 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7345 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7346 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7347 |
instruct vdiv8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7348 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7349 |
match(Set dst (DivVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7350 |
format %{ "vdivps $dst,$src,$mem\t! div packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7351 |
ins_encode %{ |
30624 | 7352 |
int vector_len = 1; |
7353 |
__ vdivps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7354 |
%} |
|
7355 |
ins_pipe( pipe_slow ); |
|
7356 |
%} |
|
7357 |
||
7358 |
instruct vdiv16F_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
7359 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
|
7360 |
match(Set dst (DivVF src1 src2)); |
|
7361 |
format %{ "vdivps $dst,$src1,$src2\t! div packed16F" %} |
|
7362 |
ins_encode %{ |
|
7363 |
int vector_len = 2; |
|
7364 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
7365 |
%} |
|
7366 |
ins_pipe( pipe_slow ); |
|
7367 |
%} |
|
7368 |
||
7369 |
instruct vdiv16F_mem(vecZ dst, vecZ src, memory mem) %{ |
|
7370 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
|
7371 |
match(Set dst (DivVF src (LoadVector mem))); |
|
7372 |
format %{ "vdivps $dst,$src,$mem\t! div packed16F" %} |
|
7373 |
ins_encode %{ |
|
7374 |
int vector_len = 2; |
|
7375 |
__ vdivps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7376 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7377 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7378 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7379 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7380 |
// Doubles vector div |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7381 |
instruct vdiv2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7382 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7383 |
match(Set dst (DivVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7384 |
format %{ "divpd $dst,$src\t! div packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7385 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7386 |
__ divpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7387 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7388 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7389 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7390 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7391 |
instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7392 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7393 |
match(Set dst (DivVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7394 |
format %{ "vdivpd $dst,$src1,$src2\t! div packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7395 |
ins_encode %{ |
30624 | 7396 |
int vector_len = 0; |
7397 |
__ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7398 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7399 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7400 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7401 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7402 |
instruct vdiv2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7403 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7404 |
match(Set dst (DivVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7405 |
format %{ "vdivpd $dst,$src,$mem\t! div packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7406 |
ins_encode %{ |
30624 | 7407 |
int vector_len = 0; |
7408 |
__ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7409 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7410 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7411 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7412 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7413 |
instruct vdiv4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7414 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7415 |
match(Set dst (DivVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7416 |
format %{ "vdivpd $dst,$src1,$src2\t! div packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7417 |
ins_encode %{ |
30624 | 7418 |
int vector_len = 1; |
7419 |
__ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7420 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7421 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7422 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7423 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7424 |
instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7425 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7426 |
match(Set dst (DivVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7427 |
format %{ "vdivpd $dst,$src,$mem\t! div packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7428 |
ins_encode %{ |
30624 | 7429 |
int vector_len = 1; |
7430 |
__ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
7431 |
%} |
|
7432 |
ins_pipe( pipe_slow ); |
|
7433 |
%} |
|
7434 |
||
7435 |
instruct vdiv8D_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
7436 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
7437 |
match(Set dst (DivVD src1 src2)); |
|
7438 |
format %{ "vdivpd $dst,$src1,$src2\t! div packed8D" %} |
|
7439 |
ins_encode %{ |
|
7440 |
int vector_len = 2; |
|
7441 |
__ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
7442 |
%} |
|
7443 |
ins_pipe( pipe_slow ); |
|
7444 |
%} |
|
7445 |
||
7446 |
instruct vdiv8D_mem(vecZ dst, vecZ src, memory mem) %{ |
|
7447 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
7448 |
match(Set dst (DivVD src (LoadVector mem))); |
|
7449 |
format %{ "vdivpd $dst,$src,$mem\t! div packed8D" %} |
|
7450 |
ins_encode %{ |
|
7451 |
int vector_len = 2; |
|
7452 |
__ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7453 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7454 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7455 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7456 |
|
13930 | 7457 |
// ------------------------------ Shift --------------------------------------- |
7458 |
||
7459 |
// Left and right shift count vectors are the same on x86 |
|
7460 |
// (only lowest bits of xmm reg are used for count). |
|
7461 |
instruct vshiftcnt(vecS dst, rRegI cnt) %{ |
|
7462 |
match(Set dst (LShiftCntV cnt)); |
|
7463 |
match(Set dst (RShiftCntV cnt)); |
|
7464 |
format %{ "movd $dst,$cnt\t! load shift count" %} |
|
7465 |
ins_encode %{ |
|
7466 |
__ movdl($dst$$XMMRegister, $cnt$$Register); |
|
7467 |
%} |
|
7468 |
ins_pipe( pipe_slow ); |
|
7469 |
%} |
|
7470 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7471 |
// ------------------------------ LeftShift ----------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7472 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7473 |
// Shorts/Chars vector left shift |
13930 | 7474 |
instruct vsll2S(vecS dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7475 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7476 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7477 |
format %{ "psllw $dst,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7478 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7479 |
__ psllw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7480 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7481 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7482 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7483 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7484 |
instruct vsll2S_imm(vecS dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7485 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7486 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7487 |
format %{ "psllw $dst,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7488 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7489 |
__ psllw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7490 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7491 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7492 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7493 |
|
13930 | 7494 |
instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7495 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7496 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7497 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7498 |
ins_encode %{ |
30624 | 7499 |
int vector_len = 0; |
7500 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7501 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7502 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7503 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7504 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7505 |
instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7506 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7507 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7508 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7509 |
ins_encode %{ |
30624 | 7510 |
int vector_len = 0; |
7511 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7512 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7513 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7514 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7515 |
|
13930 | 7516 |
instruct vsll4S(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7517 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7518 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7519 |
format %{ "psllw $dst,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7520 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7521 |
__ psllw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7522 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7523 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7524 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7525 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7526 |
instruct vsll4S_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7527 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7528 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7529 |
format %{ "psllw $dst,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7530 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7531 |
__ psllw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7532 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7533 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7534 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7535 |
|
13930 | 7536 |
instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7537 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7538 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7539 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7540 |
ins_encode %{ |
30624 | 7541 |
int vector_len = 0; |
7542 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7543 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7544 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7545 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7546 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7547 |
instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7548 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7549 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7550 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7551 |
ins_encode %{ |
30624 | 7552 |
int vector_len = 0; |
7553 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7554 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7555 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7556 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7557 |
|
13930 | 7558 |
instruct vsll8S(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7559 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7560 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7561 |
format %{ "psllw $dst,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7562 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7563 |
__ psllw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7564 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7565 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7566 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7567 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7568 |
instruct vsll8S_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7569 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7570 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7571 |
format %{ "psllw $dst,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7572 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7573 |
__ psllw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7574 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7575 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7576 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7577 |
|
13930 | 7578 |
instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7579 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7580 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7581 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7582 |
ins_encode %{ |
30624 | 7583 |
int vector_len = 0; |
7584 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7585 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7586 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7587 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7588 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7589 |
instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7590 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7591 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7592 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7593 |
ins_encode %{ |
30624 | 7594 |
int vector_len = 0; |
7595 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7596 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7597 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7598 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7599 |
|
13930 | 7600 |
instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7601 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7602 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7603 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7604 |
ins_encode %{ |
30624 | 7605 |
int vector_len = 1; |
7606 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7607 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7608 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7609 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7610 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7611 |
instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7612 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7613 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7614 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7615 |
ins_encode %{ |
30624 | 7616 |
int vector_len = 1; |
7617 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
7618 |
%} |
|
7619 |
ins_pipe( pipe_slow ); |
|
7620 |
%} |
|
7621 |
||
7622 |
instruct vsll32S_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
7623 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
7624 |
match(Set dst (LShiftVS src shift)); |
|
7625 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed32S" %} |
|
7626 |
ins_encode %{ |
|
7627 |
int vector_len = 2; |
|
7628 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
7629 |
%} |
|
7630 |
ins_pipe( pipe_slow ); |
|
7631 |
%} |
|
7632 |
||
7633 |
instruct vsll32S_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
7634 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
7635 |
match(Set dst (LShiftVS src shift)); |
|
7636 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed32S" %} |
|
7637 |
ins_encode %{ |
|
7638 |
int vector_len = 2; |
|
7639 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7640 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7641 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7642 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7643 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7644 |
// Integers vector left shift |
13930 | 7645 |
instruct vsll2I(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7646 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7647 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7648 |
format %{ "pslld $dst,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7649 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7650 |
__ pslld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7651 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7652 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7653 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7654 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7655 |
instruct vsll2I_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7656 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7657 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7658 |
format %{ "pslld $dst,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7659 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7660 |
__ pslld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7661 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7662 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7663 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7664 |
|
13930 | 7665 |
instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7666 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7667 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7668 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7669 |
ins_encode %{ |
30624 | 7670 |
int vector_len = 0; |
7671 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7672 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7673 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7674 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7675 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7676 |
instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7677 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7678 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7679 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7680 |
ins_encode %{ |
30624 | 7681 |
int vector_len = 0; |
7682 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7683 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7684 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7685 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7686 |
|
13930 | 7687 |
instruct vsll4I(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7688 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7689 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7690 |
format %{ "pslld $dst,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7691 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7692 |
__ pslld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7693 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7694 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7695 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7696 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7697 |
instruct vsll4I_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7698 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7699 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7700 |
format %{ "pslld $dst,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7701 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7702 |
__ pslld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7703 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7704 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7705 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7706 |
|
13930 | 7707 |
instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7708 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7709 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7710 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7711 |
ins_encode %{ |
30624 | 7712 |
int vector_len = 0; |
7713 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7714 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7715 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7716 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7717 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7718 |
instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7719 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7720 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7721 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7722 |
ins_encode %{ |
30624 | 7723 |
int vector_len = 0; |
7724 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7725 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7726 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7727 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7728 |
|
13930 | 7729 |
instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7730 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7731 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7732 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7733 |
ins_encode %{ |
30624 | 7734 |
int vector_len = 1; |
7735 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7736 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7737 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7738 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7739 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7740 |
instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7741 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7742 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7743 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7744 |
ins_encode %{ |
30624 | 7745 |
int vector_len = 1; |
7746 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
7747 |
%} |
|
7748 |
ins_pipe( pipe_slow ); |
|
7749 |
%} |
|
7750 |
||
7751 |
instruct vsll16I_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
7752 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
7753 |
match(Set dst (LShiftVI src shift)); |
|
7754 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed16I" %} |
|
7755 |
ins_encode %{ |
|
7756 |
int vector_len = 2; |
|
7757 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
7758 |
%} |
|
7759 |
ins_pipe( pipe_slow ); |
|
7760 |
%} |
|
7761 |
||
7762 |
instruct vsll16I_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
7763 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
7764 |
match(Set dst (LShiftVI src shift)); |
|
7765 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed16I" %} |
|
7766 |
ins_encode %{ |
|
7767 |
int vector_len = 2; |
|
7768 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7769 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7770 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7771 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7772 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7773 |
// Longs vector left shift |
13930 | 7774 |
instruct vsll2L(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7775 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7776 |
match(Set dst (LShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7777 |
format %{ "psllq $dst,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7778 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7779 |
__ psllq($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7780 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7781 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7782 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7783 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7784 |
instruct vsll2L_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7785 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7786 |
match(Set dst (LShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7787 |
format %{ "psllq $dst,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7788 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7789 |
__ psllq($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7790 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7791 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7792 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7793 |
|
13930 | 7794 |
instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7795 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7796 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7797 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7798 |
ins_encode %{ |
30624 | 7799 |
int vector_len = 0; |
7800 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7801 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7802 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7803 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7804 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7805 |
instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7806 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7807 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7808 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7809 |
ins_encode %{ |
30624 | 7810 |
int vector_len = 0; |
7811 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7812 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7813 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7814 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7815 |
|
13930 | 7816 |
instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7817 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7818 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7819 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7820 |
ins_encode %{ |
30624 | 7821 |
int vector_len = 1; |
7822 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7823 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7824 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7825 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7826 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7827 |
instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7828 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7829 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7830 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7831 |
ins_encode %{ |
30624 | 7832 |
int vector_len = 1; |
7833 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
7834 |
%} |
|
7835 |
ins_pipe( pipe_slow ); |
|
7836 |
%} |
|
7837 |
||
7838 |
instruct vsll8L_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
7839 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
7840 |
match(Set dst (LShiftVL src shift)); |
|
7841 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed8L" %} |
|
7842 |
ins_encode %{ |
|
7843 |
int vector_len = 2; |
|
7844 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
7845 |
%} |
|
7846 |
ins_pipe( pipe_slow ); |
|
7847 |
%} |
|
7848 |
||
7849 |
instruct vsll8L_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
7850 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
7851 |
match(Set dst (LShiftVL src shift)); |
|
7852 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed8L" %} |
|
7853 |
ins_encode %{ |
|
7854 |
int vector_len = 2; |
|
7855 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7856 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7857 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7858 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7859 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7860 |
// ----------------------- LogicalRightShift ----------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7861 |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7862 |
// Shorts vector logical right shift produces incorrect Java result |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
7863 |
// for negative data because java code convert short value into int with |
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7864 |
// sign extension before a shift. But char vectors are fine since chars are |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7865 |
// unsigned values. |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7866 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7867 |
instruct vsrl2S(vecS dst, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7868 |
predicate(n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7869 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7870 |
format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7871 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7872 |
__ psrlw($dst$$XMMRegister, $shift$$XMMRegister); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7873 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7874 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7875 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7876 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7877 |
instruct vsrl2S_imm(vecS dst, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7878 |
predicate(n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7879 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7880 |
format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7881 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7882 |
__ psrlw($dst$$XMMRegister, (int)$shift$$constant); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7883 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7884 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7885 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7886 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7887 |
instruct vsrl2S_reg(vecS dst, vecS src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7888 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7889 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7890 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7891 |
ins_encode %{ |
30624 | 7892 |
int vector_len = 0; |
7893 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7894 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7895 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7896 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7897 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7898 |
instruct vsrl2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7899 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7900 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7901 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7902 |
ins_encode %{ |
30624 | 7903 |
int vector_len = 0; |
7904 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7905 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7906 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7907 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7908 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7909 |
instruct vsrl4S(vecD dst, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7910 |
predicate(n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7911 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7912 |
format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7913 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7914 |
__ psrlw($dst$$XMMRegister, $shift$$XMMRegister); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7915 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7916 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7917 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7918 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7919 |
instruct vsrl4S_imm(vecD dst, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7920 |
predicate(n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7921 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7922 |
format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7923 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7924 |
__ psrlw($dst$$XMMRegister, (int)$shift$$constant); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7925 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7926 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7927 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7928 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7929 |
instruct vsrl4S_reg(vecD dst, vecD src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7930 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7931 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7932 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7933 |
ins_encode %{ |
30624 | 7934 |
int vector_len = 0; |
7935 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7936 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7937 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7938 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7939 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7940 |
instruct vsrl4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7941 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7942 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7943 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7944 |
ins_encode %{ |
30624 | 7945 |
int vector_len = 0; |
7946 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7947 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7948 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7949 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7950 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7951 |
instruct vsrl8S(vecX dst, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7952 |
predicate(n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7953 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7954 |
format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7955 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7956 |
__ psrlw($dst$$XMMRegister, $shift$$XMMRegister); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7957 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7958 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7959 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7960 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7961 |
instruct vsrl8S_imm(vecX dst, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7962 |
predicate(n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7963 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7964 |
format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7965 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7966 |
__ psrlw($dst$$XMMRegister, (int)$shift$$constant); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7967 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7968 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7969 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7970 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7971 |
instruct vsrl8S_reg(vecX dst, vecX src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7972 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7973 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7974 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7975 |
ins_encode %{ |
30624 | 7976 |
int vector_len = 0; |
7977 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7978 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7979 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7980 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7981 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7982 |
instruct vsrl8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7983 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7984 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7985 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7986 |
ins_encode %{ |
30624 | 7987 |
int vector_len = 0; |
7988 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7989 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7990 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7991 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7992 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7993 |
instruct vsrl16S_reg(vecY dst, vecY src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7994 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7995 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7996 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
7997 |
ins_encode %{ |
30624 | 7998 |
int vector_len = 1; |
7999 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8000 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8001 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8002 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8003 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8004 |
instruct vsrl16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8005 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8006 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8007 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8008 |
ins_encode %{ |
30624 | 8009 |
int vector_len = 1; |
8010 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
8011 |
%} |
|
8012 |
ins_pipe( pipe_slow ); |
|
8013 |
%} |
|
8014 |
||
8015 |
instruct vsrl32S_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
8016 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
8017 |
match(Set dst (URShiftVS src shift)); |
|
8018 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed32S" %} |
|
8019 |
ins_encode %{ |
|
8020 |
int vector_len = 2; |
|
8021 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
8022 |
%} |
|
8023 |
ins_pipe( pipe_slow ); |
|
8024 |
%} |
|
8025 |
||
8026 |
instruct vsrl32S_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
8027 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
8028 |
match(Set dst (URShiftVS src shift)); |
|
8029 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed32S" %} |
|
8030 |
ins_encode %{ |
|
8031 |
int vector_len = 2; |
|
8032 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8033 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8034 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
8035 |
%} |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8036 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8037 |
// Integers vector logical right shift |
13930 | 8038 |
instruct vsrl2I(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8039 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8040 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8041 |
format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8042 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8043 |
__ psrld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8044 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8045 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8046 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8047 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8048 |
instruct vsrl2I_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8049 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8050 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8051 |
format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8052 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8053 |
__ psrld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8054 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8055 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8056 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8057 |
|
13930 | 8058 |
instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8059 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8060 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8061 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8062 |
ins_encode %{ |
30624 | 8063 |
int vector_len = 0; |
8064 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8065 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8066 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8067 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8068 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8069 |
instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8070 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8071 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8072 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8073 |
ins_encode %{ |
30624 | 8074 |
int vector_len = 0; |
8075 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8076 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8077 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8078 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8079 |
|
13930 | 8080 |
instruct vsrl4I(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8081 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8082 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8083 |
format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8084 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8085 |
__ psrld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8086 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8087 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8088 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8089 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8090 |
instruct vsrl4I_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8091 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8092 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8093 |
format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8094 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8095 |
__ psrld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8096 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8097 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8098 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8099 |
|
13930 | 8100 |
instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8101 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8102 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8103 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8104 |
ins_encode %{ |
30624 | 8105 |
int vector_len = 0; |
8106 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8107 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8108 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8109 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8110 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8111 |
instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8112 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8113 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8114 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8115 |
ins_encode %{ |
30624 | 8116 |
int vector_len = 0; |
8117 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8118 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8119 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8120 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8121 |
|
13930 | 8122 |
instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8123 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8124 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8125 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8126 |
ins_encode %{ |
30624 | 8127 |
int vector_len = 1; |
8128 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8129 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8130 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8131 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8132 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8133 |
instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8134 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8135 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8136 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8137 |
ins_encode %{ |
30624 | 8138 |
int vector_len = 1; |
8139 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
8140 |
%} |
|
8141 |
ins_pipe( pipe_slow ); |
|
8142 |
%} |
|
8143 |
||
8144 |
instruct vsrl16I_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
8145 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
8146 |
match(Set dst (URShiftVI src shift)); |
|
8147 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed16I" %} |
|
8148 |
ins_encode %{ |
|
8149 |
int vector_len = 2; |
|
8150 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
8151 |
%} |
|
8152 |
ins_pipe( pipe_slow ); |
|
8153 |
%} |
|
8154 |
||
8155 |
instruct vsrl16I_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
8156 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
8157 |
match(Set dst (URShiftVI src shift)); |
|
8158 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed16I" %} |
|
8159 |
ins_encode %{ |
|
8160 |
int vector_len = 2; |
|
8161 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8162 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8163 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8164 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8165 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8166 |
// Longs vector logical right shift |
13930 | 8167 |
instruct vsrl2L(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8168 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8169 |
match(Set dst (URShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8170 |
format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8171 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8172 |
__ psrlq($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8173 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8174 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8175 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8176 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8177 |
instruct vsrl2L_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8178 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8179 |
match(Set dst (URShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8180 |
format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8181 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8182 |
__ psrlq($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8183 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8184 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8185 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8186 |
|
13930 | 8187 |
instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8188 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8189 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8190 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8191 |
ins_encode %{ |
30624 | 8192 |
int vector_len = 0; |
8193 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8194 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8195 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8196 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8197 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8198 |
instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8199 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8200 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8201 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8202 |
ins_encode %{ |
30624 | 8203 |
int vector_len = 0; |
8204 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8205 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8206 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8207 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8208 |
|
13930 | 8209 |
instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8210 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8211 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8212 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8213 |
ins_encode %{ |
30624 | 8214 |
int vector_len = 1; |
8215 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8216 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8217 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8218 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8219 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8220 |
instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8221 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8222 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8223 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8224 |
ins_encode %{ |
30624 | 8225 |
int vector_len = 1; |
8226 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
8227 |
%} |
|
8228 |
ins_pipe( pipe_slow ); |
|
8229 |
%} |
|
8230 |
||
8231 |
instruct vsrl8L_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
8232 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
8233 |
match(Set dst (URShiftVL src shift)); |
|
8234 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed8L" %} |
|
8235 |
ins_encode %{ |
|
8236 |
int vector_len = 2; |
|
8237 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
8238 |
%} |
|
8239 |
ins_pipe( pipe_slow ); |
|
8240 |
%} |
|
8241 |
||
8242 |
instruct vsrl8L_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
8243 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 8); |
|
8244 |
match(Set dst (URShiftVL src shift)); |
|
8245 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed8L" %} |
|
8246 |
ins_encode %{ |
|
8247 |
int vector_len = 2; |
|
8248 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8249 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8250 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8251 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8252 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8253 |
// ------------------- ArithmeticRightShift ----------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8254 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8255 |
// Shorts/Chars vector arithmetic right shift |
13930 | 8256 |
instruct vsra2S(vecS dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8257 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8258 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8259 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8260 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8261 |
__ psraw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8262 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8263 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8264 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8265 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8266 |
instruct vsra2S_imm(vecS dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8267 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8268 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8269 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8270 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8271 |
__ psraw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8272 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8273 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8274 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8275 |
|
13930 | 8276 |
instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8277 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8278 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8279 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8280 |
ins_encode %{ |
30624 | 8281 |
int vector_len = 0; |
8282 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8283 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8284 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8285 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8286 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8287 |
instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8288 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8289 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8290 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8291 |
ins_encode %{ |
30624 | 8292 |
int vector_len = 0; |
8293 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8294 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8295 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8296 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8297 |
|
13930 | 8298 |
instruct vsra4S(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8299 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8300 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8301 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8302 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8303 |
__ psraw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8304 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8305 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8306 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8307 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8308 |
instruct vsra4S_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8309 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8310 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8311 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8312 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8313 |
__ psraw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8314 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8315 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8316 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8317 |
|
13930 | 8318 |
instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8319 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8320 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8321 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8322 |
ins_encode %{ |
30624 | 8323 |
int vector_len = 0; |
8324 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8325 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8326 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8327 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8328 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8329 |
instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8330 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8331 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8332 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8333 |
ins_encode %{ |
30624 | 8334 |
int vector_len = 0; |
8335 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8336 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8337 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8338 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8339 |
|
13930 | 8340 |
instruct vsra8S(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8341 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8342 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8343 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8344 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8345 |
__ psraw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8346 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8347 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8348 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8349 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8350 |
instruct vsra8S_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8351 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8352 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8353 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8354 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8355 |
__ psraw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8356 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8357 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8358 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8359 |
|
13930 | 8360 |
instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8361 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8362 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8363 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8364 |
ins_encode %{ |
30624 | 8365 |
int vector_len = 0; |
8366 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8367 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8368 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8369 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8370 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8371 |
instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8372 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8373 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8374 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8375 |
ins_encode %{ |
30624 | 8376 |
int vector_len = 0; |
8377 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8378 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8379 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8380 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8381 |
|
13930 | 8382 |
instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8383 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8384 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8385 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8386 |
ins_encode %{ |
30624 | 8387 |
int vector_len = 1; |
8388 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8389 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8390 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8391 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8392 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8393 |
instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8394 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8395 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8396 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8397 |
ins_encode %{ |
30624 | 8398 |
int vector_len = 1; |
8399 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
8400 |
%} |
|
8401 |
ins_pipe( pipe_slow ); |
|
8402 |
%} |
|
8403 |
||
8404 |
instruct vsra32S_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
8405 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
8406 |
match(Set dst (RShiftVS src shift)); |
|
8407 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed32S" %} |
|
8408 |
ins_encode %{ |
|
8409 |
int vector_len = 2; |
|
8410 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
8411 |
%} |
|
8412 |
ins_pipe( pipe_slow ); |
|
8413 |
%} |
|
8414 |
||
8415 |
instruct vsra32S_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
8416 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 32); |
|
8417 |
match(Set dst (RShiftVS src shift)); |
|
8418 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed32S" %} |
|
8419 |
ins_encode %{ |
|
8420 |
int vector_len = 2; |
|
8421 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8422 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8423 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8424 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8425 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8426 |
// Integers vector arithmetic right shift |
13930 | 8427 |
instruct vsra2I(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8428 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8429 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8430 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8431 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8432 |
__ psrad($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8433 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8434 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8435 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8436 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8437 |
instruct vsra2I_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8438 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8439 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8440 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8441 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8442 |
__ psrad($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8443 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8444 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8445 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8446 |
|
13930 | 8447 |
instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8448 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8449 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8450 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8451 |
ins_encode %{ |
30624 | 8452 |
int vector_len = 0; |
8453 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8454 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8455 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8456 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8457 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8458 |
instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8459 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8460 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8461 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8462 |
ins_encode %{ |
30624 | 8463 |
int vector_len = 0; |
8464 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8465 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8466 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8467 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8468 |
|
13930 | 8469 |
instruct vsra4I(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8470 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8471 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8472 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8473 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8474 |
__ psrad($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8475 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8476 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8477 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8478 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8479 |
instruct vsra4I_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8480 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8481 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8482 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8483 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8484 |
__ psrad($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8485 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8486 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8487 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8488 |
|
13930 | 8489 |
instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8490 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8491 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8492 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8493 |
ins_encode %{ |
30624 | 8494 |
int vector_len = 0; |
8495 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8496 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8497 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8498 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8499 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8500 |
instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8501 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8502 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8503 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8504 |
ins_encode %{ |
30624 | 8505 |
int vector_len = 0; |
8506 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8507 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8508 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8509 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8510 |
|
13930 | 8511 |
instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8512 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8513 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8514 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8515 |
ins_encode %{ |
30624 | 8516 |
int vector_len = 1; |
8517 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8518 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8519 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8520 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8521 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8522 |
instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8523 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8524 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8525 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8526 |
ins_encode %{ |
30624 | 8527 |
int vector_len = 1; |
8528 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
8529 |
%} |
|
8530 |
ins_pipe( pipe_slow ); |
|
8531 |
%} |
|
8532 |
||
8533 |
instruct vsra16I_reg(vecZ dst, vecZ src, vecS shift) %{ |
|
8534 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
8535 |
match(Set dst (RShiftVI src shift)); |
|
8536 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed16I" %} |
|
8537 |
ins_encode %{ |
|
8538 |
int vector_len = 2; |
|
8539 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); |
|
8540 |
%} |
|
8541 |
ins_pipe( pipe_slow ); |
|
8542 |
%} |
|
8543 |
||
8544 |
instruct vsra16I_reg_imm(vecZ dst, vecZ src, immI8 shift) %{ |
|
8545 |
predicate(UseAVX > 2 && n->as_Vector()->length() == 16); |
|
8546 |
match(Set dst (RShiftVI src shift)); |
|
8547 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed16I" %} |
|
8548 |
ins_encode %{ |
|
8549 |
int vector_len = 2; |
|
8550 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8551 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8552 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8553 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8554 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8555 |
// There are no longs vector arithmetic right shift instructions. |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8556 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8557 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8558 |
// --------------------------------- AND -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8559 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8560 |
instruct vand4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8561 |
predicate(n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8562 |
match(Set dst (AndV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8563 |
format %{ "pand $dst,$src\t! and vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8564 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8565 |
__ pand($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8566 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8567 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8568 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8569 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8570 |
instruct vand4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8571 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8572 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8573 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8574 |
ins_encode %{ |
30624 | 8575 |
int vector_len = 0; |
8576 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8577 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8578 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8579 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8580 |
|
31410 | 8581 |
instruct vand4B_mem(vecS dst, vecS src, memory mem) %{ |
8582 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
|
8583 |
match(Set dst (AndV src (LoadVector mem))); |
|
8584 |
format %{ "vpand $dst,$src,$mem\t! and vectors (4 bytes)" %} |
|
8585 |
ins_encode %{ |
|
8586 |
int vector_len = 0; |
|
8587 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8588 |
%} |
|
8589 |
ins_pipe( pipe_slow ); |
|
8590 |
%} |
|
8591 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8592 |
instruct vand8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8593 |
predicate(n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8594 |
match(Set dst (AndV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8595 |
format %{ "pand $dst,$src\t! and vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8596 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8597 |
__ pand($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8598 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8599 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8600 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8601 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8602 |
instruct vand8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8603 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8604 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8605 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8606 |
ins_encode %{ |
30624 | 8607 |
int vector_len = 0; |
8608 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8609 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8610 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8611 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8612 |
|
31410 | 8613 |
instruct vand8B_mem(vecD dst, vecD src, memory mem) %{ |
8614 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
|
8615 |
match(Set dst (AndV src (LoadVector mem))); |
|
8616 |
format %{ "vpand $dst,$src,$mem\t! and vectors (8 bytes)" %} |
|
8617 |
ins_encode %{ |
|
8618 |
int vector_len = 0; |
|
8619 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8620 |
%} |
|
8621 |
ins_pipe( pipe_slow ); |
|
8622 |
%} |
|
8623 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8624 |
instruct vand16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8625 |
predicate(n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8626 |
match(Set dst (AndV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8627 |
format %{ "pand $dst,$src\t! and vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8628 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8629 |
__ pand($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8630 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8631 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8632 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8633 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8634 |
instruct vand16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8635 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8636 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8637 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8638 |
ins_encode %{ |
30624 | 8639 |
int vector_len = 0; |
8640 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8641 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8642 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8643 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8644 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8645 |
instruct vand16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8646 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8647 |
match(Set dst (AndV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8648 |
format %{ "vpand $dst,$src,$mem\t! and vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8649 |
ins_encode %{ |
30624 | 8650 |
int vector_len = 0; |
8651 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8652 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8653 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8654 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8655 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8656 |
instruct vand32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8657 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8658 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8659 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8660 |
ins_encode %{ |
30624 | 8661 |
int vector_len = 1; |
8662 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8663 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8664 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8665 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8666 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8667 |
instruct vand32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8668 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8669 |
match(Set dst (AndV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8670 |
format %{ "vpand $dst,$src,$mem\t! and vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8671 |
ins_encode %{ |
30624 | 8672 |
int vector_len = 1; |
8673 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8674 |
%} |
|
8675 |
ins_pipe( pipe_slow ); |
|
8676 |
%} |
|
8677 |
||
8678 |
instruct vand64B_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
8679 |
predicate(UseAVX > 2 && n->as_Vector()->length_in_bytes() == 64); |
|
8680 |
match(Set dst (AndV src1 src2)); |
|
8681 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (64 bytes)" %} |
|
8682 |
ins_encode %{ |
|
8683 |
int vector_len = 2; |
|
8684 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
8685 |
%} |
|
8686 |
ins_pipe( pipe_slow ); |
|
8687 |
%} |
|
8688 |
||
8689 |
instruct vand64B_mem(vecZ dst, vecZ src, memory mem) %{ |
|
8690 |
predicate(UseAVX > 2 && n->as_Vector()->length_in_bytes() == 64); |
|
8691 |
match(Set dst (AndV src (LoadVector mem))); |
|
8692 |
format %{ "vpand $dst,$src,$mem\t! and vectors (64 bytes)" %} |
|
8693 |
ins_encode %{ |
|
8694 |
int vector_len = 2; |
|
8695 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8696 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8697 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8698 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8699 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8700 |
// --------------------------------- OR --------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8701 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8702 |
instruct vor4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8703 |
predicate(n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8704 |
match(Set dst (OrV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8705 |
format %{ "por $dst,$src\t! or vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8706 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8707 |
__ por($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8708 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8709 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8710 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8711 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8712 |
instruct vor4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8713 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8714 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8715 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8716 |
ins_encode %{ |
30624 | 8717 |
int vector_len = 0; |
8718 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8719 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8720 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8721 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8722 |
|
31410 | 8723 |
instruct vor4B_mem(vecS dst, vecS src, memory mem) %{ |
8724 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
|
8725 |
match(Set dst (OrV src (LoadVector mem))); |
|
8726 |
format %{ "vpor $dst,$src,$mem\t! or vectors (4 bytes)" %} |
|
8727 |
ins_encode %{ |
|
8728 |
int vector_len = 0; |
|
8729 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8730 |
%} |
|
8731 |
ins_pipe( pipe_slow ); |
|
8732 |
%} |
|
8733 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8734 |
instruct vor8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8735 |
predicate(n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8736 |
match(Set dst (OrV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8737 |
format %{ "por $dst,$src\t! or vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8738 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8739 |
__ por($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8740 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8741 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8742 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8743 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8744 |
instruct vor8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8745 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8746 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8747 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8748 |
ins_encode %{ |
30624 | 8749 |
int vector_len = 0; |
8750 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8751 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8752 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8753 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8754 |
|
31410 | 8755 |
instruct vor8B_mem(vecD dst, vecD src, memory mem) %{ |
8756 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
|
8757 |
match(Set dst (OrV src (LoadVector mem))); |
|
8758 |
format %{ "vpor $dst,$src,$mem\t! or vectors (8 bytes)" %} |
|
8759 |
ins_encode %{ |
|
8760 |
int vector_len = 0; |
|
8761 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8762 |
%} |
|
8763 |
ins_pipe( pipe_slow ); |
|
8764 |
%} |
|
8765 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8766 |
instruct vor16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8767 |
predicate(n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8768 |
match(Set dst (OrV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8769 |
format %{ "por $dst,$src\t! or vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8770 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8771 |
__ por($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8772 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8773 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8774 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8775 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8776 |
instruct vor16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8777 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8778 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8779 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8780 |
ins_encode %{ |
30624 | 8781 |
int vector_len = 0; |
8782 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8783 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8784 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8785 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8786 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8787 |
instruct vor16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8788 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8789 |
match(Set dst (OrV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8790 |
format %{ "vpor $dst,$src,$mem\t! or vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8791 |
ins_encode %{ |
30624 | 8792 |
int vector_len = 0; |
8793 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8794 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8795 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8796 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8797 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8798 |
instruct vor32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8799 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8800 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8801 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8802 |
ins_encode %{ |
30624 | 8803 |
int vector_len = 1; |
8804 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8805 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8806 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8807 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8808 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8809 |
instruct vor32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8810 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8811 |
match(Set dst (OrV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8812 |
format %{ "vpor $dst,$src,$mem\t! or vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8813 |
ins_encode %{ |
30624 | 8814 |
int vector_len = 1; |
8815 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8816 |
%} |
|
8817 |
ins_pipe( pipe_slow ); |
|
8818 |
%} |
|
8819 |
||
8820 |
instruct vor64B_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
8821 |
predicate(UseAVX > 2 && n->as_Vector()->length_in_bytes() == 64); |
|
8822 |
match(Set dst (OrV src1 src2)); |
|
8823 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (64 bytes)" %} |
|
8824 |
ins_encode %{ |
|
8825 |
int vector_len = 2; |
|
8826 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
8827 |
%} |
|
8828 |
ins_pipe( pipe_slow ); |
|
8829 |
%} |
|
8830 |
||
8831 |
instruct vor64B_mem(vecZ dst, vecZ src, memory mem) %{ |
|
8832 |
predicate(UseAVX > 2 && n->as_Vector()->length_in_bytes() == 64); |
|
8833 |
match(Set dst (OrV src (LoadVector mem))); |
|
8834 |
format %{ "vpor $dst,$src,$mem\t! or vectors (64 bytes)" %} |
|
8835 |
ins_encode %{ |
|
8836 |
int vector_len = 2; |
|
8837 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8838 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8839 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8840 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8841 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8842 |
// --------------------------------- XOR -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8843 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8844 |
instruct vxor4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8845 |
predicate(n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8846 |
match(Set dst (XorV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8847 |
format %{ "pxor $dst,$src\t! xor vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8848 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8849 |
__ pxor($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8850 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8851 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8852 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8853 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8854 |
instruct vxor4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8855 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8856 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8857 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8858 |
ins_encode %{ |
30624 | 8859 |
int vector_len = 0; |
8860 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8861 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8862 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8863 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8864 |
|
31410 | 8865 |
instruct vxor4B_mem(vecS dst, vecS src, memory mem) %{ |
8866 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
|
8867 |
match(Set dst (XorV src (LoadVector mem))); |
|
8868 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (4 bytes)" %} |
|
8869 |
ins_encode %{ |
|
8870 |
int vector_len = 0; |
|
8871 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8872 |
%} |
|
8873 |
ins_pipe( pipe_slow ); |
|
8874 |
%} |
|
8875 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8876 |
instruct vxor8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8877 |
predicate(n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8878 |
match(Set dst (XorV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8879 |
format %{ "pxor $dst,$src\t! xor vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8880 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8881 |
__ pxor($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8882 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8883 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8884 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8885 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8886 |
instruct vxor8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8887 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8888 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8889 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8890 |
ins_encode %{ |
30624 | 8891 |
int vector_len = 0; |
8892 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8893 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8894 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8895 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8896 |
|
31410 | 8897 |
instruct vxor8B_mem(vecD dst, vecD src, memory mem) %{ |
8898 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
|
8899 |
match(Set dst (XorV src (LoadVector mem))); |
|
8900 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (8 bytes)" %} |
|
8901 |
ins_encode %{ |
|
8902 |
int vector_len = 0; |
|
8903 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8904 |
%} |
|
8905 |
ins_pipe( pipe_slow ); |
|
8906 |
%} |
|
8907 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8908 |
instruct vxor16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8909 |
predicate(n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8910 |
match(Set dst (XorV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8911 |
format %{ "pxor $dst,$src\t! xor vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8912 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8913 |
__ pxor($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8914 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8915 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8916 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8917 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8918 |
instruct vxor16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8919 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8920 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8921 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8922 |
ins_encode %{ |
30624 | 8923 |
int vector_len = 0; |
8924 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8925 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8926 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8927 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8928 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8929 |
instruct vxor16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8930 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8931 |
match(Set dst (XorV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8932 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8933 |
ins_encode %{ |
30624 | 8934 |
int vector_len = 0; |
8935 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8936 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8937 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8938 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8939 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8940 |
instruct vxor32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8941 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8942 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8943 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8944 |
ins_encode %{ |
30624 | 8945 |
int vector_len = 1; |
8946 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8947 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8948 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8949 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8950 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8951 |
instruct vxor32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8952 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8953 |
match(Set dst (XorV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8954 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
8955 |
ins_encode %{ |
30624 | 8956 |
int vector_len = 1; |
8957 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8958 |
%} |
|
8959 |
ins_pipe( pipe_slow ); |
|
8960 |
%} |
|
8961 |
||
8962 |
instruct vxor64B_reg(vecZ dst, vecZ src1, vecZ src2) %{ |
|
8963 |
predicate(UseAVX > 2 && n->as_Vector()->length_in_bytes() == 64); |
|
8964 |
match(Set dst (XorV src1 src2)); |
|
8965 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (64 bytes)" %} |
|
8966 |
ins_encode %{ |
|
8967 |
int vector_len = 2; |
|
8968 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector_len); |
|
8969 |
%} |
|
8970 |
ins_pipe( pipe_slow ); |
|
8971 |
%} |
|
8972 |
||
8973 |
instruct vxor64B_mem(vecZ dst, vecZ src, memory mem) %{ |
|
8974 |
predicate(UseAVX > 2 && n->as_Vector()->length_in_bytes() == 64); |
|
8975 |
match(Set dst (XorV src (LoadVector mem))); |
|
8976 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (64 bytes)" %} |
|
8977 |
ins_encode %{ |
|
8978 |
int vector_len = 2; |
|
8979 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector_len); |
|
8980 |
%} |
|
8981 |
ins_pipe( pipe_slow ); |
|
8982 |
%} |
|
8983 |