//

// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

//

// This code is free software; you can redistribute it and/or modify it

// under the terms of the GNU General Public License version 2 only, as

// published by the Free Software Foundation.

//

// This code is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// version 2 for more details (a copy is included in the LICENSE file that

// accompanied this code).

//

// You should have received a copy of the GNU General Public License version

// 2 along with this work; if not, write to the Free Software Foundation,

// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

//

// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

// or visit www.oracle.com if you need additional information or have any

// questions.

//

//

// X86 Common Architecture Description File

//----------REGISTER DEFINITION BLOCK------------------------------------------

// This information is used by the matcher and the register allocator to

// describe individual registers and classes of registers within the target

// archtecture.

register %{

//----------Architecture Description Register Definitions----------------------

// General Registers

// "reg_def"  name ( register save type, C convention save type,

//                   ideal register type, encoding );

// Register Save Types:

//

// NS  = No-Save:       The register allocator assumes that these registers

//                      can be used without saving upon entry to the method, &

//                      that they do not need to be saved at call sites.

//

// SOC = Save-On-Call:  The register allocator assumes that these registers

//                      can be used without saving upon entry to the method,

//                      but that they must be saved at call sites.

//

// SOE = Save-On-Entry: The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, but they do not need to be saved at call

//                      sites.

//

// AS  = Always-Save:   The register allocator assumes that these registers

//                      must be saved before using them upon entry to the

//                      method, & that they must be saved at call sites.

//

// Ideal Register Type is used to determine how to save & restore a

// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get

// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.

//

// The encoding number is the actual bit-pattern placed into the opcodes.

// XMM registers.  256-bit registers or 8 words each, labeled (a)-h.

// Word a in each register holds a Float, words ab hold a Double.

// The whole registers are used in SSE4.2 version intrinsics,

// array copy stubs and superword operations (see UseSSE42Intrinsics,

// UseXMMForArrayCopy and UseSuperword flags).

// XMM8-XMM15 must be encoded with REX (VEX for UseAVX).

// Linux ABI:   No register preserved across function calls

//              XMM0-XMM7 might hold parameters

// Windows ABI: XMM6-XMM15 preserved across function calls

//              XMM0-XMM3 might hold parameters

reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());

reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());

reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());

reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());

reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());

reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());

#ifdef _WIN64

reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());

reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());

reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());

reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());

reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());

reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());

reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());

reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());

reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());

reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());

#else // _WIN64

reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());

reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());

#ifdef _LP64

reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());

reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());

reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());

reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());

reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());

reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());

reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());

reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());

#endif // _LP64

#endif // _WIN64

#ifdef _LP64

reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());

#else

reg_def RFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());

#endif // _LP64

alloc_class chunk1(XMM0,  XMM0b,  XMM0c,  XMM0d,  XMM0e,  XMM0f,  XMM0g,  XMM0h,

                   XMM1,  XMM1b,  XMM1c,  XMM1d,  XMM1e,  XMM1f,  XMM1g,  XMM1h,

                   XMM2,  XMM2b,  XMM2c,  XMM2d,  XMM2e,  XMM2f,  XMM2g,  XMM2h,

                   XMM3,  XMM3b,  XMM3c,  XMM3d,  XMM3e,  XMM3f,  XMM3g,  XMM3h,

                   XMM4,  XMM4b,  XMM4c,  XMM4d,  XMM4e,  XMM4f,  XMM4g,  XMM4h,

                   XMM5,  XMM5b,  XMM5c,  XMM5d,  XMM5e,  XMM5f,  XMM5g,  XMM5h,

                   XMM6,  XMM6b,  XMM6c,  XMM6d,  XMM6e,  XMM6f,  XMM6g,  XMM6h,

                   XMM7,  XMM7b,  XMM7c,  XMM7d,  XMM7e,  XMM7f,  XMM7g,  XMM7h

#ifdef _LP64

                  ,XMM8,  XMM8b,  XMM8c,  XMM8d,  XMM8e,  XMM8f,  XMM8g,  XMM8h,

                   XMM9,  XMM9b,  XMM9c,  XMM9d,  XMM9e,  XMM9f,  XMM9g,  XMM9h,

                   XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h,

                   XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h,

                   XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h,

                   XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h,

                   XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h,

                   XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h

#endif

                   );

// flags allocation class should be last.

alloc_class chunk2(RFLAGS);

// Singleton class for condition codes

reg_class int_flags(RFLAGS);

// Class for all float registers

reg_class float_reg(XMM0,

                    XMM1,

                    XMM2,

                    XMM3,

                    XMM4,

                    XMM5,

                    XMM6,

                    XMM7

#ifdef _LP64

                   ,XMM8,

                    XMM9,

                    XMM10,

                    XMM11,

                    XMM12,

                    XMM13,

                    XMM14,

                    XMM15

#endif

                    );

// Class for all double registers

reg_class double_reg(XMM0,  XMM0b,

                     XMM1,  XMM1b,

                     XMM2,  XMM2b,

                     XMM3,  XMM3b,

                     XMM4,  XMM4b,

                     XMM5,  XMM5b,

                     XMM6,  XMM6b,

                     XMM7,  XMM7b

#ifdef _LP64

                    ,XMM8,  XMM8b,

                     XMM9,  XMM9b,

                     XMM10, XMM10b,

                     XMM11, XMM11b,

                     XMM12, XMM12b,

                     XMM13, XMM13b,

                     XMM14, XMM14b,

                     XMM15, XMM15b

#endif

                     );

// Class for all 32bit vector registers

reg_class vectors_reg(XMM0,

                      XMM1,

                      XMM2,

                      XMM3,

                      XMM4,

                      XMM5,

                      XMM6,

                      XMM7

#ifdef _LP64

                     ,XMM8,

                      XMM9,

                      XMM10,

                      XMM11,

                      XMM12,

                      XMM13,

                      XMM14,

                      XMM15

#endif

                      );

// Class for all 64bit vector registers

reg_class vectord_reg(XMM0,  XMM0b,

                      XMM1,  XMM1b,

                      XMM2,  XMM2b,

                      XMM3,  XMM3b,

                      XMM4,  XMM4b,

                      XMM5,  XMM5b,

                      XMM6,  XMM6b,

                      XMM7,  XMM7b

#ifdef _LP64

                     ,XMM8,  XMM8b,

                      XMM9,  XMM9b,

                      XMM10, XMM10b,

                      XMM11, XMM11b,

                      XMM12, XMM12b,

                      XMM13, XMM13b,

                      XMM14, XMM14b,

                      XMM15, XMM15b

#endif

                      );

// Class for all 128bit vector registers

reg_class vectorx_reg(XMM0,  XMM0b,  XMM0c,  XMM0d,

                      XMM1,  XMM1b,  XMM1c,  XMM1d,

                      XMM2,  XMM2b,  XMM2c,  XMM2d,

                      XMM3,  XMM3b,  XMM3c,  XMM3d,

                      XMM4,  XMM4b,  XMM4c,  XMM4d,

                      XMM5,  XMM5b,  XMM5c,  XMM5d,

                      XMM6,  XMM6b,  XMM6c,  XMM6d,

                      XMM7,  XMM7b,  XMM7c,  XMM7d

#ifdef _LP64

                     ,XMM8,  XMM8b,  XMM8c,  XMM8d,

                      XMM9,  XMM9b,  XMM9c,  XMM9d,

                      XMM10, XMM10b, XMM10c, XMM10d,

                      XMM11, XMM11b, XMM11c, XMM11d,

                      XMM12, XMM12b, XMM12c, XMM12d,

                      XMM13, XMM13b, XMM13c, XMM13d,

                      XMM14, XMM14b, XMM14c, XMM14d,

                      XMM15, XMM15b, XMM15c, XMM15d

#endif

                      );

// Class for all 256bit vector registers

reg_class vectory_reg(XMM0,  XMM0b,  XMM0c,  XMM0d,  XMM0e,  XMM0f,  XMM0g,  XMM0h,

                      XMM1,  XMM1b,  XMM1c,  XMM1d,  XMM1e,  XMM1f,  XMM1g,  XMM1h,

                      XMM2,  XMM2b,  XMM2c,  XMM2d,  XMM2e,  XMM2f,  XMM2g,  XMM2h,

                      XMM3,  XMM3b,  XMM3c,  XMM3d,  XMM3e,  XMM3f,  XMM3g,  XMM3h,

                      XMM4,  XMM4b,  XMM4c,  XMM4d,  XMM4e,  XMM4f,  XMM4g,  XMM4h,

                      XMM5,  XMM5b,  XMM5c,  XMM5d,  XMM5e,  XMM5f,  XMM5g,  XMM5h,

                      XMM6,  XMM6b,  XMM6c,  XMM6d,  XMM6e,  XMM6f,  XMM6g,  XMM6h,

                      XMM7,  XMM7b,  XMM7c,  XMM7d,  XMM7e,  XMM7f,  XMM7g,  XMM7h

#ifdef _LP64

                     ,XMM8,  XMM8b,  XMM8c,  XMM8d,  XMM8e,  XMM8f,  XMM8g,  XMM8h,

                      XMM9,  XMM9b,  XMM9c,  XMM9d,  XMM9e,  XMM9f,  XMM9g,  XMM9h,

                      XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h,

                      XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h,

                      XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h,

                      XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h,

                      XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h,

                      XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h

#endif

                      );

%}

source %{

  // Float masks come from different places depending on platform.

#ifdef _LP64

  static address float_signmask()  { return StubRoutines::x86::float_sign_mask(); }

  static address float_signflip()  { return StubRoutines::x86::float_sign_flip(); }

  static address double_signmask() { return StubRoutines::x86::double_sign_mask(); }

  static address double_signflip() { return StubRoutines::x86::double_sign_flip(); }

#else

  static address float_signmask()  { return (address)float_signmask_pool; }

  static address float_signflip()  { return (address)float_signflip_pool; }

  static address double_signmask() { return (address)double_signmask_pool; }

  static address double_signflip() { return (address)double_signflip_pool; }

#endif

// Map Types to machine register types

const int Matcher::base2reg[Type::lastype] = {

  Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,

  Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */