author | zmajo |
Mon, 27 Apr 2015 10:49:43 +0200 | |
changeset 30305 | b92a97e1e9cb |
parent 30211 | 442fbbb31f75 |
child 30624 | 2e1803c8a26d |
permissions | -rw-r--r-- |
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// |
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// Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved. |
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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// |
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// This code is free software; you can redistribute it and/or modify it |
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// under the terms of the GNU General Public License version 2 only, as |
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// published by the Free Software Foundation. |
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// |
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// This code is distributed in the hope that it will be useful, but WITHOUT |
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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// version 2 for more details (a copy is included in the LICENSE file that |
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// accompanied this code). |
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// |
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// You should have received a copy of the GNU General Public License version |
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// 2 along with this work; if not, write to the Free Software Foundation, |
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// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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// |
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// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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// or visit www.oracle.com if you need additional information or have any |
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// questions. |
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// |
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// |
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||
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// X86 Common Architecture Description File |
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//----------REGISTER DEFINITION BLOCK------------------------------------------ |
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// This information is used by the matcher and the register allocator to |
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// describe individual registers and classes of registers within the target |
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// archtecture. |
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register %{ |
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//----------Architecture Description Register Definitions---------------------- |
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// General Registers |
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// "reg_def" name ( register save type, C convention save type, |
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// ideal register type, encoding ); |
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// Register Save Types: |
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// |
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// NS = No-Save: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, & |
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// that they do not need to be saved at call sites. |
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// |
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// SOC = Save-On-Call: The register allocator assumes that these registers |
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// can be used without saving upon entry to the method, |
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// but that they must be saved at call sites. |
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// |
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// SOE = Save-On-Entry: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, but they do not need to be saved at call |
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// sites. |
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// |
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// AS = Always-Save: The register allocator assumes that these registers |
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// must be saved before using them upon entry to the |
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// method, & that they must be saved at call sites. |
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// |
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// Ideal Register Type is used to determine how to save & restore a |
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// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get |
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// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. |
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// |
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// The encoding number is the actual bit-pattern placed into the opcodes. |
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// XMM registers. 256-bit registers or 8 words each, labeled (a)-h. |
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// Word a in each register holds a Float, words ab hold a Double. |
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// The whole registers are used in SSE4.2 version intrinsics, |
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// array copy stubs and superword operations (see UseSSE42Intrinsics, |
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// UseXMMForArrayCopy and UseSuperword flags). |
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// XMM8-XMM15 must be encoded with REX (VEX for UseAVX). |
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// Linux ABI: No register preserved across function calls |
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// XMM0-XMM7 might hold parameters |
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// Windows ABI: XMM6-XMM15 preserved across function calls |
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// XMM0-XMM3 might hold parameters |
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reg_def XMM0 ( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); |
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reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(1)); |
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reg_def XMM0c( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(2)); |
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reg_def XMM0d( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(3)); |
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reg_def XMM0e( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(4)); |
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reg_def XMM0f( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(5)); |
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reg_def XMM0g( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(6)); |
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reg_def XMM0h( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next(7)); |
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reg_def XMM1 ( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); |
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reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(1)); |
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reg_def XMM1c( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(2)); |
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reg_def XMM1d( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(3)); |
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reg_def XMM1e( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(4)); |
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reg_def XMM1f( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(5)); |
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reg_def XMM1g( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(6)); |
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reg_def XMM1h( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next(7)); |
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reg_def XMM2 ( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); |
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reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(1)); |
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reg_def XMM2c( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(2)); |
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reg_def XMM2d( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(3)); |
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reg_def XMM2e( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(4)); |
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reg_def XMM2f( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(5)); |
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reg_def XMM2g( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(6)); |
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reg_def XMM2h( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next(7)); |
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reg_def XMM3 ( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); |
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reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(1)); |
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reg_def XMM3c( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(2)); |
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reg_def XMM3d( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(3)); |
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reg_def XMM3e( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(4)); |
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reg_def XMM3f( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(5)); |
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reg_def XMM3g( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(6)); |
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reg_def XMM3h( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next(7)); |
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reg_def XMM4 ( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); |
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reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(1)); |
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reg_def XMM4c( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(2)); |
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reg_def XMM4d( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(3)); |
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reg_def XMM4e( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(4)); |
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reg_def XMM4f( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(5)); |
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reg_def XMM4g( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(6)); |
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reg_def XMM4h( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next(7)); |
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reg_def XMM5 ( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); |
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reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(1)); |
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reg_def XMM5c( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(2)); |
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reg_def XMM5d( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(3)); |
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reg_def XMM5e( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(4)); |
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reg_def XMM5f( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(5)); |
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reg_def XMM5g( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(6)); |
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reg_def XMM5h( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next(7)); |
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#ifdef _WIN64 |
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reg_def XMM6 ( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); |
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reg_def XMM6b( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(1)); |
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reg_def XMM6c( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(2)); |
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reg_def XMM6d( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(3)); |
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reg_def XMM6e( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(4)); |
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reg_def XMM6f( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(5)); |
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reg_def XMM6g( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(6)); |
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reg_def XMM6h( SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next(7)); |
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reg_def XMM7 ( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); |
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reg_def XMM7b( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(1)); |
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reg_def XMM7c( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(2)); |
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reg_def XMM7d( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(3)); |
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reg_def XMM7e( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(4)); |
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reg_def XMM7f( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(5)); |
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reg_def XMM7g( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(6)); |
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reg_def XMM7h( SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next(7)); |
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reg_def XMM8 ( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); |
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reg_def XMM8b( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(1)); |
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reg_def XMM8c( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(2)); |
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reg_def XMM8d( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(3)); |
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reg_def XMM8e( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(4)); |
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reg_def XMM8f( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(5)); |
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reg_def XMM8g( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(6)); |
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reg_def XMM8h( SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next(7)); |
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reg_def XMM9 ( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); |
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reg_def XMM9b( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(1)); |
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reg_def XMM9c( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(2)); |
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reg_def XMM9d( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(3)); |
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reg_def XMM9e( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(4)); |
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reg_def XMM9f( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(5)); |
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reg_def XMM9g( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(6)); |
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reg_def XMM9h( SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next(7)); |
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reg_def XMM10 ( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); |
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reg_def XMM10b( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(1)); |
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reg_def XMM10c( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(2)); |
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reg_def XMM10d( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(3)); |
|
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reg_def XMM10e( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(4)); |
|
170 |
reg_def XMM10f( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(5)); |
|
171 |
reg_def XMM10g( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(6)); |
|
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reg_def XMM10h( SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next(7)); |
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reg_def XMM11 ( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); |
13294 | 175 |
reg_def XMM11b( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(1)); |
176 |
reg_def XMM11c( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(2)); |
|
177 |
reg_def XMM11d( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(3)); |
|
178 |
reg_def XMM11e( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(4)); |
|
179 |
reg_def XMM11f( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(5)); |
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reg_def XMM11g( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(6)); |
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181 |
reg_def XMM11h( SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next(7)); |
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reg_def XMM12 ( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); |
13294 | 184 |
reg_def XMM12b( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(1)); |
185 |
reg_def XMM12c( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(2)); |
|
186 |
reg_def XMM12d( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(3)); |
|
187 |
reg_def XMM12e( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(4)); |
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188 |
reg_def XMM12f( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(5)); |
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189 |
reg_def XMM12g( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(6)); |
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reg_def XMM12h( SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next(7)); |
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192 |
reg_def XMM13 ( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); |
13294 | 193 |
reg_def XMM13b( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(1)); |
194 |
reg_def XMM13c( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(2)); |
|
195 |
reg_def XMM13d( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(3)); |
|
196 |
reg_def XMM13e( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(4)); |
|
197 |
reg_def XMM13f( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(5)); |
|
198 |
reg_def XMM13g( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(6)); |
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reg_def XMM13h( SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next(7)); |
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200 |
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201 |
reg_def XMM14 ( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); |
13294 | 202 |
reg_def XMM14b( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(1)); |
203 |
reg_def XMM14c( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(2)); |
|
204 |
reg_def XMM14d( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(3)); |
|
205 |
reg_def XMM14e( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(4)); |
|
206 |
reg_def XMM14f( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(5)); |
|
207 |
reg_def XMM14g( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(6)); |
|
208 |
reg_def XMM14h( SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next(7)); |
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210 |
reg_def XMM15 ( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); |
13294 | 211 |
reg_def XMM15b( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(1)); |
212 |
reg_def XMM15c( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(2)); |
|
213 |
reg_def XMM15d( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(3)); |
|
214 |
reg_def XMM15e( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(4)); |
|
215 |
reg_def XMM15f( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(5)); |
|
216 |
reg_def XMM15g( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(6)); |
|
217 |
reg_def XMM15h( SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next(7)); |
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218 |
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219 |
#else // _WIN64 |
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220 |
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221 |
reg_def XMM6 ( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); |
13294 | 222 |
reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(1)); |
223 |
reg_def XMM6c( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(2)); |
|
224 |
reg_def XMM6d( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(3)); |
|
225 |
reg_def XMM6e( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(4)); |
|
226 |
reg_def XMM6f( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(5)); |
|
227 |
reg_def XMM6g( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(6)); |
|
228 |
reg_def XMM6h( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next(7)); |
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229 |
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230 |
reg_def XMM7 ( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); |
13294 | 231 |
reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(1)); |
232 |
reg_def XMM7c( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(2)); |
|
233 |
reg_def XMM7d( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(3)); |
|
234 |
reg_def XMM7e( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(4)); |
|
235 |
reg_def XMM7f( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(5)); |
|
236 |
reg_def XMM7g( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(6)); |
|
237 |
reg_def XMM7h( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next(7)); |
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238 |
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239 |
#ifdef _LP64 |
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240 |
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241 |
reg_def XMM8 ( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); |
13294 | 242 |
reg_def XMM8b( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(1)); |
243 |
reg_def XMM8c( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(2)); |
|
244 |
reg_def XMM8d( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(3)); |
|
245 |
reg_def XMM8e( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(4)); |
|
246 |
reg_def XMM8f( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(5)); |
|
247 |
reg_def XMM8g( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(6)); |
|
248 |
reg_def XMM8h( SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next(7)); |
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249 |
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250 |
reg_def XMM9 ( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); |
13294 | 251 |
reg_def XMM9b( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(1)); |
252 |
reg_def XMM9c( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(2)); |
|
253 |
reg_def XMM9d( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(3)); |
|
254 |
reg_def XMM9e( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(4)); |
|
255 |
reg_def XMM9f( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(5)); |
|
256 |
reg_def XMM9g( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(6)); |
|
257 |
reg_def XMM9h( SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next(7)); |
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258 |
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259 |
reg_def XMM10 ( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); |
13294 | 260 |
reg_def XMM10b( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(1)); |
261 |
reg_def XMM10c( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(2)); |
|
262 |
reg_def XMM10d( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(3)); |
|
263 |
reg_def XMM10e( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(4)); |
|
264 |
reg_def XMM10f( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(5)); |
|
265 |
reg_def XMM10g( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(6)); |
|
266 |
reg_def XMM10h( SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next(7)); |
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267 |
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268 |
reg_def XMM11 ( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); |
13294 | 269 |
reg_def XMM11b( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(1)); |
270 |
reg_def XMM11c( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(2)); |
|
271 |
reg_def XMM11d( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(3)); |
|
272 |
reg_def XMM11e( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(4)); |
|
273 |
reg_def XMM11f( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(5)); |
|
274 |
reg_def XMM11g( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(6)); |
|
275 |
reg_def XMM11h( SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next(7)); |
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276 |
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277 |
reg_def XMM12 ( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); |
13294 | 278 |
reg_def XMM12b( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(1)); |
279 |
reg_def XMM12c( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(2)); |
|
280 |
reg_def XMM12d( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(3)); |
|
281 |
reg_def XMM12e( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(4)); |
|
282 |
reg_def XMM12f( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(5)); |
|
283 |
reg_def XMM12g( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(6)); |
|
284 |
reg_def XMM12h( SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next(7)); |
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285 |
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286 |
reg_def XMM13 ( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); |
13294 | 287 |
reg_def XMM13b( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(1)); |
288 |
reg_def XMM13c( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(2)); |
|
289 |
reg_def XMM13d( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(3)); |
|
290 |
reg_def XMM13e( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(4)); |
|
291 |
reg_def XMM13f( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(5)); |
|
292 |
reg_def XMM13g( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(6)); |
|
293 |
reg_def XMM13h( SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next(7)); |
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294 |
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295 |
reg_def XMM14 ( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); |
13294 | 296 |
reg_def XMM14b( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(1)); |
297 |
reg_def XMM14c( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(2)); |
|
298 |
reg_def XMM14d( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(3)); |
|
299 |
reg_def XMM14e( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(4)); |
|
300 |
reg_def XMM14f( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(5)); |
|
301 |
reg_def XMM14g( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(6)); |
|
302 |
reg_def XMM14h( SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next(7)); |
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303 |
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304 |
reg_def XMM15 ( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); |
13294 | 305 |
reg_def XMM15b( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(1)); |
306 |
reg_def XMM15c( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(2)); |
|
307 |
reg_def XMM15d( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(3)); |
|
308 |
reg_def XMM15e( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(4)); |
|
309 |
reg_def XMM15f( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(5)); |
|
310 |
reg_def XMM15g( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(6)); |
|
311 |
reg_def XMM15h( SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next(7)); |
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312 |
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313 |
#endif // _LP64 |
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314 |
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315 |
#endif // _WIN64 |
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316 |
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317 |
#ifdef _LP64 |
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318 |
reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); |
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319 |
#else |
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reg_def RFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); |
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321 |
#endif // _LP64 |
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322 |
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alloc_class chunk1(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
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XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
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325 |
XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
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XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
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327 |
XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
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XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
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parents:
11794
diff
changeset
|
329 |
XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
330 |
XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
331 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
332 |
,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
333 |
XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
334 |
XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
335 |
XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
336 |
XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
337 |
XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
338 |
XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
339 |
XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
340 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
341 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
342 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
343 |
// flags allocation class should be last. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
344 |
alloc_class chunk2(RFLAGS); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
345 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
346 |
// Singleton class for condition codes |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
347 |
reg_class int_flags(RFLAGS); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
348 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
349 |
// Class for all float registers |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
350 |
reg_class float_reg(XMM0, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
351 |
XMM1, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
352 |
XMM2, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
353 |
XMM3, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
354 |
XMM4, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
355 |
XMM5, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
356 |
XMM6, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
357 |
XMM7 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
358 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
359 |
,XMM8, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
360 |
XMM9, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
361 |
XMM10, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
362 |
XMM11, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
363 |
XMM12, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
364 |
XMM13, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
365 |
XMM14, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
366 |
XMM15 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
367 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
368 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
369 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
370 |
// Class for all double registers |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
371 |
reg_class double_reg(XMM0, XMM0b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
372 |
XMM1, XMM1b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
373 |
XMM2, XMM2b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
374 |
XMM3, XMM3b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
375 |
XMM4, XMM4b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
376 |
XMM5, XMM5b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
377 |
XMM6, XMM6b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
378 |
XMM7, XMM7b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
379 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
380 |
,XMM8, XMM8b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
381 |
XMM9, XMM9b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
382 |
XMM10, XMM10b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
383 |
XMM11, XMM11b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
384 |
XMM12, XMM12b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
385 |
XMM13, XMM13b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
386 |
XMM14, XMM14b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
387 |
XMM15, XMM15b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
388 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
389 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
390 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
391 |
// Class for all 32bit vector registers |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
392 |
reg_class vectors_reg(XMM0, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
393 |
XMM1, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
394 |
XMM2, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
395 |
XMM3, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
396 |
XMM4, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
397 |
XMM5, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
398 |
XMM6, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
399 |
XMM7 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
400 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
401 |
,XMM8, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
402 |
XMM9, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
403 |
XMM10, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
404 |
XMM11, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
405 |
XMM12, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
406 |
XMM13, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
407 |
XMM14, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
408 |
XMM15 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
409 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
410 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
411 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
412 |
// Class for all 64bit vector registers |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
413 |
reg_class vectord_reg(XMM0, XMM0b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
414 |
XMM1, XMM1b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
415 |
XMM2, XMM2b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
416 |
XMM3, XMM3b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
417 |
XMM4, XMM4b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
418 |
XMM5, XMM5b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
419 |
XMM6, XMM6b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
420 |
XMM7, XMM7b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
421 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
422 |
,XMM8, XMM8b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
423 |
XMM9, XMM9b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
424 |
XMM10, XMM10b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
425 |
XMM11, XMM11b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
426 |
XMM12, XMM12b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
427 |
XMM13, XMM13b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
428 |
XMM14, XMM14b, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
429 |
XMM15, XMM15b |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
430 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
431 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
432 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
433 |
// Class for all 128bit vector registers |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
434 |
reg_class vectorx_reg(XMM0, XMM0b, XMM0c, XMM0d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
435 |
XMM1, XMM1b, XMM1c, XMM1d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
436 |
XMM2, XMM2b, XMM2c, XMM2d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
437 |
XMM3, XMM3b, XMM3c, XMM3d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
438 |
XMM4, XMM4b, XMM4c, XMM4d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
439 |
XMM5, XMM5b, XMM5c, XMM5d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
440 |
XMM6, XMM6b, XMM6c, XMM6d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
441 |
XMM7, XMM7b, XMM7c, XMM7d |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
442 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
443 |
,XMM8, XMM8b, XMM8c, XMM8d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
444 |
XMM9, XMM9b, XMM9c, XMM9d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
445 |
XMM10, XMM10b, XMM10c, XMM10d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
446 |
XMM11, XMM11b, XMM11c, XMM11d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
447 |
XMM12, XMM12b, XMM12c, XMM12d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
448 |
XMM13, XMM13b, XMM13c, XMM13d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
449 |
XMM14, XMM14b, XMM14c, XMM14d, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
450 |
XMM15, XMM15b, XMM15c, XMM15d |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
451 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
452 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
453 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
454 |
// Class for all 256bit vector registers |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
455 |
reg_class vectory_reg(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0g, XMM0h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
456 |
XMM1, XMM1b, XMM1c, XMM1d, XMM1e, XMM1f, XMM1g, XMM1h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
457 |
XMM2, XMM2b, XMM2c, XMM2d, XMM2e, XMM2f, XMM2g, XMM2h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
458 |
XMM3, XMM3b, XMM3c, XMM3d, XMM3e, XMM3f, XMM3g, XMM3h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
459 |
XMM4, XMM4b, XMM4c, XMM4d, XMM4e, XMM4f, XMM4g, XMM4h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
460 |
XMM5, XMM5b, XMM5c, XMM5d, XMM5e, XMM5f, XMM5g, XMM5h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
461 |
XMM6, XMM6b, XMM6c, XMM6d, XMM6e, XMM6f, XMM6g, XMM6h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
462 |
XMM7, XMM7b, XMM7c, XMM7d, XMM7e, XMM7f, XMM7g, XMM7h |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
463 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
464 |
,XMM8, XMM8b, XMM8c, XMM8d, XMM8e, XMM8f, XMM8g, XMM8h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
465 |
XMM9, XMM9b, XMM9c, XMM9d, XMM9e, XMM9f, XMM9g, XMM9h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
466 |
XMM10, XMM10b, XMM10c, XMM10d, XMM10e, XMM10f, XMM10g, XMM10h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
467 |
XMM11, XMM11b, XMM11c, XMM11d, XMM11e, XMM11f, XMM11g, XMM11h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
468 |
XMM12, XMM12b, XMM12c, XMM12d, XMM12e, XMM12f, XMM12g, XMM12h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
469 |
XMM13, XMM13b, XMM13c, XMM13d, XMM13e, XMM13f, XMM13g, XMM13h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
470 |
XMM14, XMM14b, XMM14c, XMM14d, XMM14e, XMM14f, XMM14g, XMM14h, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
471 |
XMM15, XMM15b, XMM15c, XMM15d, XMM15e, XMM15f, XMM15g, XMM15h |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
472 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
473 |
); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
474 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
475 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
476 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
477 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
478 |
//----------SOURCE BLOCK------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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changeset
|
479 |
// This is a block of C++ code which provides values, functions, and |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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|
480 |
// definitions necessary in the rest of the architecture description |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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changeset
|
481 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
482 |
source_hpp %{ |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
483 |
// Header information of the source block. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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|
484 |
// Method declarations/definitions which are used outside |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
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changeset
|
485 |
// the ad-scope can conveniently be defined here. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
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changeset
|
486 |
// |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
487 |
// To keep related declarations/definitions/uses close together, |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
488 |
// we switch between source %{ }% and source_hpp %{ }% freely as needed. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
489 |
|
25715
d5a8dbdc5150
8049325: Introduce and clean up umbrella headers for the files in the cpu subdirectories.
goetz
parents:
23498
diff
changeset
|
490 |
class NativeJump; |
d5a8dbdc5150
8049325: Introduce and clean up umbrella headers for the files in the cpu subdirectories.
goetz
parents:
23498
diff
changeset
|
491 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
492 |
class CallStubImpl { |
30211 | 493 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
494 |
//-------------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
495 |
//---< Used for optimization in Compile::shorten_branches >--- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
496 |
//-------------------------------------------------------------- |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
497 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
498 |
public: |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
499 |
// Size of call trampoline stub. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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changeset
|
500 |
static uint size_call_trampoline() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
501 |
return 0; // no call trampolines on this platform |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
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diff
changeset
|
502 |
} |
30211 | 503 |
|
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
504 |
// number of relocations needed by a call trampoline stub |
30211 | 505 |
static uint reloc_call_trampoline() { |
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
506 |
return 0; // no call trampolines on this platform |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
507 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
508 |
}; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
509 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
510 |
class HandlerImpl { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
511 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
512 |
public: |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
513 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
514 |
static int emit_exception_handler(CodeBuffer &cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
515 |
static int emit_deopt_handler(CodeBuffer& cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
516 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
517 |
static uint size_exception_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
518 |
// NativeCall instruction size is the same as NativeJump. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
519 |
// exception handler starts out as jump and can be patched to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
520 |
// a call be deoptimization. (4932387) |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
521 |
// Note that this value is also credited (in output.cpp) to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
522 |
// the size of the code section. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
523 |
return NativeJump::instruction_size; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
524 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
525 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
526 |
#ifdef _LP64 |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
527 |
static uint size_deopt_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
528 |
// three 5 byte instructions |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
529 |
return 15; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
530 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
531 |
#else |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
532 |
static uint size_deopt_handler() { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
533 |
// NativeCall instruction size is the same as NativeJump. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
534 |
// exception handler starts out as jump and can be patched to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
535 |
// a call be deoptimization. (4932387) |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
536 |
// Note that this value is also credited (in output.cpp) to |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
537 |
// the size of the code section. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
538 |
return 5 + NativeJump::instruction_size; // pushl(); jmp; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
539 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
540 |
#endif |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
541 |
}; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
542 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
543 |
%} // end source_hpp |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
544 |
|
11429 | 545 |
source %{ |
23498
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
546 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
547 |
// Emit exception handler code. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
548 |
// Stuff framesize into a register and call a VM stub routine. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
549 |
int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
550 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
551 |
// Note that the code buffer's insts_mark is always relative to insts. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
552 |
// That's why we must use the macroassembler to generate a handler. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
553 |
MacroAssembler _masm(&cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
554 |
address base = __ start_a_stub(size_exception_handler()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
555 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
556 |
int offset = __ offset(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
557 |
__ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
558 |
assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
559 |
__ end_a_stub(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
560 |
return offset; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
561 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
562 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
563 |
// Emit deopt handler code. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
564 |
int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
565 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
566 |
// Note that the code buffer's insts_mark is always relative to insts. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
567 |
// That's why we must use the macroassembler to generate a handler. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
568 |
MacroAssembler _masm(&cbuf); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
569 |
address base = __ start_a_stub(size_deopt_handler()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
570 |
if (base == NULL) return 0; // CodeBuffer::expand failed |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
571 |
int offset = __ offset(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
572 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
573 |
#ifdef _LP64 |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
574 |
address the_pc = (address) __ pc(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
575 |
Label next; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
576 |
// push a "the_pc" on the stack without destroying any registers |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
577 |
// as they all may be live. |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
578 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
579 |
// push address of "next" |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
580 |
__ call(next, relocInfo::none); // reloc none is fine since it is a disp32 |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
581 |
__ bind(next); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
582 |
// adjust it so it matches "the_pc" |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
583 |
__ subptr(Address(rsp, 0), __ offset() - offset); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
584 |
#else |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
585 |
InternalAddress here(__ pc()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
586 |
__ pushptr(here.addr()); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
587 |
#endif |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
588 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
589 |
__ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
590 |
assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
591 |
__ end_a_stub(); |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
592 |
return offset; |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
593 |
} |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
594 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
595 |
|
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
596 |
//============================================================================= |
a0e67b766e5c
8037821: Account for trampoline stubs when estimating code buffer sizes
goetz
parents:
22505
diff
changeset
|
597 |
|
11429 | 598 |
// Float masks come from different places depending on platform. |
599 |
#ifdef _LP64 |
|
600 |
static address float_signmask() { return StubRoutines::x86::float_sign_mask(); } |
|
601 |
static address float_signflip() { return StubRoutines::x86::float_sign_flip(); } |
|
602 |
static address double_signmask() { return StubRoutines::x86::double_sign_mask(); } |
|
603 |
static address double_signflip() { return StubRoutines::x86::double_sign_flip(); } |
|
604 |
#else |
|
605 |
static address float_signmask() { return (address)float_signmask_pool; } |
|
606 |
static address float_signflip() { return (address)float_signflip_pool; } |
|
607 |
static address double_signmask() { return (address)double_signmask_pool; } |
|
608 |
static address double_signflip() { return (address)double_signflip_pool; } |
|
609 |
#endif |
|
11794 | 610 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
611 |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
612 |
const bool Matcher::match_rule_supported(int opcode) { |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
613 |
if (!has_match_rule(opcode)) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
614 |
return false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
615 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
616 |
switch (opcode) { |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
617 |
case Op_PopCountI: |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
618 |
case Op_PopCountL: |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
619 |
if (!UsePopCountInstruction) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
620 |
return false; |
13883
6979b9850feb
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
13728
diff
changeset
|
621 |
break; |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
622 |
case Op_MulVI: |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
623 |
if ((UseSSE < 4) && (UseAVX < 1)) // only with SSE4_1 or AVX |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
624 |
return false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
625 |
break; |
30211 | 626 |
case Op_AddReductionVL: |
627 |
if (UseAVX < 3) // only EVEX : vector connectivity becomes an issue here |
|
628 |
return false; |
|
629 |
case Op_AddReductionVI: |
|
630 |
if (UseSSE < 3) // requires at least SSE3 |
|
631 |
return false; |
|
632 |
case Op_MulReductionVI: |
|
633 |
if (UseSSE < 4) // requires at least SSE4 |
|
634 |
return false; |
|
635 |
case Op_AddReductionVF: |
|
636 |
case Op_AddReductionVD: |
|
637 |
case Op_MulReductionVF: |
|
638 |
case Op_MulReductionVD: |
|
639 |
if (UseSSE < 1) // requires at least SSE |
|
640 |
return false; |
|
641 |
break; |
|
13886
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
642 |
case Op_CompareAndSwapL: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
643 |
#ifdef _LP64 |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
644 |
case Op_CompareAndSwapP: |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
645 |
#endif |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
646 |
if (!VM_Version::supports_cx8()) |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
647 |
return false; |
8d82c4dfa722
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
13883
diff
changeset
|
648 |
break; |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
649 |
} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
650 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
651 |
return true; // Per default match rules are supported. |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
652 |
} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
653 |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
654 |
// Max vector size in bytes. 0 if not supported. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
655 |
const int Matcher::vector_width_in_bytes(BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
656 |
assert(is_java_primitive(bt), "only primitive type vectors"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
657 |
if (UseSSE < 2) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
658 |
// SSE2 supports 128bit vectors for all types. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
659 |
// AVX2 supports 256bit vectors for all types. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
660 |
int size = (UseAVX > 1) ? 32 : 16; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
661 |
// AVX1 supports 256bit vectors only for FLOAT and DOUBLE. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
662 |
if (UseAVX > 0 && (bt == T_FLOAT || bt == T_DOUBLE)) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
663 |
size = 32; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
664 |
// Use flag to limit vector size. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
665 |
size = MIN2(size,(int)MaxVectorSize); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
666 |
// Minimum 2 values in vector (or 4 for bytes). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
667 |
switch (bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
668 |
case T_DOUBLE: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
669 |
case T_LONG: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
670 |
if (size < 16) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
671 |
case T_FLOAT: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
672 |
case T_INT: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
673 |
if (size < 8) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
674 |
case T_BOOLEAN: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
675 |
case T_BYTE: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
676 |
case T_CHAR: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
677 |
case T_SHORT: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
678 |
if (size < 4) return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
679 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
680 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
681 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
682 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
683 |
return size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
684 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
685 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
686 |
// Limits on vector size (number of elements) loaded into vector. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
687 |
const int Matcher::max_vector_size(const BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
688 |
return vector_width_in_bytes(bt)/type2aelembytes(bt); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
689 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
690 |
const int Matcher::min_vector_size(const BasicType bt) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
691 |
int max_size = max_vector_size(bt); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
692 |
// Min size which can be loaded into vector is 4 bytes. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
693 |
int size = (type2aelembytes(bt) == 1) ? 4 : 2; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
694 |
return MIN2(size,max_size); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
695 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
696 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
697 |
// Vector ideal reg corresponding to specidied size in bytes |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
698 |
const int Matcher::vector_ideal_reg(int size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
699 |
assert(MaxVectorSize >= size, ""); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
700 |
switch(size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
701 |
case 4: return Op_VecS; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
702 |
case 8: return Op_VecD; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
703 |
case 16: return Op_VecX; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
704 |
case 32: return Op_VecY; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
705 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
706 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
707 |
return 0; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
708 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
709 |
|
13930 | 710 |
// Only lowest bits of xmm reg are used for vector shift count. |
711 |
const int Matcher::vector_shift_count_ideal_reg(int size) { |
|
712 |
return Op_VecS; |
|
713 |
} |
|
714 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
715 |
// x86 supports misaligned vectors store/load. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
716 |
const bool Matcher::misaligned_vectors_ok() { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
717 |
return !AlignVector; // can be changed by flag |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
718 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
719 |
|
22505 | 720 |
// x86 AES instructions are compatible with SunJCE expanded |
721 |
// keys, hence we do not need to pass the original key to stubs |
|
722 |
const bool Matcher::pass_original_key_for_aes() { |
|
723 |
return false; |
|
724 |
} |
|
725 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
726 |
// Helper methods for MachSpillCopyNode::implementation(). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
727 |
static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
728 |
int src_hi, int dst_hi, uint ireg, outputStream* st) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
729 |
// In 64-bit VM size calculation is very complex. Emitting instructions |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
730 |
// into scratch buffer is used to get size in 64-bit VM. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
731 |
LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
732 |
assert(ireg == Op_VecS || // 32bit vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
733 |
(src_lo & 1) == 0 && (src_lo + 1) == src_hi && |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
734 |
(dst_lo & 1) == 0 && (dst_lo + 1) == dst_hi, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
735 |
"no non-adjacent vector moves" ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
736 |
if (cbuf) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
737 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
738 |
int offset = __ offset(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
739 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
740 |
case Op_VecS: // copy whole register |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
741 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
742 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
743 |
__ movdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
744 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
745 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
746 |
__ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
747 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
748 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
749 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
750 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
751 |
int size = __ offset() - offset; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
752 |
#ifdef ASSERT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
753 |
// VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
754 |
assert(!do_size || size == 4, "incorrect size calculattion"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
755 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
756 |
return size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
757 |
#ifndef PRODUCT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
758 |
} else if (!do_size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
759 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
760 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
761 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
762 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
763 |
st->print("movdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
764 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
765 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
766 |
st->print("vmovdqu %s,%s\t# spill",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
767 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
768 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
769 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
770 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
771 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
772 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
773 |
// VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
774 |
return 4; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
775 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
776 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
777 |
static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
778 |
int stack_offset, int reg, uint ireg, outputStream* st) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
779 |
// In 64-bit VM size calculation is very complex. Emitting instructions |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
780 |
// into scratch buffer is used to get size in 64-bit VM. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
781 |
LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
782 |
if (cbuf) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
783 |
MacroAssembler _masm(cbuf); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
784 |
int offset = __ offset(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
785 |
if (is_load) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
786 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
787 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
788 |
__ movdl(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
789 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
790 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
791 |
__ movq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
792 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
793 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
794 |
__ movdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
795 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
796 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
797 |
__ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
798 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
799 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
800 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
801 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
802 |
} else { // store |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
803 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
804 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
805 |
__ movdl(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
806 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
807 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
808 |
__ movq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
809 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
810 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
811 |
__ movdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
812 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
813 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
814 |
__ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg])); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
815 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
816 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
817 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
818 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
819 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
820 |
int size = __ offset() - offset; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
821 |
#ifdef ASSERT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
822 |
int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
823 |
// VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
824 |
assert(!do_size || size == (5+offset_size), "incorrect size calculattion"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
825 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
826 |
return size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
827 |
#ifndef PRODUCT |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
828 |
} else if (!do_size) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
829 |
if (is_load) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
830 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
831 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
832 |
st->print("movd %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
833 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
834 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
835 |
st->print("movq %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
836 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
837 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
838 |
st->print("movdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
839 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
840 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
841 |
st->print("vmovdqu %s,[rsp + %d]\t# spill", Matcher::regName[reg], stack_offset); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
842 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
843 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
844 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
845 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
846 |
} else { // store |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
847 |
switch (ireg) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
848 |
case Op_VecS: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
849 |
st->print("movd [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
850 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
851 |
case Op_VecD: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
852 |
st->print("movq [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
853 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
854 |
case Op_VecX: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
855 |
st->print("movdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
856 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
857 |
case Op_VecY: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
858 |
st->print("vmovdqu [rsp + %d],%s\t# spill", stack_offset, Matcher::regName[reg]); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
859 |
break; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
860 |
default: |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
861 |
ShouldNotReachHere(); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
862 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
863 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
864 |
#endif |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
865 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
866 |
int offset_size = (stack_offset == 0) ? 0 : ((stack_offset < 0x80) ? 1 : 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
867 |
// VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
868 |
return 5+offset_size; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
869 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
870 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
871 |
static inline jfloat replicate4_imm(int con, int width) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
872 |
// Load a constant of "width" (in bytes) and replicate it to fill 32bit. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
873 |
assert(width == 1 || width == 2, "only byte or short types here"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
874 |
int bit_width = width * 8; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
875 |
jint val = con; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
876 |
val &= (1 << bit_width) - 1; // mask off sign bits |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
877 |
while(bit_width < 32) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
878 |
val |= (val << bit_width); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
879 |
bit_width <<= 1; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
880 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
881 |
jfloat fval = *((jfloat*) &val); // coerce to float type |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
882 |
return fval; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
883 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
884 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
885 |
static inline jdouble replicate8_imm(int con, int width) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
886 |
// Load a constant of "width" (in bytes) and replicate it to fill 64bit. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
887 |
assert(width == 1 || width == 2 || width == 4, "only byte, short or int types here"); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
888 |
int bit_width = width * 8; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
889 |
jlong val = con; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
890 |
val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
891 |
while(bit_width < 64) { |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
892 |
val |= (val << bit_width); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
893 |
bit_width <<= 1; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
894 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
895 |
jdouble dval = *((jdouble*) &val); // coerce to double type |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
896 |
return dval; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
897 |
} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
898 |
|
11794 | 899 |
#ifndef PRODUCT |
900 |
void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const { |
|
901 |
st->print("nop \t# %d bytes pad for loops and calls", _count); |
|
902 |
} |
|
903 |
#endif |
|
904 |
||
905 |
void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const { |
|
906 |
MacroAssembler _masm(&cbuf); |
|
907 |
__ nop(_count); |
|
908 |
} |
|
909 |
||
910 |
uint MachNopNode::size(PhaseRegAlloc*) const { |
|
911 |
return _count; |
|
912 |
} |
|
913 |
||
914 |
#ifndef PRODUCT |
|
915 |
void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const { |
|
916 |
st->print("# breakpoint"); |
|
917 |
} |
|
918 |
#endif |
|
919 |
||
920 |
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const { |
|
921 |
MacroAssembler _masm(&cbuf); |
|
922 |
__ int3(); |
|
923 |
} |
|
924 |
||
925 |
uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const { |
|
926 |
return MachNode::size(ra_); |
|
927 |
} |
|
928 |
||
929 |
%} |
|
930 |
||
931 |
encode %{ |
|
932 |
||
933 |
enc_class call_epilog %{ |
|
934 |
if (VerifyStackAtCalls) { |
|
935 |
// Check that stack depth is unchanged: find majik cookie on stack |
|
936 |
int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word)); |
|
937 |
MacroAssembler _masm(&cbuf); |
|
938 |
Label L; |
|
939 |
__ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d); |
|
940 |
__ jccb(Assembler::equal, L); |
|
941 |
// Die if stack mismatch |
|
942 |
__ int3(); |
|
943 |
__ bind(L); |
|
944 |
} |
|
945 |
%} |
|
946 |
||
11429 | 947 |
%} |
948 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
949 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
950 |
//----------OPERANDS----------------------------------------------------------- |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
951 |
// Operand definitions must precede instruction definitions for correct parsing |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
952 |
// in the ADLC because operands constitute user defined types which are used in |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
953 |
// instruction definitions. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
954 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
955 |
// Vectors |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
956 |
operand vecS() %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
957 |
constraint(ALLOC_IN_RC(vectors_reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
958 |
match(VecS); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
959 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
960 |
format %{ %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
961 |
interface(REG_INTER); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
962 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
963 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
964 |
operand vecD() %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
965 |
constraint(ALLOC_IN_RC(vectord_reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
966 |
match(VecD); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
967 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
968 |
format %{ %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
969 |
interface(REG_INTER); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
970 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
971 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
972 |
operand vecX() %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
973 |
constraint(ALLOC_IN_RC(vectorx_reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
974 |
match(VecX); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
975 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
976 |
format %{ %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
977 |
interface(REG_INTER); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
978 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
979 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
980 |
operand vecY() %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
981 |
constraint(ALLOC_IN_RC(vectory_reg)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
982 |
match(VecY); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
983 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
984 |
format %{ %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
985 |
interface(REG_INTER); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
986 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
987 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
988 |
|
11429 | 989 |
// INSTRUCTIONS -- Platform independent definitions (same for 32- and 64-bit) |
990 |
||
11794 | 991 |
// ============================================================================ |
992 |
||
993 |
instruct ShouldNotReachHere() %{ |
|
994 |
match(Halt); |
|
995 |
format %{ "int3\t# ShouldNotReachHere" %} |
|
996 |
ins_encode %{ |
|
997 |
__ int3(); |
|
998 |
%} |
|
999 |
ins_pipe(pipe_slow); |
|
1000 |
%} |
|
1001 |
||
1002 |
// ============================================================================ |
|
1003 |
||
11429 | 1004 |
instruct addF_reg(regF dst, regF src) %{ |
1005 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1006 |
match(Set dst (AddF dst src)); |
|
1007 |
||
1008 |
format %{ "addss $dst, $src" %} |
|
1009 |
ins_cost(150); |
|
1010 |
ins_encode %{ |
|
1011 |
__ addss($dst$$XMMRegister, $src$$XMMRegister); |
|
1012 |
%} |
|
1013 |
ins_pipe(pipe_slow); |
|
1014 |
%} |
|
1015 |
||
1016 |
instruct addF_mem(regF dst, memory src) %{ |
|
1017 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1018 |
match(Set dst (AddF dst (LoadF src))); |
|
1019 |
||
1020 |
format %{ "addss $dst, $src" %} |
|
1021 |
ins_cost(150); |
|
1022 |
ins_encode %{ |
|
1023 |
__ addss($dst$$XMMRegister, $src$$Address); |
|
1024 |
%} |
|
1025 |
ins_pipe(pipe_slow); |
|
1026 |
%} |
|
1027 |
||
1028 |
instruct addF_imm(regF dst, immF con) %{ |
|
1029 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1030 |
match(Set dst (AddF dst con)); |
|
1031 |
format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1032 |
ins_cost(150); |
|
1033 |
ins_encode %{ |
|
1034 |
__ addss($dst$$XMMRegister, $constantaddress($con)); |
|
1035 |
%} |
|
1036 |
ins_pipe(pipe_slow); |
|
1037 |
%} |
|
1038 |
||
13294 | 1039 |
instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 1040 |
predicate(UseAVX > 0); |
1041 |
match(Set dst (AddF src1 src2)); |
|
1042 |
||
1043 |
format %{ "vaddss $dst, $src1, $src2" %} |
|
1044 |
ins_cost(150); |
|
1045 |
ins_encode %{ |
|
1046 |
__ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1047 |
%} |
|
1048 |
ins_pipe(pipe_slow); |
|
1049 |
%} |
|
1050 |
||
13294 | 1051 |
instruct addF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 1052 |
predicate(UseAVX > 0); |
1053 |
match(Set dst (AddF src1 (LoadF src2))); |
|
1054 |
||
1055 |
format %{ "vaddss $dst, $src1, $src2" %} |
|
1056 |
ins_cost(150); |
|
1057 |
ins_encode %{ |
|
1058 |
__ vaddss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1059 |
%} |
|
1060 |
ins_pipe(pipe_slow); |
|
1061 |
%} |
|
1062 |
||
13294 | 1063 |
instruct addF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 1064 |
predicate(UseAVX > 0); |
1065 |
match(Set dst (AddF src con)); |
|
1066 |
||
1067 |
format %{ "vaddss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1068 |
ins_cost(150); |
|
1069 |
ins_encode %{ |
|
1070 |
__ vaddss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1071 |
%} |
|
1072 |
ins_pipe(pipe_slow); |
|
1073 |
%} |
|
1074 |
||
1075 |
instruct addD_reg(regD dst, regD src) %{ |
|
1076 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1077 |
match(Set dst (AddD dst src)); |
|
1078 |
||
1079 |
format %{ "addsd $dst, $src" %} |
|
1080 |
ins_cost(150); |
|
1081 |
ins_encode %{ |
|
1082 |
__ addsd($dst$$XMMRegister, $src$$XMMRegister); |
|
1083 |
%} |
|
1084 |
ins_pipe(pipe_slow); |
|
1085 |
%} |
|
1086 |
||
1087 |
instruct addD_mem(regD dst, memory src) %{ |
|
1088 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1089 |
match(Set dst (AddD dst (LoadD src))); |
|
1090 |
||
1091 |
format %{ "addsd $dst, $src" %} |
|
1092 |
ins_cost(150); |
|
1093 |
ins_encode %{ |
|
1094 |
__ addsd($dst$$XMMRegister, $src$$Address); |
|
1095 |
%} |
|
1096 |
ins_pipe(pipe_slow); |
|
1097 |
%} |
|
1098 |
||
1099 |
instruct addD_imm(regD dst, immD con) %{ |
|
1100 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1101 |
match(Set dst (AddD dst con)); |
|
1102 |
format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1103 |
ins_cost(150); |
|
1104 |
ins_encode %{ |
|
1105 |
__ addsd($dst$$XMMRegister, $constantaddress($con)); |
|
1106 |
%} |
|
1107 |
ins_pipe(pipe_slow); |
|
1108 |
%} |
|
1109 |
||
13294 | 1110 |
instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 1111 |
predicate(UseAVX > 0); |
1112 |
match(Set dst (AddD src1 src2)); |
|
1113 |
||
1114 |
format %{ "vaddsd $dst, $src1, $src2" %} |
|
1115 |
ins_cost(150); |
|
1116 |
ins_encode %{ |
|
1117 |
__ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1118 |
%} |
|
1119 |
ins_pipe(pipe_slow); |
|
1120 |
%} |
|
1121 |
||
13294 | 1122 |
instruct addD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 1123 |
predicate(UseAVX > 0); |
1124 |
match(Set dst (AddD src1 (LoadD src2))); |
|
1125 |
||
1126 |
format %{ "vaddsd $dst, $src1, $src2" %} |
|
1127 |
ins_cost(150); |
|
1128 |
ins_encode %{ |
|
1129 |
__ vaddsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1130 |
%} |
|
1131 |
ins_pipe(pipe_slow); |
|
1132 |
%} |
|
1133 |
||
13294 | 1134 |
instruct addD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 1135 |
predicate(UseAVX > 0); |
1136 |
match(Set dst (AddD src con)); |
|
1137 |
||
1138 |
format %{ "vaddsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1139 |
ins_cost(150); |
|
1140 |
ins_encode %{ |
|
1141 |
__ vaddsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1142 |
%} |
|
1143 |
ins_pipe(pipe_slow); |
|
1144 |
%} |
|
1145 |
||
1146 |
instruct subF_reg(regF dst, regF src) %{ |
|
1147 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1148 |
match(Set dst (SubF dst src)); |
|
1149 |
||
1150 |
format %{ "subss $dst, $src" %} |
|
1151 |
ins_cost(150); |
|
1152 |
ins_encode %{ |
|
1153 |
__ subss($dst$$XMMRegister, $src$$XMMRegister); |
|
1154 |
%} |
|
1155 |
ins_pipe(pipe_slow); |
|
1156 |
%} |
|
1157 |
||
1158 |
instruct subF_mem(regF dst, memory src) %{ |
|
1159 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1160 |
match(Set dst (SubF dst (LoadF src))); |
|
1161 |
||
1162 |
format %{ "subss $dst, $src" %} |
|
1163 |
ins_cost(150); |
|
1164 |
ins_encode %{ |
|
1165 |
__ subss($dst$$XMMRegister, $src$$Address); |
|
1166 |
%} |
|
1167 |
ins_pipe(pipe_slow); |
|
1168 |
%} |
|
1169 |
||
1170 |
instruct subF_imm(regF dst, immF con) %{ |
|
1171 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1172 |
match(Set dst (SubF dst con)); |
|
1173 |
format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1174 |
ins_cost(150); |
|
1175 |
ins_encode %{ |
|
1176 |
__ subss($dst$$XMMRegister, $constantaddress($con)); |
|
1177 |
%} |
|
1178 |
ins_pipe(pipe_slow); |
|
1179 |
%} |
|
1180 |
||
13294 | 1181 |
instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 1182 |
predicate(UseAVX > 0); |
1183 |
match(Set dst (SubF src1 src2)); |
|
1184 |
||
1185 |
format %{ "vsubss $dst, $src1, $src2" %} |
|
1186 |
ins_cost(150); |
|
1187 |
ins_encode %{ |
|
1188 |
__ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1189 |
%} |
|
1190 |
ins_pipe(pipe_slow); |
|
1191 |
%} |
|
1192 |
||
13294 | 1193 |
instruct subF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 1194 |
predicate(UseAVX > 0); |
1195 |
match(Set dst (SubF src1 (LoadF src2))); |
|
1196 |
||
1197 |
format %{ "vsubss $dst, $src1, $src2" %} |
|
1198 |
ins_cost(150); |
|
1199 |
ins_encode %{ |
|
1200 |
__ vsubss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1201 |
%} |
|
1202 |
ins_pipe(pipe_slow); |
|
1203 |
%} |
|
1204 |
||
13294 | 1205 |
instruct subF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 1206 |
predicate(UseAVX > 0); |
1207 |
match(Set dst (SubF src con)); |
|
1208 |
||
1209 |
format %{ "vsubss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1210 |
ins_cost(150); |
|
1211 |
ins_encode %{ |
|
1212 |
__ vsubss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1213 |
%} |
|
1214 |
ins_pipe(pipe_slow); |
|
1215 |
%} |
|
1216 |
||
1217 |
instruct subD_reg(regD dst, regD src) %{ |
|
1218 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1219 |
match(Set dst (SubD dst src)); |
|
1220 |
||
1221 |
format %{ "subsd $dst, $src" %} |
|
1222 |
ins_cost(150); |
|
1223 |
ins_encode %{ |
|
1224 |
__ subsd($dst$$XMMRegister, $src$$XMMRegister); |
|
1225 |
%} |
|
1226 |
ins_pipe(pipe_slow); |
|
1227 |
%} |
|
1228 |
||
1229 |
instruct subD_mem(regD dst, memory src) %{ |
|
1230 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1231 |
match(Set dst (SubD dst (LoadD src))); |
|
1232 |
||
1233 |
format %{ "subsd $dst, $src" %} |
|
1234 |
ins_cost(150); |
|
1235 |
ins_encode %{ |
|
1236 |
__ subsd($dst$$XMMRegister, $src$$Address); |
|
1237 |
%} |
|
1238 |
ins_pipe(pipe_slow); |
|
1239 |
%} |
|
1240 |
||
1241 |
instruct subD_imm(regD dst, immD con) %{ |
|
1242 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1243 |
match(Set dst (SubD dst con)); |
|
1244 |
format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1245 |
ins_cost(150); |
|
1246 |
ins_encode %{ |
|
1247 |
__ subsd($dst$$XMMRegister, $constantaddress($con)); |
|
1248 |
%} |
|
1249 |
ins_pipe(pipe_slow); |
|
1250 |
%} |
|
1251 |
||
13294 | 1252 |
instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 1253 |
predicate(UseAVX > 0); |
1254 |
match(Set dst (SubD src1 src2)); |
|
1255 |
||
1256 |
format %{ "vsubsd $dst, $src1, $src2" %} |
|
1257 |
ins_cost(150); |
|
1258 |
ins_encode %{ |
|
1259 |
__ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1260 |
%} |
|
1261 |
ins_pipe(pipe_slow); |
|
1262 |
%} |
|
1263 |
||
13294 | 1264 |
instruct subD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 1265 |
predicate(UseAVX > 0); |
1266 |
match(Set dst (SubD src1 (LoadD src2))); |
|
1267 |
||
1268 |
format %{ "vsubsd $dst, $src1, $src2" %} |
|
1269 |
ins_cost(150); |
|
1270 |
ins_encode %{ |
|
1271 |
__ vsubsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1272 |
%} |
|
1273 |
ins_pipe(pipe_slow); |
|
1274 |
%} |
|
1275 |
||
13294 | 1276 |
instruct subD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 1277 |
predicate(UseAVX > 0); |
1278 |
match(Set dst (SubD src con)); |
|
1279 |
||
1280 |
format %{ "vsubsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1281 |
ins_cost(150); |
|
1282 |
ins_encode %{ |
|
1283 |
__ vsubsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1284 |
%} |
|
1285 |
ins_pipe(pipe_slow); |
|
1286 |
%} |
|
1287 |
||
1288 |
instruct mulF_reg(regF dst, regF src) %{ |
|
1289 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1290 |
match(Set dst (MulF dst src)); |
|
1291 |
||
1292 |
format %{ "mulss $dst, $src" %} |
|
1293 |
ins_cost(150); |
|
1294 |
ins_encode %{ |
|
1295 |
__ mulss($dst$$XMMRegister, $src$$XMMRegister); |
|
1296 |
%} |
|
1297 |
ins_pipe(pipe_slow); |
|
1298 |
%} |
|
1299 |
||
1300 |
instruct mulF_mem(regF dst, memory src) %{ |
|
1301 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1302 |
match(Set dst (MulF dst (LoadF src))); |
|
1303 |
||
1304 |
format %{ "mulss $dst, $src" %} |
|
1305 |
ins_cost(150); |
|
1306 |
ins_encode %{ |
|
1307 |
__ mulss($dst$$XMMRegister, $src$$Address); |
|
1308 |
%} |
|
1309 |
ins_pipe(pipe_slow); |
|
1310 |
%} |
|
1311 |
||
1312 |
instruct mulF_imm(regF dst, immF con) %{ |
|
1313 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1314 |
match(Set dst (MulF dst con)); |
|
1315 |
format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1316 |
ins_cost(150); |
|
1317 |
ins_encode %{ |
|
1318 |
__ mulss($dst$$XMMRegister, $constantaddress($con)); |
|
1319 |
%} |
|
1320 |
ins_pipe(pipe_slow); |
|
1321 |
%} |
|
1322 |
||
13294 | 1323 |
instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 1324 |
predicate(UseAVX > 0); |
1325 |
match(Set dst (MulF src1 src2)); |
|
1326 |
||
1327 |
format %{ "vmulss $dst, $src1, $src2" %} |
|
1328 |
ins_cost(150); |
|
1329 |
ins_encode %{ |
|
1330 |
__ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1331 |
%} |
|
1332 |
ins_pipe(pipe_slow); |
|
1333 |
%} |
|
1334 |
||
13294 | 1335 |
instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 1336 |
predicate(UseAVX > 0); |
1337 |
match(Set dst (MulF src1 (LoadF src2))); |
|
1338 |
||
1339 |
format %{ "vmulss $dst, $src1, $src2" %} |
|
1340 |
ins_cost(150); |
|
1341 |
ins_encode %{ |
|
1342 |
__ vmulss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1343 |
%} |
|
1344 |
ins_pipe(pipe_slow); |
|
1345 |
%} |
|
1346 |
||
13294 | 1347 |
instruct mulF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 1348 |
predicate(UseAVX > 0); |
1349 |
match(Set dst (MulF src con)); |
|
1350 |
||
1351 |
format %{ "vmulss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1352 |
ins_cost(150); |
|
1353 |
ins_encode %{ |
|
1354 |
__ vmulss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1355 |
%} |
|
1356 |
ins_pipe(pipe_slow); |
|
1357 |
%} |
|
1358 |
||
1359 |
instruct mulD_reg(regD dst, regD src) %{ |
|
1360 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1361 |
match(Set dst (MulD dst src)); |
|
1362 |
||
1363 |
format %{ "mulsd $dst, $src" %} |
|
1364 |
ins_cost(150); |
|
1365 |
ins_encode %{ |
|
1366 |
__ mulsd($dst$$XMMRegister, $src$$XMMRegister); |
|
1367 |
%} |
|
1368 |
ins_pipe(pipe_slow); |
|
1369 |
%} |
|
1370 |
||
1371 |
instruct mulD_mem(regD dst, memory src) %{ |
|
1372 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1373 |
match(Set dst (MulD dst (LoadD src))); |
|
1374 |
||
1375 |
format %{ "mulsd $dst, $src" %} |
|
1376 |
ins_cost(150); |
|
1377 |
ins_encode %{ |
|
1378 |
__ mulsd($dst$$XMMRegister, $src$$Address); |
|
1379 |
%} |
|
1380 |
ins_pipe(pipe_slow); |
|
1381 |
%} |
|
1382 |
||
1383 |
instruct mulD_imm(regD dst, immD con) %{ |
|
1384 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1385 |
match(Set dst (MulD dst con)); |
|
1386 |
format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1387 |
ins_cost(150); |
|
1388 |
ins_encode %{ |
|
1389 |
__ mulsd($dst$$XMMRegister, $constantaddress($con)); |
|
1390 |
%} |
|
1391 |
ins_pipe(pipe_slow); |
|
1392 |
%} |
|
1393 |
||
13294 | 1394 |
instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 1395 |
predicate(UseAVX > 0); |
1396 |
match(Set dst (MulD src1 src2)); |
|
1397 |
||
1398 |
format %{ "vmulsd $dst, $src1, $src2" %} |
|
1399 |
ins_cost(150); |
|
1400 |
ins_encode %{ |
|
1401 |
__ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1402 |
%} |
|
1403 |
ins_pipe(pipe_slow); |
|
1404 |
%} |
|
1405 |
||
13294 | 1406 |
instruct mulD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 1407 |
predicate(UseAVX > 0); |
1408 |
match(Set dst (MulD src1 (LoadD src2))); |
|
1409 |
||
1410 |
format %{ "vmulsd $dst, $src1, $src2" %} |
|
1411 |
ins_cost(150); |
|
1412 |
ins_encode %{ |
|
1413 |
__ vmulsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1414 |
%} |
|
1415 |
ins_pipe(pipe_slow); |
|
1416 |
%} |
|
1417 |
||
13294 | 1418 |
instruct mulD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 1419 |
predicate(UseAVX > 0); |
1420 |
match(Set dst (MulD src con)); |
|
1421 |
||
1422 |
format %{ "vmulsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1423 |
ins_cost(150); |
|
1424 |
ins_encode %{ |
|
1425 |
__ vmulsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1426 |
%} |
|
1427 |
ins_pipe(pipe_slow); |
|
1428 |
%} |
|
1429 |
||
1430 |
instruct divF_reg(regF dst, regF src) %{ |
|
1431 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1432 |
match(Set dst (DivF dst src)); |
|
1433 |
||
1434 |
format %{ "divss $dst, $src" %} |
|
1435 |
ins_cost(150); |
|
1436 |
ins_encode %{ |
|
1437 |
__ divss($dst$$XMMRegister, $src$$XMMRegister); |
|
1438 |
%} |
|
1439 |
ins_pipe(pipe_slow); |
|
1440 |
%} |
|
1441 |
||
1442 |
instruct divF_mem(regF dst, memory src) %{ |
|
1443 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1444 |
match(Set dst (DivF dst (LoadF src))); |
|
1445 |
||
1446 |
format %{ "divss $dst, $src" %} |
|
1447 |
ins_cost(150); |
|
1448 |
ins_encode %{ |
|
1449 |
__ divss($dst$$XMMRegister, $src$$Address); |
|
1450 |
%} |
|
1451 |
ins_pipe(pipe_slow); |
|
1452 |
%} |
|
1453 |
||
1454 |
instruct divF_imm(regF dst, immF con) %{ |
|
1455 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1456 |
match(Set dst (DivF dst con)); |
|
1457 |
format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1458 |
ins_cost(150); |
|
1459 |
ins_encode %{ |
|
1460 |
__ divss($dst$$XMMRegister, $constantaddress($con)); |
|
1461 |
%} |
|
1462 |
ins_pipe(pipe_slow); |
|
1463 |
%} |
|
1464 |
||
13294 | 1465 |
instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ |
11429 | 1466 |
predicate(UseAVX > 0); |
1467 |
match(Set dst (DivF src1 src2)); |
|
1468 |
||
1469 |
format %{ "vdivss $dst, $src1, $src2" %} |
|
1470 |
ins_cost(150); |
|
1471 |
ins_encode %{ |
|
1472 |
__ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1473 |
%} |
|
1474 |
ins_pipe(pipe_slow); |
|
1475 |
%} |
|
1476 |
||
13294 | 1477 |
instruct divF_reg_mem(regF dst, regF src1, memory src2) %{ |
11429 | 1478 |
predicate(UseAVX > 0); |
1479 |
match(Set dst (DivF src1 (LoadF src2))); |
|
1480 |
||
1481 |
format %{ "vdivss $dst, $src1, $src2" %} |
|
1482 |
ins_cost(150); |
|
1483 |
ins_encode %{ |
|
1484 |
__ vdivss($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1485 |
%} |
|
1486 |
ins_pipe(pipe_slow); |
|
1487 |
%} |
|
1488 |
||
13294 | 1489 |
instruct divF_reg_imm(regF dst, regF src, immF con) %{ |
11429 | 1490 |
predicate(UseAVX > 0); |
1491 |
match(Set dst (DivF src con)); |
|
1492 |
||
1493 |
format %{ "vdivss $dst, $src, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1494 |
ins_cost(150); |
|
1495 |
ins_encode %{ |
|
1496 |
__ vdivss($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1497 |
%} |
|
1498 |
ins_pipe(pipe_slow); |
|
1499 |
%} |
|
1500 |
||
1501 |
instruct divD_reg(regD dst, regD src) %{ |
|
1502 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1503 |
match(Set dst (DivD dst src)); |
|
1504 |
||
1505 |
format %{ "divsd $dst, $src" %} |
|
1506 |
ins_cost(150); |
|
1507 |
ins_encode %{ |
|
1508 |
__ divsd($dst$$XMMRegister, $src$$XMMRegister); |
|
1509 |
%} |
|
1510 |
ins_pipe(pipe_slow); |
|
1511 |
%} |
|
1512 |
||
1513 |
instruct divD_mem(regD dst, memory src) %{ |
|
1514 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1515 |
match(Set dst (DivD dst (LoadD src))); |
|
1516 |
||
1517 |
format %{ "divsd $dst, $src" %} |
|
1518 |
ins_cost(150); |
|
1519 |
ins_encode %{ |
|
1520 |
__ divsd($dst$$XMMRegister, $src$$Address); |
|
1521 |
%} |
|
1522 |
ins_pipe(pipe_slow); |
|
1523 |
%} |
|
1524 |
||
1525 |
instruct divD_imm(regD dst, immD con) %{ |
|
1526 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1527 |
match(Set dst (DivD dst con)); |
|
1528 |
format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1529 |
ins_cost(150); |
|
1530 |
ins_encode %{ |
|
1531 |
__ divsd($dst$$XMMRegister, $constantaddress($con)); |
|
1532 |
%} |
|
1533 |
ins_pipe(pipe_slow); |
|
1534 |
%} |
|
1535 |
||
13294 | 1536 |
instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ |
11429 | 1537 |
predicate(UseAVX > 0); |
1538 |
match(Set dst (DivD src1 src2)); |
|
1539 |
||
1540 |
format %{ "vdivsd $dst, $src1, $src2" %} |
|
1541 |
ins_cost(150); |
|
1542 |
ins_encode %{ |
|
1543 |
__ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
1544 |
%} |
|
1545 |
ins_pipe(pipe_slow); |
|
1546 |
%} |
|
1547 |
||
13294 | 1548 |
instruct divD_reg_mem(regD dst, regD src1, memory src2) %{ |
11429 | 1549 |
predicate(UseAVX > 0); |
1550 |
match(Set dst (DivD src1 (LoadD src2))); |
|
1551 |
||
1552 |
format %{ "vdivsd $dst, $src1, $src2" %} |
|
1553 |
ins_cost(150); |
|
1554 |
ins_encode %{ |
|
1555 |
__ vdivsd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$Address); |
|
1556 |
%} |
|
1557 |
ins_pipe(pipe_slow); |
|
1558 |
%} |
|
1559 |
||
13294 | 1560 |
instruct divD_reg_imm(regD dst, regD src, immD con) %{ |
11429 | 1561 |
predicate(UseAVX > 0); |
1562 |
match(Set dst (DivD src con)); |
|
1563 |
||
1564 |
format %{ "vdivsd $dst, $src, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1565 |
ins_cost(150); |
|
1566 |
ins_encode %{ |
|
1567 |
__ vdivsd($dst$$XMMRegister, $src$$XMMRegister, $constantaddress($con)); |
|
1568 |
%} |
|
1569 |
ins_pipe(pipe_slow); |
|
1570 |
%} |
|
1571 |
||
1572 |
instruct absF_reg(regF dst) %{ |
|
1573 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1574 |
match(Set dst (AbsF dst)); |
|
1575 |
ins_cost(150); |
|
1576 |
format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} |
|
1577 |
ins_encode %{ |
|
1578 |
__ andps($dst$$XMMRegister, ExternalAddress(float_signmask())); |
|
1579 |
%} |
|
1580 |
ins_pipe(pipe_slow); |
|
1581 |
%} |
|
1582 |
||
13294 | 1583 |
instruct absF_reg_reg(regF dst, regF src) %{ |
11429 | 1584 |
predicate(UseAVX > 0); |
1585 |
match(Set dst (AbsF src)); |
|
1586 |
ins_cost(150); |
|
1587 |
format %{ "vandps $dst, $src, [0x7fffffff]\t# abs float by sign masking" %} |
|
1588 |
ins_encode %{ |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1589 |
bool vector256 = false; |
11429 | 1590 |
__ vandps($dst$$XMMRegister, $src$$XMMRegister, |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1591 |
ExternalAddress(float_signmask()), vector256); |
11429 | 1592 |
%} |
1593 |
ins_pipe(pipe_slow); |
|
1594 |
%} |
|
1595 |
||
1596 |
instruct absD_reg(regD dst) %{ |
|
1597 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1598 |
match(Set dst (AbsD dst)); |
|
1599 |
ins_cost(150); |
|
1600 |
format %{ "andpd $dst, [0x7fffffffffffffff]\t" |
|
1601 |
"# abs double by sign masking" %} |
|
1602 |
ins_encode %{ |
|
1603 |
__ andpd($dst$$XMMRegister, ExternalAddress(double_signmask())); |
|
1604 |
%} |
|
1605 |
ins_pipe(pipe_slow); |
|
1606 |
%} |
|
1607 |
||
13294 | 1608 |
instruct absD_reg_reg(regD dst, regD src) %{ |
11429 | 1609 |
predicate(UseAVX > 0); |
1610 |
match(Set dst (AbsD src)); |
|
1611 |
ins_cost(150); |
|
1612 |
format %{ "vandpd $dst, $src, [0x7fffffffffffffff]\t" |
|
1613 |
"# abs double by sign masking" %} |
|
1614 |
ins_encode %{ |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1615 |
bool vector256 = false; |
11429 | 1616 |
__ vandpd($dst$$XMMRegister, $src$$XMMRegister, |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1617 |
ExternalAddress(double_signmask()), vector256); |
11429 | 1618 |
%} |
1619 |
ins_pipe(pipe_slow); |
|
1620 |
%} |
|
1621 |
||
1622 |
instruct negF_reg(regF dst) %{ |
|
1623 |
predicate((UseSSE>=1) && (UseAVX == 0)); |
|
1624 |
match(Set dst (NegF dst)); |
|
1625 |
ins_cost(150); |
|
1626 |
format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} |
|
1627 |
ins_encode %{ |
|
1628 |
__ xorps($dst$$XMMRegister, ExternalAddress(float_signflip())); |
|
1629 |
%} |
|
1630 |
ins_pipe(pipe_slow); |
|
1631 |
%} |
|
1632 |
||
13294 | 1633 |
instruct negF_reg_reg(regF dst, regF src) %{ |
11429 | 1634 |
predicate(UseAVX > 0); |
1635 |
match(Set dst (NegF src)); |
|
1636 |
ins_cost(150); |
|
1637 |
format %{ "vxorps $dst, $src, [0x80000000]\t# neg float by sign flipping" %} |
|
1638 |
ins_encode %{ |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1639 |
bool vector256 = false; |
11429 | 1640 |
__ vxorps($dst$$XMMRegister, $src$$XMMRegister, |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1641 |
ExternalAddress(float_signflip()), vector256); |
11429 | 1642 |
%} |
1643 |
ins_pipe(pipe_slow); |
|
1644 |
%} |
|
1645 |
||
1646 |
instruct negD_reg(regD dst) %{ |
|
1647 |
predicate((UseSSE>=2) && (UseAVX == 0)); |
|
1648 |
match(Set dst (NegD dst)); |
|
1649 |
ins_cost(150); |
|
1650 |
format %{ "xorpd $dst, [0x8000000000000000]\t" |
|
1651 |
"# neg double by sign flipping" %} |
|
1652 |
ins_encode %{ |
|
1653 |
__ xorpd($dst$$XMMRegister, ExternalAddress(double_signflip())); |
|
1654 |
%} |
|
1655 |
ins_pipe(pipe_slow); |
|
1656 |
%} |
|
1657 |
||
13294 | 1658 |
instruct negD_reg_reg(regD dst, regD src) %{ |
11429 | 1659 |
predicate(UseAVX > 0); |
1660 |
match(Set dst (NegD src)); |
|
1661 |
ins_cost(150); |
|
1662 |
format %{ "vxorpd $dst, $src, [0x8000000000000000]\t" |
|
1663 |
"# neg double by sign flipping" %} |
|
1664 |
ins_encode %{ |
|
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1665 |
bool vector256 = false; |
11429 | 1666 |
__ vxorpd($dst$$XMMRegister, $src$$XMMRegister, |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
1667 |
ExternalAddress(double_signflip()), vector256); |
11429 | 1668 |
%} |
1669 |
ins_pipe(pipe_slow); |
|
1670 |
%} |
|
1671 |
||
1672 |
instruct sqrtF_reg(regF dst, regF src) %{ |
|
1673 |
predicate(UseSSE>=1); |
|
1674 |
match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); |
|
1675 |
||
1676 |
format %{ "sqrtss $dst, $src" %} |
|
1677 |
ins_cost(150); |
|
1678 |
ins_encode %{ |
|
1679 |
__ sqrtss($dst$$XMMRegister, $src$$XMMRegister); |
|
1680 |
%} |
|
1681 |
ins_pipe(pipe_slow); |
|
1682 |
%} |
|
1683 |
||
1684 |
instruct sqrtF_mem(regF dst, memory src) %{ |
|
1685 |
predicate(UseSSE>=1); |
|
1686 |
match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); |
|
1687 |
||
1688 |
format %{ "sqrtss $dst, $src" %} |
|
1689 |
ins_cost(150); |
|
1690 |
ins_encode %{ |
|
1691 |
__ sqrtss($dst$$XMMRegister, $src$$Address); |
|
1692 |
%} |
|
1693 |
ins_pipe(pipe_slow); |
|
1694 |
%} |
|
1695 |
||
1696 |
instruct sqrtF_imm(regF dst, immF con) %{ |
|
1697 |
predicate(UseSSE>=1); |
|
1698 |
match(Set dst (ConvD2F (SqrtD (ConvF2D con)))); |
|
1699 |
format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %} |
|
1700 |
ins_cost(150); |
|
1701 |
ins_encode %{ |
|
1702 |
__ sqrtss($dst$$XMMRegister, $constantaddress($con)); |
|
1703 |
%} |
|
1704 |
ins_pipe(pipe_slow); |
|
1705 |
%} |
|
1706 |
||
1707 |
instruct sqrtD_reg(regD dst, regD src) %{ |
|
1708 |
predicate(UseSSE>=2); |
|
1709 |
match(Set dst (SqrtD src)); |
|
1710 |
||
1711 |
format %{ "sqrtsd $dst, $src" %} |
|
1712 |
ins_cost(150); |
|
1713 |
ins_encode %{ |
|
1714 |
__ sqrtsd($dst$$XMMRegister, $src$$XMMRegister); |
|
1715 |
%} |
|
1716 |
ins_pipe(pipe_slow); |
|
1717 |
%} |
|
1718 |
||
1719 |
instruct sqrtD_mem(regD dst, memory src) %{ |
|
1720 |
predicate(UseSSE>=2); |
|
1721 |
match(Set dst (SqrtD (LoadD src))); |
|
1722 |
||
1723 |
format %{ "sqrtsd $dst, $src" %} |
|
1724 |
ins_cost(150); |
|
1725 |
ins_encode %{ |
|
1726 |
__ sqrtsd($dst$$XMMRegister, $src$$Address); |
|
1727 |
%} |
|
1728 |
ins_pipe(pipe_slow); |
|
1729 |
%} |
|
1730 |
||
1731 |
instruct sqrtD_imm(regD dst, immD con) %{ |
|
1732 |
predicate(UseSSE>=2); |
|
1733 |
match(Set dst (SqrtD con)); |
|
1734 |
format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %} |
|
1735 |
ins_cost(150); |
|
1736 |
ins_encode %{ |
|
1737 |
__ sqrtsd($dst$$XMMRegister, $constantaddress($con)); |
|
1738 |
%} |
|
1739 |
ins_pipe(pipe_slow); |
|
1740 |
%} |
|
1741 |
||
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1742 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1743 |
// ====================VECTOR INSTRUCTIONS===================================== |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1744 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1745 |
// Load vectors (4 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1746 |
instruct loadV4(vecS dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1747 |
predicate(n->as_LoadVector()->memory_size() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1748 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1749 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1750 |
format %{ "movd $dst,$mem\t! load vector (4 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1751 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1752 |
__ movdl($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1753 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1754 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1755 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1756 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1757 |
// Load vectors (8 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1758 |
instruct loadV8(vecD dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1759 |
predicate(n->as_LoadVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1760 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1761 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1762 |
format %{ "movq $dst,$mem\t! load vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1763 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1764 |
__ movq($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1765 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1766 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1767 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1768 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1769 |
// Load vectors (16 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1770 |
instruct loadV16(vecX dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1771 |
predicate(n->as_LoadVector()->memory_size() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1772 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1773 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1774 |
format %{ "movdqu $dst,$mem\t! load vector (16 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1775 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1776 |
__ movdqu($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1777 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1778 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1779 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1780 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1781 |
// Load vectors (32 bytes long) |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1782 |
instruct loadV32(vecY dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1783 |
predicate(n->as_LoadVector()->memory_size() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1784 |
match(Set dst (LoadVector mem)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1785 |
ins_cost(125); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1786 |
format %{ "vmovdqu $dst,$mem\t! load vector (32 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1787 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1788 |
__ vmovdqu($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1789 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1790 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1791 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1792 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1793 |
// Store vectors |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1794 |
instruct storeV4(memory mem, vecS src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1795 |
predicate(n->as_StoreVector()->memory_size() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1796 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1797 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1798 |
format %{ "movd $mem,$src\t! store vector (4 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1799 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1800 |
__ movdl($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1801 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1802 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1803 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1804 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1805 |
instruct storeV8(memory mem, vecD src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1806 |
predicate(n->as_StoreVector()->memory_size() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1807 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1808 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1809 |
format %{ "movq $mem,$src\t! store vector (8 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1810 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1811 |
__ movq($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1812 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1813 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1814 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1815 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1816 |
instruct storeV16(memory mem, vecX src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1817 |
predicate(n->as_StoreVector()->memory_size() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1818 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1819 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1820 |
format %{ "movdqu $mem,$src\t! store vector (16 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1821 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1822 |
__ movdqu($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1823 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1824 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1825 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1826 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1827 |
instruct storeV32(memory mem, vecY src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1828 |
predicate(n->as_StoreVector()->memory_size() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1829 |
match(Set mem (StoreVector mem src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1830 |
ins_cost(145); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1831 |
format %{ "vmovdqu $mem,$src\t! store vector (32 bytes)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1832 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1833 |
__ vmovdqu($mem$$Address, $src$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1834 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1835 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1836 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1837 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1838 |
// Replicate byte scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1839 |
instruct Repl4B(vecS dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1840 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1841 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1842 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1843 |
"punpcklbw $dst,$dst\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1844 |
"pshuflw $dst,$dst,0x00\t! replicate4B" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1845 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1846 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1847 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1848 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1849 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1850 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1851 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1852 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1853 |
instruct Repl8B(vecD dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1854 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1855 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1856 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1857 |
"punpcklbw $dst,$dst\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1858 |
"pshuflw $dst,$dst,0x00\t! replicate8B" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1859 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1860 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1861 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1862 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1863 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1864 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1865 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1866 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1867 |
instruct Repl16B(vecX dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1868 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1869 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1870 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1871 |
"punpcklbw $dst,$dst\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1872 |
"pshuflw $dst,$dst,0x00\n\t" |
13294 | 1873 |
"punpcklqdq $dst,$dst\t! replicate16B" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1874 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1875 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1876 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1877 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
13294 | 1878 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1879 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1880 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1881 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1882 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1883 |
instruct Repl32B(vecY dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1884 |
predicate(n->as_Vector()->length() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1885 |
match(Set dst (ReplicateB src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1886 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1887 |
"punpcklbw $dst,$dst\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1888 |
"pshuflw $dst,$dst,0x00\n\t" |
13294 | 1889 |
"punpcklqdq $dst,$dst\n\t" |
1890 |
"vinserti128h $dst,$dst,$dst\t! replicate32B" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1891 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1892 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1893 |
__ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1894 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
13294 | 1895 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
1896 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1897 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1898 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1899 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1900 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1901 |
// Replicate byte scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1902 |
instruct Repl4B_imm(vecS dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1903 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1904 |
match(Set dst (ReplicateB con)); |
13294 | 1905 |
format %{ "movdl $dst,[$constantaddress]\t! replicate4B($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1906 |
ins_encode %{ |
13294 | 1907 |
__ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 1))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1908 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1909 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1910 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1911 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1912 |
instruct Repl8B_imm(vecD dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1913 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1914 |
match(Set dst (ReplicateB con)); |
13294 | 1915 |
format %{ "movq $dst,[$constantaddress]\t! replicate8B($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1916 |
ins_encode %{ |
13294 | 1917 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1918 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1919 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1920 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1921 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1922 |
instruct Repl16B_imm(vecX dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1923 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1924 |
match(Set dst (ReplicateB con)); |
13294 | 1925 |
format %{ "movq $dst,[$constantaddress]\n\t" |
1926 |
"punpcklqdq $dst,$dst\t! replicate16B($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1927 |
ins_encode %{ |
13294 | 1928 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
1929 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1930 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1931 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1932 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1933 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1934 |
instruct Repl32B_imm(vecY dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1935 |
predicate(n->as_Vector()->length() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1936 |
match(Set dst (ReplicateB con)); |
13294 | 1937 |
format %{ "movq $dst,[$constantaddress]\n\t" |
1938 |
"punpcklqdq $dst,$dst\n\t" |
|
1939 |
"vinserti128h $dst,$dst,$dst\t! lreplicate32B($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1940 |
ins_encode %{ |
13294 | 1941 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 1))); |
1942 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
1943 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1944 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1945 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1946 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1947 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1948 |
// Replicate byte scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1949 |
instruct Repl4B_zero(vecS dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1950 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1951 |
match(Set dst (ReplicateB zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1952 |
format %{ "pxor $dst,$dst\t! replicate4B zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1953 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1954 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1955 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1956 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1957 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1958 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1959 |
instruct Repl8B_zero(vecD dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1960 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1961 |
match(Set dst (ReplicateB zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1962 |
format %{ "pxor $dst,$dst\t! replicate8B zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1963 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1964 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1965 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1966 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1967 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1968 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1969 |
instruct Repl16B_zero(vecX dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1970 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1971 |
match(Set dst (ReplicateB zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1972 |
format %{ "pxor $dst,$dst\t! replicate16B zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1973 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1974 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1975 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1976 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1977 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1978 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1979 |
instruct Repl32B_zero(vecY dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1980 |
predicate(n->as_Vector()->length() == 32); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1981 |
match(Set dst (ReplicateB zero)); |
13294 | 1982 |
format %{ "vpxor $dst,$dst,$dst\t! replicate32B zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1983 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1984 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1985 |
bool vector256 = true; |
13294 | 1986 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1987 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1988 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1989 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1990 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1991 |
// Replicate char/short (2 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1992 |
instruct Repl2S(vecS dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1993 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1994 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1995 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1996 |
"pshuflw $dst,$dst,0x00\t! replicate2S" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1997 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1998 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
1999 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2000 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2001 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2002 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2003 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2004 |
instruct Repl4S(vecD dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2005 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2006 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2007 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2008 |
"pshuflw $dst,$dst,0x00\t! replicate4S" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2009 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2010 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2011 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2012 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2013 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2014 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2015 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2016 |
instruct Repl8S(vecX dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2017 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2018 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2019 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2020 |
"pshuflw $dst,$dst,0x00\n\t" |
13294 | 2021 |
"punpcklqdq $dst,$dst\t! replicate8S" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2022 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2023 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2024 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
13294 | 2025 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2026 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2027 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2028 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2029 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2030 |
instruct Repl16S(vecY dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2031 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2032 |
match(Set dst (ReplicateS src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2033 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2034 |
"pshuflw $dst,$dst,0x00\n\t" |
13294 | 2035 |
"punpcklqdq $dst,$dst\n\t" |
2036 |
"vinserti128h $dst,$dst,$dst\t! replicate16S" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2037 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2038 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2039 |
__ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
13294 | 2040 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2041 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2042 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2043 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2044 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2045 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2046 |
// Replicate char/short (2 byte) scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2047 |
instruct Repl2S_imm(vecS dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2048 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2049 |
match(Set dst (ReplicateS con)); |
13294 | 2050 |
format %{ "movdl $dst,[$constantaddress]\t! replicate2S($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2051 |
ins_encode %{ |
13294 | 2052 |
__ movdl($dst$$XMMRegister, $constantaddress(replicate4_imm($con$$constant, 2))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2053 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2054 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2055 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2056 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2057 |
instruct Repl4S_imm(vecD dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2058 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2059 |
match(Set dst (ReplicateS con)); |
13294 | 2060 |
format %{ "movq $dst,[$constantaddress]\t! replicate4S($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2061 |
ins_encode %{ |
13294 | 2062 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2063 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2064 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2065 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2066 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2067 |
instruct Repl8S_imm(vecX dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2068 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2069 |
match(Set dst (ReplicateS con)); |
13294 | 2070 |
format %{ "movq $dst,[$constantaddress]\n\t" |
2071 |
"punpcklqdq $dst,$dst\t! replicate8S($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2072 |
ins_encode %{ |
13294 | 2073 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
2074 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2075 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2076 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2077 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2078 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2079 |
instruct Repl16S_imm(vecY dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2080 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2081 |
match(Set dst (ReplicateS con)); |
13294 | 2082 |
format %{ "movq $dst,[$constantaddress]\n\t" |
2083 |
"punpcklqdq $dst,$dst\n\t" |
|
2084 |
"vinserti128h $dst,$dst,$dst\t! replicate16S($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2085 |
ins_encode %{ |
13294 | 2086 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 2))); |
2087 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2088 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2089 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2090 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2091 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2092 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2093 |
// Replicate char/short (2 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2094 |
instruct Repl2S_zero(vecS dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2095 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2096 |
match(Set dst (ReplicateS zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2097 |
format %{ "pxor $dst,$dst\t! replicate2S zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2098 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2099 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2100 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2101 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2102 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2103 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2104 |
instruct Repl4S_zero(vecD dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2105 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2106 |
match(Set dst (ReplicateS zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2107 |
format %{ "pxor $dst,$dst\t! replicate4S zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2108 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2109 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2110 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2111 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2112 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2113 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2114 |
instruct Repl8S_zero(vecX dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2115 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2116 |
match(Set dst (ReplicateS zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2117 |
format %{ "pxor $dst,$dst\t! replicate8S zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2118 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2119 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2120 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2121 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2122 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2123 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2124 |
instruct Repl16S_zero(vecY dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2125 |
predicate(n->as_Vector()->length() == 16); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2126 |
match(Set dst (ReplicateS zero)); |
13294 | 2127 |
format %{ "vpxor $dst,$dst,$dst\t! replicate16S zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2128 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2129 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2130 |
bool vector256 = true; |
13294 | 2131 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2132 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2133 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2134 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2135 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2136 |
// Replicate integer (4 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2137 |
instruct Repl2I(vecD dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2138 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2139 |
match(Set dst (ReplicateI src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2140 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2141 |
"pshufd $dst,$dst,0x00\t! replicate2I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2142 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2143 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2144 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2145 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2146 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2147 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2148 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2149 |
instruct Repl4I(vecX dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2150 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2151 |
match(Set dst (ReplicateI src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2152 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2153 |
"pshufd $dst,$dst,0x00\t! replicate4I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2154 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2155 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2156 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2157 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2158 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2159 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2160 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2161 |
instruct Repl8I(vecY dst, rRegI src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2162 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2163 |
match(Set dst (ReplicateI src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2164 |
format %{ "movd $dst,$src\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2165 |
"pshufd $dst,$dst,0x00\n\t" |
13294 | 2166 |
"vinserti128h $dst,$dst,$dst\t! replicate8I" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2167 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2168 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2169 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
13294 | 2170 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2171 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2172 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2173 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2174 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2175 |
// Replicate integer (4 byte) scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2176 |
instruct Repl2I_imm(vecD dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2177 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2178 |
match(Set dst (ReplicateI con)); |
13294 | 2179 |
format %{ "movq $dst,[$constantaddress]\t! replicate2I($con)" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2180 |
ins_encode %{ |
13294 | 2181 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2182 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2183 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2184 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2185 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2186 |
instruct Repl4I_imm(vecX dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2187 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2188 |
match(Set dst (ReplicateI con)); |
13294 | 2189 |
format %{ "movq $dst,[$constantaddress]\t! replicate4I($con)\n\t" |
2190 |
"punpcklqdq $dst,$dst" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2191 |
ins_encode %{ |
13294 | 2192 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
2193 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2194 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2195 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2196 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2197 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2198 |
instruct Repl8I_imm(vecY dst, immI con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2199 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2200 |
match(Set dst (ReplicateI con)); |
13294 | 2201 |
format %{ "movq $dst,[$constantaddress]\t! replicate8I($con)\n\t" |
2202 |
"punpcklqdq $dst,$dst\n\t" |
|
2203 |
"vinserti128h $dst,$dst,$dst" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2204 |
ins_encode %{ |
13294 | 2205 |
__ movq($dst$$XMMRegister, $constantaddress(replicate8_imm($con$$constant, 4))); |
2206 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2207 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2208 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2209 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2210 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2211 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2212 |
// Integer could be loaded into xmm register directly from memory. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2213 |
instruct Repl2I_mem(vecD dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2214 |
predicate(n->as_Vector()->length() == 2); |
13294 | 2215 |
match(Set dst (ReplicateI (LoadI mem))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2216 |
format %{ "movd $dst,$mem\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2217 |
"pshufd $dst,$dst,0x00\t! replicate2I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2218 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2219 |
__ movdl($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2220 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2221 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2222 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2223 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2224 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2225 |
instruct Repl4I_mem(vecX dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2226 |
predicate(n->as_Vector()->length() == 4); |
13294 | 2227 |
match(Set dst (ReplicateI (LoadI mem))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2228 |
format %{ "movd $dst,$mem\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2229 |
"pshufd $dst,$dst,0x00\t! replicate4I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2230 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2231 |
__ movdl($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2232 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2233 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2234 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2235 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2236 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2237 |
instruct Repl8I_mem(vecY dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2238 |
predicate(n->as_Vector()->length() == 8); |
13294 | 2239 |
match(Set dst (ReplicateI (LoadI mem))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2240 |
format %{ "movd $dst,$mem\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2241 |
"pshufd $dst,$dst,0x00\n\t" |
13294 | 2242 |
"vinserti128h $dst,$dst,$dst\t! replicate8I" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2243 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2244 |
__ movdl($dst$$XMMRegister, $mem$$Address); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2245 |
__ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
13294 | 2246 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2247 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2248 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2249 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2250 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2251 |
// Replicate integer (4 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2252 |
instruct Repl2I_zero(vecD dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2253 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2254 |
match(Set dst (ReplicateI zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2255 |
format %{ "pxor $dst,$dst\t! replicate2I" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2256 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2257 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2258 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2259 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2260 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2261 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2262 |
instruct Repl4I_zero(vecX dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2263 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2264 |
match(Set dst (ReplicateI zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2265 |
format %{ "pxor $dst,$dst\t! replicate4I zero)" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2266 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2267 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2268 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2269 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2270 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2271 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2272 |
instruct Repl8I_zero(vecY dst, immI0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2273 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2274 |
match(Set dst (ReplicateI zero)); |
13294 | 2275 |
format %{ "vpxor $dst,$dst,$dst\t! replicate8I zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2276 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2277 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2278 |
bool vector256 = true; |
13294 | 2279 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2280 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2281 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2282 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2283 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2284 |
// Replicate long (8 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2285 |
#ifdef _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2286 |
instruct Repl2L(vecX dst, rRegL src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2287 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2288 |
match(Set dst (ReplicateL src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2289 |
format %{ "movdq $dst,$src\n\t" |
13294 | 2290 |
"punpcklqdq $dst,$dst\t! replicate2L" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2291 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2292 |
__ movdq($dst$$XMMRegister, $src$$Register); |
13294 | 2293 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2294 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2295 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2296 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2297 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2298 |
instruct Repl4L(vecY dst, rRegL src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2299 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2300 |
match(Set dst (ReplicateL src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2301 |
format %{ "movdq $dst,$src\n\t" |
13294 | 2302 |
"punpcklqdq $dst,$dst\n\t" |
2303 |
"vinserti128h $dst,$dst,$dst\t! replicate4L" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2304 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2305 |
__ movdq($dst$$XMMRegister, $src$$Register); |
13294 | 2306 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2307 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2308 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2309 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2310 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2311 |
#else // _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2312 |
instruct Repl2L(vecX dst, eRegL src, regD tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2313 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2314 |
match(Set dst (ReplicateL src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2315 |
effect(TEMP dst, USE src, TEMP tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2316 |
format %{ "movdl $dst,$src.lo\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2317 |
"movdl $tmp,$src.hi\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2318 |
"punpckldq $dst,$tmp\n\t" |
13294 | 2319 |
"punpcklqdq $dst,$dst\t! replicate2L"%} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2320 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2321 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2322 |
__ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2323 |
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
13294 | 2324 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2325 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2326 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2327 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2328 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2329 |
instruct Repl4L(vecY dst, eRegL src, regD tmp) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2330 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2331 |
match(Set dst (ReplicateL src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2332 |
effect(TEMP dst, USE src, TEMP tmp); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2333 |
format %{ "movdl $dst,$src.lo\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2334 |
"movdl $tmp,$src.hi\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2335 |
"punpckldq $dst,$tmp\n\t" |
13294 | 2336 |
"punpcklqdq $dst,$dst\n\t" |
2337 |
"vinserti128h $dst,$dst,$dst\t! replicate4L" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2338 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2339 |
__ movdl($dst$$XMMRegister, $src$$Register); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2340 |
__ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2341 |
__ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); |
13294 | 2342 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2343 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2344 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2345 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2346 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2347 |
#endif // _LP64 |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2348 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2349 |
// Replicate long (8 byte) scalar immediate to be vector by loading from const table. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2350 |
instruct Repl2L_imm(vecX dst, immL con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2351 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2352 |
match(Set dst (ReplicateL con)); |
13294 | 2353 |
format %{ "movq $dst,[$constantaddress]\n\t" |
2354 |
"punpcklqdq $dst,$dst\t! replicate2L($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2355 |
ins_encode %{ |
13294 | 2356 |
__ movq($dst$$XMMRegister, $constantaddress($con)); |
2357 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2358 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2359 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2360 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2361 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2362 |
instruct Repl4L_imm(vecY dst, immL con) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2363 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2364 |
match(Set dst (ReplicateL con)); |
13294 | 2365 |
format %{ "movq $dst,[$constantaddress]\n\t" |
2366 |
"punpcklqdq $dst,$dst\n\t" |
|
2367 |
"vinserti128h $dst,$dst,$dst\t! replicate4L($con)" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2368 |
ins_encode %{ |
13294 | 2369 |
__ movq($dst$$XMMRegister, $constantaddress($con)); |
2370 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
|
2371 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2372 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2373 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2374 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2375 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2376 |
// Long could be loaded into xmm register directly from memory. |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2377 |
instruct Repl2L_mem(vecX dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2378 |
predicate(n->as_Vector()->length() == 2); |
13294 | 2379 |
match(Set dst (ReplicateL (LoadL mem))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2380 |
format %{ "movq $dst,$mem\n\t" |
13294 | 2381 |
"punpcklqdq $dst,$dst\t! replicate2L" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2382 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2383 |
__ movq($dst$$XMMRegister, $mem$$Address); |
13294 | 2384 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2385 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2386 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2387 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2388 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2389 |
instruct Repl4L_mem(vecY dst, memory mem) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2390 |
predicate(n->as_Vector()->length() == 4); |
13294 | 2391 |
match(Set dst (ReplicateL (LoadL mem))); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2392 |
format %{ "movq $dst,$mem\n\t" |
13294 | 2393 |
"punpcklqdq $dst,$dst\n\t" |
2394 |
"vinserti128h $dst,$dst,$dst\t! replicate4L" %} |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2395 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2396 |
__ movq($dst$$XMMRegister, $mem$$Address); |
13294 | 2397 |
__ punpcklqdq($dst$$XMMRegister, $dst$$XMMRegister); |
2398 |
__ vinserti128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
|
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2399 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2400 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2401 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2402 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2403 |
// Replicate long (8 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2404 |
instruct Repl2L_zero(vecX dst, immL0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2405 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2406 |
match(Set dst (ReplicateL zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2407 |
format %{ "pxor $dst,$dst\t! replicate2L zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2408 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2409 |
__ pxor($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2410 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2411 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2412 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2413 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2414 |
instruct Repl4L_zero(vecY dst, immL0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2415 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2416 |
match(Set dst (ReplicateL zero)); |
13294 | 2417 |
format %{ "vpxor $dst,$dst,$dst\t! replicate4L zero" %} |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2418 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2419 |
// Use vxorpd since AVX does not have vpxor for 256-bit (AVX2 will have it). |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2420 |
bool vector256 = true; |
13294 | 2421 |
__ vpxor($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
13104
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2422 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2423 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2424 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2425 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2426 |
// Replicate float (4 byte) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2427 |
instruct Repl2F(vecD dst, regF src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2428 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2429 |
match(Set dst (ReplicateF src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2430 |
format %{ "pshufd $dst,$dst,0x00\t! replicate2F" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2431 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2432 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2433 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2434 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2435 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2436 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2437 |
instruct Repl4F(vecX dst, regF src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2438 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2439 |
match(Set dst (ReplicateF src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2440 |
format %{ "pshufd $dst,$dst,0x00\t! replicate4F" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2441 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2442 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2443 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2444 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2445 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2446 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2447 |
instruct Repl8F(vecY dst, regF src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2448 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2449 |
match(Set dst (ReplicateF src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2450 |
format %{ "pshufd $dst,$src,0x00\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2451 |
"vinsertf128h $dst,$dst,$dst\t! replicate8F" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2452 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2453 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2454 |
__ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2455 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2456 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2457 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2458 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2459 |
// Replicate float (4 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2460 |
instruct Repl2F_zero(vecD dst, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2461 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2462 |
match(Set dst (ReplicateF zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2463 |
format %{ "xorps $dst,$dst\t! replicate2F zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2464 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2465 |
__ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2466 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2467 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2468 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2469 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2470 |
instruct Repl4F_zero(vecX dst, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2471 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2472 |
match(Set dst (ReplicateF zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2473 |
format %{ "xorps $dst,$dst\t! replicate4F zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2474 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2475 |
__ xorps($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2476 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2477 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2478 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2479 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2480 |
instruct Repl8F_zero(vecY dst, immF0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2481 |
predicate(n->as_Vector()->length() == 8); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2482 |
match(Set dst (ReplicateF zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2483 |
format %{ "vxorps $dst,$dst,$dst\t! replicate8F zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2484 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2485 |
bool vector256 = true; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2486 |
__ vxorps($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2487 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2488 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2489 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2490 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2491 |
// Replicate double (8 bytes) scalar to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2492 |
instruct Repl2D(vecX dst, regD src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2493 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2494 |
match(Set dst (ReplicateD src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2495 |
format %{ "pshufd $dst,$src,0x44\t! replicate2D" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2496 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2497 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2498 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2499 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2500 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2501 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2502 |
instruct Repl4D(vecY dst, regD src) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2503 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2504 |
match(Set dst (ReplicateD src)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2505 |
format %{ "pshufd $dst,$src,0x44\n\t" |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2506 |
"vinsertf128h $dst,$dst,$dst\t! replicate4D" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2507 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2508 |
__ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x44); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2509 |
__ vinsertf128h($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2510 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2511 |
ins_pipe( pipe_slow ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2512 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2513 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2514 |
// Replicate double (8 byte) scalar zero to be vector |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2515 |
instruct Repl2D_zero(vecX dst, immD0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2516 |
predicate(n->as_Vector()->length() == 2); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2517 |
match(Set dst (ReplicateD zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2518 |
format %{ "xorpd $dst,$dst\t! replicate2D zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2519 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2520 |
__ xorpd($dst$$XMMRegister, $dst$$XMMRegister); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2521 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2522 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2523 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2524 |
|
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2525 |
instruct Repl4D_zero(vecY dst, immD0 zero) %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2526 |
predicate(n->as_Vector()->length() == 4); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2527 |
match(Set dst (ReplicateD zero)); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2528 |
format %{ "vxorpd $dst,$dst,$dst,vect256\t! replicate4D zero" %} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2529 |
ins_encode %{ |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2530 |
bool vector256 = true; |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2531 |
__ vxorpd($dst$$XMMRegister, $dst$$XMMRegister, $dst$$XMMRegister, vector256); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2532 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2533 |
ins_pipe( fpu_reg_reg ); |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2534 |
%} |
657b387034fb
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
11794
diff
changeset
|
2535 |
|
30211 | 2536 |
// ====================REDUCTION ARITHMETIC======================================= |
2537 |
||
2538 |
instruct rsadd2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2539 |
predicate(UseSSE > 2 && UseAVX == 0); |
|
2540 |
match(Set dst (AddReductionVI src1 src2)); |
|
2541 |
effect(TEMP tmp2, TEMP tmp); |
|
2542 |
format %{ "movdqu $tmp2,$src2\n\t" |
|
2543 |
"phaddd $tmp2,$tmp2\n\t" |
|
2544 |
"movd $tmp,$src1\n\t" |
|
2545 |
"paddd $tmp,$tmp2\n\t" |
|
2546 |
"movd $dst,$tmp\t! add reduction2I" %} |
|
2547 |
ins_encode %{ |
|
2548 |
__ movdqu($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
2549 |
__ phaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister); |
|
2550 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
2551 |
__ paddd($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2552 |
__ movdl($dst$$Register, $tmp$$XMMRegister); |
|
2553 |
%} |
|
2554 |
ins_pipe( pipe_slow ); |
|
2555 |
%} |
|
2556 |
||
2557 |
instruct rvadd2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2558 |
predicate(UseAVX > 0); |
|
2559 |
match(Set dst (AddReductionVI src1 src2)); |
|
2560 |
effect(TEMP tmp, TEMP tmp2); |
|
2561 |
format %{ "vphaddd $tmp,$src2,$src2\n\t" |
|
2562 |
"movd $tmp2,$src1\n\t" |
|
2563 |
"vpaddd $tmp2,$tmp2,$tmp\n\t" |
|
2564 |
"movd $dst,$tmp2\t! add reduction2I" %} |
|
2565 |
ins_encode %{ |
|
2566 |
__ vphaddd($tmp$$XMMRegister, $src2$$XMMRegister, $src2$$XMMRegister, false); |
|
2567 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
2568 |
__ vpaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, false); |
|
2569 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2570 |
%} |
|
2571 |
ins_pipe( pipe_slow ); |
|
2572 |
%} |
|
2573 |
||
2574 |
instruct rsadd4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2575 |
predicate(UseSSE > 2 && UseAVX == 0); |
|
2576 |
match(Set dst (AddReductionVI src1 src2)); |
|
2577 |
effect(TEMP tmp2, TEMP tmp); |
|
2578 |
format %{ "movdqu $tmp2,$src2\n\t" |
|
2579 |
"phaddd $tmp2,$tmp2\n\t" |
|
2580 |
"phaddd $tmp2,$tmp2\n\t" |
|
2581 |
"movd $tmp,$src1\n\t" |
|
2582 |
"paddd $tmp,$tmp2\n\t" |
|
2583 |
"movd $dst,$tmp\t! add reduction4I" %} |
|
2584 |
ins_encode %{ |
|
2585 |
__ movdqu($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
2586 |
__ phaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister); |
|
2587 |
__ phaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister); |
|
2588 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
2589 |
__ paddd($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2590 |
__ movdl($dst$$Register, $tmp$$XMMRegister); |
|
2591 |
%} |
|
2592 |
ins_pipe( pipe_slow ); |
|
2593 |
%} |
|
2594 |
||
2595 |
instruct rvadd4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2596 |
predicate(UseAVX > 0); |
|
2597 |
match(Set dst (AddReductionVI src1 src2)); |
|
2598 |
effect(TEMP tmp, TEMP tmp2); |
|
2599 |
format %{ "vphaddd $tmp,$src2,$src2\n\t" |
|
2600 |
"vphaddd $tmp,$tmp,$tmp2\n\t" |
|
2601 |
"movd $tmp2,$src1\n\t" |
|
2602 |
"vpaddd $tmp2,$tmp2,$tmp\n\t" |
|
2603 |
"movd $dst,$tmp2\t! add reduction4I" %} |
|
2604 |
ins_encode %{ |
|
2605 |
__ vphaddd($tmp$$XMMRegister, $src2$$XMMRegister, $src2$$XMMRegister, false); |
|
2606 |
__ vphaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2607 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
2608 |
__ vpaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, false); |
|
2609 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2610 |
%} |
|
2611 |
ins_pipe( pipe_slow ); |
|
2612 |
%} |
|
2613 |
||
2614 |
instruct rvadd8I_reduction_reg(rRegI dst, rRegI src1, vecY src2, regF tmp, regF tmp2) %{ |
|
2615 |
predicate(UseAVX > 0); |
|
2616 |
match(Set dst (AddReductionVI src1 src2)); |
|
2617 |
effect(TEMP tmp, TEMP tmp2); |
|
2618 |
format %{ "vphaddd $tmp,$src2,$src2\n\t" |
|
2619 |
"vphaddd $tmp,$tmp,$tmp2\n\t" |
|
2620 |
"vextractf128 $tmp2,$tmp\n\t" |
|
2621 |
"vpaddd $tmp,$tmp,$tmp2\n\t" |
|
2622 |
"movd $tmp2,$src1\n\t" |
|
2623 |
"vpaddd $tmp2,$tmp2,$tmp\n\t" |
|
2624 |
"movd $dst,$tmp2\t! add reduction8I" %} |
|
2625 |
ins_encode %{ |
|
2626 |
__ vphaddd($tmp$$XMMRegister, $src2$$XMMRegister, $src2$$XMMRegister, true); |
|
2627 |
__ vphaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, true); |
|
2628 |
__ vextractf128h($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2629 |
__ vpaddd($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2630 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
2631 |
__ vpaddd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister, false); |
|
2632 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2633 |
%} |
|
2634 |
ins_pipe( pipe_slow ); |
|
2635 |
%} |
|
2636 |
||
2637 |
instruct rsadd2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2638 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
2639 |
match(Set dst (AddReductionVF src1 src2)); |
|
2640 |
effect(TEMP tmp, TEMP tmp2); |
|
2641 |
format %{ "movdqu $tmp,$src1\n\t" |
|
2642 |
"addss $tmp,$src2\n\t" |
|
2643 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
2644 |
"addss $tmp,$tmp2\n\t" |
|
2645 |
"movdqu $dst,$tmp\t! add reduction2F" %} |
|
2646 |
ins_encode %{ |
|
2647 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
2648 |
__ addss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
2649 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2650 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2651 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
2652 |
%} |
|
2653 |
ins_pipe( pipe_slow ); |
|
2654 |
%} |
|
2655 |
||
2656 |
instruct rvadd2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2657 |
predicate(UseAVX > 0); |
|
2658 |
match(Set dst (AddReductionVF src1 src2)); |
|
2659 |
effect(TEMP tmp2, TEMP tmp); |
|
2660 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
2661 |
"pshufd $tmp,$src2,0x01\n\t" |
|
2662 |
"vaddss $dst,$tmp2,$tmp\t! add reduction2F" %} |
|
2663 |
ins_encode %{ |
|
2664 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2665 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2666 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2667 |
%} |
|
2668 |
ins_pipe( pipe_slow ); |
|
2669 |
%} |
|
2670 |
||
2671 |
instruct rsadd4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2672 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
2673 |
match(Set dst (AddReductionVF src1 src2)); |
|
2674 |
effect(TEMP tmp, TEMP tmp2); |
|
2675 |
format %{ "movdqu $tmp,$src1\n\t" |
|
2676 |
"addss $tmp,$src2\n\t" |
|
2677 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
2678 |
"addss $tmp,$tmp2\n\t" |
|
2679 |
"pshufd $tmp2,$src2,0x02\n\t" |
|
2680 |
"addss $tmp,$tmp2\n\t" |
|
2681 |
"pshufd $tmp2,$src2,0x03\n\t" |
|
2682 |
"addss $tmp,$tmp2\n\t" |
|
2683 |
"movdqu $dst,$tmp\t! add reduction4F" %} |
|
2684 |
ins_encode %{ |
|
2685 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
2686 |
__ addss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
2687 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2688 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2689 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
2690 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2691 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
2692 |
__ addss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2693 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
2694 |
%} |
|
2695 |
ins_pipe( pipe_slow ); |
|
2696 |
%} |
|
2697 |
||
2698 |
instruct rvadd4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2699 |
predicate(UseAVX > 0); |
|
2700 |
match(Set dst (AddReductionVF src1 src2)); |
|
2701 |
effect(TEMP tmp, TEMP tmp2); |
|
2702 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
2703 |
"pshufd $tmp,$src2,0x01\n\t" |
|
2704 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2705 |
"pshufd $tmp,$src2,0x02\n\t" |
|
2706 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2707 |
"pshufd $tmp,$src2,0x03\n\t" |
|
2708 |
"vaddss $dst,$tmp2,$tmp\t! add reduction4F" %} |
|
2709 |
ins_encode %{ |
|
2710 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2711 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2712 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2713 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
2714 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2715 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
2716 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2717 |
%} |
|
2718 |
ins_pipe( pipe_slow ); |
|
2719 |
%} |
|
2720 |
||
2721 |
instruct radd8F_reduction_reg(regF dst, regF src1, vecY src2, regF tmp, regF tmp2, regF tmp3) %{ |
|
2722 |
predicate(UseAVX > 0); |
|
2723 |
match(Set dst (AddReductionVF src1 src2)); |
|
2724 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
2725 |
format %{ "vaddss $tmp2,$src1,$src2\n\t" |
|
2726 |
"pshufd $tmp,$src2,0x01\n\t" |
|
2727 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2728 |
"pshufd $tmp,$src2,0x02\n\t" |
|
2729 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2730 |
"pshufd $tmp,$src2,0x03\n\t" |
|
2731 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2732 |
"vextractf128 $tmp3,$src2\n\t" |
|
2733 |
"vaddss $tmp2,$tmp2,$tmp3\n\t" |
|
2734 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
2735 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2736 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
2737 |
"vaddss $tmp2,$tmp2,$tmp\n\t" |
|
2738 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
2739 |
"vaddss $dst,$tmp2,$tmp\t! add reduction8F" %} |
|
2740 |
ins_encode %{ |
|
2741 |
__ vaddss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2742 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2743 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2744 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
2745 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2746 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
2747 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2748 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
2749 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
2750 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
2751 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2752 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
2753 |
__ vaddss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2754 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
2755 |
__ vaddss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2756 |
%} |
|
2757 |
ins_pipe( pipe_slow ); |
|
2758 |
%} |
|
2759 |
||
2760 |
instruct rsadd2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp) %{ |
|
2761 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
2762 |
match(Set dst (AddReductionVD src1 src2)); |
|
2763 |
effect(TEMP tmp, TEMP dst); |
|
2764 |
format %{ "movdqu $tmp,$src1\n\t" |
|
2765 |
"addsd $tmp,$src2\n\t" |
|
2766 |
"pshufd $dst,$src2,0xE\n\t" |
|
2767 |
"addsd $dst,$tmp\t! add reduction2D" %} |
|
2768 |
ins_encode %{ |
|
2769 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
2770 |
__ addsd($tmp$$XMMRegister, $src2$$XMMRegister); |
|
2771 |
__ pshufd($dst$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
2772 |
__ addsd($dst$$XMMRegister, $tmp$$XMMRegister); |
|
2773 |
%} |
|
2774 |
ins_pipe( pipe_slow ); |
|
2775 |
%} |
|
2776 |
||
2777 |
instruct rvadd2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp, regD tmp2) %{ |
|
2778 |
predicate(UseAVX > 0); |
|
2779 |
match(Set dst (AddReductionVD src1 src2)); |
|
2780 |
effect(TEMP tmp, TEMP tmp2); |
|
2781 |
format %{ "vaddsd $tmp2,$src1,$src2\n\t" |
|
2782 |
"pshufd $tmp,$src2,0xE\n\t" |
|
2783 |
"vaddsd $dst,$tmp2,$tmp\t! add reduction2D" %} |
|
2784 |
ins_encode %{ |
|
2785 |
__ vaddsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2786 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
2787 |
__ vaddsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2788 |
%} |
|
2789 |
ins_pipe( pipe_slow ); |
|
2790 |
%} |
|
2791 |
||
2792 |
instruct rvadd4D_reduction_reg(regD dst, regD src1, vecY src2, regD tmp, regD tmp2, regD tmp3) %{ |
|
2793 |
predicate(UseAVX > 0); |
|
2794 |
match(Set dst (AddReductionVD src1 src2)); |
|
2795 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
2796 |
format %{ "vaddsd $tmp2,$src1,$src2\n\t" |
|
2797 |
"pshufd $tmp,$src2,0xE\n\t" |
|
2798 |
"vaddsd $tmp2,$tmp2,$tmp\n\t" |
|
2799 |
"vextractf128 $tmp3,$src2\n\t" |
|
2800 |
"vaddsd $tmp2,$tmp2,$tmp3\n\t" |
|
2801 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
2802 |
"vaddsd $dst,$tmp2,$tmp\t! add reduction4D" %} |
|
2803 |
ins_encode %{ |
|
2804 |
__ vaddsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2805 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
2806 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2807 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
2808 |
__ vaddsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
2809 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
2810 |
__ vaddsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2811 |
%} |
|
2812 |
ins_pipe( pipe_slow ); |
|
2813 |
%} |
|
2814 |
||
2815 |
instruct rsmul2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2816 |
predicate(UseSSE > 3 && UseAVX == 0); |
|
2817 |
match(Set dst (MulReductionVI src1 src2)); |
|
2818 |
effect(TEMP tmp, TEMP tmp2); |
|
2819 |
format %{ "pshufd $tmp2,$src2,0x1\n\t" |
|
2820 |
"pmulld $tmp2,$src2\n\t" |
|
2821 |
"movd $tmp,$src1\n\t" |
|
2822 |
"pmulld $tmp2,$tmp\n\t" |
|
2823 |
"movd $dst,$tmp2\t! mul reduction2I" %} |
|
2824 |
ins_encode %{ |
|
2825 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
2826 |
__ pmulld($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
2827 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
2828 |
__ pmulld($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2829 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2830 |
%} |
|
2831 |
ins_pipe( pipe_slow ); |
|
2832 |
%} |
|
2833 |
||
2834 |
instruct rvmul2I_reduction_reg(rRegI dst, rRegI src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2835 |
predicate(UseAVX > 0); |
|
2836 |
match(Set dst (MulReductionVI src1 src2)); |
|
2837 |
effect(TEMP tmp, TEMP tmp2); |
|
2838 |
format %{ "pshufd $tmp2,$src2,0x1\n\t" |
|
2839 |
"vpmulld $tmp,$src2,$tmp2\n\t" |
|
2840 |
"movd $tmp2,$src1\n\t" |
|
2841 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
2842 |
"movd $dst,$tmp2\t! mul reduction2I" %} |
|
2843 |
ins_encode %{ |
|
2844 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x1); |
|
2845 |
__ vpmulld($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2846 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
2847 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2848 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2849 |
%} |
|
2850 |
ins_pipe( pipe_slow ); |
|
2851 |
%} |
|
2852 |
||
2853 |
instruct rsmul4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2854 |
predicate(UseSSE > 3 && UseAVX == 0); |
|
2855 |
match(Set dst (MulReductionVI src1 src2)); |
|
2856 |
effect(TEMP tmp, TEMP tmp2); |
|
2857 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
|
2858 |
"pmulld $tmp2,$src2\n\t" |
|
2859 |
"pshufd $tmp,$tmp2,0x1\n\t" |
|
2860 |
"pmulld $tmp2,$tmp\n\t" |
|
2861 |
"movd $tmp,$src1\n\t" |
|
2862 |
"pmulld $tmp2,$tmp\n\t" |
|
2863 |
"movd $dst,$tmp2\t! mul reduction4I" %} |
|
2864 |
ins_encode %{ |
|
2865 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
2866 |
__ pmulld($tmp2$$XMMRegister, $src2$$XMMRegister); |
|
2867 |
__ pshufd($tmp$$XMMRegister, $tmp2$$XMMRegister, 0x1); |
|
2868 |
__ pmulld($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2869 |
__ movdl($tmp$$XMMRegister, $src1$$Register); |
|
2870 |
__ pmulld($tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2871 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2872 |
%} |
|
2873 |
ins_pipe( pipe_slow ); |
|
2874 |
%} |
|
2875 |
||
2876 |
instruct rvmul4I_reduction_reg(rRegI dst, rRegI src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2877 |
predicate(UseAVX > 0); |
|
2878 |
match(Set dst (MulReductionVI src1 src2)); |
|
2879 |
effect(TEMP tmp, TEMP tmp2); |
|
2880 |
format %{ "pshufd $tmp2,$src2,0xE\n\t" |
|
2881 |
"vpmulld $tmp,$src2,$tmp2\n\t" |
|
2882 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
2883 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
2884 |
"movd $tmp2,$src1\n\t" |
|
2885 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
2886 |
"movd $dst,$tmp2\t! mul reduction4I" %} |
|
2887 |
ins_encode %{ |
|
2888 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
2889 |
__ vpmulld($tmp$$XMMRegister, $src2$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2890 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
|
2891 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2892 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
2893 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2894 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2895 |
%} |
|
2896 |
ins_pipe( pipe_slow ); |
|
2897 |
%} |
|
2898 |
||
2899 |
instruct rvmul8I_reduction_reg(rRegI dst, rRegI src1, vecY src2, regF tmp, regF tmp2) %{ |
|
2900 |
predicate(UseAVX > 0); |
|
2901 |
match(Set dst (MulReductionVI src1 src2)); |
|
2902 |
effect(TEMP tmp, TEMP tmp2); |
|
2903 |
format %{ "vextractf128 $tmp,$src2\n\t" |
|
2904 |
"vpmulld $tmp,$tmp,$src2\n\t" |
|
2905 |
"pshufd $tmp2,$tmp,0xE\n\t" |
|
2906 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
2907 |
"pshufd $tmp2,$tmp,0x1\n\t" |
|
2908 |
"vpmulld $tmp,$tmp,$tmp2\n\t" |
|
2909 |
"movd $tmp2,$src1\n\t" |
|
2910 |
"vpmulld $tmp2,$tmp,$tmp2\n\t" |
|
2911 |
"movd $dst,$tmp2\t! mul reduction8I" %} |
|
2912 |
ins_encode %{ |
|
2913 |
__ vextractf128h($tmp$$XMMRegister, $src2$$XMMRegister); |
|
2914 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $src2$$XMMRegister, false); |
|
2915 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0xE); |
|
2916 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2917 |
__ pshufd($tmp2$$XMMRegister, $tmp$$XMMRegister, 0x1); |
|
2918 |
__ vpmulld($tmp$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2919 |
__ movdl($tmp2$$XMMRegister, $src1$$Register); |
|
2920 |
__ vpmulld($tmp2$$XMMRegister, $tmp$$XMMRegister, $tmp2$$XMMRegister, false); |
|
2921 |
__ movdl($dst$$Register, $tmp2$$XMMRegister); |
|
2922 |
%} |
|
2923 |
ins_pipe( pipe_slow ); |
|
2924 |
%} |
|
2925 |
||
2926 |
instruct rsmul2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2927 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
2928 |
match(Set dst (MulReductionVF src1 src2)); |
|
2929 |
effect(TEMP tmp, TEMP tmp2); |
|
2930 |
format %{ "movdqu $tmp,$src1\n\t" |
|
2931 |
"mulss $tmp,$src2\n\t" |
|
2932 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
2933 |
"mulss $tmp,$tmp2\n\t" |
|
2934 |
"movdqu $dst,$tmp\t! add reduction2F" %} |
|
2935 |
ins_encode %{ |
|
2936 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
2937 |
__ mulss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
2938 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2939 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2940 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
2941 |
%} |
|
2942 |
ins_pipe( pipe_slow ); |
|
2943 |
%} |
|
2944 |
||
2945 |
instruct rvmul2F_reduction_reg(regF dst, regF src1, vecD src2, regF tmp, regF tmp2) %{ |
|
2946 |
predicate(UseAVX > 0); |
|
2947 |
match(Set dst (MulReductionVF src1 src2)); |
|
2948 |
effect(TEMP tmp, TEMP tmp2); |
|
2949 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
2950 |
"pshufd $tmp,$src2,0x01\n\t" |
|
2951 |
"vmulss $dst,$tmp2,$tmp\t! add reduction2F" %} |
|
2952 |
ins_encode %{ |
|
2953 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
2954 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2955 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
2956 |
%} |
|
2957 |
ins_pipe( pipe_slow ); |
|
2958 |
%} |
|
2959 |
||
2960 |
instruct rsmul4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2961 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
2962 |
match(Set dst (MulReductionVF src1 src2)); |
|
2963 |
effect(TEMP tmp, TEMP tmp2); |
|
2964 |
format %{ "movdqu $tmp,$src1\n\t" |
|
2965 |
"mulss $tmp,$src2\n\t" |
|
2966 |
"pshufd $tmp2,$src2,0x01\n\t" |
|
2967 |
"mulss $tmp,$tmp2\n\t" |
|
2968 |
"pshufd $tmp2,$src2,0x02\n\t" |
|
2969 |
"mulss $tmp,$tmp2\n\t" |
|
2970 |
"pshufd $tmp2,$src2,0x03\n\t" |
|
2971 |
"mulss $tmp,$tmp2\n\t" |
|
2972 |
"movdqu $dst,$tmp\t! add reduction4F" %} |
|
2973 |
ins_encode %{ |
|
2974 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
2975 |
__ mulss($tmp$$XMMRegister, $src2$$XMMRegister); |
|
2976 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
2977 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2978 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
2979 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2980 |
__ pshufd($tmp2$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
2981 |
__ mulss($tmp$$XMMRegister, $tmp2$$XMMRegister); |
|
2982 |
__ movdqu($dst$$XMMRegister, $tmp$$XMMRegister); |
|
2983 |
%} |
|
2984 |
ins_pipe( pipe_slow ); |
|
2985 |
%} |
|
2986 |
||
2987 |
instruct rvmul4F_reduction_reg(regF dst, regF src1, vecX src2, regF tmp, regF tmp2) %{ |
|
2988 |
predicate(UseAVX > 0); |
|
2989 |
match(Set dst (MulReductionVF src1 src2)); |
|
2990 |
effect(TEMP tmp, TEMP tmp2); |
|
2991 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
2992 |
"pshufd $tmp,$src2,0x01\n\t" |
|
2993 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
2994 |
"pshufd $tmp,$src2,0x02\n\t" |
|
2995 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
2996 |
"pshufd $tmp,$src2,0x03\n\t" |
|
2997 |
"vmulss $dst,$tmp2,$tmp\t! add reduction4F" %} |
|
2998 |
ins_encode %{ |
|
2999 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
3000 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
3001 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3002 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
3003 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3004 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
3005 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3006 |
%} |
|
3007 |
ins_pipe( pipe_slow ); |
|
3008 |
%} |
|
3009 |
||
3010 |
instruct rvmul8F_reduction_reg(regF dst, regF src1, vecY src2, regF tmp, regF tmp2, regF tmp3) %{ |
|
3011 |
predicate(UseAVX > 0); |
|
3012 |
match(Set dst (MulReductionVF src1 src2)); |
|
3013 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
3014 |
format %{ "vmulss $tmp2,$src1,$src2\n\t" |
|
3015 |
"pshufd $tmp,$src2,0x01\n\t" |
|
3016 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
3017 |
"pshufd $tmp,$src2,0x02\n\t" |
|
3018 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
3019 |
"pshufd $tmp,$src2,0x03\n\t" |
|
3020 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
3021 |
"vextractf128 $tmp3,$src2\n\t" |
|
3022 |
"vmulss $tmp2,$tmp2,$tmp3\n\t" |
|
3023 |
"pshufd $tmp,$tmp3,0x01\n\t" |
|
3024 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
3025 |
"pshufd $tmp,$tmp3,0x02\n\t" |
|
3026 |
"vmulss $tmp2,$tmp2,$tmp\n\t" |
|
3027 |
"pshufd $tmp,$tmp3,0x03\n\t" |
|
3028 |
"vmulss $dst,$tmp2,$tmp\t! mul reduction8F" %} |
|
3029 |
ins_encode %{ |
|
3030 |
__ vmulss($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
3031 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x01); |
|
3032 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3033 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x02); |
|
3034 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3035 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0x03); |
|
3036 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3037 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
3038 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
3039 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x01); |
|
3040 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3041 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x02); |
|
3042 |
__ vmulss($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3043 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0x03); |
|
3044 |
__ vmulss($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3045 |
%} |
|
3046 |
ins_pipe( pipe_slow ); |
|
3047 |
%} |
|
3048 |
||
3049 |
instruct rsmul2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp) %{ |
|
3050 |
predicate(UseSSE >= 1 && UseAVX == 0); |
|
3051 |
match(Set dst (MulReductionVD src1 src2)); |
|
3052 |
effect(TEMP tmp, TEMP dst); |
|
3053 |
format %{ "movdqu $tmp,$src1\n\t" |
|
3054 |
"mulsd $tmp,$src2\n\t" |
|
3055 |
"pshufd $dst,$src2,0xE\n\t" |
|
3056 |
"mulsd $dst,$tmp\t! add reduction2D" %} |
|
3057 |
ins_encode %{ |
|
3058 |
__ movdqu($tmp$$XMMRegister, $src1$$XMMRegister); |
|
3059 |
__ mulsd($tmp$$XMMRegister, $src2$$XMMRegister); |
|
3060 |
__ pshufd($dst$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
3061 |
__ mulsd($dst$$XMMRegister, $tmp$$XMMRegister); |
|
3062 |
%} |
|
3063 |
ins_pipe( pipe_slow ); |
|
3064 |
%} |
|
3065 |
||
3066 |
instruct rvmul2D_reduction_reg(regD dst, regD src1, vecX src2, regD tmp, regD tmp2) %{ |
|
3067 |
predicate(UseAVX > 0); |
|
3068 |
match(Set dst (MulReductionVD src1 src2)); |
|
3069 |
effect(TEMP tmp, TEMP tmp2); |
|
3070 |
format %{ "vmulsd $tmp2,$src1,$src2\n\t" |
|
3071 |
"pshufd $tmp,$src2,0xE\n\t" |
|
3072 |
"vmulsd $dst,$tmp2,$tmp\t! mul reduction2D" %} |
|
3073 |
ins_encode %{ |
|
3074 |
__ vmulsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
3075 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
3076 |
__ vmulsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3077 |
%} |
|
3078 |
ins_pipe( pipe_slow ); |
|
3079 |
%} |
|
3080 |
||
3081 |
instruct rvmul4D_reduction_reg(regD dst, regD src1, vecY src2, regD tmp, regD tmp2, regD tmp3) %{ |
|
3082 |
predicate(UseAVX > 0); |
|
3083 |
match(Set dst (MulReductionVD src1 src2)); |
|
3084 |
effect(TEMP tmp, TEMP tmp2, TEMP tmp3); |
|
3085 |
format %{ "vmulsd $tmp2,$src1,$src2\n\t" |
|
3086 |
"pshufd $tmp,$src2,0xE\n\t" |
|
3087 |
"vmulsd $tmp2,$tmp2,$tmp\n\t" |
|
3088 |
"vextractf128 $tmp3,$src2\n\t" |
|
3089 |
"vmulsd $tmp2,$tmp2,$tmp3\n\t" |
|
3090 |
"pshufd $tmp,$tmp3,0xE\n\t" |
|
3091 |
"vmulsd $dst,$tmp2,$tmp\t! mul reduction4D" %} |
|
3092 |
ins_encode %{ |
|
3093 |
__ vmulsd($tmp2$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister); |
|
3094 |
__ pshufd($tmp$$XMMRegister, $src2$$XMMRegister, 0xE); |
|
3095 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3096 |
__ vextractf128h($tmp3$$XMMRegister, $src2$$XMMRegister); |
|
3097 |
__ vmulsd($tmp2$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister); |
|
3098 |
__ pshufd($tmp$$XMMRegister, $tmp3$$XMMRegister, 0xE); |
|
3099 |
__ vmulsd($dst$$XMMRegister, $tmp2$$XMMRegister, $tmp$$XMMRegister); |
|
3100 |
%} |
|
3101 |
ins_pipe( pipe_slow ); |
|
3102 |
%} |
|
3103 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3104 |
// ====================VECTOR ARITHMETIC======================================= |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3105 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3106 |
// --------------------------------- ADD -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3107 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3108 |
// Bytes vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3109 |
instruct vadd4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3110 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3111 |
match(Set dst (AddVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3112 |
format %{ "paddb $dst,$src\t! add packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3113 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3114 |
__ paddb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3115 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3116 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3117 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3118 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3119 |
instruct vadd4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3120 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3121 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3122 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3123 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3124 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3125 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3126 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3127 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3128 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3129 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3130 |
instruct vadd8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3131 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3132 |
match(Set dst (AddVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3133 |
format %{ "paddb $dst,$src\t! add packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3134 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3135 |
__ paddb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3136 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3137 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3138 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3139 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3140 |
instruct vadd8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3141 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3142 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3143 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3144 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3145 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3146 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3147 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3148 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3149 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3150 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3151 |
instruct vadd16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3152 |
predicate(n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3153 |
match(Set dst (AddVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3154 |
format %{ "paddb $dst,$src\t! add packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3155 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3156 |
__ paddb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3157 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3158 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3159 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3160 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3161 |
instruct vadd16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3162 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3163 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3164 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3165 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3166 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3167 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3168 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3169 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3170 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3171 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3172 |
instruct vadd16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3173 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3174 |
match(Set dst (AddVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3175 |
format %{ "vpaddb $dst,$src,$mem\t! add packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3176 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3177 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3178 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3179 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3180 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3181 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3182 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3183 |
instruct vadd32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3184 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3185 |
match(Set dst (AddVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3186 |
format %{ "vpaddb $dst,$src1,$src2\t! add packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3187 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3188 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3189 |
__ vpaddb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3190 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3191 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3192 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3193 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3194 |
instruct vadd32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3195 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3196 |
match(Set dst (AddVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3197 |
format %{ "vpaddb $dst,$src,$mem\t! add packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3198 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3199 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3200 |
__ vpaddb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3201 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3202 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3203 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3204 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3205 |
// Shorts/Chars vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3206 |
instruct vadd2S(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3207 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3208 |
match(Set dst (AddVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3209 |
format %{ "paddw $dst,$src\t! add packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3210 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3211 |
__ paddw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3212 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3213 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3214 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3215 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3216 |
instruct vadd2S_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3217 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3218 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3219 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3220 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3221 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3222 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3223 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3224 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3225 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3226 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3227 |
instruct vadd4S(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3228 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3229 |
match(Set dst (AddVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3230 |
format %{ "paddw $dst,$src\t! add packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3231 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3232 |
__ paddw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3233 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3234 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3235 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3236 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3237 |
instruct vadd4S_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3238 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3239 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3240 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3241 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3242 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3243 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3244 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3245 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3246 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3247 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3248 |
instruct vadd8S(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3249 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3250 |
match(Set dst (AddVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3251 |
format %{ "paddw $dst,$src\t! add packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3252 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3253 |
__ paddw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3254 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3255 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3256 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3257 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3258 |
instruct vadd8S_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3259 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3260 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3261 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3262 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3263 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3264 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3265 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3266 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3267 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3268 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3269 |
instruct vadd8S_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3270 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3271 |
match(Set dst (AddVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3272 |
format %{ "vpaddw $dst,$src,$mem\t! add packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3273 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3274 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3275 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3276 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3277 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3278 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3279 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3280 |
instruct vadd16S_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3281 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3282 |
match(Set dst (AddVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3283 |
format %{ "vpaddw $dst,$src1,$src2\t! add packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3284 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3285 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3286 |
__ vpaddw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3287 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3288 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3289 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3290 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3291 |
instruct vadd16S_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3292 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3293 |
match(Set dst (AddVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3294 |
format %{ "vpaddw $dst,$src,$mem\t! add packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3295 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3296 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3297 |
__ vpaddw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3298 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3299 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3300 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3301 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3302 |
// Integers vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3303 |
instruct vadd2I(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3304 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3305 |
match(Set dst (AddVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3306 |
format %{ "paddd $dst,$src\t! add packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3307 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3308 |
__ paddd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3309 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3310 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3311 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3312 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3313 |
instruct vadd2I_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3314 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3315 |
match(Set dst (AddVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3316 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3317 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3318 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3319 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3320 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3321 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3322 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3323 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3324 |
instruct vadd4I(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3325 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3326 |
match(Set dst (AddVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3327 |
format %{ "paddd $dst,$src\t! add packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3328 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3329 |
__ paddd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3330 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3331 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3332 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3333 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3334 |
instruct vadd4I_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3335 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3336 |
match(Set dst (AddVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3337 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3338 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3339 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3340 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3341 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3342 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3343 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3344 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3345 |
instruct vadd4I_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3346 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3347 |
match(Set dst (AddVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3348 |
format %{ "vpaddd $dst,$src,$mem\t! add packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3349 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3350 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3351 |
__ vpaddd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3352 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3353 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3354 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3355 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3356 |
instruct vadd8I_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3357 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3358 |
match(Set dst (AddVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3359 |
format %{ "vpaddd $dst,$src1,$src2\t! add packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3360 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3361 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3362 |
__ vpaddd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3363 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3364 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3365 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3366 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3367 |
instruct vadd8I_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3368 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3369 |
match(Set dst (AddVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3370 |
format %{ "vpaddd $dst,$src,$mem\t! add packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3371 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3372 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3373 |
__ vpaddd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3374 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3375 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3376 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3377 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3378 |
// Longs vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3379 |
instruct vadd2L(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3380 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3381 |
match(Set dst (AddVL dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3382 |
format %{ "paddq $dst,$src\t! add packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3383 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3384 |
__ paddq($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3385 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3386 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3387 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3388 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3389 |
instruct vadd2L_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3390 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3391 |
match(Set dst (AddVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3392 |
format %{ "vpaddq $dst,$src1,$src2\t! add packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3393 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3394 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3395 |
__ vpaddq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3396 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3397 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3398 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3399 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3400 |
instruct vadd2L_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3401 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3402 |
match(Set dst (AddVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3403 |
format %{ "vpaddq $dst,$src,$mem\t! add packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3404 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3405 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3406 |
__ vpaddq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3407 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3408 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3409 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3410 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3411 |
instruct vadd4L_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3412 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3413 |
match(Set dst (AddVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3414 |
format %{ "vpaddq $dst,$src1,$src2\t! add packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3415 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3416 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3417 |
__ vpaddq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3418 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3419 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3420 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3421 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3422 |
instruct vadd4L_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3423 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3424 |
match(Set dst (AddVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3425 |
format %{ "vpaddq $dst,$src,$mem\t! add packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3426 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3427 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3428 |
__ vpaddq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3429 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3430 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3431 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3432 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3433 |
// Floats vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3434 |
instruct vadd2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3435 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3436 |
match(Set dst (AddVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3437 |
format %{ "addps $dst,$src\t! add packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3438 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3439 |
__ addps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3440 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3441 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3442 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3443 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3444 |
instruct vadd2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3445 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3446 |
match(Set dst (AddVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3447 |
format %{ "vaddps $dst,$src1,$src2\t! add packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3448 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3449 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3450 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3451 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3452 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3453 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3454 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3455 |
instruct vadd4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3456 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3457 |
match(Set dst (AddVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3458 |
format %{ "addps $dst,$src\t! add packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3459 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3460 |
__ addps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3461 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3462 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3463 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3464 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3465 |
instruct vadd4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3466 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3467 |
match(Set dst (AddVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3468 |
format %{ "vaddps $dst,$src1,$src2\t! add packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3469 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3470 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3471 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3472 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3473 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3474 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3475 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3476 |
instruct vadd4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3477 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3478 |
match(Set dst (AddVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3479 |
format %{ "vaddps $dst,$src,$mem\t! add packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3480 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3481 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3482 |
__ vaddps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3483 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3484 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3485 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3486 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3487 |
instruct vadd8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3488 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3489 |
match(Set dst (AddVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3490 |
format %{ "vaddps $dst,$src1,$src2\t! add packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3491 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3492 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3493 |
__ vaddps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3494 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3495 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3496 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3497 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3498 |
instruct vadd8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3499 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3500 |
match(Set dst (AddVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3501 |
format %{ "vaddps $dst,$src,$mem\t! add packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3502 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3503 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3504 |
__ vaddps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3505 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3506 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3507 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3508 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3509 |
// Doubles vector add |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3510 |
instruct vadd2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3511 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3512 |
match(Set dst (AddVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3513 |
format %{ "addpd $dst,$src\t! add packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3514 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3515 |
__ addpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3516 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3517 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3518 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3519 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3520 |
instruct vadd2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3521 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3522 |
match(Set dst (AddVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3523 |
format %{ "vaddpd $dst,$src1,$src2\t! add packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3524 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3525 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3526 |
__ vaddpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3527 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3528 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3529 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3530 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3531 |
instruct vadd2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3532 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3533 |
match(Set dst (AddVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3534 |
format %{ "vaddpd $dst,$src,$mem\t! add packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3535 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3536 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3537 |
__ vaddpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3538 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3539 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3540 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3541 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3542 |
instruct vadd4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3543 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3544 |
match(Set dst (AddVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3545 |
format %{ "vaddpd $dst,$src1,$src2\t! add packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3546 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3547 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3548 |
__ vaddpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3549 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3550 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3551 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3552 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3553 |
instruct vadd4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3554 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3555 |
match(Set dst (AddVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3556 |
format %{ "vaddpd $dst,$src,$mem\t! add packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3557 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3558 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3559 |
__ vaddpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3560 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3561 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3562 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3563 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3564 |
// --------------------------------- SUB -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3565 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3566 |
// Bytes vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3567 |
instruct vsub4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3568 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3569 |
match(Set dst (SubVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3570 |
format %{ "psubb $dst,$src\t! sub packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3571 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3572 |
__ psubb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3573 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3574 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3575 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3576 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3577 |
instruct vsub4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3578 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3579 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3580 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed4B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3581 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3582 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3583 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3584 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3585 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3586 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3587 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3588 |
instruct vsub8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3589 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3590 |
match(Set dst (SubVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3591 |
format %{ "psubb $dst,$src\t! sub packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3592 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3593 |
__ psubb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3594 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3595 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3596 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3597 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3598 |
instruct vsub8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3599 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3600 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3601 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed8B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3602 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3603 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3604 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3605 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3606 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3607 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3608 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3609 |
instruct vsub16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3610 |
predicate(n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3611 |
match(Set dst (SubVB dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3612 |
format %{ "psubb $dst,$src\t! sub packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3613 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3614 |
__ psubb($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3615 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3616 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3617 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3618 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3619 |
instruct vsub16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3620 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3621 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3622 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3623 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3624 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3625 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3626 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3627 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3628 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3629 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3630 |
instruct vsub16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3631 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3632 |
match(Set dst (SubVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3633 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed16B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3634 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3635 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3636 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3637 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3638 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3639 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3640 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3641 |
instruct vsub32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3642 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3643 |
match(Set dst (SubVB src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3644 |
format %{ "vpsubb $dst,$src1,$src2\t! sub packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3645 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3646 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3647 |
__ vpsubb($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3648 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3649 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3650 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3651 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3652 |
instruct vsub32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3653 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3654 |
match(Set dst (SubVB src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3655 |
format %{ "vpsubb $dst,$src,$mem\t! sub packed32B" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3656 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3657 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3658 |
__ vpsubb($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3659 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3660 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3661 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3662 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3663 |
// Shorts/Chars vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3664 |
instruct vsub2S(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3665 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3666 |
match(Set dst (SubVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3667 |
format %{ "psubw $dst,$src\t! sub packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3668 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3669 |
__ psubw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3670 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3671 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3672 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3673 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3674 |
instruct vsub2S_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3675 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3676 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3677 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3678 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3679 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3680 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3681 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3682 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3683 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3684 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3685 |
instruct vsub4S(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3686 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3687 |
match(Set dst (SubVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3688 |
format %{ "psubw $dst,$src\t! sub packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3689 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3690 |
__ psubw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3691 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3692 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3693 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3694 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3695 |
instruct vsub4S_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3696 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3697 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3698 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3699 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3700 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3701 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3702 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3703 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3704 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3705 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3706 |
instruct vsub8S(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3707 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3708 |
match(Set dst (SubVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3709 |
format %{ "psubw $dst,$src\t! sub packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3710 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3711 |
__ psubw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3712 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3713 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3714 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3715 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3716 |
instruct vsub8S_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3717 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3718 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3719 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3720 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3721 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3722 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3723 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3724 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3725 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3726 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3727 |
instruct vsub8S_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3728 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3729 |
match(Set dst (SubVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3730 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3731 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3732 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3733 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3734 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3735 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3736 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3737 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3738 |
instruct vsub16S_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3739 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3740 |
match(Set dst (SubVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3741 |
format %{ "vpsubw $dst,$src1,$src2\t! sub packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3742 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3743 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3744 |
__ vpsubw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3745 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3746 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3747 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3748 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3749 |
instruct vsub16S_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3750 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3751 |
match(Set dst (SubVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3752 |
format %{ "vpsubw $dst,$src,$mem\t! sub packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3753 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3754 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3755 |
__ vpsubw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3756 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3757 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3758 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3759 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3760 |
// Integers vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3761 |
instruct vsub2I(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3762 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3763 |
match(Set dst (SubVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3764 |
format %{ "psubd $dst,$src\t! sub packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3765 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3766 |
__ psubd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3767 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3768 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3769 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3770 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3771 |
instruct vsub2I_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3772 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3773 |
match(Set dst (SubVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3774 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3775 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3776 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3777 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3778 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3779 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3780 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3781 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3782 |
instruct vsub4I(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3783 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3784 |
match(Set dst (SubVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3785 |
format %{ "psubd $dst,$src\t! sub packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3786 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3787 |
__ psubd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3788 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3789 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3790 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3791 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3792 |
instruct vsub4I_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3793 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3794 |
match(Set dst (SubVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3795 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3796 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3797 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3798 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3799 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3800 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3801 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3802 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3803 |
instruct vsub4I_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3804 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3805 |
match(Set dst (SubVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3806 |
format %{ "vpsubd $dst,$src,$mem\t! sub packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3807 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3808 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3809 |
__ vpsubd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3810 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3811 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3812 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3813 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3814 |
instruct vsub8I_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3815 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3816 |
match(Set dst (SubVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3817 |
format %{ "vpsubd $dst,$src1,$src2\t! sub packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3818 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3819 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3820 |
__ vpsubd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3821 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3822 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3823 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3824 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3825 |
instruct vsub8I_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3826 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3827 |
match(Set dst (SubVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3828 |
format %{ "vpsubd $dst,$src,$mem\t! sub packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3829 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3830 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3831 |
__ vpsubd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3832 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3833 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3834 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3835 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3836 |
// Longs vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3837 |
instruct vsub2L(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3838 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3839 |
match(Set dst (SubVL dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3840 |
format %{ "psubq $dst,$src\t! sub packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3841 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3842 |
__ psubq($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3843 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3844 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3845 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3846 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3847 |
instruct vsub2L_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3848 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3849 |
match(Set dst (SubVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3850 |
format %{ "vpsubq $dst,$src1,$src2\t! sub packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3851 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3852 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3853 |
__ vpsubq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3854 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3855 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3856 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3857 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3858 |
instruct vsub2L_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3859 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3860 |
match(Set dst (SubVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3861 |
format %{ "vpsubq $dst,$src,$mem\t! sub packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3862 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3863 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3864 |
__ vpsubq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3865 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3866 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3867 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3868 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3869 |
instruct vsub4L_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3870 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3871 |
match(Set dst (SubVL src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3872 |
format %{ "vpsubq $dst,$src1,$src2\t! sub packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3873 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3874 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3875 |
__ vpsubq($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3876 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3877 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3878 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3879 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3880 |
instruct vsub4L_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3881 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3882 |
match(Set dst (SubVL src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3883 |
format %{ "vpsubq $dst,$src,$mem\t! sub packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3884 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3885 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3886 |
__ vpsubq($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3887 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3888 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3889 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3890 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3891 |
// Floats vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3892 |
instruct vsub2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3893 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3894 |
match(Set dst (SubVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3895 |
format %{ "subps $dst,$src\t! sub packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3896 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3897 |
__ subps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3898 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3899 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3900 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3901 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3902 |
instruct vsub2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3903 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3904 |
match(Set dst (SubVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3905 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3906 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3907 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3908 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3909 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3910 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3911 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3912 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3913 |
instruct vsub4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3914 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3915 |
match(Set dst (SubVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3916 |
format %{ "subps $dst,$src\t! sub packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3917 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3918 |
__ subps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3919 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3920 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3921 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3922 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3923 |
instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3924 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3925 |
match(Set dst (SubVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3926 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3927 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3928 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3929 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3930 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3931 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3932 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3933 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3934 |
instruct vsub4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3935 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3936 |
match(Set dst (SubVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3937 |
format %{ "vsubps $dst,$src,$mem\t! sub packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3938 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3939 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3940 |
__ vsubps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3941 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3942 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3943 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3944 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3945 |
instruct vsub8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3946 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3947 |
match(Set dst (SubVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3948 |
format %{ "vsubps $dst,$src1,$src2\t! sub packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3949 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3950 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3951 |
__ vsubps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3952 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3953 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3954 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3955 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3956 |
instruct vsub8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3957 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3958 |
match(Set dst (SubVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3959 |
format %{ "vsubps $dst,$src,$mem\t! sub packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3960 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3961 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3962 |
__ vsubps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3963 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3964 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3965 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3966 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3967 |
// Doubles vector sub |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3968 |
instruct vsub2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3969 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3970 |
match(Set dst (SubVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3971 |
format %{ "subpd $dst,$src\t! sub packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3972 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3973 |
__ subpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3974 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3975 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3976 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3977 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3978 |
instruct vsub2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3979 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3980 |
match(Set dst (SubVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3981 |
format %{ "vsubpd $dst,$src1,$src2\t! sub packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3982 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3983 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3984 |
__ vsubpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3985 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3986 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3987 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3988 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3989 |
instruct vsub2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3990 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3991 |
match(Set dst (SubVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3992 |
format %{ "vsubpd $dst,$src,$mem\t! sub packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3993 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3994 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3995 |
__ vsubpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3996 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3997 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3998 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
3999 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4000 |
instruct vsub4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4001 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4002 |
match(Set dst (SubVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4003 |
format %{ "vsubpd $dst,$src1,$src2\t! sub packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4004 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4005 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4006 |
__ vsubpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4007 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4008 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4009 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4010 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4011 |
instruct vsub4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4012 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4013 |
match(Set dst (SubVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4014 |
format %{ "vsubpd $dst,$src,$mem\t! sub packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4015 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4016 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4017 |
__ vsubpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4018 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4019 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4020 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4021 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4022 |
// --------------------------------- MUL -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4023 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4024 |
// Shorts/Chars vector mul |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4025 |
instruct vmul2S(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4026 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4027 |
match(Set dst (MulVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4028 |
format %{ "pmullw $dst,$src\t! mul packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4029 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4030 |
__ pmullw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4031 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4032 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4033 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4034 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4035 |
instruct vmul2S_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4036 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4037 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4038 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4039 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4040 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4041 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4042 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4043 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4044 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4045 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4046 |
instruct vmul4S(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4047 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4048 |
match(Set dst (MulVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4049 |
format %{ "pmullw $dst,$src\t! mul packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4050 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4051 |
__ pmullw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4052 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4053 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4054 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4055 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4056 |
instruct vmul4S_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4057 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4058 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4059 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4060 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4061 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4062 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4063 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4064 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4065 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4066 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4067 |
instruct vmul8S(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4068 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4069 |
match(Set dst (MulVS dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4070 |
format %{ "pmullw $dst,$src\t! mul packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4071 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4072 |
__ pmullw($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4073 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4074 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4075 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4076 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4077 |
instruct vmul8S_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4078 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4079 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4080 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4081 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4082 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4083 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4084 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4085 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4086 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4087 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4088 |
instruct vmul8S_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4089 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4090 |
match(Set dst (MulVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4091 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4092 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4093 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4094 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4095 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4096 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4097 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4098 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4099 |
instruct vmul16S_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4100 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4101 |
match(Set dst (MulVS src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4102 |
format %{ "vpmullw $dst,$src1,$src2\t! mul packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4103 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4104 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4105 |
__ vpmullw($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4106 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4107 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4108 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4109 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4110 |
instruct vmul16S_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4111 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4112 |
match(Set dst (MulVS src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4113 |
format %{ "vpmullw $dst,$src,$mem\t! mul packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4114 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4115 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4116 |
__ vpmullw($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4117 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4118 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4119 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4120 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4121 |
// Integers vector mul (sse4_1) |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4122 |
instruct vmul2I(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4123 |
predicate(UseSSE > 3 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4124 |
match(Set dst (MulVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4125 |
format %{ "pmulld $dst,$src\t! mul packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4126 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4127 |
__ pmulld($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4128 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4129 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4130 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4131 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4132 |
instruct vmul2I_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4133 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4134 |
match(Set dst (MulVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4135 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4136 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4137 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4138 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4139 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4140 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4141 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4142 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4143 |
instruct vmul4I(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4144 |
predicate(UseSSE > 3 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4145 |
match(Set dst (MulVI dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4146 |
format %{ "pmulld $dst,$src\t! mul packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4147 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4148 |
__ pmulld($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4149 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4150 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4151 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4152 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4153 |
instruct vmul4I_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4154 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4155 |
match(Set dst (MulVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4156 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4157 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4158 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4159 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4160 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4161 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4162 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4163 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4164 |
instruct vmul4I_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4165 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4166 |
match(Set dst (MulVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4167 |
format %{ "vpmulld $dst,$src,$mem\t! mul packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4168 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4169 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4170 |
__ vpmulld($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4171 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4172 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4173 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4174 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4175 |
instruct vmul8I_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4176 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4177 |
match(Set dst (MulVI src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4178 |
format %{ "vpmulld $dst,$src1,$src2\t! mul packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4179 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4180 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4181 |
__ vpmulld($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4182 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4183 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4184 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4185 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4186 |
instruct vmul8I_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4187 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4188 |
match(Set dst (MulVI src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4189 |
format %{ "vpmulld $dst,$src,$mem\t! mul packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4190 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4191 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4192 |
__ vpmulld($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4193 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4194 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4195 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4196 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4197 |
// Floats vector mul |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4198 |
instruct vmul2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4199 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4200 |
match(Set dst (MulVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4201 |
format %{ "mulps $dst,$src\t! mul packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4202 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4203 |
__ mulps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4204 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4205 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4206 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4207 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4208 |
instruct vmul2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4209 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4210 |
match(Set dst (MulVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4211 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4212 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4213 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4214 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4215 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4216 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4217 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4218 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4219 |
instruct vmul4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4220 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4221 |
match(Set dst (MulVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4222 |
format %{ "mulps $dst,$src\t! mul packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4223 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4224 |
__ mulps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4225 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4226 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4227 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4228 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4229 |
instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4230 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4231 |
match(Set dst (MulVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4232 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4233 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4234 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4235 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4236 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4237 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4238 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4239 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4240 |
instruct vmul4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4241 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4242 |
match(Set dst (MulVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4243 |
format %{ "vmulps $dst,$src,$mem\t! mul packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4244 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4245 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4246 |
__ vmulps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4247 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4248 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4249 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4250 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4251 |
instruct vmul8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4252 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4253 |
match(Set dst (MulVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4254 |
format %{ "vmulps $dst,$src1,$src2\t! mul packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4255 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4256 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4257 |
__ vmulps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4258 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4259 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4260 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4261 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4262 |
instruct vmul8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4263 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4264 |
match(Set dst (MulVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4265 |
format %{ "vmulps $dst,$src,$mem\t! mul packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4266 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4267 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4268 |
__ vmulps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4269 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4270 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4271 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4272 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4273 |
// Doubles vector mul |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4274 |
instruct vmul2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4275 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4276 |
match(Set dst (MulVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4277 |
format %{ "mulpd $dst,$src\t! mul packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4278 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4279 |
__ mulpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4280 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4281 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4282 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4283 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4284 |
instruct vmul2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4285 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4286 |
match(Set dst (MulVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4287 |
format %{ "vmulpd $dst,$src1,$src2\t! mul packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4288 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4289 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4290 |
__ vmulpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4291 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4292 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4293 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4294 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4295 |
instruct vmul2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4296 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4297 |
match(Set dst (MulVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4298 |
format %{ "vmulpd $dst,$src,$mem\t! mul packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4299 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4300 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4301 |
__ vmulpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4302 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4303 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4304 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4305 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4306 |
instruct vmul4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4307 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4308 |
match(Set dst (MulVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4309 |
format %{ "vmulpd $dst,$src1,$src2\t! mul packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4310 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4311 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4312 |
__ vmulpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4313 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4314 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4315 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4316 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4317 |
instruct vmul4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4318 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4319 |
match(Set dst (MulVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4320 |
format %{ "vmulpd $dst,$src,$mem\t! mul packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4321 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4322 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4323 |
__ vmulpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4324 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4325 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4326 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4327 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4328 |
// --------------------------------- DIV -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4329 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4330 |
// Floats vector div |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4331 |
instruct vdiv2F(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4332 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4333 |
match(Set dst (DivVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4334 |
format %{ "divps $dst,$src\t! div packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4335 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4336 |
__ divps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4337 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4338 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4339 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4340 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4341 |
instruct vdiv2F_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4342 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4343 |
match(Set dst (DivVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4344 |
format %{ "vdivps $dst,$src1,$src2\t! div packed2F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4345 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4346 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4347 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4348 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4349 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4350 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4351 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4352 |
instruct vdiv4F(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4353 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4354 |
match(Set dst (DivVF dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4355 |
format %{ "divps $dst,$src\t! div packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4356 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4357 |
__ divps($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4358 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4359 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4360 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4361 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4362 |
instruct vdiv4F_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4363 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4364 |
match(Set dst (DivVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4365 |
format %{ "vdivps $dst,$src1,$src2\t! div packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4366 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4367 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4368 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4369 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4370 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4371 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4372 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4373 |
instruct vdiv4F_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4374 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4375 |
match(Set dst (DivVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4376 |
format %{ "vdivps $dst,$src,$mem\t! div packed4F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4377 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4378 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4379 |
__ vdivps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4380 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4381 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4382 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4383 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4384 |
instruct vdiv8F_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4385 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4386 |
match(Set dst (DivVF src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4387 |
format %{ "vdivps $dst,$src1,$src2\t! div packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4388 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4389 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4390 |
__ vdivps($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4391 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4392 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4393 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4394 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4395 |
instruct vdiv8F_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4396 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4397 |
match(Set dst (DivVF src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4398 |
format %{ "vdivps $dst,$src,$mem\t! div packed8F" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4399 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4400 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4401 |
__ vdivps($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4402 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4403 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4404 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4405 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4406 |
// Doubles vector div |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4407 |
instruct vdiv2D(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4408 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4409 |
match(Set dst (DivVD dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4410 |
format %{ "divpd $dst,$src\t! div packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4411 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4412 |
__ divpd($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4413 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4414 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4415 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4416 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4417 |
instruct vdiv2D_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4418 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4419 |
match(Set dst (DivVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4420 |
format %{ "vdivpd $dst,$src1,$src2\t! div packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4421 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4422 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4423 |
__ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4424 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4425 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4426 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4427 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4428 |
instruct vdiv2D_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4429 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4430 |
match(Set dst (DivVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4431 |
format %{ "vdivpd $dst,$src,$mem\t! div packed2D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4432 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4433 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4434 |
__ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4435 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4436 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4437 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4438 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4439 |
instruct vdiv4D_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4440 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4441 |
match(Set dst (DivVD src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4442 |
format %{ "vdivpd $dst,$src1,$src2\t! div packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4443 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4444 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4445 |
__ vdivpd($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4446 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4447 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4448 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4449 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4450 |
instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4451 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4452 |
match(Set dst (DivVD src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4453 |
format %{ "vdivpd $dst,$src,$mem\t! div packed4D" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4454 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4455 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4456 |
__ vdivpd($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4457 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4458 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4459 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4460 |
|
13930 | 4461 |
// ------------------------------ Shift --------------------------------------- |
4462 |
||
4463 |
// Left and right shift count vectors are the same on x86 |
|
4464 |
// (only lowest bits of xmm reg are used for count). |
|
4465 |
instruct vshiftcnt(vecS dst, rRegI cnt) %{ |
|
4466 |
match(Set dst (LShiftCntV cnt)); |
|
4467 |
match(Set dst (RShiftCntV cnt)); |
|
4468 |
format %{ "movd $dst,$cnt\t! load shift count" %} |
|
4469 |
ins_encode %{ |
|
4470 |
__ movdl($dst$$XMMRegister, $cnt$$Register); |
|
4471 |
%} |
|
4472 |
ins_pipe( pipe_slow ); |
|
4473 |
%} |
|
4474 |
||
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4475 |
// ------------------------------ LeftShift ----------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4476 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4477 |
// Shorts/Chars vector left shift |
13930 | 4478 |
instruct vsll2S(vecS dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4479 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4480 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4481 |
format %{ "psllw $dst,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4482 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4483 |
__ psllw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4484 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4485 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4486 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4487 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4488 |
instruct vsll2S_imm(vecS dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4489 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4490 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4491 |
format %{ "psllw $dst,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4492 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4493 |
__ psllw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4494 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4495 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4496 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4497 |
|
13930 | 4498 |
instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4499 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4500 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4501 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4502 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4503 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4504 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4505 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4506 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4507 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4508 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4509 |
instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4510 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4511 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4512 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4513 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4514 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4515 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4516 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4517 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4518 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4519 |
|
13930 | 4520 |
instruct vsll4S(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4521 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4522 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4523 |
format %{ "psllw $dst,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4524 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4525 |
__ psllw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4526 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4527 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4528 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4529 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4530 |
instruct vsll4S_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4531 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4532 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4533 |
format %{ "psllw $dst,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4534 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4535 |
__ psllw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4536 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4537 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4538 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4539 |
|
13930 | 4540 |
instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4541 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4542 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4543 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4544 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4545 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4546 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4547 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4548 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4549 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4550 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4551 |
instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4552 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4553 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4554 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4555 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4556 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4557 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4558 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4559 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4560 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4561 |
|
13930 | 4562 |
instruct vsll8S(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4563 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4564 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4565 |
format %{ "psllw $dst,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4566 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4567 |
__ psllw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4568 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4569 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4570 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4571 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4572 |
instruct vsll8S_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4573 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4574 |
match(Set dst (LShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4575 |
format %{ "psllw $dst,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4576 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4577 |
__ psllw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4578 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4579 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4580 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4581 |
|
13930 | 4582 |
instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4583 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4584 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4585 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4586 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4587 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4588 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4589 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4590 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4591 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4592 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4593 |
instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4594 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4595 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4596 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4597 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4598 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4599 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4600 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4601 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4602 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4603 |
|
13930 | 4604 |
instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4605 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4606 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4607 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4608 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4609 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4610 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4611 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4612 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4613 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4614 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4615 |
instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4616 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4617 |
match(Set dst (LShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4618 |
format %{ "vpsllw $dst,$src,$shift\t! left shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4619 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4620 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4621 |
__ vpsllw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4622 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4623 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4624 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4625 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4626 |
// Integers vector left shift |
13930 | 4627 |
instruct vsll2I(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4628 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4629 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4630 |
format %{ "pslld $dst,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4631 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4632 |
__ pslld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4633 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4634 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4635 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4636 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4637 |
instruct vsll2I_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4638 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4639 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4640 |
format %{ "pslld $dst,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4641 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4642 |
__ pslld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4643 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4644 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4645 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4646 |
|
13930 | 4647 |
instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4648 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4649 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4650 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4651 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4652 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4653 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4654 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4655 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4656 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4657 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4658 |
instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4659 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4660 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4661 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4662 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4663 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4664 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4665 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4666 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4667 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4668 |
|
13930 | 4669 |
instruct vsll4I(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4670 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4671 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4672 |
format %{ "pslld $dst,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4673 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4674 |
__ pslld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4675 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4676 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4677 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4678 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4679 |
instruct vsll4I_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4680 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4681 |
match(Set dst (LShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4682 |
format %{ "pslld $dst,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4683 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4684 |
__ pslld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4685 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4686 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4687 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4688 |
|
13930 | 4689 |
instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4690 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4691 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4692 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4693 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4694 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4695 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4696 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4697 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4698 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4699 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4700 |
instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4701 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4702 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4703 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4704 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4705 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4706 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4707 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4708 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4709 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4710 |
|
13930 | 4711 |
instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4712 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4713 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4714 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4715 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4716 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4717 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4718 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4719 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4720 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4721 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4722 |
instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4723 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4724 |
match(Set dst (LShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4725 |
format %{ "vpslld $dst,$src,$shift\t! left shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4726 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4727 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4728 |
__ vpslld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4729 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4730 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4731 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4732 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4733 |
// Longs vector left shift |
13930 | 4734 |
instruct vsll2L(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4735 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4736 |
match(Set dst (LShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4737 |
format %{ "psllq $dst,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4738 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4739 |
__ psllq($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4740 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4741 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4742 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4743 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4744 |
instruct vsll2L_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4745 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4746 |
match(Set dst (LShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4747 |
format %{ "psllq $dst,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4748 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4749 |
__ psllq($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4750 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4751 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4752 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4753 |
|
13930 | 4754 |
instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4755 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4756 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4757 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4758 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4759 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4760 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4761 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4762 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4763 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4764 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4765 |
instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4766 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4767 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4768 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4769 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4770 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4771 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4772 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4773 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4774 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4775 |
|
13930 | 4776 |
instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4777 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4778 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4779 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4780 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4781 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4782 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4783 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4784 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4785 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4786 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4787 |
instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4788 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4789 |
match(Set dst (LShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4790 |
format %{ "vpsllq $dst,$src,$shift\t! left shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4791 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4792 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4793 |
__ vpsllq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4794 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4795 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4796 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4797 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4798 |
// ----------------------- LogicalRightShift ----------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4799 |
|
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4800 |
// Shorts vector logical right shift produces incorrect Java result |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4801 |
// for negative data because java code convert short value into int with |
14131
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4802 |
// sign extension before a shift. But char vectors are fine since chars are |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4803 |
// unsigned values. |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4804 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4805 |
instruct vsrl2S(vecS dst, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4806 |
predicate(n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4807 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4808 |
format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4809 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4810 |
__ psrlw($dst$$XMMRegister, $shift$$XMMRegister); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4811 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4812 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4813 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4814 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4815 |
instruct vsrl2S_imm(vecS dst, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4816 |
predicate(n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4817 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4818 |
format %{ "psrlw $dst,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4819 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4820 |
__ psrlw($dst$$XMMRegister, (int)$shift$$constant); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4821 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4822 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4823 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4824 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4825 |
instruct vsrl2S_reg(vecS dst, vecS src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4826 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4827 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4828 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4829 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4830 |
bool vector256 = false; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4831 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4832 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4833 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4834 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4835 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4836 |
instruct vsrl2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4837 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4838 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4839 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed2S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4840 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4841 |
bool vector256 = false; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4842 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4843 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4844 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4845 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4846 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4847 |
instruct vsrl4S(vecD dst, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4848 |
predicate(n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4849 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4850 |
format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4851 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4852 |
__ psrlw($dst$$XMMRegister, $shift$$XMMRegister); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4853 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4854 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4855 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4856 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4857 |
instruct vsrl4S_imm(vecD dst, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4858 |
predicate(n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4859 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4860 |
format %{ "psrlw $dst,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4861 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4862 |
__ psrlw($dst$$XMMRegister, (int)$shift$$constant); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4863 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4864 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4865 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4866 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4867 |
instruct vsrl4S_reg(vecD dst, vecD src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4868 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4869 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4870 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4871 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4872 |
bool vector256 = false; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4873 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4874 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4875 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4876 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4877 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4878 |
instruct vsrl4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4879 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4880 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4881 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed4S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4882 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4883 |
bool vector256 = false; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4884 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4885 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4886 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4887 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4888 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4889 |
instruct vsrl8S(vecX dst, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4890 |
predicate(n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4891 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4892 |
format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4893 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4894 |
__ psrlw($dst$$XMMRegister, $shift$$XMMRegister); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4895 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4896 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4897 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4898 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4899 |
instruct vsrl8S_imm(vecX dst, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4900 |
predicate(n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4901 |
match(Set dst (URShiftVS dst shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4902 |
format %{ "psrlw $dst,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4903 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4904 |
__ psrlw($dst$$XMMRegister, (int)$shift$$constant); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4905 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4906 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4907 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4908 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4909 |
instruct vsrl8S_reg(vecX dst, vecX src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4910 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4911 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4912 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4913 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4914 |
bool vector256 = false; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4915 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4916 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4917 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4918 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4919 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4920 |
instruct vsrl8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4921 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4922 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4923 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed8S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4924 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4925 |
bool vector256 = false; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4926 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4927 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4928 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4929 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4930 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4931 |
instruct vsrl16S_reg(vecY dst, vecY src, vecS shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4932 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4933 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4934 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4935 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4936 |
bool vector256 = true; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4937 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4938 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4939 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4940 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4941 |
|
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4942 |
instruct vsrl16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4943 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4944 |
match(Set dst (URShiftVS src shift)); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4945 |
format %{ "vpsrlw $dst,$src,$shift\t! logical right shift packed16S" %} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4946 |
ins_encode %{ |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4947 |
bool vector256 = true; |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4948 |
__ vpsrlw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4949 |
%} |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4950 |
ins_pipe( pipe_slow ); |
e376e3d428c9
8001183: incorrect results of char vectors right shift operaiton
kvn
parents:
13930
diff
changeset
|
4951 |
%} |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4952 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4953 |
// Integers vector logical right shift |
13930 | 4954 |
instruct vsrl2I(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4955 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4956 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4957 |
format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4958 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4959 |
__ psrld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4960 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4961 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4962 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4963 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4964 |
instruct vsrl2I_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4965 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4966 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4967 |
format %{ "psrld $dst,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4968 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4969 |
__ psrld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4970 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4971 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4972 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4973 |
|
13930 | 4974 |
instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4975 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4976 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4977 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4978 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4979 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4980 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4981 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4982 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4983 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4984 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4985 |
instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4986 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4987 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4988 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4989 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4990 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4991 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4992 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4993 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4994 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4995 |
|
13930 | 4996 |
instruct vsrl4I(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4997 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4998 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
4999 |
format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5000 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5001 |
__ psrld($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5002 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5003 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5004 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5005 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5006 |
instruct vsrl4I_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5007 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5008 |
match(Set dst (URShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5009 |
format %{ "psrld $dst,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5010 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5011 |
__ psrld($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5012 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5013 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5014 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5015 |
|
13930 | 5016 |
instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5017 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5018 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5019 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5020 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5021 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5022 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5023 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5024 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5025 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5026 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5027 |
instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5028 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5029 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5030 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5031 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5032 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5033 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5034 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5035 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5036 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5037 |
|
13930 | 5038 |
instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5039 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5040 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5041 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5042 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5043 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5044 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5045 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5046 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5047 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5048 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5049 |
instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5050 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5051 |
match(Set dst (URShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5052 |
format %{ "vpsrld $dst,$src,$shift\t! logical right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5053 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5054 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5055 |
__ vpsrld($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5056 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5057 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5058 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5059 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5060 |
// Longs vector logical right shift |
13930 | 5061 |
instruct vsrl2L(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5062 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5063 |
match(Set dst (URShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5064 |
format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5065 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5066 |
__ psrlq($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5067 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5068 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5069 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5070 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5071 |
instruct vsrl2L_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5072 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5073 |
match(Set dst (URShiftVL dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5074 |
format %{ "psrlq $dst,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5075 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5076 |
__ psrlq($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5077 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5078 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5079 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5080 |
|
13930 | 5081 |
instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5082 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5083 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5084 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5085 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5086 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5087 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5088 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5089 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5090 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5091 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5092 |
instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5093 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5094 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5095 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed2L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5096 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5097 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5098 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5099 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5100 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5101 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5102 |
|
13930 | 5103 |
instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5104 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5105 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5106 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5107 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5108 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5109 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5110 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5111 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5112 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5113 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5114 |
instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5115 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5116 |
match(Set dst (URShiftVL src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5117 |
format %{ "vpsrlq $dst,$src,$shift\t! logical right shift packed4L" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5118 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5119 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5120 |
__ vpsrlq($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5121 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5122 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5123 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5124 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5125 |
// ------------------- ArithmeticRightShift ----------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5126 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5127 |
// Shorts/Chars vector arithmetic right shift |
13930 | 5128 |
instruct vsra2S(vecS dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5129 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5130 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5131 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5132 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5133 |
__ psraw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5134 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5135 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5136 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5137 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5138 |
instruct vsra2S_imm(vecS dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5139 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5140 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5141 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5142 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5143 |
__ psraw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5144 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5145 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5146 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5147 |
|
13930 | 5148 |
instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5149 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5150 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5151 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5152 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5153 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5154 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5155 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5156 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5157 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5158 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5159 |
instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5160 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5161 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5162 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed2S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5163 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5164 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5165 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5166 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5167 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5168 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5169 |
|
13930 | 5170 |
instruct vsra4S(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5171 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5172 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5173 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5174 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5175 |
__ psraw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5176 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5177 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5178 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5179 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5180 |
instruct vsra4S_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5181 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5182 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5183 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5184 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5185 |
__ psraw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5186 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5187 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5188 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5189 |
|
13930 | 5190 |
instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5191 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5192 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5193 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5194 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5195 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5196 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5197 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5198 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5199 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5200 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5201 |
instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5202 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5203 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5204 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed4S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5205 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5206 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5207 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5208 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5209 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5210 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5211 |
|
13930 | 5212 |
instruct vsra8S(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5213 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5214 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5215 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5216 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5217 |
__ psraw($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5218 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5219 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5220 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5221 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5222 |
instruct vsra8S_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5223 |
predicate(n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5224 |
match(Set dst (RShiftVS dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5225 |
format %{ "psraw $dst,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5226 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5227 |
__ psraw($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5228 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5229 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5230 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5231 |
|
13930 | 5232 |
instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5233 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5234 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5235 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5236 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5237 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5238 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5239 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5240 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5241 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5242 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5243 |
instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5244 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5245 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5246 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed8S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5247 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5248 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5249 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5250 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5251 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5252 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5253 |
|
13930 | 5254 |
instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5255 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5256 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5257 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5258 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5259 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5260 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5261 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5262 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5263 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5264 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5265 |
instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5266 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5267 |
match(Set dst (RShiftVS src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5268 |
format %{ "vpsraw $dst,$src,$shift\t! arithmetic right shift packed16S" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5269 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5270 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5271 |
__ vpsraw($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5272 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5273 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5274 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5275 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5276 |
// Integers vector arithmetic right shift |
13930 | 5277 |
instruct vsra2I(vecD dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5278 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5279 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5280 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5281 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5282 |
__ psrad($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5283 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5284 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5285 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5286 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5287 |
instruct vsra2I_imm(vecD dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5288 |
predicate(n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5289 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5290 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5291 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5292 |
__ psrad($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5293 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5294 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5295 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5296 |
|
13930 | 5297 |
instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5298 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5299 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5300 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5301 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5302 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5303 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5304 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5305 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5306 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5307 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5308 |
instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5309 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 2); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5310 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5311 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed2I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5312 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5313 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5314 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5315 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5316 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5317 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5318 |
|
13930 | 5319 |
instruct vsra4I(vecX dst, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5320 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5321 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5322 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5323 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5324 |
__ psrad($dst$$XMMRegister, $shift$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5325 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5326 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5327 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5328 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5329 |
instruct vsra4I_imm(vecX dst, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5330 |
predicate(n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5331 |
match(Set dst (RShiftVI dst shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5332 |
format %{ "psrad $dst,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5333 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5334 |
__ psrad($dst$$XMMRegister, (int)$shift$$constant); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5335 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5336 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5337 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5338 |
|
13930 | 5339 |
instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5340 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5341 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5342 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5343 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5344 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5345 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5346 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5347 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5348 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5349 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5350 |
instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5351 |
predicate(UseAVX > 0 && n->as_Vector()->length() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5352 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5353 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed4I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5354 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5355 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5356 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5357 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5358 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5359 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5360 |
|
13930 | 5361 |
instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{ |
13485
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5362 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5363 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5364 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5365 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5366 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5367 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5368 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5369 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5370 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5371 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5372 |
instruct vsra8I_reg_imm(vecY dst, vecY src, immI8 shift) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5373 |
predicate(UseAVX > 1 && n->as_Vector()->length() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5374 |
match(Set dst (RShiftVI src shift)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5375 |
format %{ "vpsrad $dst,$src,$shift\t! arithmetic right shift packed8I" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5376 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5377 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5378 |
__ vpsrad($dst$$XMMRegister, $src$$XMMRegister, (int)$shift$$constant, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5379 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5380 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5381 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5382 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5383 |
// There are no longs vector arithmetic right shift instructions. |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5384 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5385 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5386 |
// --------------------------------- AND -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5387 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5388 |
instruct vand4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5389 |
predicate(n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5390 |
match(Set dst (AndV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5391 |
format %{ "pand $dst,$src\t! and vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5392 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5393 |
__ pand($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5394 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5395 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5396 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5397 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5398 |
instruct vand4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5399 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5400 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5401 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5402 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5403 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5404 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5405 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5406 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5407 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5408 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5409 |
instruct vand8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5410 |
predicate(n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5411 |
match(Set dst (AndV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5412 |
format %{ "pand $dst,$src\t! and vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5413 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5414 |
__ pand($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5415 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5416 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5417 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5418 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5419 |
instruct vand8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5420 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5421 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5422 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5423 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5424 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5425 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5426 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5427 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5428 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5429 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5430 |
instruct vand16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5431 |
predicate(n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5432 |
match(Set dst (AndV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5433 |
format %{ "pand $dst,$src\t! and vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5434 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5435 |
__ pand($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5436 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5437 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5438 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5439 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5440 |
instruct vand16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5441 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5442 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5443 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5444 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5445 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5446 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5447 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5448 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5449 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5450 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5451 |
instruct vand16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5452 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5453 |
match(Set dst (AndV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5454 |
format %{ "vpand $dst,$src,$mem\t! and vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5455 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5456 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5457 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5458 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5459 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5460 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5461 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5462 |
instruct vand32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5463 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5464 |
match(Set dst (AndV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5465 |
format %{ "vpand $dst,$src1,$src2\t! and vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5466 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5467 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5468 |
__ vpand($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5469 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5470 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5471 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5472 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5473 |
instruct vand32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5474 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5475 |
match(Set dst (AndV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5476 |
format %{ "vpand $dst,$src,$mem\t! and vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5477 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5478 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5479 |
__ vpand($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5480 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5481 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5482 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5483 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5484 |
// --------------------------------- OR --------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5485 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5486 |
instruct vor4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5487 |
predicate(n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5488 |
match(Set dst (OrV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5489 |
format %{ "por $dst,$src\t! or vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5490 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5491 |
__ por($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5492 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5493 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5494 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5495 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5496 |
instruct vor4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5497 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5498 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5499 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5500 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5501 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5502 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5503 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5504 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5505 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5506 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5507 |
instruct vor8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5508 |
predicate(n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5509 |
match(Set dst (OrV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5510 |
format %{ "por $dst,$src\t! or vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5511 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5512 |
__ por($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5513 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5514 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5515 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5516 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5517 |
instruct vor8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5518 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5519 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5520 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5521 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5522 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5523 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5524 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5525 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5526 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5527 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5528 |
instruct vor16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5529 |
predicate(n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5530 |
match(Set dst (OrV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5531 |
format %{ "por $dst,$src\t! or vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5532 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5533 |
__ por($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5534 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5535 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5536 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5537 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5538 |
instruct vor16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5539 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5540 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5541 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5542 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5543 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5544 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5545 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5546 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5547 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5548 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5549 |
instruct vor16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5550 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5551 |
match(Set dst (OrV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5552 |
format %{ "vpor $dst,$src,$mem\t! or vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5553 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5554 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5555 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5556 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5557 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5558 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5559 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5560 |
instruct vor32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5561 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5562 |
match(Set dst (OrV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5563 |
format %{ "vpor $dst,$src1,$src2\t! or vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5564 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5565 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5566 |
__ vpor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5567 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5568 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5569 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5570 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5571 |
instruct vor32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5572 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5573 |
match(Set dst (OrV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5574 |
format %{ "vpor $dst,$src,$mem\t! or vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5575 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5576 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5577 |
__ vpor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5578 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5579 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5580 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5581 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5582 |
// --------------------------------- XOR -------------------------------------- |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5583 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5584 |
instruct vxor4B(vecS dst, vecS src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5585 |
predicate(n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5586 |
match(Set dst (XorV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5587 |
format %{ "pxor $dst,$src\t! xor vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5588 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5589 |
__ pxor($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5590 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5591 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5592 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5593 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5594 |
instruct vxor4B_reg(vecS dst, vecS src1, vecS src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5595 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 4); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5596 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5597 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (4 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5598 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5599 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5600 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5601 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5602 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5603 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5604 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5605 |
instruct vxor8B(vecD dst, vecD src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5606 |
predicate(n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5607 |
match(Set dst (XorV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5608 |
format %{ "pxor $dst,$src\t! xor vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5609 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5610 |
__ pxor($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5611 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5612 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5613 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5614 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5615 |
instruct vxor8B_reg(vecD dst, vecD src1, vecD src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5616 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 8); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5617 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5618 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (8 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5619 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5620 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5621 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5622 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5623 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5624 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5625 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5626 |
instruct vxor16B(vecX dst, vecX src) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5627 |
predicate(n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5628 |
match(Set dst (XorV dst src)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5629 |
format %{ "pxor $dst,$src\t! xor vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5630 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5631 |
__ pxor($dst$$XMMRegister, $src$$XMMRegister); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5632 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5633 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5634 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5635 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5636 |
instruct vxor16B_reg(vecX dst, vecX src1, vecX src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5637 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5638 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5639 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (16 bytes)" %} |
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6340864: Implement vectorization optimizations in hotspot-server
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parents:
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changeset
|
5640 |
ins_encode %{ |
6c7faa516fc6
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changeset
|
5641 |
bool vector256 = false; |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
5642 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
5643 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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changeset
|
5644 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5645 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5646 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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changeset
|
5647 |
instruct vxor16B_mem(vecX dst, vecX src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5648 |
predicate(UseAVX > 0 && n->as_Vector()->length_in_bytes() == 16); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5649 |
match(Set dst (XorV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5650 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (16 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5651 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5652 |
bool vector256 = false; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5653 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5654 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5655 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5656 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5657 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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changeset
|
5658 |
instruct vxor32B_reg(vecY dst, vecY src1, vecY src2) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5659 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5660 |
match(Set dst (XorV src1 src2)); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5661 |
format %{ "vpxor $dst,$src1,$src2\t! xor vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5662 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5663 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
5664 |
__ vpxor($dst$$XMMRegister, $src1$$XMMRegister, $src2$$XMMRegister, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5665 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5666 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5667 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5668 |
|
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5669 |
instruct vxor32B_mem(vecY dst, vecY src, memory mem) %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5670 |
predicate(UseAVX > 1 && n->as_Vector()->length_in_bytes() == 32); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5671 |
match(Set dst (XorV src (LoadVector mem))); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5672 |
format %{ "vpxor $dst,$src,$mem\t! xor vectors (32 bytes)" %} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5673 |
ins_encode %{ |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5674 |
bool vector256 = true; |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5675 |
__ vpxor($dst$$XMMRegister, $src$$XMMRegister, $mem$$Address, vector256); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5676 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5677 |
ins_pipe( pipe_slow ); |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5678 |
%} |
6c7faa516fc6
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
13294
diff
changeset
|
5679 |