src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/vector/AMD64VectorBinary.java
author dlong
Thu, 14 Nov 2019 12:21:00 -0800
changeset 59095 03fbcd06b4c0
parent 57537 ecc6e394475f
permissions -rw-r--r--
8233841: Update Graal Reviewed-by: kvn
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/*
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 * Copyright (c) 2013, 2019, Oracle and/or its affiliates. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 */
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package org.graalvm.compiler.lir.amd64.vector;
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import static jdk.vm.ci.code.ValueUtil.asRegister;
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import static jdk.vm.ci.code.ValueUtil.isRegister;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
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import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
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import org.graalvm.compiler.asm.amd64.AMD64Address;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRRIOp;
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import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp;
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import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
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import org.graalvm.compiler.asm.amd64.AVXKind;
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import org.graalvm.compiler.lir.ConstantValue;
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import org.graalvm.compiler.lir.LIRFrameState;
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import org.graalvm.compiler.lir.LIRInstructionClass;
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import org.graalvm.compiler.lir.Opcode;
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import org.graalvm.compiler.lir.amd64.AMD64AddressValue;
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import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
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import jdk.vm.ci.amd64.AMD64Kind;
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import jdk.vm.ci.meta.AllocatableValue;
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public class AMD64VectorBinary {
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    public static final class AVXBinaryOp extends AMD64VectorInstruction {
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        public static final LIRInstructionClass<AVXBinaryOp> TYPE = LIRInstructionClass.create(AVXBinaryOp.class);
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        @Opcode private final VexRVMOp opcode;
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG}) protected AllocatableValue x;
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        @Use({REG, STACK}) protected AllocatableValue y;
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        public AVXBinaryOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
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            super(TYPE, size);
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            this.opcode = opcode;
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            this.result = result;
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            this.x = x;
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            this.y = y;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (isRegister(y)) {
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                opcode.emit(masm, size, asRegister(result), asRegister(x), asRegister(y));
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            } else {
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                opcode.emit(masm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asAddress(y));
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            }
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        }
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    }
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    public static final class AVXBinaryConstOp extends AMD64VectorInstruction {
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        public static final LIRInstructionClass<AVXBinaryConstOp> TYPE = LIRInstructionClass.create(AVXBinaryConstOp.class);
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        @Opcode private final VexRRIOp opcode;
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG}) protected AllocatableValue x;
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        protected int y;
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        public AVXBinaryConstOp(VexRRIOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, int y) {
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            super(TYPE, size);
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            assert (y & 0xFF) == y;
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            this.opcode = opcode;
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            this.result = result;
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            this.x = x;
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            this.y = y;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            opcode.emit(masm, size, asRegister(result), asRegister(x), y);
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        }
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    }
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    public static final class AVXBinaryConstFloatOp extends AMD64VectorInstruction {
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        public static final LIRInstructionClass<AVXBinaryConstFloatOp> TYPE = LIRInstructionClass.create(AVXBinaryConstFloatOp.class);
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        @Opcode private final VexRVMOp opcode;
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG}) protected AllocatableValue x;
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        protected ConstantValue y;
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        public AVXBinaryConstFloatOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, ConstantValue y) {
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            super(TYPE, size);
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            assert y.getPlatformKind() == AMD64Kind.SINGLE || y.getPlatformKind() == AMD64Kind.DOUBLE;
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            this.opcode = opcode;
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            this.result = result;
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            this.x = x;
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            this.y = y;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (y.getPlatformKind() == AMD64Kind.SINGLE) {
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                opcode.emit(masm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asFloatConstRef(y.getJavaConstant()));
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            } else {
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                assert y.getPlatformKind() == AMD64Kind.DOUBLE;
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                opcode.emit(masm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asDoubleConstRef(y.getJavaConstant()));
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            }
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        }
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    }
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    public static final class AVXBinaryMemoryOp extends AMD64VectorInstruction {
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        public static final LIRInstructionClass<AVXBinaryMemoryOp> TYPE = LIRInstructionClass.create(AVXBinaryMemoryOp.class);
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        @Opcode private final VexRVMOp opcode;
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        @Def({REG}) protected AllocatableValue result;
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        @Use({REG}) protected AllocatableValue x;
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        @Use({COMPOSITE}) protected AMD64AddressValue y;
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        @State protected LIRFrameState state;
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        public AVXBinaryMemoryOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AMD64AddressValue y, LIRFrameState state) {
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            super(TYPE, size);
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            this.opcode = opcode;
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            this.result = result;
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            this.x = x;
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            this.y = y;
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            this.state = state;
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        }
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        @Override
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        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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            if (state != null) {
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                crb.recordImplicitException(masm.position(), state);
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            }
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            opcode.emit(masm, size, asRegister(result), asRegister(x), y.toAddress());
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        }
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    }
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}