--- a/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/vector/AMD64VectorBinary.java	Fri Aug 17 11:56:59 2018 -0500
+++ b/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.amd64/src/org/graalvm/compiler/lir/amd64/vector/AMD64VectorBinary.java	Fri Aug 17 13:20:53 2018 -0700
@@ -24,35 +24,39 @@
 
 package org.graalvm.compiler.lir.amd64.vector;
 
-import jdk.vm.ci.meta.AllocatableValue;
-import org.graalvm.compiler.asm.amd64.AMD64Address;
-import org.graalvm.compiler.asm.amd64.AMD64VectorAssembler;
-import org.graalvm.compiler.asm.amd64.AVXKind;
-import org.graalvm.compiler.lir.LIRFrameState;
-import org.graalvm.compiler.lir.LIRInstructionClass;
-import org.graalvm.compiler.lir.Opcode;
-import org.graalvm.compiler.lir.amd64.AMD64AddressValue;
-import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
-
 import static jdk.vm.ci.code.ValueUtil.asRegister;
 import static jdk.vm.ci.code.ValueUtil.isRegister;
 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.COMPOSITE;
 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;
 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK;
 
+import org.graalvm.compiler.asm.amd64.AMD64Address;
+import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRRIOp;
+import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp;
+import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
+import org.graalvm.compiler.asm.amd64.AVXKind;
+import org.graalvm.compiler.lir.LIRFrameState;
+import org.graalvm.compiler.lir.LIRInstructionClass;
+import org.graalvm.compiler.lir.Opcode;
+import org.graalvm.compiler.lir.amd64.AMD64AddressValue;
+import org.graalvm.compiler.lir.amd64.AMD64LIRInstruction;
+import org.graalvm.compiler.lir.asm.CompilationResultBuilder;
+
+import jdk.vm.ci.meta.AllocatableValue;
+
 public class AMD64VectorBinary {
 
-    public static final class AVXBinaryOp extends AMD64VectorLIRInstruction {
+    public static final class AVXBinaryOp extends AMD64LIRInstruction {
         public static final LIRInstructionClass<AVXBinaryOp> TYPE = LIRInstructionClass.create(AVXBinaryOp.class);
 
-        @Opcode private final AMD64VectorAssembler.VexRVMOp opcode;
+        @Opcode private final VexRVMOp opcode;
         private final AVXKind.AVXSize size;
 
         @Def({REG}) protected AllocatableValue result;
         @Use({REG}) protected AllocatableValue x;
         @Use({REG, STACK}) protected AllocatableValue y;
 
-        public AVXBinaryOp(AMD64VectorAssembler.VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
+        public AVXBinaryOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
             super(TYPE);
             this.opcode = opcode;
             this.size = size;
@@ -62,27 +66,27 @@
         }
 
         @Override
-        public void emitCode(CompilationResultBuilder crb, AMD64VectorAssembler vasm) {
+        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
             if (isRegister(y)) {
-                opcode.emit(vasm, size, asRegister(result), asRegister(x), asRegister(y));
+                opcode.emit(masm, size, asRegister(result), asRegister(x), asRegister(y));
             } else {
-                opcode.emit(vasm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asAddress(y));
+                opcode.emit(masm, size, asRegister(result), asRegister(x), (AMD64Address) crb.asAddress(y));
             }
         }
     }
 
-    public static final class AVXBinaryConstOp extends AMD64VectorLIRInstruction {
+    public static final class AVXBinaryConstOp extends AMD64LIRInstruction {
 
         public static final LIRInstructionClass<AVXBinaryConstOp> TYPE = LIRInstructionClass.create(AVXBinaryConstOp.class);
 
-        @Opcode private final AMD64VectorAssembler.VexRRIOp opcode;
+        @Opcode private final VexRRIOp opcode;
         private final AVXKind.AVXSize size;
 
         @Def({REG}) protected AllocatableValue result;
         @Use({REG}) protected AllocatableValue x;
         protected int y;
 
-        public AVXBinaryConstOp(AMD64VectorAssembler.VexRRIOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, int y) {
+        public AVXBinaryConstOp(VexRRIOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, int y) {
             super(TYPE);
             assert (y & 0xFF) == y;
             this.opcode = opcode;
@@ -93,15 +97,15 @@
         }
 
         @Override
-        public void emitCode(CompilationResultBuilder crb, AMD64VectorAssembler vasm) {
-            opcode.emit(vasm, size, asRegister(result), asRegister(x), y);
+        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
+            opcode.emit(masm, size, asRegister(result), asRegister(x), y);
         }
     }
 
-    public static final class AVXBinaryMemoryOp extends AMD64VectorLIRInstruction {
+    public static final class AVXBinaryMemoryOp extends AMD64LIRInstruction {
         public static final LIRInstructionClass<AVXBinaryMemoryOp> TYPE = LIRInstructionClass.create(AVXBinaryMemoryOp.class);
 
-        @Opcode private final AMD64VectorAssembler.VexRVMOp opcode;
+        @Opcode private final VexRVMOp opcode;
         private final AVXKind.AVXSize size;
 
         @Def({REG}) protected AllocatableValue result;
@@ -109,7 +113,7 @@
         @Use({COMPOSITE}) protected AMD64AddressValue y;
         @State protected LIRFrameState state;
 
-        public AVXBinaryMemoryOp(AMD64VectorAssembler.VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AMD64AddressValue y, LIRFrameState state) {
+        public AVXBinaryMemoryOp(VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AMD64AddressValue y, LIRFrameState state) {
             super(TYPE);
             this.opcode = opcode;
             this.size = size;
@@ -120,11 +124,11 @@
         }
 
         @Override
-        public void emitCode(CompilationResultBuilder crb, AMD64VectorAssembler vasm) {
+        public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
             if (state != null) {
-                crb.recordImplicitException(vasm.position(), state);
+                crb.recordImplicitException(masm.position(), state);
             }
-            opcode.emit(vasm, size, asRegister(result), asRegister(x), y.toAddress());
+            opcode.emit(masm, size, asRegister(result), asRegister(x), y.toAddress());
         }
     }
 }