/*

 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "memory/allocation.inline.hpp"

#include "opto/block.hpp"

#include "opto/c2compiler.hpp"

#include "opto/callnode.hpp"

#include "opto/cfgnode.hpp"

#include "opto/machnode.hpp"

#include "opto/runtime.hpp"

#ifdef TARGET_ARCH_MODEL_x86_32

# include "adfiles/ad_x86_32.hpp"

#endif

#ifdef TARGET_ARCH_MODEL_x86_64

# include "adfiles/ad_x86_64.hpp"

#endif

#ifdef TARGET_ARCH_MODEL_sparc

# include "adfiles/ad_sparc.hpp"

#endif

#ifdef TARGET_ARCH_MODEL_zero

# include "adfiles/ad_zero.hpp"

#endif

#ifdef TARGET_ARCH_MODEL_arm

# include "adfiles/ad_arm.hpp"

#endif

#ifdef TARGET_ARCH_MODEL_ppc

# include "adfiles/ad_ppc.hpp"

#endif

// Optimization - Graph Style

//------------------------------implicit_null_check----------------------------

// Detect implicit-null-check opportunities.  Basically, find NULL checks

// with suitable memory ops nearby.  Use the memory op to do the NULL check.

// I can generate a memory op if there is not one nearby.

// The proj is the control projection for the not-null case.

// The val is the pointer being checked for nullness or

// decodeHeapOop_not_null node if it did not fold into address.

void Block::implicit_null_check(PhaseCFG *cfg, Node *proj, Node *val, int allowed_reasons) {

  // Assume if null check need for 0 offset then always needed

  // Intel solaris doesn't support any null checks yet and no

  // mechanism exists (yet) to set the switches at an os_cpu level

  if( !ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(0)) return;

  // Make sure the ptr-is-null path appears to be uncommon!

  float f = end()->as_MachIf()->_prob;

  if( proj->Opcode() == Op_IfTrue ) f = 1.0f - f;

  if( f > PROB_UNLIKELY_MAG(4) ) return;

  uint bidx = 0;                // Capture index of value into memop

  bool was_store;               // Memory op is a store op

  // Get the successor block for if the test ptr is non-null

  Block* not_null_block;  // this one goes with the proj

  Block* null_block;

  if (_nodes[_nodes.size()-1] == proj) {

    null_block     = _succs[0];

    not_null_block = _succs[1];

  } else {

    assert(_nodes[_nodes.size()-2] == proj, "proj is one or the other");

    not_null_block = _succs[0];

    null_block     = _succs[1];

  }

  while (null_block->is_Empty() == Block::empty_with_goto) {

    null_block     = null_block->_succs[0];

  }

  // Search the exception block for an uncommon trap.

  // (See Parse::do_if and Parse::do_ifnull for the reason

  // we need an uncommon trap.  Briefly, we need a way to

  // detect failure of this optimization, as in 6366351.)

  {

    bool found_trap = false;

    for (uint i1 = 0; i1 < null_block->_nodes.size(); i1++) {

      Node* nn = null_block->_nodes[i1];

      if (nn->is_MachCall() &&

          nn->as_MachCall()->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {

        const Type* trtype = nn->in(TypeFunc::Parms)->bottom_type();

        if (trtype->isa_int() && trtype->is_int()->is_con()) {

          jint tr_con = trtype->is_int()->get_con();

          Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);

          Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);

          assert((int)reason < (int)BitsPerInt, "recode bit map");

          if (is_set_nth_bit(allowed_reasons, (int) reason)

              && action != Deoptimization::Action_none) {

            // This uncommon trap is sure to recompile, eventually.

            // When that happens, C->too_many_traps will prevent

            // this transformation from happening again.

            found_trap = true;

          }

        }

        break;

      }

    }

    if (!found_trap) {

      // We did not find an uncommon trap.

      return;

    }

  }

  // Check for decodeHeapOop_not_null node which did not fold into address

  bool is_decoden = ((intptr_t)val) & 1;

  val = (Node*)(((intptr_t)val) & ~1);

  assert(!is_decoden || (val->in(0) == NULL) && val->is_Mach() &&

         (val->as_Mach()->ideal_Opcode() == Op_DecodeN), "sanity");

  // Search the successor block for a load or store who's base value is also

  // the tested value.  There may be several.

  Node_List *out = new Node_List(Thread::current()->resource_area());

  MachNode *best = NULL;        // Best found so far

  for (DUIterator i = val->outs(); val->has_out(i); i++) {

    Node *m = val->out(i);

    if( !m->is_Mach() ) continue;

    MachNode *mach = m->as_Mach();

    was_store = false;

    int iop = mach->ideal_Opcode();

    switch( iop ) {

    case Op_LoadB:

    case Op_LoadUB:

    case Op_LoadUS:

    case Op_LoadD:

    case Op_LoadF:

    case Op_LoadI:

    case Op_LoadL:

    case Op_LoadP:

    case Op_LoadN:

    case Op_LoadS:

    case Op_LoadKlass:

    case Op_LoadNKlass:

    case Op_LoadRange:

    case Op_LoadD_unaligned:

    case Op_LoadL_unaligned:

      assert(mach->in(2) == val, "should be address");

      break;

    case Op_StoreB:

    case Op_StoreC:

    case Op_StoreCM:

    case Op_StoreD:

    case Op_StoreF:

    case Op_StoreI:

    case Op_StoreL:

    case Op_StoreP:

    case Op_StoreN:

    case Op_StoreNKlass:

      was_store = true;         // Memory op is a store op

      // Stores will have their address in slot 2 (memory in slot 1).

      // If the value being nul-checked is in another slot, it means we

      // are storing the checked value, which does NOT check the value!

      if( mach->in(2) != val ) continue;

      break;                    // Found a memory op?

    case Op_StrComp:

    case Op_StrEquals:

    case Op_StrIndexOf:

    case Op_AryEq:

      // Not a legit memory op for implicit null check regardless of

      // embedded loads

      continue;

    default:                    // Also check for embedded loads

      if( !mach->needs_anti_dependence_check() )

        continue;               // Not an memory op; skip it

      if( must_clone[iop] ) {

        // Do not move nodes which produce flags because

        // RA will try to clone it to place near branch and

        // it will cause recompilation, see clone_node().

        continue;

      }

      {

        // Check that value is used in memory address in

        // instructions with embedded load (CmpP val1,(val2+off)).

        Node* base;

        Node* index;

        const MachOper* oper = mach->memory_inputs(base, index);

        if (oper == NULL || oper == (MachOper*)-1) {

          continue;             // Not an memory op; skip it

        }

        if (val == base ||

            val == index && val->bottom_type()->isa_narrowoop()) {

          break;                // Found it

        } else {

          continue;             // Skip it

        }

      }

      break;

    }

    // check if the offset is not too high for implicit exception

    {

      intptr_t offset = 0;

      const TypePtr *adr_type = NULL;  // Do not need this return value here

      const Node* base = mach->get_base_and_disp(offset, adr_type);

      if (base == NULL || base == NodeSentinel) {

        // Narrow oop address doesn't have base, only index

        if( val->bottom_type()->isa_narrowoop() &&

            MacroAssembler::needs_explicit_null_check(offset) )

          continue;             // Give up if offset is beyond page size

        // cannot reason about it; is probably not implicit null exception

      } else {

        const TypePtr* tptr;

        if (UseCompressedOops && Universe::narrow_oop_shift() == 0) {

          // 32-bits narrow oop can be the base of address expressions

          tptr = base->bottom_type()->make_ptr();

        } else {

          // only regular oops are expected here

          tptr = base->bottom_type()->is_ptr();

        }

        // Give up if offset is not a compile-time constant

        if( offset == Type::OffsetBot || tptr->_offset == Type::OffsetBot )

          continue;

        offset += tptr->_offset; // correct if base is offseted

        if( MacroAssembler::needs_explicit_null_check(offset) )

          continue;             // Give up is reference is beyond 4K page size

      }

    }

    // Check ctrl input to see if the null-check dominates the memory op

    Block *cb = cfg->_bbs[mach->_idx];

    cb = cb->_idom;             // Always hoist at least 1 block

    if( !was_store ) {          // Stores can be hoisted only one block

      while( cb->_dom_depth > (_dom_depth + 1))

        cb = cb->_idom;         // Hoist loads as far as we want

      // The non-null-block should dominate the memory op, too. Live

      // range spilling will insert a spill in the non-null-block if it is

      // needs to spill the memory op for an implicit null check.

      if (cb->_dom_depth == (_dom_depth + 1)) {

        if (cb != not_null_block) continue;

        cb = cb->_idom;

      }

    }

    if( cb != this ) continue;

    // Found a memory user; see if it can be hoisted to check-block

    uint vidx = 0;              // Capture index of value into memop

    uint j;

    for( j = mach->req()-1; j > 0; j-- ) {

      if( mach->in(j) == val ) {

        vidx = j;

        // Ignore DecodeN val which could be hoisted to where needed.

        if( is_decoden ) continue;

      }

      // Block of memory-op input

      Block *inb = cfg->_bbs[mach->in(j)->_idx];

      Block *b = this;          // Start from nul check

      while( b != inb && b->_dom_depth > inb->_dom_depth )

        b = b->_idom;           // search upwards for input

      // See if input dominates null check

      if( b != inb )

        break;

    }

    if( j > 0 )

      continue;

    Block *mb = cfg->_bbs[mach->_idx];

    // Hoisting stores requires more checks for the anti-dependence case.

    // Give up hoisting if we have to move the store past any load.

    if( was_store ) {

      Block *b = mb;            // Start searching here for a local load

      // mach use (faulting) trying to hoist

      // n might be blocker to hoisting

      while( b != this ) {

        uint k;

        for( k = 1; k < b->_nodes.size(); k++ ) {

          Node *n = b->_nodes[k];

          if( n->needs_anti_dependence_check() &&

              n->in(LoadNode::Memory) == mach->in(StoreNode::Memory) )

            break;              // Found anti-dependent load

        }

        if( k < b->_nodes.size() )

          break;                // Found anti-dependent load

        // Make sure control does not do a merge (would have to check allpaths)

        if( b->num_preds() != 2 ) break;

        b = cfg->_bbs[b->pred(1)->_idx]; // Move up to predecessor block

      }

      if( b != this ) continue;

    }

    // Make sure this memory op is not already being used for a NullCheck

    Node *e = mb->end();

    if( e->is_MachNullCheck() && e->in(1) == mach )

      continue;                 // Already being used as a NULL check

    // Found a candidate!  Pick one with least dom depth - the highest

    // in the dom tree should be closest to the null check.

    if( !best ||

        cfg->_bbs[mach->_idx]->_dom_depth < cfg->_bbs[best->_idx]->_dom_depth ) {

      best = mach;

      bidx = vidx;

    }

  }

  // No candidate!

  if( !best ) return;

  // ---- Found an implicit null check

  extern int implicit_null_checks;

  implicit_null_checks++;

  if( is_decoden ) {

    // Check if we need to hoist decodeHeapOop_not_null first.

    Block *valb = cfg->_bbs[val->_idx];

    if( this != valb && this->_dom_depth < valb->_dom_depth ) {

      // Hoist it up to the end of the test block.

      valb->find_remove(val);

      this->add_inst(val);

      cfg->_bbs.map(val->_idx,this);

      // DecodeN on x86 may kill flags. Check for flag-killing projections

      // that also need to be hoisted.

      for (DUIterator_Fast jmax, j = val->fast_outs(jmax); j < jmax; j++) {

        Node* n = val->fast_out(j);

        if( n->is_MachProj() ) {

          cfg->_bbs[n->_idx]->find_remove(n);

          this->add_inst(n);

          cfg->_bbs.map(n->_idx,this);

        }

      }

    }

  }

  // Hoist the memory candidate up to the end of the test block.

  Block *old_block = cfg->_bbs[best->_idx];

  old_block->find_remove(best);

  add_inst(best);

  cfg->_bbs.map(best->_idx,this);

  // Move the control dependence

  if (best->in(0) && best->in(0) == old_block->_nodes[0])

    best->set_req(0, _nodes[0]);

  // Check for flag-killing projections that also need to be hoisted

  // Should be DU safe because no edge updates.

  for (DUIterator_Fast jmax, j = best->fast_outs(jmax); j < jmax; j++) {

    Node* n = best->fast_out(j);

    if( n->is_MachProj() ) {

      cfg->_bbs[n->_idx]->find_remove(n);

      add_inst(n);

      cfg->_bbs.map(n->_idx,this);

    }

  }

  Compile *C = cfg->C;

  // proj==Op_True --> ne test; proj==Op_False --> eq test.

  // One of two graph shapes got matched:

  //   (IfTrue  (If (Bool NE (CmpP ptr NULL))))

  //   (IfFalse (If (Bool EQ (CmpP ptr NULL))))

  // NULL checks are always branch-if-eq.  If we see a IfTrue projection

  // then we are replacing a 'ne' test with a 'eq' NULL check test.

  // We need to flip the projections to keep the same semantics.

  if( proj->Opcode() == Op_IfTrue ) {

    // Swap order of projections in basic block to swap branch targets

    Node *tmp1 = _nodes[end_idx()+1];

    Node *tmp2 = _nodes[end_idx()+2];

    _nodes.map(end_idx()+1, tmp2);

    _nodes.map(end_idx()+2, tmp1);

    Node *tmp = new (C) Node(C->top()); // Use not NULL input

    tmp1->replace_by(tmp);

    tmp2->replace_by(tmp1);

    tmp->replace_by(tmp2);

    tmp->destruct();

  }

  // Remove the existing null check; use a new implicit null check instead.

  // Since schedule-local needs precise def-use info, we need to correct

  // it as well.

  Node *old_tst = proj->in(0);

  MachNode *nul_chk = new (C) MachNullCheckNode(old_tst->in(0),best,bidx);

  _nodes.map(end_idx(),nul_chk);

  cfg->_bbs.map(nul_chk->_idx,this);

  // Redirect users of old_test to nul_chk

  for (DUIterator_Last i2min, i2 = old_tst->last_outs(i2min); i2 >= i2min; --i2)

    old_tst->last_out(i2)->set_req(0, nul_chk);

  // Clean-up any dead code

  for (uint i3 = 0; i3 < old_tst->req(); i3++)

    old_tst->set_req(i3, NULL);

  cfg->latency_from_uses(nul_chk);

  cfg->latency_from_uses(best);

}

//------------------------------select-----------------------------------------

// Select a nice fellow from the worklist to schedule next. If there is only

// one choice, then use it. Projections take top priority for correctness

// reasons - if I see a projection, then it is next.  There are a number of

// other special cases, for instructions that consume condition codes, et al.

// These are chosen immediately. Some instructions are required to immediately

// precede the last instruction in the block, and these are taken last. Of the

// remaining cases (most), choose the instruction with the greatest latency

// (that is, the most number of pseudo-cycles required to the end of the

// routine). If there is a tie, choose the instruction with the most inputs.

Node *Block::select(PhaseCFG *cfg, Node_List &worklist, GrowableArray<int> &ready_cnt, VectorSet &next_call, uint sched_slot) {

  // If only a single entry on the stack, use it

  uint cnt = worklist.size();

  if (cnt == 1) {

    Node *n = worklist[0];

    worklist.map(0,worklist.pop());

    return n;

  }

  uint choice  = 0; // Bigger is most important

  uint latency = 0; // Bigger is scheduled first

  uint score   = 0; // Bigger is better

  int idx = -1;     // Index in worklist

  for( uint i=0; i<cnt; i++ ) { // Inspect entire worklist

    // Order in worklist is used to break ties.

    // See caller for how this is used to delay scheduling

    // of induction variable increments to after the other

    // uses of the phi are scheduled.

    Node *n = worklist[i];      // Get Node on worklist

    int iop = n->is_Mach() ? n->as_Mach()->ideal_Opcode() : 0;

    if( n->is_Proj() ||         // Projections always win

        n->Opcode()== Op_Con || // So does constant 'Top'

        iop == Op_CreateEx ||   // Create-exception must start block

        iop == Op_CheckCastPP

        ) {

      worklist.map(i,worklist.pop());

      return n;

    }

    // Final call in a block must be adjacent to 'catch'

    Node *e = end();

    if( e->is_Catch() && e->in(0)->in(0) == n )

      continue;

    // Memory op for an implicit null check has to be at the end of the block

    if( e->is_MachNullCheck() && e->in(1) == n )

      continue;

    // Schedule IV increment last.

    if (e->is_Mach() && e->as_Mach()->ideal_Opcode() == Op_CountedLoopEnd &&

        e->in(1)->in(1) == n && n->is_iteratively_computed())

      continue;

    uint n_choice  = 2;

    // See if this instruction is consumed by a branch. If so, then (as the

    // branch is the last instruction in the basic block) force it to the

    // end of the basic block

    if ( must_clone[iop] ) {

      // See if any use is a branch

      bool found_machif = false;

      for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {

        Node* use = n->fast_out(j);

        // The use is a conditional branch, make them adjacent

        if (use->is_MachIf() && cfg->_bbs[use->_idx]==this ) {

          found_machif = true;

          break;

        }

        // More than this instruction pending for successor to be ready,

        // don't choose this if other opportunities are ready

        if (ready_cnt.at(use->_idx) > 1)

          n_choice = 1;

      }

      // loop terminated, prefer not to use this instruction

      if (found_machif)

        continue;

    }

    // See if this has a predecessor that is "must_clone", i.e. sets the

    // condition code. If so, choose this first

    for (uint j = 0; j < n->req() ; j++) {

      Node *inn = n->in(j);

      if (inn) {

        if (inn->is_Mach() && must_clone[inn->as_Mach()->ideal_Opcode()] ) {

          n_choice = 3;

          break;

        }

      }

    }

    // MachTemps should be scheduled last so they are near their uses

    if (n->is_MachTemp()) {

      n_choice = 1;

    }

    uint n_latency = cfg->_node_latency->at_grow(n->_idx);

    uint n_score   = n->req();   // Many inputs get high score to break ties

    // Keep best latency found

    if( choice < n_choice ||

        ( choice == n_choice &&

          ( latency < n_latency ||

            ( latency == n_latency &&

              ( score < n_score ))))) {

      choice  = n_choice;

      latency = n_latency;

      score   = n_score;

      idx     = i;               // Also keep index in worklist

    }

  } // End of for all ready nodes in worklist