8160245: C1: Clean up platform #defines in c1_LIR.hpp.
Summary: Also add fnoreg on x86, LIR_Address constructor without scale, clean up templateInterpreterGenerator.hpp and remove PPC32 special cases.
Reviewed-by: coleenp, thartmann
--- a/hotspot/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -808,7 +808,6 @@
} else {
a = new LIR_Address(obj.result(),
offset.result(),
- LIR_Address::times_1,
0,
as_BasicType(type));
}
@@ -1002,7 +1001,6 @@
LIR_Address* a = new LIR_Address(base_op,
index,
- LIR_Address::times_1,
offset,
T_BYTE);
BasicTypeList signature(3);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/aarch64/vm/c1_LIR_aarch64.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+#include "asm/register.hpp"
+#include "c1/c1_LIR.hpp"
+
+FloatRegister LIR_OprDesc::as_float_reg() const {
+ return as_FloatRegister(fpu_regnr());
+}
+
+FloatRegister LIR_OprDesc::as_double_reg() const {
+ return as_FloatRegister(fpu_regnrLo());
+}
+
+// Reg2 unused.
+LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
+ assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
+ return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+ (reg1 << LIR_OprDesc::reg2_shift) |
+ LIR_OprDesc::double_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::double_size);
+}
+
+#ifndef PRODUCT
+void LIR_Address::verify() const {
+ assert(base()->is_cpu_register(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
+ "wrong type for addresses");
+}
+#endif // PRODUCT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/ppc/vm/c1_LIR_ppc.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016 SAP SE. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+#include "asm/register.hpp"
+#include "c1/c1_LIR.hpp"
+
+FloatRegister LIR_OprDesc::as_float_reg() const {
+ return as_FloatRegister(fpu_regnr());
+}
+
+FloatRegister LIR_OprDesc::as_double_reg() const {
+ return as_FloatRegister(fpu_regnrLo());
+}
+
+// Reg2 unused.
+LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
+ assert(!as_FloatRegister(reg2)->is_valid(), "Not used on this platform");
+ return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+ (reg1 << LIR_OprDesc::reg2_shift) |
+ LIR_OprDesc::double_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::double_size);
+}
+
+#ifndef PRODUCT
+void LIR_Address::verify() const {
+ assert(scale() == times_1, "Scaled addressing mode not available on PPC and should not be used");
+ assert(disp() == 0 || index()->is_illegal(), "can't have both");
+#ifdef _LP64
+ assert(base()->is_cpu_register(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
+ "wrong type for addresses");
+#else
+ assert(base()->is_single_cpu(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
+ "wrong type for addresses");
+#endif
+}
+#endif // PRODUCT
--- a/hotspot/src/cpu/ppc/vm/register_ppc.hpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/cpu/ppc/vm/register_ppc.hpp Thu Jun 23 22:33:46 2016 +0200
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -76,7 +76,7 @@
typedef RegisterImpl* Register;
inline Register as_Register(int encoding) {
- assert(encoding >= 0 && encoding < 32, "bad register encoding");
+ assert(encoding >= -1 && encoding < 32, "bad register encoding");
return (Register)(intptr_t)encoding;
}
@@ -91,7 +91,7 @@
inline friend Register as_Register(int encoding);
// accessors
- int encoding() const { assert(is_valid(), "invalid register"); return value(); }
+ int encoding() const { assert(is_valid(), "invalid register"); return value(); }
inline VMReg as_VMReg();
Register successor() const { return as_Register(encoding() + 1); }
@@ -247,7 +247,7 @@
typedef FloatRegisterImpl* FloatRegister;
inline FloatRegister as_FloatRegister(int encoding) {
- assert(encoding >= 0 && encoding < 32, "bad float register encoding");
+ assert(encoding >= -1 && encoding < 32, "bad float register encoding");
return (FloatRegister)(intptr_t)encoding;
}
@@ -267,7 +267,7 @@
FloatRegister successor() const { return as_FloatRegister(encoding() + 1); }
// testers
- bool is_valid() const { return (0 <= value() && value() < number_of_registers); }
+ bool is_valid() const { return (0 <= value() && value() < number_of_registers); }
const char* name() const;
};
--- a/hotspot/src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/cpu/ppc/vm/templateInterpreterGenerator_ppc.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -881,10 +881,6 @@
BLOCK_COMMENT("} stack_overflow_check_with_compare");
}
-void TemplateInterpreterGenerator::unlock_method(bool check_exceptions) {
- __ unlock_object(R26_monitor, check_exceptions);
-}
-
// Lock the current method, interpreter register window must be set up!
void TemplateInterpreterGenerator::lock_method(Register Rflags, Register Rscratch1, Register Rscratch2, bool flags_preloaded) {
const Register Robj_to_lock = Rscratch2;
@@ -1566,7 +1562,7 @@
if (synchronized) {
// Don't check for exceptions since we're still in the i2n frame. Do that
// manually afterwards.
- unlock_method(false);
+ __ unlock_object(R26_monitor, false); // Can also unlock methods.
}
// Reset active handles after returning from native.
@@ -1609,7 +1605,7 @@
if (synchronized) {
// Don't check for exceptions since we're still in the i2n frame. Do that
// manually afterwards.
- unlock_method(false);
+ __ unlock_object(R26_monitor, false); // Can also unlock methods.
}
BIND(exception_return_sync_check_already_unlocked);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/sparc/vm/c1_LIR_sparc.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+#include "asm/register.hpp"
+#include "c1/c1_FrameMap.hpp"
+#include "c1/c1_LIR.hpp"
+
+FloatRegister LIR_OprDesc::as_float_reg() const {
+ return FrameMap::nr2floatreg(fpu_regnr());
+}
+
+FloatRegister LIR_OprDesc::as_double_reg() const {
+ return FrameMap::nr2floatreg(fpu_regnrHi());
+}
+
+LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
+ assert(as_FloatRegister(reg2) != fnoreg, "Sparc holds double in two regs.");
+ return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+ (reg2 << LIR_OprDesc::reg2_shift) |
+ LIR_OprDesc::double_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::double_size);
+}
+
+#ifndef PRODUCT
+void LIR_Address::verify() const {
+ assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used");
+ assert(disp() == 0 || index()->is_illegal(), "can't have both");
+#ifdef _LP64
+ assert(base()->is_cpu_register(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
+ "wrong type for addresses");
+#else
+ assert(base()->is_single_cpu(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
+ "wrong type for addresses");
+#endif
+}
+#endif // PRODUCT
--- a/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -761,7 +761,6 @@
} else {
a = new LIR_Address(obj.result(),
offset.result(),
- LIR_Address::times_1,
0,
as_BasicType(type));
}
@@ -1081,7 +1080,6 @@
LIR_Address* a = new LIR_Address(base_op,
index,
- LIR_Address::times_1,
offset,
T_BYTE);
BasicTypeList signature(3);
@@ -1157,13 +1155,11 @@
LIR_Address* addr_a = new LIR_Address(result_a,
result_aOffset,
- LIR_Address::times_1,
constant_aOffset,
T_BYTE);
LIR_Address* addr_b = new LIR_Address(result_b,
result_bOffset,
- LIR_Address::times_1,
constant_bOffset,
T_BYTE);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/hotspot/src/cpu/x86/vm/c1_LIR_x86.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ *
+ */
+
+#include "precompiled.hpp"
+#include "asm/register.hpp"
+#include "c1/c1_FrameMap.hpp"
+#include "c1/c1_LIR.hpp"
+
+
+FloatRegister LIR_OprDesc::as_float_reg() const {
+ ShouldNotReachHere();
+ return fnoreg;
+}
+
+FloatRegister LIR_OprDesc::as_double_reg() const {
+ ShouldNotReachHere();
+ return fnoreg;
+}
+
+XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
+ return FrameMap::nr2xmmreg(xmm_regnr());
+}
+
+XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
+ assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
+ return FrameMap::nr2xmmreg(xmm_regnrLo());
+}
+
+// Reg2 unused.
+LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {
+ assert(as_FloatRegister(reg2) == fnoreg, "Not used on this platform");
+ return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+ (reg1 << LIR_OprDesc::reg2_shift) |
+ LIR_OprDesc::double_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::double_size);
+}
+
+#ifndef PRODUCT
+void LIR_Address::verify() const {
+#ifdef _LP64
+ assert(base()->is_cpu_register(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
+ "wrong type for addresses");
+#else
+ assert(base()->is_single_cpu(), "wrong base operand");
+ assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
+ assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
+ "wrong type for addresses");
+#endif
+}
+#endif // PRODUCT
--- a/hotspot/src/cpu/x86/vm/register_definitions_x86.cpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/cpu/x86/vm/register_definitions_x86.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -50,6 +50,8 @@
REGISTER_DEFINITION(Register, r15);
#endif // AMD64
+REGISTER_DEFINITION(FloatRegister, fnoreg);
+
REGISTER_DEFINITION(XMMRegister, xnoreg);
REGISTER_DEFINITION(XMMRegister, xmm0 );
REGISTER_DEFINITION(XMMRegister, xmm1 );
--- a/hotspot/src/cpu/x86/vm/register_x86.hpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/cpu/x86/vm/register_x86.hpp Thu Jun 23 22:33:46 2016 +0200
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -124,6 +124,8 @@
};
+CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, (-1));
+
// Use XMMRegister as shortcut
class XMMRegisterImpl;
typedef XMMRegisterImpl* XMMRegister;
--- a/hotspot/src/share/vm/c1/c1_Compilation.hpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/share/vm/c1/c1_Compilation.hpp Thu Jun 23 22:33:46 2016 +0200
@@ -194,12 +194,7 @@
const char* bailout_msg() const { return _bailout_msg; }
static int desired_max_code_buffer_size() {
-#ifndef PPC32
- return (int) NMethodSizeLimit; // default 256K or 512K
-#else
- // conditional branches on PPC are restricted to 16 bit signed
- return MIN2((unsigned int)NMethodSizeLimit,32*K);
-#endif
+ return (int)NMethodSizeLimit; // default 64K
}
static int desired_max_constant_size() {
return desired_max_code_buffer_size() / 10;
--- a/hotspot/src/share/vm/c1/c1_LIR.cpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/share/vm/c1/c1_LIR.cpp Thu Jun 23 22:33:46 2016 +0200
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -42,44 +42,6 @@
return FrameMap::cpu_rnr2reg(cpu_regnrHi());
}
-#if defined(X86)
-
-XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
- return FrameMap::nr2xmmreg(xmm_regnr());
-}
-
-XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
- assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
- return FrameMap::nr2xmmreg(xmm_regnrLo());
-}
-
-#endif // X86
-
-#if defined(SPARC) || defined(PPC32)
-
-FloatRegister LIR_OprDesc::as_float_reg() const {
- return FrameMap::nr2floatreg(fpu_regnr());
-}
-
-FloatRegister LIR_OprDesc::as_double_reg() const {
- return FrameMap::nr2floatreg(fpu_regnrHi());
-}
-
-#endif
-
-#if defined(ARM) || defined(AARCH64) || defined(PPC64)
-
-FloatRegister LIR_OprDesc::as_float_reg() const {
- return as_FloatRegister(fpu_regnr());
-}
-
-FloatRegister LIR_OprDesc::as_double_reg() const {
- return as_FloatRegister(fpu_regnrLo());
-}
-
-#endif
-
-
LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
LIR_Opr LIR_OprFact::value_type(ValueType* type) {
@@ -140,32 +102,6 @@
return LIR_Address::times_1;
}
-
-#ifndef PRODUCT
-void LIR_Address::verify0() const {
-#if defined(SPARC) || defined(PPC)
- assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
- assert(disp() == 0 || index()->is_illegal(), "can't have both");
-#endif
-#ifdef _LP64
- assert(base()->is_cpu_register(), "wrong base operand");
-#ifndef AARCH64
- assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
-#else
- assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
-#endif
- assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
- "wrong type for addresses");
-#else
- assert(base()->is_single_cpu(), "wrong base operand");
- assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
- assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
- "wrong type for addresses");
-#endif
-}
-#endif
-
-
//---------------------------------------------------
char LIR_OprDesc::type_char(BasicType t) {
--- a/hotspot/src/share/vm/c1/c1_LIR.hpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/share/vm/c1/c1_LIR.hpp Thu Jun 23 22:33:46 2016 +0200
@@ -28,6 +28,7 @@
#include "c1/c1_Defs.hpp"
#include "c1/c1_ValueType.hpp"
#include "oops/method.hpp"
+#include "utilities/globalDefinitions.hpp"
class BlockBegin;
class BlockList;
@@ -438,15 +439,13 @@
return as_register();
}
+ FloatRegister as_float_reg () const;
+ FloatRegister as_double_reg () const;
#ifdef X86
- XMMRegister as_xmm_float_reg() const;
+ XMMRegister as_xmm_float_reg () const;
XMMRegister as_xmm_double_reg() const;
// for compatibility with RInfo
- int fpu () const { return lo_reg_half(); }
-#endif
-#if defined(SPARC) || defined(ARM) || defined(PPC) || defined(AARCH64)
- FloatRegister as_float_reg () const;
- FloatRegister as_double_reg () const;
+ int fpu() const { return lo_reg_half(); }
#endif
jint as_jint() const { return as_constant_ptr()->as_jint(); }
@@ -534,14 +533,19 @@
, _type(type)
, _disp(0) { verify(); }
-#if defined(X86) || defined(ARM) || defined(AARCH64)
+ LIR_Address(LIR_Opr base, LIR_Opr index, intx disp, BasicType type):
+ _base(base)
+ , _index(index)
+ , _scale(times_1)
+ , _type(type)
+ , _disp(disp) { verify(); }
+
LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
_base(base)
, _index(index)
, _scale(scale)
, _type(type)
, _disp(disp) { verify(); }
-#endif // X86 || ARM
LIR_Opr base() const { return _base; }
LIR_Opr index() const { return _index; }
@@ -554,13 +558,7 @@
virtual BasicType type() const { return _type; }
virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
- void verify0() const PRODUCT_RETURN;
-#if defined(LIR_ADDRESS_PD_VERIFY) && !defined(PRODUCT)
- void pd_verify() const;
- void verify() const { pd_verify(); }
-#else
- void verify() const { verify0(); }
-#endif
+ void verify() const PRODUCT_RETURN;
static Scale scale(BasicType type);
};
@@ -605,59 +603,49 @@
LIR_OprDesc::double_size);
}
- static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- LIR_OprDesc::float_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::single_size); }
-#if defined(ARM32)
- static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::fpu_register | LIR_OprDesc::double_size); }
- static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) | LIR_OprDesc::float_type | LIR_OprDesc::cpu_register | LIR_OprDesc::single_size); }
- static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg1 << LIR_OprDesc::reg1_shift) | (reg2 << LIR_OprDesc::reg2_shift) | LIR_OprDesc::double_type | LIR_OprDesc::cpu_register | LIR_OprDesc::double_size); }
-#endif
-#ifdef SPARC
- static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
- (reg2 << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size); }
-#endif
-#if defined(X86) || defined(AARCH64)
- static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- (reg << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size); }
+ static LIR_Opr single_fpu(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ LIR_OprDesc::float_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::single_size);
+ }
+
+ // Platform dependant.
+ static LIR_Opr double_fpu(int reg1, int reg2 = -1 /*fnoreg*/);
- static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- LIR_OprDesc::float_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::single_size |
- LIR_OprDesc::is_xmm_mask); }
- static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- (reg << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size |
- LIR_OprDesc::is_xmm_mask); }
+#ifdef __SOFTFP__
+ static LIR_Opr single_softfp(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ LIR_OprDesc::float_type |
+ LIR_OprDesc::cpu_register |
+ LIR_OprDesc::single_size);
+ }
+ static LIR_Opr double_softfp(int reg1, int reg2) {
+ return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
+ (reg2 << LIR_OprDesc::reg2_shift) |
+ LIR_OprDesc::double_type |
+ LIR_OprDesc::cpu_register |
+ LIR_OprDesc::double_size);
+ }
+#endif // __SOFTFP__
+
+#if defined(X86)
+ static LIR_Opr single_xmm(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ LIR_OprDesc::float_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::single_size |
+ LIR_OprDesc::is_xmm_mask);
+ }
+ static LIR_Opr double_xmm(int reg) {
+ return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
+ (reg << LIR_OprDesc::reg2_shift) |
+ LIR_OprDesc::double_type |
+ LIR_OprDesc::fpu_register |
+ LIR_OprDesc::double_size |
+ LIR_OprDesc::is_xmm_mask);
+ }
#endif // X86
-#if defined(PPC)
- static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
- (reg << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::fpu_register |
- LIR_OprDesc::double_size); }
-#endif
-#ifdef PPC32
- static LIR_Opr single_softfp(int reg) { return (LIR_Opr)((reg << LIR_OprDesc::reg1_shift) |
- LIR_OprDesc::float_type |
- LIR_OprDesc::cpu_register |
- LIR_OprDesc::single_size); }
- static LIR_Opr double_softfp(int reg1, int reg2) { return (LIR_Opr)((reg2 << LIR_OprDesc::reg1_shift) |
- (reg1 << LIR_OprDesc::reg2_shift) |
- LIR_OprDesc::double_type |
- LIR_OprDesc::cpu_register |
- LIR_OprDesc::double_size); }
-#endif // PPC32
static LIR_Opr virtual_register(int index, BasicType type) {
LIR_Opr res;
@@ -1467,37 +1455,15 @@
private:
Bytecodes::Code _bytecode;
ConversionStub* _stub;
-#ifdef PPC32
- LIR_Opr _tmp1;
- LIR_Opr _tmp2;
-#endif
public:
LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
: LIR_Op1(lir_convert, opr, result)
, _stub(stub)
-#ifdef PPC32
- , _tmp1(LIR_OprDesc::illegalOpr())
- , _tmp2(LIR_OprDesc::illegalOpr())
-#endif
, _bytecode(code) {}
-#ifdef PPC32
- LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
- ,LIR_Opr tmp1, LIR_Opr tmp2)
- : LIR_Op1(lir_convert, opr, result)
- , _stub(stub)
- , _tmp1(tmp1)
- , _tmp2(tmp2)
- , _bytecode(code) {}
-#endif
-
Bytecodes::Code bytecode() const { return _bytecode; }
ConversionStub* stub() const { return _stub; }
-#ifdef PPC32
- LIR_Opr tmp1() const { return _tmp1; }
- LIR_Opr tmp2() const { return _tmp2; }
-#endif
virtual void emit_code(LIR_Assembler* masm);
virtual LIR_OpConvert* as_OpConvert() { return this; }
@@ -2136,9 +2102,6 @@
void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); }
-#ifdef PPC32
- void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
-#endif
void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }
void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); }
--- a/hotspot/src/share/vm/interpreter/templateInterpreterGenerator.hpp Thu Jul 14 20:11:55 2016 +0300
+++ b/hotspot/src/share/vm/interpreter/templateInterpreterGenerator.hpp Thu Jun 23 22:33:46 2016 +0200
@@ -101,14 +101,16 @@
address generate_Double_longBitsToDouble_entry();
address generate_Double_doubleToRawLongBits_entry();
#endif // IA32
+ // Some platforms don't need registers, other need two. Unused function is
+ // left unimplemented.
void generate_stack_overflow_check(void);
+ void generate_stack_overflow_check(Register Rframe_size, Register Rscratch);
void generate_counter_incr(Label* overflow, Label* profile_method, Label* profile_method_continue);
void generate_counter_overflow(Label& continue_entry);
void generate_fixed_frame(bool native_call);
#ifdef SPARC
- void generate_stack_overflow_check(Register Rframe_size, Register Rscratch);
void save_native_result(void);
void restore_native_result(void);
#endif // SPARC
@@ -119,10 +121,7 @@
#ifdef PPC
void lock_method(Register Rflags, Register Rscratch1, Register Rscratch2, bool flags_preloaded=false);
- void unlock_method(bool check_exceptions = true);
-
void generate_fixed_frame(bool native_call, Register Rsize_of_parameters, Register Rsize_of_locals);
- void generate_stack_overflow_check(Register Rframe_size, Register Rscratch1);
#endif // PPC
public: