1 /*

     2  * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

    20  * or visit www.oracle.com if you need additional information or have any

    21  * questions.

    22  *

    23  */

    24 

    25 #include "precompiled.hpp"

    26 #include "asm/register.hpp"

    27 #include "c1/c1_FrameMap.hpp"

    28 #include "c1/c1_LIR.hpp"

    29 

    30 FloatRegister LIR_OprDesc::as_float_reg() const {

    31   return FrameMap::nr2floatreg(fpu_regnr());

    32 }

    33 

    34 FloatRegister LIR_OprDesc::as_double_reg() const {

    35   return FrameMap::nr2floatreg(fpu_regnrHi());

    36 }

    37 

    38 LIR_Opr LIR_OprFact::double_fpu(int reg1, int reg2) {

    39   assert(as_FloatRegister(reg2) != fnoreg, "Sparc holds double in two regs.");

    40   return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |

    41                              (reg2 << LIR_OprDesc::reg2_shift) |

    42                              LIR_OprDesc::double_type          |

    43                              LIR_OprDesc::fpu_register         |

    44                              LIR_OprDesc::double_size);

    45 }

    46 

    47 #ifndef PRODUCT

    48 void LIR_Address::verify() const {

    49   assert(scale() == times_1, "Scaled addressing mode not available on SPARC and should not be used");

    50   assert(disp() == 0 || index()->is_illegal(), "can't have both");

    51 #ifdef _LP64

    52   assert(base()->is_cpu_register(), "wrong base operand");

    53   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");

    54   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,

    55          "wrong type for addresses");

    56 #else

    57   assert(base()->is_single_cpu(), "wrong base operand");

    58   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");

    59   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,

    60          "wrong type for addresses");

    61 #endif

    62 }

    63 #endif // PRODUCT