/*

 * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_ARM_ASSEMBLER_ARM_32_HPP

#define CPU_ARM_ASSEMBLER_ARM_32_HPP

// ARM Addressing Mode 1 - Data processing operands

class AsmOperand {

 private:

  int _encoding;

  void initialize_rotated_imm(unsigned int imm);

  void encode(int imm_8) {

    if ((imm_8 >> 8) == 0) {

      _encoding = 1 << 25 | imm_8;  // the most common case

    } else {

      initialize_rotated_imm((unsigned int)imm_8);  // slow case

    }

  }

  void encode(Register rm, AsmShift shift, int shift_imm) {

    assert((shift_imm >> 5) == 0, "encoding constraint");

    _encoding = shift_imm << 7 | shift << 5 | rm->encoding();

  }

 public:

  AsmOperand(Register reg) {

    _encoding = reg->encoding();

  }

  AsmOperand(int imm_8) {

    encode(imm_8);

  }

#ifdef ASSERT

  AsmOperand(ByteSize bytesize_8) {

    const int imm_8 = in_bytes(bytesize_8);

    encode(imm_8);

  }

#endif // ASSERT

  AsmOperand(Register rm, AsmShift shift, int shift_imm) {

    encode(rm,shift,shift_imm);

  }

  AsmOperand(Register rm, AsmShift shift, Register rs) {

    assert(rm != PC && rs != PC, "unpredictable instruction");

    _encoding = rs->encoding() << 8 | shift << 5 | 1 << 4 | rm->encoding();

  }

  AsmOperand(RegisterOrConstant offset, AsmShift shift = lsl, int shift_imm = 0) {

    if (offset.is_register()) {

      encode(offset.as_register(), shift, shift_imm);

    } else {

      assert(shift == lsl,"shift type not yet encoded");

      int imm_8 = ((int)offset.as_constant()) << shift_imm;

      encode(imm_8);

    }

  }

  int encoding() const {

    return _encoding;

  }

  bool is_immediate() const {

    return _encoding & (1 << 25) ? true : false;

  }

  Register base_register() const {

    assert(!is_immediate(), "is_immediate, no base reg");

    return as_Register(_encoding & 15);

  }

  static bool is_rotated_imm(unsigned int imm);

};

// ARM Addressing Mode 4 - Load and store multiple

class RegisterSet {

 private:

  int _encoding;

  RegisterSet(int encoding) {

    _encoding = encoding;

  }

 public:

  RegisterSet(Register reg) {

    _encoding = 1 << reg->encoding();

  }

  RegisterSet() {

    _encoding = 0;

  }

  RegisterSet(Register first, Register last) {

    assert(first < last, "encoding constraint");

    _encoding = (1 << (last->encoding() + 1)) - (1 << first->encoding());

  }

  friend RegisterSet operator | (const RegisterSet set1, const RegisterSet set2) {

    assert((set1._encoding & set2._encoding) == 0,

           "encoding constraint");

    return RegisterSet(set1._encoding | set2._encoding);

  }

  int encoding() const {

    return _encoding;

  }

  bool contains(Register reg) const {

    return (_encoding & (1 << reg->encoding())) != 0;

  }

  // number of registers in the set

  int size() const {

    int count = 0;

    unsigned int remaining = (unsigned int) _encoding;

    while (remaining != 0) {

      if ((remaining & 1) != 0) count++;

      remaining >>= 1;

    }

    return count;

  }

};

#if R9_IS_SCRATCHED

#define R9ifScratched RegisterSet(R9)

#else

#define R9ifScratched RegisterSet()

#endif

// ARM Addressing Mode 5 - Load and store multiple VFP registers

class FloatRegisterSet {

 private:

  int _encoding;

 public:

  FloatRegisterSet(FloatRegister reg) {

    if (reg->hi_bit() == 0) {

      _encoding = reg->hi_bits() << 12 | reg->lo_bit() << 22 | 1;

    } else {

      assert (reg->lo_bit() == 0, "impossible encoding");

      _encoding = reg->hi_bits() << 12 | reg->hi_bit() << 22 | 1;

    }

  }

  FloatRegisterSet(FloatRegister first, int count) {

    assert(count >= 1, "encoding constraint");

    if (first->hi_bit() == 0) {

      _encoding = first->hi_bits() << 12 | first->lo_bit() << 22 | count;

    } else {

      assert (first->lo_bit() == 0, "impossible encoding");

      _encoding = first->hi_bits() << 12 | first->hi_bit() << 22 | count;

    }

  }

  int encoding_s() const {

    return _encoding;

  }

  int encoding_d() const {

    assert((_encoding & 0xFF) <= 16, "no more than 16 double registers" );

    return (_encoding & 0xFFFFFF00) | ((_encoding & 0xFF) << 1);

  }

};

class Assembler : public AbstractAssembler  {

 public:

  static const int LogInstructionSize = 2;

  static const int InstructionSize    = 1 << LogInstructionSize;

  static inline AsmCondition inverse(AsmCondition cond) {

    assert ((cond != al) && (cond != nv), "AL and NV conditions cannot be inversed");

    return (AsmCondition)((int)cond ^ 1);

  }

  // Returns true if given value can be used as immediate in arithmetic (add/sub/cmp/cmn) instructions.

  static inline bool is_arith_imm_in_range(intx value) {

    return AsmOperand::is_rotated_imm(value);

  }

  // Arithmetic instructions

#define F(mnemonic, opcode) \

  void mnemonic(Register rd, Register rn, AsmOperand operand, AsmCondition cond = al) {    \

    emit_int32(cond << 28 | opcode << 21 | rn->encoding() << 16 |                          \

               rd->encoding() << 12 | operand.encoding());                                 \

  }                                                                                        \

  void mnemonic##s(Register rd, Register rn, AsmOperand operand, AsmCondition cond = al) { \

    emit_int32(cond << 28 | opcode << 21 | 1 << 20 | rn->encoding() << 16 |                \

               rd->encoding() << 12 | operand.encoding());                                 \

  }

  F(andr, 0)

  F(eor,  1)

  F(sub,  2)

  F(rsb,  3)

  F(add,  4)

  F(adc,  5)

  F(sbc,  6)

  F(rsc,  7)

  F(orr,  12)

  F(bic,  14)

#undef F

#define F(mnemonic, opcode) \

  void mnemonic(Register rn, AsmOperand operand, AsmCondition cond = al) {  \

    emit_int32(cond << 28 | opcode << 21 | 1 << 20 | rn->encoding() << 16 | \

              operand.encoding());                                          \

  }

  F(tst, 8)

  F(teq, 9)

  F(cmp, 10)

  F(cmn, 11)

#undef F

#define F(mnemonic, opcode) \

  void mnemonic(Register rd, AsmOperand operand, AsmCondition cond = al) {    \

    emit_int32(cond << 28 | opcode << 21 | rd->encoding() << 12 |             \

              operand.encoding());                                            \

  }                                                                           \

  void mnemonic##s(Register rd, AsmOperand operand, AsmCondition cond = al) { \

    emit_int32(cond << 28 | opcode << 21 | 1 << 20 | rd->encoding() << 12 |   \

              operand.encoding());                                            \

  }

  F(mov, 13)

  F(mvn, 15)

#undef F

  void msr(uint fields, AsmOperand operand, AsmCondition cond = al) {

    assert((operand.encoding() & (1<<25)) || ((operand.encoding() & 0xff0) == 0), "invalid addressing mode");

    emit_int32(cond << 28 | 1 << 24 | 1 << 21 | fields << 16 | 0xf << 12 | operand.encoding());

  }

  void mrs(uint fields, Register Rd, AsmCondition cond = al) {

    emit_int32(cond << 28 | 1 << 24 | (fields|0xf) << 16 | (Rd->encoding() << 12));

  }

  enum {

    CPSR = 0x00, CPSR_c = 0x01, CPSR_x = 0x02, CPSR_xc = 0x03,

    CPSR_s = 0x004, CPSR_sc = 0x05, CPSR_sx = 0x06, CPSR_sxc = 0x07,

    CPSR_f = 0x08, CPSR_fc = 0x09, CPSR_fx = 0x0a, CPSR_fxc = 0x0b,

    CPSR_fs = 0x0c, CPSR_fsc = 0x0d, CPSR_fsx = 0x0e, CPSR_fsxc = 0x0f,

    SPSR = 0x40, SPSR_c = 0x41, SPSR_x = 0x42, SPSR_xc = 0x43,

    SPSR_s = 0x44, SPSR_sc = 0x45, SPSR_sx = 0x46, SPSR_sxc = 0x47,

    SPSR_f = 0x48, SPSR_fc = 0x49, SPSR_fx = 0x4a, SPSR_fxc = 0x4b,

    SPSR_fs = 0x4c, SPSR_fsc = 0x4d, SPSR_fsx = 0x4e, SPSR_fsxc = 0x4f

  };

#define F(mnemonic, opcode) \

  void mnemonic(Register rdlo, Register rdhi, Register rm, Register rs,                  \

                AsmCondition cond = al) {                                                \

    emit_int32(cond << 28 | opcode << 21 | rdhi->encoding() << 16 |                      \

              rdlo->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding()); \

  }                                                                                      \

  void mnemonic##s(Register rdlo, Register rdhi, Register rm, Register rs,               \

                   AsmCondition cond = al) {                                             \

    emit_int32(cond << 28 | opcode << 21 | 1 << 20 | rdhi->encoding() << 16 |            \

              rdlo->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding()); \

  }

  F(umull, 4)

  F(umlal, 5)

  F(smull, 6)

  F(smlal, 7)

#undef F

  void mul(Register rd, Register rm, Register rs, AsmCondition cond = al) {

    emit_int32(cond << 28 | rd->encoding() << 16 |

              rs->encoding() << 8 | 0x9 << 4 | rm->encoding());

  }

  void muls(Register rd, Register rm, Register rs, AsmCondition cond = al) {

    emit_int32(cond << 28 | 1 << 20 | rd->encoding() << 16 |

              rs->encoding() << 8 | 0x9 << 4 | rm->encoding());

  }

  void mla(Register rd, Register rm, Register rs, Register rn, AsmCondition cond = al) {

    emit_int32(cond << 28 | 1 << 21 | rd->encoding() << 16 |

              rn->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding());

  }

  void mlas(Register rd, Register rm, Register rs, Register rn, AsmCondition cond = al) {

    emit_int32(cond << 28 | 1 << 21 | 1 << 20 | rd->encoding() << 16 |

              rn->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding());

  }

  // Loads and stores

#define F(mnemonic, l, b) \

  void mnemonic(Register rd, Address addr, AsmCondition cond = al) { \

    emit_int32(cond << 28 | 1 << 26 | b << 22 | l << 20 |            \

              rd->encoding() << 12 | addr.encoding2());              \

  }

  F(ldr,  1, 0)

  F(ldrb, 1, 1)

  F(str,  0, 0)

  F(strb, 0, 1)

#undef F

#undef F

#define F(mnemonic, l, sh, even) \

  void mnemonic(Register rd, Address addr, AsmCondition cond = al) { \

    assert(!even || (rd->encoding() & 1) == 0, "must be even");      \

    emit_int32(cond << 28 | l << 20 | rd->encoding() << 12 |         \

              1 << 7 | sh << 5 | 1 << 4 | addr.encoding3());         \

  }

  F(strh,  0, 1, false)

  F(ldrh,  1, 1, false)

  F(ldrsb, 1, 2, false)

  F(ldrsh, 1, 3, false)

  F(strd,  0, 3, true)

#undef F

  void ldrd(Register rd, Address addr, AsmCondition cond = al) {

    assert((rd->encoding() & 1) == 0, "must be even");

    assert(!addr.index()->is_valid() ||

           (addr.index()->encoding() != rd->encoding() &&

            addr.index()->encoding() != (rd->encoding()+1)), "encoding constraint");

    emit_int32(cond << 28 | rd->encoding() << 12 | 0xD /* 0b1101 */ << 4 | addr.encoding3());

  }

#define F(mnemonic, l, pu) \

  void mnemonic(Register rn, RegisterSet reg_set,                        \

                AsmWriteback w = no_writeback, AsmCondition cond = al) { \

    assert(reg_set.encoding() != 0 && (w == no_writeback ||              \

           (reg_set.encoding() & (1 << rn->encoding())) == 0),           \

           "unpredictable instruction");                                 \

    emit_int32(cond << 28 | 4 << 25 | pu << 23 | w << 21 | l << 20 |     \

              rn->encoding() << 16 | reg_set.encoding());                \

  }

  F(ldmda, 1, 0)    F(ldmfa, 1, 0)

  F(ldmia, 1, 1)    F(ldmfd, 1, 1)

  F(ldmdb, 1, 2)    F(ldmea, 1, 2)

  F(ldmib, 1, 3)    F(ldmed, 1, 3)

  F(stmda, 0, 0)    F(stmed, 0, 0)

  F(stmia, 0, 1)    F(stmea, 0, 1)

  F(stmdb, 0, 2)    F(stmfd, 0, 2)

  F(stmib, 0, 3)    F(stmfa, 0, 3)

#undef F

  void ldrex(Register rd, Address addr, AsmCondition cond = al) {

    assert(rd != PC, "unpredictable instruction");

    emit_int32(cond << 28 | 0x19 << 20 | addr.encoding_ex() |

              rd->encoding()  << 12 | 0xf9f);

  }

  void strex(Register rs, Register rd, Address addr, AsmCondition cond = al) {

    assert(rd != PC && rs != PC &&

           rs != rd && rs != addr.base(), "unpredictable instruction");

    emit_int32(cond << 28 | 0x18 << 20 | addr.encoding_ex() |

              rs->encoding()  << 12 | 0xf90 | rd->encoding());

  }

  void ldrexd(Register rd, Address addr, AsmCondition cond = al) {

    assert(rd != PC, "unpredictable instruction");

    emit_int32(cond << 28 | 0x1B << 20 | addr.encoding_ex() |

              rd->encoding()  << 12 | 0xf9f);

  }

  void strexd(Register rs, Register rd, Address addr, AsmCondition cond = al) {

    assert(rd != PC && rs != PC &&

           rs != rd && rs != addr.base(), "unpredictable instruction");

    emit_int32(cond << 28 | 0x1A << 20 | addr.encoding_ex() |

              rs->encoding()  << 12 | 0xf90 | rd->encoding());

  }

  void clrex() {

    emit_int32(0xF << 28 | 0x57 << 20 | 0xFF  << 12 | 0x01f);

  }

  // Miscellaneous instructions

  void clz(Register rd, Register rm, AsmCondition cond = al) {

    emit_int32(cond << 28 | 0x016f0f10 | rd->encoding() << 12 | rm->encoding());

  }

  void rev(Register rd, Register rm, AsmCondition cond = al) {

    emit_int32(cond << 28 | 0x06bf0f30 | rd->encoding() << 12 | rm->encoding());

  }

  void rev16(Register rd, Register rm, AsmCondition cond = al) {

    emit_int32(cond << 28 | 0x6bf0fb0 | rd->encoding() << 12 | rm->encoding());

  }

  void revsh(Register rd, Register rm, AsmCondition cond = al) {

    emit_int32(cond << 28 | 0x6ff0fb0 | rd->encoding() << 12 | rm->encoding());

  }

  void rbit(Register rd, Register rm, AsmCondition cond = al) {

    emit_int32(cond << 28 | 0x6ff0f30 | rd->encoding() << 12 | rm->encoding());

  }

  void pld(Address addr) {

    emit_int32(0xf550f000 | addr.encoding2());

  }

  void pldw(Address addr) {

    assert(!VM_Version::is_initialized() ||

           (VM_Version::arm_arch() >= 7 && VM_Version::has_multiprocessing_extensions()),

           "PLDW is available on ARMv7 with Multiprocessing Extensions only");

    emit_int32(0xf510f000 | addr.encoding2());

  }

  void svc(int imm_24, AsmCondition cond = al) {

    assert((imm_24 >> 24) == 0, "encoding constraint");

    emit_int32(cond << 28 | 0xf << 24 | imm_24);

  }

  void ubfx(Register rd, Register rn, unsigned int lsb, unsigned int width, AsmCondition cond = al) {

    assert(VM_Version::arm_arch() >= 7, "no ubfx on this processor");

    assert(width > 0, "must be");

    assert(lsb < 32, "must be");

    emit_int32(cond << 28 | 0x3f << 21 | (width - 1)  << 16 | rd->encoding() << 12 |

              lsb << 7 | 0x5 << 4 | rn->encoding());

  }

  void uxtb(Register rd, Register rm, unsigned int rotation = 0, AsmCondition cond = al) {

    assert(VM_Version::arm_arch() >= 7, "no uxtb on this processor");

    assert((rotation % 8) == 0 && (rotation <= 24), "encoding constraint");

    emit_int32(cond << 28 | 0x6e << 20 | 0xf << 16 | rd->encoding() << 12 |

              (rotation >> 3) << 10 | 0x7 << 4 | rm->encoding());

  }

  // ARM Memory Barriers

  //

  // There are two types of memory barriers defined for the ARM processor

  // DataSynchronizationBarrier and DataMemoryBarrier

  //

  // The Linux kernel uses the DataMemoryBarrier for all of it's

  // memory barrier operations (smp_mb, smp_rmb, smp_wmb)

  //

  // There are two forms of each barrier instruction.

  // The mcr forms are supported on armv5 and newer architectures

  //

  // The dmb, dsb instructions were added in armv7

  // architectures and are compatible with their mcr

  // predecessors.

  //

  // Here are the encodings for future reference:

  //

  // DataSynchronizationBarrier (dsb)

  // on ARMv7 - emit_int32(0xF57FF04F)

  //

  // on ARMv5+ - mcr p15, 0, Rtmp, c7, c10, 4  on earlier processors

  //             emit_int32(0xe << 28 | 0xe << 24 | 0x7 << 16 | Rtmp->encoding() << 12  |

  //                       0xf << 8  | 0x9 << 4  | 0xa);

  //

  // DataMemoryBarrier (dmb)

  // on ARMv7 - emit_int32(0xF57FF05F)

  //

  // on ARMv5+ - mcr p15, 0, Rtmp, c7, c10, 5 on earlier processors

  //             emit_int32(0xe << 28 | 0xe << 24 | 0x7 << 16 | Rtmp->encoding() << 12  |

  //                       0xf << 8  | 0xb << 4  | 0xa);

  //

  enum DMB_Opt {

    DMB_all = 0xf,

    DMB_st  = 0xe,

  };

  void dmb(DMB_Opt opt, Register reg) {

    if (VM_Version::arm_arch() >= 7) {

      emit_int32(0xF57FF050 | opt);

    } else if (VM_Version::arm_arch() == 6) {

      bool preserve_tmp = (reg == noreg);

      if(preserve_tmp) {

        reg = Rtemp;

        str(reg, Address(SP, -wordSize, pre_indexed));

      }

      mov(reg, 0);

      // DataMemoryBarrier

      emit_int32(0xe << 28 |

                0xe << 24 |

                0x7 << 16 |

                reg->encoding() << 12  |

                0xf << 8  |

                0xb << 4  |

                0xa);

      if(preserve_tmp) {