author | rraghavan |
Mon, 19 Jun 2017 01:23:58 -0700 | |
changeset 46547 | e1b926a0b23f |
parent 42024 | f3ee61fe224c |
child 46591 | 3f3105af599e |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
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#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
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#include "runtime/globals_extension.hpp" |
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#include "runtime/vm_version.hpp" |
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class VM_Version: public Abstract_VM_Version { |
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friend class VMStructs; |
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friend class JVMCIVMStructs; |
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protected: |
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enum Feature_Flag { |
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v8_instructions = 0, |
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hardware_mul32 = 1, |
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hardware_div32 = 2, |
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hardware_fsmuld = 3, |
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hardware_popc = 4, |
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v9_instructions = 5, |
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vis1_instructions = 6, |
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vis2_instructions = 7, |
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sun4v_instructions = 8, |
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blk_init_instructions = 9, |
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fmaf_instructions = 10, |
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vis3_instructions = 11, |
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cbcond_instructions = 12, |
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sparc64_family = 13, |
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M_family = 14, |
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S_family = 15, |
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T_family = 16, |
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T1_model = 17, |
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sparc5_instructions = 18, |
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aes_instructions = 19, |
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sha1_instruction = 20, |
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sha256_instruction = 21, |
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sha512_instruction = 22, |
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crc32c_instruction = 23 |
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}; |
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enum Feature_Flag_Set { |
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unknown_m = 0, |
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all_features_m = -1, |
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v8_instructions_m = 1 << v8_instructions, |
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hardware_mul32_m = 1 << hardware_mul32, |
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hardware_div32_m = 1 << hardware_div32, |
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hardware_fsmuld_m = 1 << hardware_fsmuld, |
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hardware_popc_m = 1 << hardware_popc, |
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v9_instructions_m = 1 << v9_instructions, |
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vis1_instructions_m = 1 << vis1_instructions, |
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vis2_instructions_m = 1 << vis2_instructions, |
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sun4v_m = 1 << sun4v_instructions, |
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blk_init_instructions_m = 1 << blk_init_instructions, |
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fmaf_instructions_m = 1 << fmaf_instructions, |
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vis3_instructions_m = 1 << vis3_instructions, |
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cbcond_instructions_m = 1 << cbcond_instructions, |
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sparc64_family_m = 1 << sparc64_family, |
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M_family_m = 1 << M_family, |
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S_family_m = 1 << S_family, |
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T_family_m = 1 << T_family, |
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T1_model_m = 1 << T1_model, |
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sparc5_instructions_m = 1 << sparc5_instructions, |
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aes_instructions_m = 1 << aes_instructions, |
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sha1_instruction_m = 1 << sha1_instruction, |
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sha256_instruction_m = 1 << sha256_instruction, |
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sha512_instruction_m = 1 << sha512_instruction, |
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crc32c_instruction_m = 1 << crc32c_instruction, |
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generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, |
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generic_v9_m = generic_v8_m | v9_instructions_m, |
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ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, |
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// Temporary until we have something more accurate |
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niagara1_unique_m = sun4v_m, |
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niagara1_m = generic_v9_m | niagara1_unique_m |
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}; |
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static unsigned int _L2_data_cache_line_size; |
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static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; } |
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static void print_features(); |
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static int determine_features(); |
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static int platform_features(int features); |
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// Returns true if the platform is in the niagara line (T series) |
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static bool is_M_family(int features) { return (features & M_family_m) != 0; } |
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static bool is_S_family(int features) { return (features & S_family_m) != 0; } |
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static bool is_T_family(int features) { return (features & T_family_m) != 0; } |
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static bool is_niagara() { return is_T_family(_features); } |
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#ifdef ASSERT |
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static bool is_niagara(int features) { |
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// 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as |
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// on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'. |
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return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0; |
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} |
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#endif |
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// Returns true if it is niagara1 (T1). |
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static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } |
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static int maximum_niagara1_processor_count() { return 32; } |
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static int parse_features(const char* implementation); |
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public: |
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// Initialization |
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static void initialize(); |
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static void init_before_ergo() { _features = determine_features(); } |
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// Instruction support |
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static bool has_v8() { return (_features & v8_instructions_m) != 0; } |
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static bool has_v9() { return (_features & v9_instructions_m) != 0; } |
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static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } |
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static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } |
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static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } |
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static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } |
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static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } |
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static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } |
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static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } |
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static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } |
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static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } |
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static bool has_sparc5_instr() { return (_features & sparc5_instructions_m) != 0; } |
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static bool has_aes() { return (_features & aes_instructions_m) != 0; } |
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static bool has_sha1() { return (_features & sha1_instruction_m) != 0; } |
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static bool has_sha256() { return (_features & sha256_instruction_m) != 0; } |
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static bool has_sha512() { return (_features & sha512_instruction_m) != 0; } |
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static bool has_crc32c() { return (_features & crc32c_instruction_m) != 0; } |
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static bool supports_compare_and_exchange() |
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{ return has_v9(); } |
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// Returns true if the platform is in the niagara line (T series) |
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// and newer than the niagara1. |
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static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } |
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static bool is_M_series() { return is_M_family(_features); } |
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static bool is_S_series() { return is_S_family(_features); } |
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static bool is_T4() { return is_T_family(_features) && has_cbcond(); } |
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static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); } |
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// Fujitsu SPARC64 |
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static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } |
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static bool is_sun4v() { return (_features & sun4v_m) != 0; } |
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static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } |
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static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } |
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static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } |
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// T4 and newer Sparc have fast RDPC instruction. |
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static bool has_fast_rdpc() { return is_T4(); } |
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// On T4 and newer Sparc BIS to the beginning of cache line always zeros it. |
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static bool has_block_zeroing() { return has_blk_init() && is_T4(); } |
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// default prefetch block size on sparc |
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static intx prefetch_data_size() { return L2_data_cache_line_size(); } |
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// Prefetch |
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static intx prefetch_copy_interval_in_bytes() { |
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return (has_v9() ? 512 : 0); |
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} |
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static intx prefetch_scan_interval_in_bytes() { |
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return (has_v9() ? 512 : 0); |
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} |
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static intx prefetch_fields_ahead() { |
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return (is_ultra3() ? 1 : 0); |
1 | 190 |
} |
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192 |
// Assembler testing |
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static void allow_all(); |
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static void revert(); |
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// Override the Abstract_VM_Version implementation. |
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static uint page_size_count() { return is_sun4v() ? 4 : 2; } |
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// Calculates the number of parallel threads |
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|
200 |
static unsigned int calc_parallel_worker_threads(); |
1 | 201 |
}; |
7397 | 202 |
|
203 |
#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP |