author | roland |
Tue, 14 Aug 2018 16:54:47 +0200 | |
changeset 51482 | d7029542d67a |
parent 50599 | ecc2af326b5f |
child 51485 | 0c7040d1d1ca |
permissions | -rw-r--r-- |
50180 | 1 |
/* |
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* Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#include "precompiled.hpp" |
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#include "gc/shared/c2/barrierSetC2.hpp" |
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#include "opto/arraycopynode.hpp" |
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#include "opto/graphKit.hpp" |
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#include "opto/idealKit.hpp" |
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#include "opto/narrowptrnode.hpp" |
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#include "utilities/macros.hpp" |
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// By default this is a no-op. |
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void BarrierSetC2::resolve_address(C2Access& access) const { } |
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void* C2Access::barrier_set_state() const { |
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return _kit->barrier_set_state(); |
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} |
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bool C2Access::needs_cpu_membar() const { |
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bool mismatched = (_decorators & C2_MISMATCHED) != 0; |
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bool is_unordered = (_decorators & MO_UNORDERED) != 0; |
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bool anonymous = (_decorators & C2_UNSAFE_ACCESS) != 0; |
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bool in_heap = (_decorators & IN_HEAP) != 0; |
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bool is_write = (_decorators & C2_WRITE_ACCESS) != 0; |
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bool is_read = (_decorators & C2_READ_ACCESS) != 0; |
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bool is_atomic = is_read && is_write; |
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if (is_atomic) { |
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// Atomics always need to be wrapped in CPU membars |
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return true; |
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} |
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if (anonymous) { |
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// We will need memory barriers unless we can determine a unique |
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// alias category for this reference. (Note: If for some reason |
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// the barriers get omitted and the unsafe reference begins to "pollute" |
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// the alias analysis of the rest of the graph, either Compile::can_alias |
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// or Compile::must_alias will throw a diagnostic assert.) |
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if (!in_heap || !is_unordered || (mismatched && !_addr.type()->isa_aryptr())) { |
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return true; |
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} |
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} |
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return false; |
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} |
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Node* BarrierSetC2::store_at_resolved(C2Access& access, C2AccessValue& val) const { |
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DecoratorSet decorators = access.decorators(); |
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GraphKit* kit = access.kit(); |
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bool mismatched = (decorators & C2_MISMATCHED) != 0; |
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bool unaligned = (decorators & C2_UNALIGNED) != 0; |
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bool requires_atomic_access = (decorators & MO_UNORDERED) == 0; |
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bool in_native = (decorators & IN_NATIVE) != 0; |
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assert(!in_native, "not supported yet"); |
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if (access.type() == T_DOUBLE) { |
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Node* new_val = kit->dstore_rounding(val.node()); |
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val.set_node(new_val); |
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} |
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MemNode::MemOrd mo = access.mem_node_mo(); |
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Node* store = kit->store_to_memory(kit->control(), access.addr().node(), val.node(), access.type(), |
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access.addr().type(), mo, requires_atomic_access, unaligned, mismatched); |
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access.set_raw_access(store); |
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return store; |
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} |
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Node* BarrierSetC2::load_at_resolved(C2Access& access, const Type* val_type) const { |
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DecoratorSet decorators = access.decorators(); |
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GraphKit* kit = access.kit(); |
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Node* adr = access.addr().node(); |
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const TypePtr* adr_type = access.addr().type(); |
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bool mismatched = (decorators & C2_MISMATCHED) != 0; |
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bool requires_atomic_access = (decorators & MO_UNORDERED) == 0; |
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bool unaligned = (decorators & C2_UNALIGNED) != 0; |
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bool control_dependent = (decorators & C2_CONTROL_DEPENDENT_LOAD) != 0; |
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bool pinned = (decorators & C2_PINNED_LOAD) != 0; |
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bool in_native = (decorators & IN_NATIVE) != 0; |
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assert(!in_native, "not supported yet"); |
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MemNode::MemOrd mo = access.mem_node_mo(); |
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LoadNode::ControlDependency dep = pinned ? LoadNode::Pinned : LoadNode::DependsOnlyOnTest; |
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Node* control = control_dependent ? kit->control() : NULL; |
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Node* load = kit->make_load(control, adr, val_type, access.type(), adr_type, mo, |
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dep, requires_atomic_access, unaligned, mismatched); |
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access.set_raw_access(load); |
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return load; |
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} |
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class C2AccessFence: public StackObj { |
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C2Access& _access; |
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Node* _leading_membar; |
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public: |
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C2AccessFence(C2Access& access) : |
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_access(access), _leading_membar(NULL) { |
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GraphKit* kit = access.kit(); |
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DecoratorSet decorators = access.decorators(); |
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bool is_write = (decorators & C2_WRITE_ACCESS) != 0; |
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bool is_read = (decorators & C2_READ_ACCESS) != 0; |
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bool is_atomic = is_read && is_write; |
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bool is_volatile = (decorators & MO_SEQ_CST) != 0; |
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bool is_release = (decorators & MO_RELEASE) != 0; |
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if (is_atomic) { |
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// Memory-model-wise, a LoadStore acts like a little synchronized |
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// block, so needs barriers on each side. These don't translate |
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// into actual barriers on most machines, but we still need rest of |
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// compiler to respect ordering. |
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if (is_release) { |
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_leading_membar = kit->insert_mem_bar(Op_MemBarRelease); |
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} else if (is_volatile) { |
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if (support_IRIW_for_not_multiple_copy_atomic_cpu) { |
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_leading_membar = kit->insert_mem_bar(Op_MemBarVolatile); |
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} else { |
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_leading_membar = kit->insert_mem_bar(Op_MemBarRelease); |
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} |
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} |
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} else if (is_write) { |
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// If reference is volatile, prevent following memory ops from |
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// floating down past the volatile write. Also prevents commoning |
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// another volatile read. |
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if (is_volatile || is_release) { |
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_leading_membar = kit->insert_mem_bar(Op_MemBarRelease); |
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} |
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} else { |
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// Memory barrier to prevent normal and 'unsafe' accesses from |
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// bypassing each other. Happens after null checks, so the |
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// exception paths do not take memory state from the memory barrier, |
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// so there's no problems making a strong assert about mixing users |
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// of safe & unsafe memory. |
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if (is_volatile && support_IRIW_for_not_multiple_copy_atomic_cpu) { |
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_leading_membar = kit->insert_mem_bar(Op_MemBarVolatile); |
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} |
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} |
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if (access.needs_cpu_membar()) { |
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kit->insert_mem_bar(Op_MemBarCPUOrder); |
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} |
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if (is_atomic) { |
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// 4984716: MemBars must be inserted before this |
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// memory node in order to avoid a false |
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// dependency which will confuse the scheduler. |
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access.set_memory(); |
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} |
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} |
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~C2AccessFence() { |
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GraphKit* kit = _access.kit(); |
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DecoratorSet decorators = _access.decorators(); |
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bool is_write = (decorators & C2_WRITE_ACCESS) != 0; |
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bool is_read = (decorators & C2_READ_ACCESS) != 0; |
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bool is_atomic = is_read && is_write; |
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bool is_volatile = (decorators & MO_SEQ_CST) != 0; |
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bool is_acquire = (decorators & MO_ACQUIRE) != 0; |
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// If reference is volatile, prevent following volatiles ops from |
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// floating up before the volatile access. |
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if (_access.needs_cpu_membar()) { |
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kit->insert_mem_bar(Op_MemBarCPUOrder); |
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} |
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if (is_atomic) { |
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if (is_acquire || is_volatile) { |
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Node* n = _access.raw_access(); |
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Node* mb = kit->insert_mem_bar(Op_MemBarAcquire, n); |
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if (_leading_membar != NULL) { |
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MemBarNode::set_load_store_pair(_leading_membar->as_MemBar(), mb->as_MemBar()); |
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} |
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} |
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} else if (is_write) { |
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// If not multiple copy atomic, we do the MemBarVolatile before the load. |
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if (is_volatile && !support_IRIW_for_not_multiple_copy_atomic_cpu) { |
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Node* n = _access.raw_access(); |
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Node* mb = kit->insert_mem_bar(Op_MemBarVolatile, n); // Use fat membar |
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if (_leading_membar != NULL) { |
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MemBarNode::set_store_pair(_leading_membar->as_MemBar(), mb->as_MemBar()); |
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} |
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} |
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} else { |
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if (is_volatile || is_acquire) { |
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Node* n = _access.raw_access(); |
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assert(_leading_membar == NULL || support_IRIW_for_not_multiple_copy_atomic_cpu, "no leading membar expected"); |
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Node* mb = kit->insert_mem_bar(Op_MemBarAcquire, n); |
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mb->as_MemBar()->set_trailing_load(); |
50180 | 221 |
} |
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} |
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} |
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}; |
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Node* BarrierSetC2::store_at(C2Access& access, C2AccessValue& val) const { |
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C2AccessFence fence(access); |
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resolve_address(access); |
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return store_at_resolved(access, val); |
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} |
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Node* BarrierSetC2::load_at(C2Access& access, const Type* val_type) const { |
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C2AccessFence fence(access); |
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resolve_address(access); |
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return load_at_resolved(access, val_type); |
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} |
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MemNode::MemOrd C2Access::mem_node_mo() const { |
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bool is_write = (_decorators & C2_WRITE_ACCESS) != 0; |
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bool is_read = (_decorators & C2_READ_ACCESS) != 0; |
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if ((_decorators & MO_SEQ_CST) != 0) { |
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if (is_write && is_read) { |
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// For atomic operations |
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return MemNode::seqcst; |
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} else if (is_write) { |
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return MemNode::release; |
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} else { |
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assert(is_read, "what else?"); |
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return MemNode::acquire; |
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} |
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} else if ((_decorators & MO_RELEASE) != 0) { |
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return MemNode::release; |
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} else if ((_decorators & MO_ACQUIRE) != 0) { |
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return MemNode::acquire; |
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} else if (is_write) { |
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// Volatile fields need releasing stores. |
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// Non-volatile fields also need releasing stores if they hold an |
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// object reference, because the object reference might point to |
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// a freshly created object. |
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// Conservatively release stores of object references. |
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return StoreNode::release_if_reference(_type); |
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} else { |
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return MemNode::unordered; |
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} |
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} |
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266 |
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267 |
void C2Access::fixup_decorators() { |
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268 |
bool default_mo = (_decorators & MO_DECORATOR_MASK) == 0; |
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269 |
bool is_unordered = (_decorators & MO_UNORDERED) != 0 || default_mo; |
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bool anonymous = (_decorators & C2_UNSAFE_ACCESS) != 0; |
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271 |
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272 |
bool is_read = (_decorators & C2_READ_ACCESS) != 0; |
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273 |
bool is_write = (_decorators & C2_WRITE_ACCESS) != 0; |
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274 |
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275 |
if (AlwaysAtomicAccesses && is_unordered) { |
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276 |
_decorators &= ~MO_DECORATOR_MASK; // clear the MO bits |
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277 |
_decorators |= MO_RELAXED; // Force the MO_RELAXED decorator with AlwaysAtomicAccess |
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278 |
} |
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279 |
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280 |
_decorators = AccessInternal::decorator_fixup(_decorators); |
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281 |
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282 |
if (is_read && !is_write && anonymous) { |
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283 |
// To be valid, unsafe loads may depend on other conditions than |
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284 |
// the one that guards them: pin the Load node |
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285 |
_decorators |= C2_CONTROL_DEPENDENT_LOAD; |
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286 |
_decorators |= C2_PINNED_LOAD; |
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287 |
const TypePtr* adr_type = _addr.type(); |
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288 |
Node* adr = _addr.node(); |
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289 |
if (!needs_cpu_membar() && adr_type->isa_instptr()) { |
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290 |
assert(adr_type->meet(TypePtr::NULL_PTR) != adr_type->remove_speculative(), "should be not null"); |
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291 |
intptr_t offset = Type::OffsetBot; |
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292 |
AddPNode::Ideal_base_and_offset(adr, &_kit->gvn(), offset); |
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293 |
if (offset >= 0) { |
|
294 |
int s = Klass::layout_helper_size_in_bytes(adr_type->isa_instptr()->klass()->layout_helper()); |
|
295 |
if (offset < s) { |
|
296 |
// Guaranteed to be a valid access, no need to pin it |
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297 |
_decorators ^= C2_CONTROL_DEPENDENT_LOAD; |
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298 |
_decorators ^= C2_PINNED_LOAD; |
|
299 |
} |
|
300 |
} |
|
301 |
} |
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302 |
} |
|
303 |
} |
|
304 |
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305 |
//--------------------------- atomic operations--------------------------------- |
|
306 |
||
307 |
static void pin_atomic_op(C2AtomicAccess& access) { |
|
308 |
if (!access.needs_pinning()) { |
|
309 |
return; |
|
310 |
} |
|
311 |
// SCMemProjNodes represent the memory state of a LoadStore. Their |
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312 |
// main role is to prevent LoadStore nodes from being optimized away |
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313 |
// when their results aren't used. |
|
314 |
GraphKit* kit = access.kit(); |
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315 |
Node* load_store = access.raw_access(); |
|
316 |
assert(load_store != NULL, "must pin atomic op"); |
|
317 |
Node* proj = kit->gvn().transform(new SCMemProjNode(load_store)); |
|
318 |
kit->set_memory(proj, access.alias_idx()); |
|
319 |
} |
|
320 |
||
321 |
void C2AtomicAccess::set_memory() { |
|
322 |
Node *mem = _kit->memory(_alias_idx); |
|
323 |
_memory = mem; |
|
324 |
} |
|
325 |
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326 |
Node* BarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* expected_val, |
|
327 |
Node* new_val, const Type* value_type) const { |
|
328 |
GraphKit* kit = access.kit(); |
|
329 |
MemNode::MemOrd mo = access.mem_node_mo(); |
|
330 |
Node* mem = access.memory(); |
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331 |
||
332 |
Node* adr = access.addr().node(); |
|
333 |
const TypePtr* adr_type = access.addr().type(); |
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334 |
||
335 |
Node* load_store = NULL; |
|
336 |
||
337 |
if (access.is_oop()) { |
|
338 |
#ifdef _LP64 |
|
339 |
if (adr->bottom_type()->is_ptr_to_narrowoop()) { |
|
340 |
Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); |
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341 |
Node *oldval_enc = kit->gvn().transform(new EncodePNode(expected_val, expected_val->bottom_type()->make_narrowoop())); |
|
342 |
load_store = kit->gvn().transform(new CompareAndExchangeNNode(kit->control(), mem, adr, newval_enc, oldval_enc, adr_type, value_type->make_narrowoop(), mo)); |
|
343 |
} else |
|
344 |
#endif |
|
345 |
{ |
|
346 |
load_store = kit->gvn().transform(new CompareAndExchangePNode(kit->control(), mem, adr, new_val, expected_val, adr_type, value_type->is_oopptr(), mo)); |
|
347 |
} |
|
348 |
} else { |
|
349 |
switch (access.type()) { |
|
350 |
case T_BYTE: { |
|
351 |
load_store = kit->gvn().transform(new CompareAndExchangeBNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); |
|
352 |
break; |
|
353 |
} |
|
354 |
case T_SHORT: { |
|
355 |
load_store = kit->gvn().transform(new CompareAndExchangeSNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); |
|
356 |
break; |
|
357 |
} |
|
358 |
case T_INT: { |
|
359 |
load_store = kit->gvn().transform(new CompareAndExchangeINode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); |
|
360 |
break; |
|
361 |
} |
|
362 |
case T_LONG: { |
|
363 |
load_store = kit->gvn().transform(new CompareAndExchangeLNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); |
|
364 |
break; |
|
365 |
} |
|
366 |
default: |
|
367 |
ShouldNotReachHere(); |
|
368 |
} |
|
369 |
} |
|
370 |
||
371 |
access.set_raw_access(load_store); |
|
372 |
pin_atomic_op(access); |
|
373 |
||
374 |
#ifdef _LP64 |
|
375 |
if (access.is_oop() && adr->bottom_type()->is_ptr_to_narrowoop()) { |
|
376 |
return kit->gvn().transform(new DecodeNNode(load_store, load_store->get_ptr_type())); |
|
377 |
} |
|
378 |
#endif |
|
379 |
||
380 |
return load_store; |
|
381 |
} |
|
382 |
||
383 |
Node* BarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node* expected_val, |
|
384 |
Node* new_val, const Type* value_type) const { |
|
385 |
GraphKit* kit = access.kit(); |
|
386 |
DecoratorSet decorators = access.decorators(); |
|
387 |
MemNode::MemOrd mo = access.mem_node_mo(); |
|
388 |
Node* mem = access.memory(); |
|
389 |
bool is_weak_cas = (decorators & C2_WEAK_CMPXCHG) != 0; |
|
390 |
Node* load_store = NULL; |
|
391 |
Node* adr = access.addr().node(); |
|
392 |
||
393 |
if (access.is_oop()) { |
|
394 |
#ifdef _LP64 |
|
395 |
if (adr->bottom_type()->is_ptr_to_narrowoop()) { |
|
396 |
Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); |
|
397 |
Node *oldval_enc = kit->gvn().transform(new EncodePNode(expected_val, expected_val->bottom_type()->make_narrowoop())); |
|
398 |
if (is_weak_cas) { |
|
399 |
load_store = kit->gvn().transform(new WeakCompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo)); |
|
400 |
} else { |
|
401 |
load_store = kit->gvn().transform(new CompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo)); |
|
402 |
} |
|
403 |
} else |
|
404 |
#endif |
|
405 |
{ |
|
406 |
if (is_weak_cas) { |
|
407 |
load_store = kit->gvn().transform(new WeakCompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
408 |
} else { |
|
409 |
load_store = kit->gvn().transform(new CompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
410 |
} |
|
411 |
} |
|
412 |
} else { |
|
413 |
switch(access.type()) { |
|
414 |
case T_BYTE: { |
|
415 |
if (is_weak_cas) { |
|
416 |
load_store = kit->gvn().transform(new WeakCompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
417 |
} else { |
|
418 |
load_store = kit->gvn().transform(new CompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
419 |
} |
|
420 |
break; |
|
421 |
} |
|
422 |
case T_SHORT: { |
|
423 |
if (is_weak_cas) { |
|
424 |
load_store = kit->gvn().transform(new WeakCompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
425 |
} else { |
|
426 |
load_store = kit->gvn().transform(new CompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
427 |
} |
|
428 |
break; |
|
429 |
} |
|
430 |
case T_INT: { |
|
431 |
if (is_weak_cas) { |
|
432 |
load_store = kit->gvn().transform(new WeakCompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
433 |
} else { |
|
434 |
load_store = kit->gvn().transform(new CompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
435 |
} |
|
436 |
break; |
|
437 |
} |
|
438 |
case T_LONG: { |
|
439 |
if (is_weak_cas) { |
|
440 |
load_store = kit->gvn().transform(new WeakCompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
441 |
} else { |
|
442 |
load_store = kit->gvn().transform(new CompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo)); |
|
443 |
} |
|
444 |
break; |
|
445 |
} |
|
446 |
default: |
|
447 |
ShouldNotReachHere(); |
|
448 |
} |
|
449 |
} |
|
450 |
||
451 |
access.set_raw_access(load_store); |
|
452 |
pin_atomic_op(access); |
|
453 |
||
454 |
return load_store; |
|
455 |
} |
|
456 |
||
457 |
Node* BarrierSetC2::atomic_xchg_at_resolved(C2AtomicAccess& access, Node* new_val, const Type* value_type) const { |
|
458 |
GraphKit* kit = access.kit(); |
|
459 |
Node* mem = access.memory(); |
|
460 |
Node* adr = access.addr().node(); |
|
461 |
const TypePtr* adr_type = access.addr().type(); |
|
462 |
Node* load_store = NULL; |
|
463 |
||
464 |
if (access.is_oop()) { |
|
465 |
#ifdef _LP64 |
|
466 |
if (adr->bottom_type()->is_ptr_to_narrowoop()) { |
|
467 |
Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); |
|
468 |
load_store = kit->gvn().transform(new GetAndSetNNode(kit->control(), mem, adr, newval_enc, adr_type, value_type->make_narrowoop())); |
|
469 |
} else |
|
470 |
#endif |
|
471 |
{ |
|
472 |
load_store = kit->gvn().transform(new GetAndSetPNode(kit->control(), mem, adr, new_val, adr_type, value_type->is_oopptr())); |
|
473 |
} |
|
474 |
} else { |
|
475 |
switch (access.type()) { |
|
476 |
case T_BYTE: |
|
477 |
load_store = kit->gvn().transform(new GetAndSetBNode(kit->control(), mem, adr, new_val, adr_type)); |
|
478 |
break; |
|
479 |
case T_SHORT: |
|
480 |
load_store = kit->gvn().transform(new GetAndSetSNode(kit->control(), mem, adr, new_val, adr_type)); |
|
481 |
break; |
|
482 |
case T_INT: |
|
483 |
load_store = kit->gvn().transform(new GetAndSetINode(kit->control(), mem, adr, new_val, adr_type)); |
|
484 |
break; |
|
485 |
case T_LONG: |
|
486 |
load_store = kit->gvn().transform(new GetAndSetLNode(kit->control(), mem, adr, new_val, adr_type)); |
|
487 |
break; |
|
488 |
default: |
|
489 |
ShouldNotReachHere(); |
|
490 |
} |
|
491 |
} |
|
492 |
||
493 |
access.set_raw_access(load_store); |
|
494 |
pin_atomic_op(access); |
|
495 |
||
496 |
#ifdef _LP64 |
|
497 |
if (access.is_oop() && adr->bottom_type()->is_ptr_to_narrowoop()) { |
|
498 |
return kit->gvn().transform(new DecodeNNode(load_store, load_store->get_ptr_type())); |
|
499 |
} |
|
500 |
#endif |
|
501 |
||
502 |
return load_store; |
|
503 |
} |
|
504 |
||
505 |
Node* BarrierSetC2::atomic_add_at_resolved(C2AtomicAccess& access, Node* new_val, const Type* value_type) const { |
|
506 |
Node* load_store = NULL; |
|
507 |
GraphKit* kit = access.kit(); |
|
508 |
Node* adr = access.addr().node(); |
|
509 |
const TypePtr* adr_type = access.addr().type(); |
|
510 |
Node* mem = access.memory(); |
|
511 |
||
512 |
switch(access.type()) { |
|
513 |
case T_BYTE: |
|
514 |
load_store = kit->gvn().transform(new GetAndAddBNode(kit->control(), mem, adr, new_val, adr_type)); |
|
515 |
break; |
|
516 |
case T_SHORT: |
|
517 |
load_store = kit->gvn().transform(new GetAndAddSNode(kit->control(), mem, adr, new_val, adr_type)); |
|
518 |
break; |
|
519 |
case T_INT: |
|
520 |
load_store = kit->gvn().transform(new GetAndAddINode(kit->control(), mem, adr, new_val, adr_type)); |
|
521 |
break; |
|
522 |
case T_LONG: |
|
523 |
load_store = kit->gvn().transform(new GetAndAddLNode(kit->control(), mem, adr, new_val, adr_type)); |
|
524 |
break; |
|
525 |
default: |
|
526 |
ShouldNotReachHere(); |
|
527 |
} |
|
528 |
||
529 |
access.set_raw_access(load_store); |
|
530 |
pin_atomic_op(access); |
|
531 |
||
532 |
return load_store; |
|
533 |
} |
|
534 |
||
535 |
Node* BarrierSetC2::atomic_cmpxchg_val_at(C2AtomicAccess& access, Node* expected_val, |
|
536 |
Node* new_val, const Type* value_type) const { |
|
537 |
C2AccessFence fence(access); |
|
538 |
resolve_address(access); |
|
539 |
return atomic_cmpxchg_val_at_resolved(access, expected_val, new_val, value_type); |
|
540 |
} |
|
541 |
||
542 |
Node* BarrierSetC2::atomic_cmpxchg_bool_at(C2AtomicAccess& access, Node* expected_val, |
|
543 |
Node* new_val, const Type* value_type) const { |
|
544 |
C2AccessFence fence(access); |
|
545 |
resolve_address(access); |
|
546 |
return atomic_cmpxchg_bool_at_resolved(access, expected_val, new_val, value_type); |
|
547 |
} |
|
548 |
||
549 |
Node* BarrierSetC2::atomic_xchg_at(C2AtomicAccess& access, Node* new_val, const Type* value_type) const { |
|
550 |
C2AccessFence fence(access); |
|
551 |
resolve_address(access); |
|
552 |
return atomic_xchg_at_resolved(access, new_val, value_type); |
|
553 |
} |
|
554 |
||
555 |
Node* BarrierSetC2::atomic_add_at(C2AtomicAccess& access, Node* new_val, const Type* value_type) const { |
|
556 |
C2AccessFence fence(access); |
|
557 |
resolve_address(access); |
|
558 |
return atomic_add_at_resolved(access, new_val, value_type); |
|
559 |
} |
|
560 |
||
561 |
void BarrierSetC2::clone(GraphKit* kit, Node* src, Node* dst, Node* size, bool is_array) const { |
|
562 |
// Exclude the header but include array length to copy by 8 bytes words. |
|
563 |
// Can't use base_offset_in_bytes(bt) since basic type is unknown. |
|
564 |
int base_off = is_array ? arrayOopDesc::length_offset_in_bytes() : |
|
565 |
instanceOopDesc::base_offset_in_bytes(); |
|
566 |
// base_off: |
|
567 |
// 8 - 32-bit VM |
|
568 |
// 12 - 64-bit VM, compressed klass |
|
569 |
// 16 - 64-bit VM, normal klass |
|
570 |
if (base_off % BytesPerLong != 0) { |
|
571 |
assert(UseCompressedClassPointers, ""); |
|
572 |
if (is_array) { |
|
573 |
// Exclude length to copy by 8 bytes words. |
|
574 |
base_off += sizeof(int); |
|
575 |
} else { |
|
576 |
// Include klass to copy by 8 bytes words. |
|
577 |
base_off = instanceOopDesc::klass_offset_in_bytes(); |
|
578 |
} |
|
579 |
assert(base_off % BytesPerLong == 0, "expect 8 bytes alignment"); |
|
580 |
} |
|
581 |
Node* src_base = kit->basic_plus_adr(src, base_off); |
|
582 |
Node* dst_base = kit->basic_plus_adr(dst, base_off); |
|
583 |
||
584 |
// Compute the length also, if needed: |
|
585 |
Node* countx = size; |
|
586 |
countx = kit->gvn().transform(new SubXNode(countx, kit->MakeConX(base_off))); |
|
587 |
countx = kit->gvn().transform(new URShiftXNode(countx, kit->intcon(LogBytesPerLong) )); |
|
588 |
||
589 |
const TypePtr* raw_adr_type = TypeRawPtr::BOTTOM; |
|
590 |
||
591 |
ArrayCopyNode* ac = ArrayCopyNode::make(kit, false, src_base, NULL, dst_base, NULL, countx, false, false); |
|
592 |
ac->set_clonebasic(); |
|
593 |
Node* n = kit->gvn().transform(ac); |
|
594 |
if (n == ac) { |
|
595 |
kit->set_predefined_output_for_runtime_call(ac, ac->in(TypeFunc::Memory), raw_adr_type); |
|
596 |
} else { |
|
597 |
kit->set_all_memory(n); |
|
598 |
} |
|
599 |
} |