author | neliasso |
Tue, 27 Jun 2017 15:50:09 +0200 | |
changeset 46597 | d669fb842ae3 |
parent 46596 | a7c9706d25a9 |
permissions | -rw-r--r-- |
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/* |
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* Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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||
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#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |
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#define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |
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||
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#include "asm/register.hpp" |
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// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction |
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// level; i.e., what you write is what you get. The Assembler is generating code |
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// into a CodeBuffer. |
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class Assembler : public AbstractAssembler { |
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friend class AbstractAssembler; |
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friend class AddressLiteral; |
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// code patchers need various routines like inv_wdisp() |
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friend class NativeInstruction; |
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friend class NativeGeneralJump; |
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friend class Relocation; |
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friend class Label; |
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public: |
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// op carries format info; see page 62 & 267 |
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enum ops { |
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call_op = 1, // fmt 1 |
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branch_op = 0, // also sethi (fmt2) |
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arith_op = 2, // fmt 3, arith & misc |
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ldst_op = 3 // fmt 3, load/store |
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}; |
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enum op2s { |
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bpr_op2 = 3, |
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fb_op2 = 6, |
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fbp_op2 = 5, |
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br_op2 = 2, |
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bp_op2 = 1, |
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sethi_op2 = 4 |
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}; |
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enum op3s { |
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// selected op3s |
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add_op3 = 0x00, |
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and_op3 = 0x01, |
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or_op3 = 0x02, |
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xor_op3 = 0x03, |
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sub_op3 = 0x04, |
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andn_op3 = 0x05, |
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orn_op3 = 0x06, |
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xnor_op3 = 0x07, |
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addc_op3 = 0x08, |
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mulx_op3 = 0x09, |
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umul_op3 = 0x0a, |
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smul_op3 = 0x0b, |
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subc_op3 = 0x0c, |
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udivx_op3 = 0x0d, |
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udiv_op3 = 0x0e, |
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sdiv_op3 = 0x0f, |
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addcc_op3 = 0x10, |
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andcc_op3 = 0x11, |
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orcc_op3 = 0x12, |
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xorcc_op3 = 0x13, |
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subcc_op3 = 0x14, |
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andncc_op3 = 0x15, |
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orncc_op3 = 0x16, |
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xnorcc_op3 = 0x17, |
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addccc_op3 = 0x18, |
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aes4_op3 = 0x19, |
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umulcc_op3 = 0x1a, |
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smulcc_op3 = 0x1b, |
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subccc_op3 = 0x1c, |
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udivcc_op3 = 0x1e, |
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sdivcc_op3 = 0x1f, |
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taddcc_op3 = 0x20, |
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tsubcc_op3 = 0x21, |
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taddcctv_op3 = 0x22, |
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tsubcctv_op3 = 0x23, |
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mulscc_op3 = 0x24, |
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sll_op3 = 0x25, |
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sllx_op3 = 0x25, |
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srl_op3 = 0x26, |
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srlx_op3 = 0x26, |
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sra_op3 = 0x27, |
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srax_op3 = 0x27, |
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rdreg_op3 = 0x28, |
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membar_op3 = 0x28, |
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flushw_op3 = 0x2b, |
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movcc_op3 = 0x2c, |
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sdivx_op3 = 0x2d, |
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popc_op3 = 0x2e, |
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movr_op3 = 0x2f, |
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sir_op3 = 0x30, |
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wrreg_op3 = 0x30, |
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saved_op3 = 0x31, |
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fpop1_op3 = 0x34, |
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fpop2_op3 = 0x35, |
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impdep1_op3 = 0x36, |
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aes3_op3 = 0x36, |
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sha_op3 = 0x36, |
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bmask_op3 = 0x36, |
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bshuffle_op3 = 0x36, |
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alignaddr_op3 = 0x36, |
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faligndata_op3 = 0x36, |
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flog3_op3 = 0x36, |
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edge_op3 = 0x36, |
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fzero_op3 = 0x36, |
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fsrc_op3 = 0x36, |
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fnot_op3 = 0x36, |
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xmulx_op3 = 0x36, |
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crc32c_op3 = 0x36, |
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impdep2_op3 = 0x37, |
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stpartialf_op3 = 0x37, |
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jmpl_op3 = 0x38, |
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rett_op3 = 0x39, |
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trap_op3 = 0x3a, |
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flush_op3 = 0x3b, |
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save_op3 = 0x3c, |
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restore_op3 = 0x3d, |
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done_op3 = 0x3e, |
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retry_op3 = 0x3e, |
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lduw_op3 = 0x00, |
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ldub_op3 = 0x01, |
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lduh_op3 = 0x02, |
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ldd_op3 = 0x03, |
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stw_op3 = 0x04, |
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stb_op3 = 0x05, |
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sth_op3 = 0x06, |
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std_op3 = 0x07, |
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ldsw_op3 = 0x08, |
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ldsb_op3 = 0x09, |
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ldsh_op3 = 0x0a, |
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ldx_op3 = 0x0b, |
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stx_op3 = 0x0e, |
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swap_op3 = 0x0f, |
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stwa_op3 = 0x14, |
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stxa_op3 = 0x1e, |
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ldf_op3 = 0x20, |
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ldfsr_op3 = 0x21, |
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ldqf_op3 = 0x22, |
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lddf_op3 = 0x23, |
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stf_op3 = 0x24, |
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stfsr_op3 = 0x25, |
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stqf_op3 = 0x26, |
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stdf_op3 = 0x27, |
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prefetch_op3 = 0x2d, |
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casa_op3 = 0x3c, |
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casxa_op3 = 0x3e, |
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mftoi_op3 = 0x36, |
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alt_bit_op3 = 0x10, |
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cc_bit_op3 = 0x10 |
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}; |
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enum opfs { |
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// selected opfs |
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edge8n_opf = 0x01, |
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fmovs_opf = 0x01, |
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fmovd_opf = 0x02, |
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fnegs_opf = 0x05, |
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fnegd_opf = 0x06, |
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alignaddr_opf = 0x18, |
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bmask_opf = 0x19, |
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fadds_opf = 0x41, |
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faddd_opf = 0x42, |
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fsubs_opf = 0x45, |
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fsubd_opf = 0x46, |
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faligndata_opf = 0x48, |
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fmuls_opf = 0x49, |
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fmuld_opf = 0x4a, |
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bshuffle_opf = 0x4c, |
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fdivs_opf = 0x4d, |
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fdivd_opf = 0x4e, |
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fcmps_opf = 0x51, |
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fcmpd_opf = 0x52, |
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fstox_opf = 0x81, |
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fdtox_opf = 0x82, |
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fxtos_opf = 0x84, |
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fxtod_opf = 0x88, |
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fitos_opf = 0xc4, |
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fdtos_opf = 0xc6, |
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fitod_opf = 0xc8, |
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fstod_opf = 0xc9, |
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fstoi_opf = 0xd1, |
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fdtoi_opf = 0xd2, |
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1 | 227 |
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mdtox_opf = 0x110, |
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mstouw_opf = 0x111, |
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mstosw_opf = 0x113, |
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xmulx_opf = 0x115, |
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xmulxhi_opf = 0x116, |
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mxtod_opf = 0x118, |
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mwtos_opf = 0x119, |
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aes_kexpand0_opf = 0x130, |
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aes_kexpand2_opf = 0x131, |
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sha1_opf = 0x141, |
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sha256_opf = 0x142, |
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sha512_opf = 0x143, |
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crc32c_opf = 0x147 |
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}; |
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enum op5s { |
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aes_eround01_op5 = 0x00, |
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aes_eround23_op5 = 0x01, |
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aes_dround01_op5 = 0x02, |
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aes_dround23_op5 = 0x03, |
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aes_eround01_l_op5 = 0x04, |
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aes_eround23_l_op5 = 0x05, |
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aes_dround01_l_op5 = 0x06, |
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aes_dround23_l_op5 = 0x07, |
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aes_kexpand1_op5 = 0x08 |
1 | 256 |
}; |
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enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; |
1 | 259 |
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enum Condition { |
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261 |
// for FBfcc & FBPfcc instruction |
|
262 |
f_never = 0, |
|
263 |
f_notEqual = 1, |
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264 |
f_notZero = 1, |
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265 |
f_lessOrGreater = 2, |
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266 |
f_unorderedOrLess = 3, |
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267 |
f_less = 4, |
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268 |
f_unorderedOrGreater = 5, |
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269 |
f_greater = 6, |
|
270 |
f_unordered = 7, |
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271 |
f_always = 8, |
|
272 |
f_equal = 9, |
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273 |
f_zero = 9, |
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274 |
f_unorderedOrEqual = 10, |
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275 |
f_greaterOrEqual = 11, |
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276 |
f_unorderedOrGreaterOrEqual = 12, |
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277 |
f_lessOrEqual = 13, |
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278 |
f_unorderedOrLessOrEqual = 14, |
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279 |
f_ordered = 15, |
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280 |
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281 |
// for integers |
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282 |
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never = 0, |
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equal = 1, |
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zero = 1, |
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lessEqual = 2, |
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less = 3, |
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288 |
lessEqualUnsigned = 4, |
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lessUnsigned = 5, |
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carrySet = 5, |
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negative = 6, |
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overflowSet = 7, |
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always = 8, |
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notEqual = 9, |
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notZero = 9, |
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greater = 10, |
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greaterEqual = 11, |
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greaterUnsigned = 12, |
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greaterEqualUnsigned = 13, |
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300 |
carryClear = 13, |
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301 |
positive = 14, |
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302 |
overflowClear = 15 |
1 | 303 |
}; |
304 |
||
305 |
enum CC { |
|
306 |
// ptr_cc is the correct condition code for a pointer or intptr_t: |
|
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307 |
icc = 0, xcc = 2, ptr_cc = xcc, |
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308 |
fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 |
1 | 309 |
}; |
310 |
||
311 |
enum PrefetchFcn { |
|
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312 |
severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 |
1 | 313 |
}; |
314 |
||
315 |
public: |
|
316 |
// Helper functions for groups of instructions |
|
317 |
||
318 |
enum Predict { pt = 1, pn = 0 }; // pt = predict taken |
|
319 |
||
320 |
enum Membar_mask_bits { // page 184, v9 |
|
321 |
StoreStore = 1 << 3, |
|
322 |
LoadStore = 1 << 2, |
|
323 |
StoreLoad = 1 << 1, |
|
324 |
LoadLoad = 1 << 0, |
|
325 |
||
326 |
Sync = 1 << 6, |
|
327 |
MemIssue = 1 << 5, |
|
328 |
Lookaside = 1 << 4 |
|
329 |
}; |
|
330 |
||
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331 |
static bool is_in_wdisp_range(address a, address b, int nbits) { |
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332 |
intptr_t d = intptr_t(b) - intptr_t(a); |
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333 |
return is_simm(d, nbits + 2); |
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334 |
} |
1 | 335 |
|
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336 |
address target_distance(Label &L) { |
10252 | 337 |
// Assembler::target(L) should be called only when |
338 |
// a branch instruction is emitted since non-bound |
|
339 |
// labels record current pc() as a branch address. |
|
340 |
if (L.is_bound()) return target(L); |
|
341 |
// Return current address for non-bound labels. |
|
342 |
return pc(); |
|
343 |
} |
|
344 |
||
6774 | 345 |
// test if label is in simm16 range in words (wdisp16). |
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346 |
bool is_in_wdisp16_range(Label &L) { |
10252 | 347 |
return is_in_wdisp_range(target_distance(L), pc(), 16); |
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348 |
} |
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349 |
// test if the distance between two addresses fits in simm30 range in words |
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350 |
static bool is_in_wdisp30_range(address a, address b) { |
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351 |
return is_in_wdisp_range(a, b, 30); |
6774 | 352 |
} |
353 |
||
1 | 354 |
enum ASIs { // page 72, v9 |
10501 | 355 |
ASI_PRIMARY = 0x80, |
356 |
ASI_PRIMARY_NOFAULT = 0x82, |
|
357 |
ASI_PRIMARY_LITTLE = 0x88, |
|
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|
358 |
// 8x8-bit partial store |
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|
359 |
ASI_PST8_PRIMARY = 0xC0, |
10267 | 360 |
// Block initializing store |
361 |
ASI_ST_BLKINIT_PRIMARY = 0xE2, |
|
362 |
// Most-Recently-Used (MRU) BIS variant |
|
363 |
ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 |
|
1 | 364 |
// add more from book as needed |
365 |
}; |
|
366 |
||
367 |
protected: |
|
368 |
// helpers |
|
369 |
||
370 |
// x is supposed to fit in a field "nbits" wide |
|
371 |
// and be sign-extended. Check the range. |
|
372 |
||
373 |
static void assert_signed_range(intptr_t x, int nbits) { |
|
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374 |
assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), |
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|
375 |
"value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits); |
1 | 376 |
} |
377 |
||
378 |
static void assert_signed_word_disp_range(intptr_t x, int nbits) { |
|
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379 |
assert((x & 3) == 0, "not word aligned"); |
1 | 380 |
assert_signed_range(x, nbits + 2); |
381 |
} |
|
382 |
||
383 |
static void assert_unsigned_const(int x, int nbits) { |
|
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|
384 |
assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); |
1 | 385 |
} |
386 |
||
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|
387 |
// fields: note bits numbered from LSB = 0, fields known by inclusive bit range |
1 | 388 |
|
389 |
static int fmask(juint hi_bit, juint lo_bit) { |
|
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|
390 |
assert(hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); |
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|
391 |
return (1 << (hi_bit-lo_bit + 1)) - 1; |
1 | 392 |
} |
393 |
||
394 |
// inverse of u_field |
|
395 |
||
396 |
static int inv_u_field(int x, int hi_bit, int lo_bit) { |
|
397 |
juint r = juint(x) >> lo_bit; |
|
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|
398 |
r &= fmask(hi_bit, lo_bit); |
1 | 399 |
return int(r); |
400 |
} |
|
401 |
||
402 |
// signed version: extract from field and sign-extend |
|
403 |
||
404 |
static int inv_s_field(int x, int hi_bit, int lo_bit) { |
|
405 |
int sign_shift = 31 - hi_bit; |
|
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|
406 |
return inv_u_field(((x << sign_shift) >> sign_shift), hi_bit, lo_bit); |
1 | 407 |
} |
408 |
||
409 |
// given a field that ranges from hi_bit to lo_bit (inclusive, |
|
410 |
// LSB = 0), and an unsigned value for the field, |
|
411 |
// shift it into the field |
|
412 |
||
413 |
#ifdef ASSERT |
|
414 |
static int u_field(int x, int hi_bit, int lo_bit) { |
|
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|
415 |
assert((x & ~fmask(hi_bit, lo_bit)) == 0, |
1 | 416 |
"value out of range"); |
417 |
int r = x << lo_bit; |
|
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|
418 |
assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); |
1 | 419 |
return r; |
420 |
} |
|
421 |
#else |
|
422 |
// make sure this is inlined as it will reduce code size significantly |
|
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|
423 |
#define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) |
1 | 424 |
#endif |
425 |
||
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|
426 |
static int inv_op(int x) { return inv_u_field(x, 31, 30); } |
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|
427 |
static int inv_op2(int x) { return inv_u_field(x, 24, 22); } |
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|
428 |
static int inv_op3(int x) { return inv_u_field(x, 24, 19); } |
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|
429 |
static int inv_cond(int x) { return inv_u_field(x, 28, 25); } |
1 | 430 |
|
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|
431 |
static bool inv_immed(int x) { return (x & Assembler::immed(true)) != 0; } |
1 | 432 |
|
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|
433 |
static Register inv_rd(int x) { return as_Register(inv_u_field(x, 29, 25)); } |
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|
434 |
static Register inv_rs1(int x) { return as_Register(inv_u_field(x, 18, 14)); } |
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|
435 |
static Register inv_rs2(int x) { return as_Register(inv_u_field(x, 4, 0)); } |
1 | 436 |
|
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|
437 |
static int op(int x) { return u_field(x, 31, 30); } |
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|
438 |
static int rd(Register r) { return u_field(r->encoding(), 29, 25); } |
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|
439 |
static int fcn(int x) { return u_field(x, 29, 25); } |
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|
440 |
static int op3(int x) { return u_field(x, 24, 19); } |
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|
441 |
static int rs1(Register r) { return u_field(r->encoding(), 18, 14); } |
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|
442 |
static int rs2(Register r) { return u_field(r->encoding(), 4, 0); } |
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|
443 |
static int annul(bool a) { return u_field(a ? 1 : 0, 29, 29); } |
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|
444 |
static int cond(int x) { return u_field(x, 28, 25); } |
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|
445 |
static int cond_mov(int x) { return u_field(x, 17, 14); } |
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|
446 |
static int rcond(RCondition x) { return u_field(x, 12, 10); } |
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|
447 |
static int op2(int x) { return u_field(x, 24, 22); } |
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|
448 |
static int predict(bool p) { return u_field(p ? 1 : 0, 19, 19); } |
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|
449 |
static int branchcc(CC fcca) { return u_field(fcca, 21, 20); } |
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|
450 |
static int cmpcc(CC fcca) { return u_field(fcca, 26, 25); } |
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|
451 |
static int imm_asi(int x) { return u_field(x, 12, 5); } |
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|
452 |
static int immed(bool i) { return u_field(i ? 1 : 0, 13, 13); } |
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|
453 |
static int opf_low6(int w) { return u_field(w, 10, 5); } |
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|
454 |
static int opf_low5(int w) { return u_field(w, 9, 5); } |
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|
455 |
static int op5(int x) { return u_field(x, 8, 5); } |
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|
456 |
static int trapcc(CC cc) { return u_field(cc, 12, 11); } |
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|
457 |
static int sx(int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit |
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|
458 |
static int opf(int x) { return u_field(x, 13, 5); } |
1 | 459 |
|
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changeset
|
460 |
static bool is_cbcond(int x) { |
10252 | 461 |
return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) && |
462 |
inv_op(x) == branch_op && inv_op2(x) == bpr_op2); |
|
463 |
} |
|
46596
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|
464 |
static bool is_cxb(int x) { |
10252 | 465 |
assert(is_cbcond(x), "wrong instruction"); |
46596
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changeset
|
466 |
return (x & (1 << 21)) != 0; |
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changeset
|
467 |
} |
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changeset
|
468 |
static bool is_branch(int x) { |
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changeset
|
469 |
if (inv_op(x) != Assembler::branch_op) return false; |
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changeset
|
470 |
|
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changeset
|
471 |
bool is_bpr = inv_op2(x) == Assembler::bpr_op2; |
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|
472 |
bool is_bp = inv_op2(x) == Assembler::bp_op2; |
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|
473 |
bool is_br = inv_op2(x) == Assembler::br_op2; |
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|
474 |
bool is_fp = inv_op2(x) == Assembler::fb_op2; |
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changeset
|
475 |
bool is_fbp = inv_op2(x) == Assembler::fbp_op2; |
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changeset
|
476 |
|
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changeset
|
477 |
return is_bpr || is_bp || is_br || is_fp || is_fbp; |
10252 | 478 |
} |
46596
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|
479 |
static bool is_call(int x) { |
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changeset
|
480 |
return inv_op(x) == Assembler::call_op; |
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changeset
|
481 |
} |
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changeset
|
482 |
static bool is_jump(int x) { |
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changeset
|
483 |
if (inv_op(x) != Assembler::arith_op) return false; |
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changeset
|
484 |
|
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changeset
|
485 |
bool is_jmpl = inv_op3(x) == Assembler::jmpl_op3; |
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changeset
|
486 |
bool is_rett = inv_op3(x) == Assembler::rett_op3; |
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changeset
|
487 |
|
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changeset
|
488 |
return is_jmpl || is_rett; |
a7c9706d25a9
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changeset
|
489 |
} |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
490 |
static bool is_rdpc(int x) { |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
491 |
return (inv_op(x) == Assembler::arith_op && inv_op3(x) == Assembler::rdreg_op3 && |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
492 |
inv_u_field(x, 18, 14) == 5); |
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diff
changeset
|
493 |
} |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
494 |
static bool is_cti(int x) { |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
495 |
return is_branch(x) || is_call(x) || is_jump(x); // Ignoring done/retry |
10252 | 496 |
} |
497 |
||
46596
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changeset
|
498 |
static int cond_cbcond(int x) { return u_field((((x & 8) << 1) + 8 + (x & 7)), 29, 25); } |
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|
499 |
static int inv_cond_cbcond(int x) { |
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changeset
|
500 |
assert(is_cbcond(x), "wrong instruction"); |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
501 |
return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29) << 3); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
502 |
} |
1 | 503 |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
504 |
static int opf_cc(CC c, bool useFloat) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } |
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|
505 |
static int mov_cc(CC c, bool useFloat) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } |
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changeset
|
506 |
|
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changeset
|
507 |
static int fd(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
508 |
static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; |
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changeset
|
509 |
static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; |
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changeset
|
510 |
static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); }; |
1 | 511 |
|
512 |
// some float instructions use this encoding on the op3 field |
|
513 |
static int alt_op3(int op, FloatRegisterImpl::Width w) { |
|
514 |
int r; |
|
515 |
switch(w) { |
|
516 |
case FloatRegisterImpl::S: r = op + 0; break; |
|
517 |
case FloatRegisterImpl::D: r = op + 3; break; |
|
518 |
case FloatRegisterImpl::Q: r = op + 2; break; |
|
519 |
default: ShouldNotReachHere(); break; |
|
520 |
} |
|
521 |
return op3(r); |
|
522 |
} |
|
523 |
||
524 |
// compute inverse of simm |
|
525 |
static int inv_simm(int x, int nbits) { |
|
526 |
return (int)(x << (32 - nbits)) >> (32 - nbits); |
|
527 |
} |
|
528 |
||
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|
529 |
static int inv_simm13(int x) { return inv_simm(x, 13); } |
1 | 530 |
|
531 |
// signed immediate, in low bits, nbits long |
|
532 |
static int simm(int x, int nbits) { |
|
533 |
assert_signed_range(x, nbits); |
|
46596
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changeset
|
534 |
return x & ((1 << nbits) - 1); |
1 | 535 |
} |
536 |
||
537 |
// compute inverse of wdisp16 |
|
538 |
static intptr_t inv_wdisp16(int x, intptr_t pos) { |
|
46596
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diff
changeset
|
539 |
int lo = x & ((1 << 14) - 1); |
1 | 540 |
int hi = (x >> 20) & 3; |
541 |
if (hi >= 2) hi |= ~1; |
|
542 |
return (((hi << 14) | lo) << 2) + pos; |
|
543 |
} |
|
544 |
||
545 |
// word offset, 14 bits at LSend, 2 bits at B21, B20 |
|
546 |
static int wdisp16(intptr_t x, intptr_t off) { |
|
547 |
intptr_t xx = x - off; |
|
548 |
assert_signed_word_disp_range(xx, 16); |
|
46596
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changeset
|
549 |
int r = (xx >> 2) & ((1 << 14) - 1) | (((xx >> (2+14)) & 3) << 20); |
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changeset
|
550 |
assert(inv_wdisp16(r, off) == x, "inverse is not inverse"); |
1 | 551 |
return r; |
552 |
} |
|
553 |
||
10252 | 554 |
// compute inverse of wdisp10 |
555 |
static intptr_t inv_wdisp10(int x, intptr_t pos) { |
|
556 |
assert(is_cbcond(x), "wrong instruction"); |
|
557 |
int lo = inv_u_field(x, 12, 5); |
|
558 |
int hi = (x >> 19) & 3; |
|
559 |
if (hi >= 2) hi |= ~1; |
|
560 |
return (((hi << 8) | lo) << 2) + pos; |
|
561 |
} |
|
562 |
||
563 |
// word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19] |
|
564 |
static int wdisp10(intptr_t x, intptr_t off) { |
|
565 |
assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction"); |
|
566 |
intptr_t xx = x - off; |
|
567 |
assert_signed_word_disp_range(xx, 10); |
|
46596
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changeset
|
568 |
int r = (((xx >> 2) & ((1 << 8) - 1)) << 5) | (((xx >> (2+8)) & 3) << 19); |
10252 | 569 |
// Have to fake cbcond instruction to pass assert in inv_wdisp10() |
46596
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changeset
|
570 |
assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse"); |
10252 | 571 |
return r; |
572 |
} |
|
1 | 573 |
|
574 |
// word displacement in low-order nbits bits |
|
575 |
||
46596
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changeset
|
576 |
static intptr_t inv_wdisp(int x, intptr_t pos, int nbits) { |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
577 |
int pre_sign_extend = x & ((1 << nbits) - 1); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
578 |
int r = (pre_sign_extend >= (1 << (nbits - 1)) ? |
a7c9706d25a9
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changeset
|
579 |
pre_sign_extend | ~((1 << nbits) - 1) : pre_sign_extend); |
1 | 580 |
return (r << 2) + pos; |
581 |
} |
|
582 |
||
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diff
changeset
|
583 |
static int wdisp(intptr_t x, intptr_t off, int nbits) { |
1 | 584 |
intptr_t xx = x - off; |
585 |
assert_signed_word_disp_range(xx, nbits); |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
586 |
int r = (xx >> 2) & ((1 << nbits) - 1); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
587 |
assert(inv_wdisp(r, off, nbits) == x, "inverse not inverse"); |
1 | 588 |
return r; |
589 |
} |
|
590 |
||
591 |
||
592 |
// Extract the top 32 bits in a 64 bit word |
|
46596
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changeset
|
593 |
static int32_t hi32(int64_t x) { |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
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diff
changeset
|
594 |
int32_t r = int32_t((uint64_t)x >> 32); |
1 | 595 |
return r; |
596 |
} |
|
597 |
||
598 |
// given a sethi instruction, extract the constant, left-justified |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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46594
diff
changeset
|
599 |
static int inv_hi22(int x) { |
1 | 600 |
return x << 10; |
601 |
} |
|
602 |
||
603 |
// create an imm22 field, given a 32-bit left-justified constant |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
604 |
static int hi22(int x) { |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
605 |
int r = int(juint(x) >> 10); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
606 |
assert((r & ~((1 << 22) - 1)) == 0, "just checkin'"); |
1 | 607 |
return r; |
608 |
} |
|
609 |
||
610 |
// create a low10 __value__ (not a field) for a given a 32-bit constant |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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46594
diff
changeset
|
611 |
static int low10(int x) { |
1 | 612 |
return x & ((1 << 10) - 1); |
613 |
} |
|
614 |
||
31515 | 615 |
// create a low12 __value__ (not a field) for a given a 32-bit constant |
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
616 |
static int low12(int x) { |
31515 | 617 |
return x & ((1 << 12) - 1); |
618 |
} |
|
619 |
||
22505 | 620 |
// AES crypto instructions supported only on certain processors |
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
621 |
static void aes_only() { assert(VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); } |
22505 | 622 |
|
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24328
diff
changeset
|
623 |
// SHA crypto instructions supported only on certain processors |
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
624 |
static void sha1_only() { assert(VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); } |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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46594
diff
changeset
|
625 |
static void sha256_only() { assert(VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); } |
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
626 |
static void sha512_only() { assert(VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); } |
24953
9680119572be
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
kvn
parents:
24328
diff
changeset
|
627 |
|
31515 | 628 |
// CRC32C instruction supported only on certain processors |
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
629 |
static void crc32c_only() { assert(VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); } |
31515 | 630 |
|
46597
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46596
diff
changeset
|
631 |
// FMAf instructions supported only on certain processors |
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
neliasso
parents:
46596
diff
changeset
|
632 |
static void fmaf_only() { assert(VM_Version::has_fmaf(), "This instruction only works on SPARC with FMAf"); } |
d669fb842ae3
8164888: Intrinsify fused mac operations on SPARC
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parents:
46596
diff
changeset
|
633 |
|
22505 | 634 |
// instruction only in VIS1 |
46596
a7c9706d25a9
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46594
diff
changeset
|
635 |
static void vis1_only() { assert(VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); } |
22505 | 636 |
|
24328
bddefb356fba
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents:
24008
diff
changeset
|
637 |
// instruction only in VIS2 |
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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46594
diff
changeset
|
638 |
static void vis2_only() { assert(VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); } |
24328
bddefb356fba
8035936: SIGBUS in StubRoutines::aesencryptBlock, solaris-sparc
kvn
parents:
24008
diff
changeset
|
639 |
|
10027 | 640 |
// instruction only in VIS3 |
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
641 |
static void vis3_only() { assert(VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } |
10027 | 642 |
|
1 | 643 |
// instruction deprecated in v9 |
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
644 |
static void v9_dep() { } // do nothing for now |
1 | 645 |
|
646 |
protected: |
|
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
647 |
#ifdef ASSERT |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
648 |
#define VALIDATE_PIPELINE |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
649 |
#endif |
1 | 650 |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
651 |
#ifdef VALIDATE_PIPELINE |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
652 |
// A simple delay-slot scheme: |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
653 |
// In order to check the programmer, the assembler keeps track of delay-slots. |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
654 |
// It forbids CTIs in delay-slots (conservative, but should be OK). Also, when |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
655 |
// emitting an instruction into a delay-slot, you must do so using delayed(), |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
656 |
// e.g. asm->delayed()->add(...), in order to check that you do not omit the |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
657 |
// delay-slot instruction. To implement this, we use a simple FSA. |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
658 |
enum { NoDelay, AtDelay, FillDelay } _delay_state; |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
659 |
|
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
660 |
// A simple hazard scheme: |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
661 |
// In order to avoid pipeline stalls, due to single cycle pipeline hazards, we |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
662 |
// adopt a simplistic state tracking mechanism that will enforce an additional |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
663 |
// 'nop' instruction to be inserted prior to emitting an instruction that can |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
664 |
// expose a given hazard (currently, PC-related hazards only). |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
665 |
enum { NoHazard, PcHazard } _hazard_state; |
1 | 666 |
#endif |
667 |
||
668 |
public: |
|
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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46594
diff
changeset
|
669 |
// Tell the assembler that the next instruction must NOT be in delay-slot. |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
670 |
// Use at start of multi-instruction macros. |
1 | 671 |
void assert_not_delayed() { |
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
672 |
// This is a separate entry to avoid the creation of string constants in |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
673 |
// non-asserted code, with some compilers this pollutes the object code. |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
674 |
#ifdef VALIDATE_PIPELINE |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
675 |
assert_no_delay("Next instruction should not be in a delay-slot."); |
1 | 676 |
#endif |
677 |
} |
|
678 |
||
679 |
protected: |
|
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
680 |
void assert_no_delay(const char* msg) { |
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|
681 |
#ifdef VALIDATE_PIPELINE |
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|
682 |
assert(_delay_state == NoDelay, msg); |
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|
683 |
#endif |
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|
684 |
} |
35090
1f5b6aa795d0
8144748: Move assembler/macroAssembler inline function definitions to corresponding inline.hpp files
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parents:
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changeset
|
685 |
|
46596
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|
686 |
void assert_no_hazard() { |
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|
687 |
#ifdef VALIDATE_PIPELINE |
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|
688 |
assert(_hazard_state == NoHazard, "Unsolicited pipeline hazard."); |
1 | 689 |
#endif |
690 |
} |
|
691 |
||
46596
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|
692 |
private: |
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|
693 |
inline int32_t prev_insn() { |
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|
694 |
assert(offset() > 0, "Interface violation."); |
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|
695 |
int32_t* addr = (int32_t*)pc() - 1; |
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|
696 |
return *addr; |
a7c9706d25a9
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|
697 |
} |
a7c9706d25a9
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changeset
|
698 |
|
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changeset
|
699 |
#ifdef VALIDATE_PIPELINE |
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|
700 |
void validate_no_pipeline_hazards(); |
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|
701 |
#endif |
a7c9706d25a9
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changeset
|
702 |
|
a7c9706d25a9
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|
703 |
protected: |
a7c9706d25a9
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|
704 |
// Avoid possible pipeline stall by inserting an additional 'nop' instruction, |
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|
705 |
// if the previous instruction is a 'cbcond' or a 'rdpc'. |
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|
706 |
inline void avoid_pipeline_stall(); |
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|
707 |
|
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changeset
|
708 |
// A call to cti() is made before emitting a control-transfer instruction (CTI) |
a7c9706d25a9
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|
709 |
// in order to assert a CTI is not emitted right after a 'cbcond', nor in the |
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|
710 |
// delay-slot of another CTI. Only effective when assertions are enabled. |
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|
711 |
void cti() { |
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changeset
|
712 |
// A 'cbcond' or 'rdpc' instruction immediately followed by a CTI introduces |
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|
713 |
// a pipeline stall, which we make sure to prohibit. |
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|
714 |
assert_no_cbcond_before(); |
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|
715 |
assert_no_rdpc_before(); |
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|
716 |
#ifdef VALIDATE_PIPELINE |
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|
717 |
assert_no_hazard(); |
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changeset
|
718 |
assert_no_delay("CTI in delay-slot."); |
1 | 719 |
#endif |
720 |
} |
|
721 |
||
46596
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|
722 |
// Called when emitting CTI with a delay-slot, AFTER emitting. |
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changeset
|
723 |
inline void induce_delay_slot() { |
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|
724 |
#ifdef VALIDATE_PIPELINE |
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|
725 |
assert_no_delay("Already in delay-slot."); |
a7c9706d25a9
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changeset
|
726 |
_delay_state = AtDelay; |
a7c9706d25a9
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changeset
|
727 |
#endif |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
728 |
} |
a7c9706d25a9
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diff
changeset
|
729 |
|
a7c9706d25a9
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changeset
|
730 |
inline void induce_pc_hazard() { |
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changeset
|
731 |
#ifdef VALIDATE_PIPELINE |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
732 |
assert_no_hazard(); |
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changeset
|
733 |
_hazard_state = PcHazard; |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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changeset
|
734 |
#endif |
10252 | 735 |
} |
736 |
||
46596
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|
737 |
bool is_cbcond_before() { return offset() > 0 ? is_cbcond(prev_insn()) : false; } |
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changeset
|
738 |
|
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
739 |
bool is_rdpc_before() { return offset() > 0 ? is_rdpc(prev_insn()) : false; } |
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changeset
|
740 |
|
a7c9706d25a9
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diff
changeset
|
741 |
void assert_no_cbcond_before() { |
a7c9706d25a9
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changeset
|
742 |
assert(offset() == 0 || !is_cbcond_before(), "CBCOND should not be followed by CTI."); |
10252 | 743 |
} |
10264 | 744 |
|
46596
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changeset
|
745 |
void assert_no_rdpc_before() { |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
746 |
assert(offset() == 0 || !is_rdpc_before(), "RDPC should not be followed by CTI."); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
747 |
} |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
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diff
changeset
|
748 |
|
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
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diff
changeset
|
749 |
public: |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
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diff
changeset
|
750 |
|
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
751 |
bool use_cbcond(Label &L) { |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
752 |
if (!UseCBCond || is_cbcond_before()) return false; |
10252 | 753 |
intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc()); |
46596
a7c9706d25a9
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parents:
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diff
changeset
|
754 |
assert((x & 3) == 0, "not word aligned"); |
11190
d561d41f241a
7003454: order constants in constant table by number of references in code
twisti
parents:
10519
diff
changeset
|
755 |
return is_simm12(x); |
10252 | 756 |
} |
757 |
||
1 | 758 |
// Tells assembler you know that next instruction is delayed |
759 |
Assembler* delayed() { |
|
46596
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diff
changeset
|
760 |
#ifdef VALIDATE_PIPELINE |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
761 |
assert(_delay_state == AtDelay, "Delayed instruction not in delay-slot."); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
762 |
_delay_state = FillDelay; |
1 | 763 |
#endif |
764 |
return this; |
|
765 |
} |
|
766 |
||
767 |
void flush() { |
|
46596
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diff
changeset
|
768 |
#ifdef VALIDATE_PIPELINE |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
769 |
assert(_delay_state == NoDelay, "Ending code with a delay-slot."); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
770 |
validate_no_pipeline_hazards(); |
1 | 771 |
#endif |
772 |
AbstractAssembler::flush(); |
|
773 |
} |
|
774 |
||
15116
af423dcb739c
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
parents:
14631
diff
changeset
|
775 |
inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 |
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
776 |
inline void emit_data(int); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
777 |
inline void emit_data(int, RelocationHolder const &rspec); |
1 | 778 |
inline void emit_data(int, relocInfo::relocType rtype); |
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
779 |
// helper for above functions |
1 | 780 |
inline void check_delay(); |
781 |
||
782 |
||
783 |
public: |
|
784 |
// instructions, refer to page numbers in the SPARC Architecture Manual, V9 |
|
785 |
||
46596
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changeset
|
786 |
// pp 135 |
1 | 787 |
|
46596
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8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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diff
changeset
|
788 |
inline void add(Register s1, Register s2, Register d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
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diff
changeset
|
789 |
inline void add(Register s1, int simm13a, Register d); |
1 | 790 |
|
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
791 |
inline void addcc(Register s1, Register s2, Register d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
792 |
inline void addcc(Register s1, int simm13a, Register d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
793 |
inline void addc(Register s1, Register s2, Register d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
794 |
inline void addc(Register s1, int simm13a, Register d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
795 |
inline void addccc(Register s1, Register s2, Register d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
796 |
inline void addccc(Register s1, int simm13a, Register d); |
1 | 797 |
|
10252 | 798 |
|
22505 | 799 |
// 4-operand AES instructions |
800 |
||
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
801 |
inline void aes_eround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
802 |
inline void aes_eround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
803 |
inline void aes_dround01(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
804 |
inline void aes_dround23(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
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changeset
|
805 |
inline void aes_eround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
806 |
inline void aes_eround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
neliasso
parents:
46594
diff
changeset
|
807 |
inline void aes_dround01_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
808 |
inline void aes_dround23_l(FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
809 |
inline void aes_kexpand1(FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d); |
22505 | 810 |
|
811 |
||
812 |
// 3-operand AES instructions |
|
813 |
||
46596
a7c9706d25a9
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parents:
46594
diff
changeset
|
814 |
inline void aes_kexpand0(FloatRegister s1, FloatRegister s2, FloatRegister d); |
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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parents:
46594
diff
changeset
|
815 |
inline void aes_kexpand2(FloatRegister s1, FloatRegister s2, FloatRegister d); |
22505 | 816 |
|
1 | 817 |
// pp 136 |
818 |
||
10252 | 819 |
inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); |
46596
a7c9706d25a9
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parents:
46594
diff
changeset
|
820 |
inline void bpr(RCondition c, bool a, Predict p, Register s1, Label &L); |
1 | 821 |
|
10264 | 822 |
// compare and branch |
46596
a7c9706d25a9
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parents:
46594
diff
changeset
|
823 |
inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label &L); |
a7c9706d25a9
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parents:
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diff
changeset
|
824 |
inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label &L); |
10264 | 825 |
|
1 | 826 |
protected: // use MacroAssembler::br instead |
827 |
||
828 |
// pp 138 |
|
829 |
||
46596
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parents:
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diff
changeset
|
830 |
inline void fb(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none); |
a7c9706d25a9
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changeset
|
831 |
inline void fb(Condition c, bool a, Label &L); |
1 | 832 |
|
833 |
// pp 141 |
|
834 |
||
46596
a7c9706d25a9
8144448: Avoid placing CTI immediately following or preceding RDPC instruction
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diff
changeset
|
835 |
inline void fbp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none); |
a7c9706d25a9
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parents:
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diff
changeset
|
836 |
inline void fbp(Condition c, bool a, CC cc, Predict p, Label &L); |
1 | 837 |
|
838 |
// pp 144 |
|
839 |
||
46596
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diff
changeset
|
840 |
inline void br(Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none); |
a7c9706d25a9
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|
841 |
inline void br(Condition c, bool a, Label &L); |
1 | 842 |
|
843 |
// pp 146 |
|
844 |
||
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|
845 |
inline void bp(Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none); |
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|
846 |
inline void bp(Condition c, bool a, CC cc, Predict p, Label &L); |
1 | 847 |
|
848 |
// pp 149 |
|
849 |
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|
850 |
inline void call(address d, relocInfo::relocType rt = relocInfo::runtime_call_type); |
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|
851 |
inline void call(Label &L, relocInfo::relocType rt = relocInfo::runtime_call_type); |
1 | 852 |
|
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|
853 |
inline void call(address d, RelocationHolder const &rspec); |
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|
854 |
|
10252 | 855 |
public: |
856 |
||
1 | 857 |
// pp 150 |
858 |
||
859 |
// These instructions compare the contents of s2 with the contents of |
|
860 |
// memory at address in s1. If the values are equal, the contents of memory |
|
861 |
// at address s1 is swapped with the data in d. If the values are not equal, |
|
862 |
// the the contents of memory at s1 is loaded into d, without the swap. |
|
863 |
||
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|
864 |
inline void casa(Register s1, Register s2, Register d, int ia = -1); |
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|
865 |
inline void casxa(Register s1, Register s2, Register d, int ia = -1); |
1 | 866 |
|
867 |
// pp 152 |
|
868 |
||
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|
869 |
inline void udiv(Register s1, Register s2, Register d); |
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870 |
inline void udiv(Register s1, int simm13a, Register d); |
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|
871 |
inline void sdiv(Register s1, Register s2, Register d); |
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|
872 |
inline void sdiv(Register s1, int simm13a, Register d); |
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|
873 |
inline void udivcc(Register s1, Register s2, Register d); |
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|
874 |
inline void udivcc(Register s1, int simm13a, Register d); |
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|
875 |
inline void sdivcc(Register s1, Register s2, Register d); |
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|
876 |
inline void sdivcc(Register s1, int simm13a, Register d); |
1 | 877 |
|
878 |
// pp 155 |
|
879 |
||
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|
880 |
inline void done(); |
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|
881 |
inline void retry(); |
1 | 882 |
|
883 |
// pp 156 |
|
884 |
||
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885 |
inline void fadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); |
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|
886 |
inline void fsub(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); |
1 | 887 |
|
888 |
// pp 157 |
|
889 |
||
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|
890 |
inline void fcmp(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2); |
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|
891 |
inline void fcmpe(FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2); |
1 | 892 |
|
893 |
// pp 159 |
|
894 |
||
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|
895 |
inline void ftox(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
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|
896 |
inline void ftoi(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
1 | 897 |
|
898 |
// pp 160 |
|
899 |
||
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|
900 |
inline void ftof(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d); |
1 | 901 |
|
902 |
// pp 161 |
|
903 |
||
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|
904 |
inline void fxtof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
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|
905 |
inline void fitof(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
1 | 906 |
|
907 |
// pp 162 |
|
908 |
||
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|
909 |
inline void fmov(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
1 | 910 |
|
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|
911 |
inline void fneg(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
1 | 912 |
|
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|
913 |
inline void fabs(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
1 | 914 |
|
915 |
// pp 163 |
|
916 |
||
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|
917 |
inline void fmul(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); |
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|
918 |
inline void fmul(FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d); |
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|
919 |
inline void fdiv(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); |
1 | 920 |
|
22505 | 921 |
// FXORs/FXORd instructions |
922 |
||
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|
923 |
inline void fxor(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d); |
22505 | 924 |
|
1 | 925 |
// pp 164 |
926 |
||
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|
927 |
inline void fsqrt(FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); |
1 | 928 |
|
46597
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|
929 |
// fmaf instructions. |
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|
930 |
|
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|
931 |
inline void fmadd(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d); |
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|
932 |
|
1 | 933 |
// pp 165 |
934 |
||
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|
935 |
inline void flush(Register s1, Register s2); |
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|
936 |
inline void flush(Register s1, int simm13a); |
1 | 937 |
|
938 |
// pp 167 |
|
939 |
||
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|
940 |
void flushw(); |
1 | 941 |
|
942 |
// pp 168 |
|
943 |
||
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|
944 |
void illtrap(int const22a); |
1 | 945 |
|
946 |
// pp 169 |
|
947 |
||
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|
948 |
void impdep1(int id1, int const19a); |
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|
949 |
void impdep2(int id1, int const19a); |
1 | 950 |
|
951 |
// pp 170 |
|
952 |
||
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|
953 |
void jmpl(Register s1, Register s2, Register d); |
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|
954 |
void jmpl(Register s1, int simm13a, Register d, |
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|
955 |
RelocationHolder const &rspec = RelocationHolder()); |
1 | 956 |
|
957 |
// 171 |
|
958 |
||
2571 | 959 |
inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); |
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|
960 |
inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, |
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|
961 |
RelocationHolder const &rspec = RelocationHolder()); |
2571 | 962 |
|
1 | 963 |
|
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|
964 |
inline void ldfsr(Register s1, Register s2); |
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|
965 |
inline void ldfsr(Register s1, int simm13a); |
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|
966 |
inline void ldxfsr(Register s1, Register s2); |
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|
967 |
inline void ldxfsr(Register s1, int simm13a); |
1 | 968 |
|
969 |
// 173 |
|
970 |
||
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|
971 |
inline void ldfa(FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d); |
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|
972 |
inline void ldfa(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d); |
1 | 973 |
|
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|
974 |
// pp 175 |
1 | 975 |
|
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|
976 |
inline void ldsb(Register s1, Register s2, Register d); |
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|
977 |
inline void ldsb(Register s1, int simm13a, Register d); |
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|
978 |
inline void ldsh(Register s1, Register s2, Register d); |
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|
979 |
inline void ldsh(Register s1, int simm13a, Register d); |
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|
980 |
inline void ldsw(Register s1, Register s2, Register d); |
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|
981 |
inline void ldsw(Register s1, int simm13a, Register d); |
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|
982 |
inline void ldub(Register s1, Register s2, Register d); |
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|
983 |
inline void ldub(Register s1, int simm13a, Register d); |
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|
984 |
inline void lduh(Register s1, Register s2, Register d); |
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|
985 |
inline void lduh(Register s1, int simm13a, Register d); |
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|
986 |
inline void lduw(Register s1, Register s2, Register d); |
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|
987 |
inline void lduw(Register s1, int simm13a, Register d); |
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|
988 |
inline void ldx(Register s1, Register s2, Register d); |
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|
989 |
inline void ldx(Register s1, int simm13a, Register d); |
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|
990 |
inline void ldd(Register s1, Register s2, Register d); |
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|
991 |
inline void ldd(Register s1, int simm13a, Register d); |
1 | 992 |
|
993 |
// pp 177 |
|
994 |
||
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|
995 |
inline void ldsba(Register s1, Register s2, int ia, Register d); |
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|
996 |
inline void ldsba(Register s1, int simm13a, Register d); |
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|
997 |
inline void ldsha(Register s1, Register s2, int ia, Register d); |
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|
998 |
inline void ldsha(Register s1, int simm13a, Register d); |
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|
999 |
inline void ldswa(Register s1, Register s2, int ia, Register d); |
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|
1000 |
inline void ldswa(Register s1, int simm13a, Register d); |
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|
1001 |
inline void lduba(Register s1, Register s2, int ia, Register d); |
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|
1002 |
inline void lduba(Register s1, int simm13a, Register d); |
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|
1003 |
inline void lduha(Register s1, Register s2, int ia, Register d); |
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|
1004 |
inline void lduha(Register s1, int simm13a, Register d); |
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|
1005 |
inline void lduwa(Register s1, Register s2, int ia, Register d); |
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|
1006 |
inline void lduwa(Register s1, int simm13a, Register d); |
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|
1007 |
inline void ldxa(Register s1, Register s2, int ia, Register d); |
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|
1008 |
inline void ldxa(Register s1, int simm13a, Register d); |
1 | 1009 |
|
1010 |
// pp 181 |
|
1011 |
||
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|
1012 |
inline void and3(Register s1, Register s2, Register d); |
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|
1013 |
inline void and3(Register s1, int simm13a, Register d); |
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|
1014 |
inline void andcc(Register s1, Register s2, Register d); |
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|
1015 |
inline void andcc(Register s1, int simm13a, Register d); |
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1016 |
inline void andn(Register s1, Register s2, Register d); |
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1017 |
inline void andn(Register s1, int simm13a, Register d); |
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1018 |
inline void andncc(Register s1, Register s2, Register d); |
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|
1019 |
inline void andncc(Register s1, int simm13a, Register d); |
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1020 |
inline void or3(Register s1, Register s2, Register d); |
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|
1021 |
inline void or3(Register s1, int simm13a, Register d); |
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1022 |
inline void orcc(Register s1, Register s2, Register d); |
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|
1023 |
inline void orcc(Register s1, int simm13a, Register d); |
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1024 |
inline void orn(Register s1, Register s2, Register d); |
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1025 |
inline void orn(Register s1, int simm13a, Register d); |
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1026 |
inline void orncc(Register s1, Register s2, Register d); |
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1027 |
inline void orncc(Register s1, int simm13a, Register d); |
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1028 |
inline void xor3(Register s1, Register s2, Register d); |
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1029 |
inline void xor3(Register s1, int simm13a, Register d); |
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1030 |
inline void xorcc(Register s1, Register s2, Register d); |
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1031 |
inline void xorcc(Register s1, int simm13a, Register d); |
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1032 |
inline void xnor(Register s1, Register s2, Register d); |
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1033 |
inline void xnor(Register s1, int simm13a, Register d); |
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1034 |
inline void xnorcc(Register s1, Register s2, Register d); |
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|
1035 |
inline void xnorcc(Register s1, int simm13a, Register d); |
1 | 1036 |
|
1037 |
// pp 183 |
|
1038 |
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1039 |
inline void membar(Membar_mask_bits const7a); |
1 | 1040 |
|
1041 |
// pp 185 |
|
1042 |
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|
1043 |
inline void fmov(FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d); |
1 | 1044 |
|
1045 |
// pp 189 |
|
1046 |
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1047 |
inline void fmov(FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d); |
1 | 1048 |
|
1049 |
// pp 191 |
|
1050 |
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1051 |
inline void movcc(Condition c, bool floatCC, CC cca, Register s2, Register d); |
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1052 |
inline void movcc(Condition c, bool floatCC, CC cca, int simm11a, Register d); |
1 | 1053 |
|
1054 |
// pp 195 |
|
1055 |
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1056 |
inline void movr(RCondition c, Register s1, Register s2, Register d); |
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1057 |
inline void movr(RCondition c, Register s1, int simm10a, Register d); |
1 | 1058 |
|
1059 |
// pp 196 |
|
1060 |
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|
1061 |
inline void mulx(Register s1, Register s2, Register d); |
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|
1062 |
inline void mulx(Register s1, int simm13a, Register d); |
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|
1063 |
inline void sdivx(Register s1, Register s2, Register d); |
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|
1064 |
inline void sdivx(Register s1, int simm13a, Register d); |
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|
1065 |
inline void udivx(Register s1, Register s2, Register d); |
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1066 |
inline void udivx(Register s1, int simm13a, Register d); |
1 | 1067 |
|
1068 |
// pp 197 |
|
1069 |
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|
1070 |
inline void umul(Register s1, Register s2, Register d); |
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|
1071 |
inline void umul(Register s1, int simm13a, Register d); |
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1072 |
inline void smul(Register s1, Register s2, Register d); |
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|
1073 |
inline void smul(Register s1, int simm13a, Register d); |
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|
1074 |
inline void umulcc(Register s1, Register s2, Register d); |
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1075 |
inline void umulcc(Register s1, int simm13a, Register d); |
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|
1076 |
inline void smulcc(Register s1, Register s2, Register d); |
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|
1077 |
inline void smulcc(Register s1, int simm13a, Register d); |
1 | 1078 |
|
1079 |
// pp 201 |
|
1080 |
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|
1081 |
inline void nop(); |
1 | 1082 |
|
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1083 |
inline void sw_count(); |
1 | 1084 |
|
1085 |
// pp 202 |
|
1086 |
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|
1087 |
inline void popc(Register s, Register d); |
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|
1088 |
inline void popc(int simm13a, Register d); |
1 | 1089 |
|
1090 |
// pp 203 |
|
1091 |
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|
1092 |
inline void prefetch(Register s1, Register s2, PrefetchFcn f); |
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|
1093 |
inline void prefetch(Register s1, int simm13a, PrefetchFcn f); |
14631
526804361522
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|
1094 |
|
46596
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|
1095 |
inline void prefetcha(Register s1, Register s2, int ia, PrefetchFcn f); |
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|
1096 |
inline void prefetcha(Register s1, int simm13a, PrefetchFcn f); |
1 | 1097 |
|
1098 |
// pp 208 |
|
1099 |
||
1100 |
// not implementing read privileged register |
|
1101 |
||
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|
1102 |
inline void rdy(Register d); |
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|
1103 |
inline void rdccr(Register d); |
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|
1104 |
inline void rdasi(Register d); |
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|
1105 |
inline void rdtick(Register d); |
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|
1106 |
inline void rdpc(Register d); |
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|
1107 |
inline void rdfprs(Register d); |
1 | 1108 |
|
1109 |
// pp 213 |
|
1110 |
||
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|
1111 |
inline void rett(Register s1, Register s2); |
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|
1112 |
inline void rett(Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); |
1 | 1113 |
|
1114 |
// pp 214 |
|
1115 |
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|
1116 |
inline void save(Register s1, Register s2, Register d); |
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|
1117 |
inline void save(Register s1, int simm13a, Register d); |
1 | 1118 |
|
46596
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|
1119 |
inline void restore(Register s1 = G0, Register s2 = G0, Register d = G0); |
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|
1120 |
inline void restore(Register s1, int simm13a, Register d); |
1 | 1121 |
|
1122 |
// pp 216 |
|
1123 |
||
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|
1124 |
inline void saved(); |
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|
1125 |
inline void restored(); |
1 | 1126 |
|
1127 |
// pp 217 |
|
1128 |
||
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|
1129 |
inline void sethi(int imm22a, Register d, RelocationHolder const &rspec = RelocationHolder()); |
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|
1130 |
|
1 | 1131 |
// pp 218 |
1132 |
||
46596
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|
1133 |
inline void sll(Register s1, Register s2, Register d); |
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|
1134 |
inline void sll(Register s1, int imm5a, Register d); |
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|
1135 |
inline void srl(Register s1, Register s2, Register d); |
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|
1136 |
inline void srl(Register s1, int imm5a, Register d); |
a7c9706d25a9
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|
1137 |
inline void sra(Register s1, Register s2, Register d); |
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|
1138 |
inline void sra(Register s1, int imm5a, Register d); |
1 | 1139 |
|
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|
1140 |
inline void sllx(Register s1, Register s2, Register d); |
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|
1141 |
inline void sllx(Register s1, int imm6a, Register d); |
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|
1142 |
inline void srlx(Register s1, Register s2, Register d); |
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|
1143 |
inline void srlx(Register s1, int imm6a, Register d); |
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|
1144 |
inline void srax(Register s1, Register s2, Register d); |
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|
1145 |
inline void srax(Register s1, int imm6a, Register d); |
1 | 1146 |
|
1147 |
// pp 220 |
|
1148 |
||
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|
1149 |
inline void sir(int simm13a); |
1 | 1150 |
|
1151 |
// pp 221 |
|
1152 |
||
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|
1153 |
inline void stbar(); |
1 | 1154 |
|
1155 |
// pp 222 |
|
1156 |
||
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|
1157 |
inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); |
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|
1158 |
inline void stf(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); |
1 | 1159 |
|
46596
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|
1160 |
inline void stfsr(Register s1, Register s2); |
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|
1161 |
inline void stfsr(Register s1, int simm13a); |
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|
1162 |
inline void stxfsr(Register s1, Register s2); |
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|
1163 |
inline void stxfsr(Register s1, int simm13a); |
1 | 1164 |
|
46596
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|
1165 |
// pp 224 |
1 | 1166 |
|
46596
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|
1167 |
inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia); |
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|
1168 |
inline void stfa(FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); |
1 | 1169 |
|
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|
1170 |
// pp 226 |
1 | 1171 |
|
46596
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|
1172 |
inline void stb(Register d, Register s1, Register s2); |
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|
1173 |
inline void stb(Register d, Register s1, int simm13a); |
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|
1174 |
inline void sth(Register d, Register s1, Register s2); |
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|
1175 |
inline void sth(Register d, Register s1, int simm13a); |
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|
1176 |
inline void stw(Register d, Register s1, Register s2); |
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|
1177 |
inline void stw(Register d, Register s1, int simm13a); |
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|
1178 |
inline void stx(Register d, Register s1, Register s2); |
a7c9706d25a9
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changeset
|
1179 |
inline void stx(Register d, Register s1, int simm13a); |
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1180 |
inline void std(Register d, Register s1, Register s2); |
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1181 |
inline void std(Register d, Register s1, int simm13a); |
1 | 1182 |
|
1183 |
// pp 177 |
|
1184 |
||
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1185 |
inline void stba(Register d, Register s1, Register s2, int ia); |
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1186 |
inline void stba(Register d, Register s1, int simm13a); |
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1187 |
inline void stha(Register d, Register s1, Register s2, int ia); |
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1188 |
inline void stha(Register d, Register s1, int simm13a); |
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1189 |
inline void stwa(Register d, Register s1, Register s2, int ia); |
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1190 |
inline void stwa(Register d, Register s1, int simm13a); |
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1191 |
inline void stxa(Register d, Register s1, Register s2, int ia); |
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1192 |
inline void stxa(Register d, Register s1, int simm13a); |
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1193 |
inline void stda(Register d, Register s1, Register s2, int ia); |
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1194 |
inline void stda(Register d, Register s1, int simm13a); |
1 | 1195 |
|
1196 |
// pp 230 |
|
1197 |
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1198 |
inline void sub(Register s1, Register s2, Register d); |
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1199 |
inline void sub(Register s1, int simm13a, Register d); |
7433 | 1200 |
|
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1201 |
inline void subcc(Register s1, Register s2, Register d); |
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1202 |
inline void subcc(Register s1, int simm13a, Register d); |
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1203 |
inline void subc(Register s1, Register s2, Register d); |
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1204 |
inline void subc(Register s1, int simm13a, Register d); |
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1205 |
inline void subccc(Register s1, Register s2, Register d); |
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1206 |
inline void subccc(Register s1, int simm13a, Register d); |
1 | 1207 |
|
1208 |
// pp 231 |
|
1209 |
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1210 |
inline void swap(Register s1, Register s2, Register d); |
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1211 |
inline void swap(Register s1, int simm13a, Register d); |
1 | 1212 |
|
1213 |
// pp 232 |
|
1214 |
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1215 |
inline void swapa(Register s1, Register s2, int ia, Register d); |
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1216 |
inline void swapa(Register s1, int simm13a, Register d); |
1 | 1217 |
|
1218 |
// pp 234, note op in book is wrong, see pp 268 |
|
1219 |
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1220 |
inline void taddcc(Register s1, Register s2, Register d); |
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1221 |
inline void taddcc(Register s1, int simm13a, Register d); |
1 | 1222 |
|
1223 |
// pp 235 |
|
1224 |
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1225 |
inline void tsubcc(Register s1, Register s2, Register d); |
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1226 |
inline void tsubcc(Register s1, int simm13a, Register d); |
1 | 1227 |
|
1228 |
// pp 237 |
|
1229 |
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1230 |
inline void trap(Condition c, CC cc, Register s1, Register s2); |
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1231 |
inline void trap(Condition c, CC cc, Register s1, int trapa); |
1 | 1232 |
// simple uncond. trap |
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1233 |
inline void trap(int trapa); |
1 | 1234 |
|
1235 |
// pp 239 omit write priv register for now |
|
1236 |
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1237 |
inline void wry(Register d); |
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1238 |
inline void wrccr(Register s); |
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1239 |
inline void wrccr(Register s, int simm13a); |
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1240 |
inline void wrasi(Register d); |
10501 | 1241 |
// wrasi(d, imm) stores (d xor imm) to asi |
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1242 |
inline void wrasi(Register d, int simm13a); |
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1243 |
inline void wrfprs(Register d); |
1 | 1244 |
|
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1245 |
// VIS1 instructions |
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|
1246 |
|
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1247 |
inline void alignaddr(Register s1, Register s2, Register d); |
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|
1248 |
|
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1249 |
inline void faligndata(FloatRegister s1, FloatRegister s2, FloatRegister d); |
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1250 |
|
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1251 |
inline void fzero(FloatRegisterImpl::Width w, FloatRegister d); |
31515 | 1252 |
|
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1253 |
inline void fsrc2(FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d); |
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|
1254 |
|
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1255 |
inline void fnot1(FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d); |
31515 | 1256 |
|
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1257 |
inline void fpmerge(FloatRegister s1, FloatRegister s2, FloatRegister d); |
31515 | 1258 |
|
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1259 |
inline void stpartialf(Register s1, Register s2, FloatRegister d, int ia = -1); |
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|
1260 |
|
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|
1261 |
// VIS2 instructions |
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|
1262 |
|
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|
1263 |
inline void edge8n(Register s1, Register s2, Register d); |
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|
1264 |
|
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|
1265 |
inline void bmask(Register s1, Register s2, Register d); |
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|
1266 |
inline void bshuffle(FloatRegister s1, FloatRegister s2, FloatRegister d); |
33628 | 1267 |
|
10027 | 1268 |
// VIS3 instructions |
1269 |
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|
1270 |
inline void movstosw(FloatRegister s, Register d); |
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|
1271 |
inline void movstouw(FloatRegister s, Register d); |
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|
1272 |
inline void movdtox(FloatRegister s, Register d); |
10027 | 1273 |
|
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1274 |
inline void movwtos(Register s, FloatRegister d); |
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|
1275 |
inline void movxtod(Register s, FloatRegister d); |
10027 | 1276 |
|
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1277 |
inline void xmulx(Register s1, Register s2, Register d); |
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|
1278 |
inline void xmulxhi(Register s1, Register s2, Register d); |
31404
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|
1279 |
|
24953
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|
1280 |
// Crypto SHA instructions |
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|
1281 |
|
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|
1282 |
inline void sha1(); |
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|
1283 |
inline void sha256(); |
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|
1284 |
inline void sha512(); |
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|
1285 |
|
31515 | 1286 |
// CRC32C instruction |
1287 |
||
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|
1288 |
inline void crc32c(FloatRegister s1, FloatRegister s2, FloatRegister d); |
31515 | 1289 |
|
1 | 1290 |
// Creation |
1291 |
Assembler(CodeBuffer* code) : AbstractAssembler(code) { |
|
46596
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|
1292 |
#ifdef VALIDATE_PIPELINE |
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|
1293 |
_delay_state = NoDelay; |
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|
1294 |
_hazard_state = NoHazard; |
1 | 1295 |
#endif |
1296 |
} |
|
1297 |
}; |
|
1298 |
||
7397 | 1299 |
#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |