/*

 * Copyright 1997-2007 Sun Microsystems, Inc.  All Rights Reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

 * CA 95054 USA or visit www.sun.com if you need additional information or

 * have any questions.

 *

 */

#include "incls/_precompiled.incl"

#include "incls/_assembler_x86_32.cpp.incl"

// Implementation of AddressLiteral

AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {

  _is_lval = false;

  _target = target;

  switch (rtype) {

  case relocInfo::oop_type:

    // Oops are a special case. Normally they would be their own section

    // but in cases like icBuffer they are literals in the code stream that

    // we don't have a section for. We use none so that we get a literal address

    // which is always patchable.

    break;

  case relocInfo::external_word_type:

    _rspec = external_word_Relocation::spec(target);

    break;

  case relocInfo::internal_word_type:

    _rspec = internal_word_Relocation::spec(target);

    break;

  case relocInfo::opt_virtual_call_type:

    _rspec = opt_virtual_call_Relocation::spec();

    break;

  case relocInfo::static_call_type:

    _rspec = static_call_Relocation::spec();

    break;

  case relocInfo::runtime_call_type:

    _rspec = runtime_call_Relocation::spec();

    break;

  case relocInfo::poll_type:

  case relocInfo::poll_return_type:

    _rspec = Relocation::spec_simple(rtype);

    break;

  case relocInfo::none:

    break;

  default:

    ShouldNotReachHere();

    break;

  }

}

// Implementation of Address

Address Address::make_array(ArrayAddress adr) {

#ifdef _LP64

  // Not implementable on 64bit machines

  // Should have been handled higher up the call chain.

  ShouldNotReachHere();

#else

  AddressLiteral base = adr.base();

  Address index = adr.index();

  assert(index._disp == 0, "must not have disp"); // maybe it can?

  Address array(index._base, index._index, index._scale, (intptr_t) base.target());

  array._rspec = base._rspec;

  return array;

#endif // _LP64

}

#ifndef _LP64

// exceedingly dangerous constructor

Address::Address(address loc, RelocationHolder spec) {

  _base  = noreg;

  _index = noreg;

  _scale = no_scale;

  _disp  = (intptr_t) loc;

  _rspec = spec;

}

#endif // _LP64

// Convert the raw encoding form into the form expected by the constructor for

// Address.  An index of 4 (rsp) corresponds to having no index, so convert

// that to noreg for the Address constructor.

Address Address::make_raw(int base, int index, int scale, int disp) {

  bool valid_index = index != rsp->encoding();

  if (valid_index) {

    Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));

    return madr;

  } else {

    Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));

    return madr;

  }

}

// Implementation of Assembler

int AbstractAssembler::code_fill_byte() {

  return (u_char)'\xF4'; // hlt

}

// make this go away someday

void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {

  if (rtype == relocInfo::none)

        emit_long(data);

  else  emit_data(data, Relocation::spec_simple(rtype), format);

}

void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {

  assert(imm32_operand == 0, "default format must be imm32 in this file");

  assert(inst_mark() != NULL, "must be inside InstructionMark");

  if (rspec.type() !=  relocInfo::none) {

    #ifdef ASSERT

      check_relocation(rspec, format);

    #endif

    // Do not use AbstractAssembler::relocate, which is not intended for

    // embedded words.  Instead, relocate to the enclosing instruction.

    // hack. call32 is too wide for mask so use disp32

    if (format == call32_operand)

      code_section()->relocate(inst_mark(), rspec, disp32_operand);

    else

      code_section()->relocate(inst_mark(), rspec, format);

  }

  emit_long(data);

}

void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {

  assert(dst->has_byte_register(), "must have byte register");

  assert(isByte(op1) && isByte(op2), "wrong opcode");

  assert(isByte(imm8), "not a byte");

  assert((op1 & 0x01) == 0, "should be 8bit operation");

  emit_byte(op1);

  emit_byte(op2 | dst->encoding());

  emit_byte(imm8);

}

void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {

  assert(isByte(op1) && isByte(op2), "wrong opcode");

  assert((op1 & 0x01) == 1, "should be 32bit operation");

  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

  if (is8bit(imm32)) {

    emit_byte(op1 | 0x02); // set sign bit

    emit_byte(op2 | dst->encoding());

    emit_byte(imm32 & 0xFF);

  } else {

    emit_byte(op1);

    emit_byte(op2 | dst->encoding());

    emit_long(imm32);

  }

}

// immediate-to-memory forms

void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) {

  assert((op1 & 0x01) == 1, "should be 32bit operation");

  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

  if (is8bit(imm32)) {

    emit_byte(op1 | 0x02); // set sign bit

    emit_operand(rm,adr);

    emit_byte(imm32 & 0xFF);

  } else {

    emit_byte(op1);

    emit_operand(rm,adr);

    emit_long(imm32);

  }

}

void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {

  assert(isByte(op1) && isByte(op2), "wrong opcode");

  assert((op1 & 0x01) == 1, "should be 32bit operation");

  assert((op1 & 0x02) == 0, "sign-extension bit should not be set");

  InstructionMark im(this);

  emit_byte(op1);

  emit_byte(op2 | dst->encoding());

  emit_data((int)obj, relocInfo::oop_type, 0);

}

void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {

  assert(isByte(op1) && isByte(op2), "wrong opcode");

  emit_byte(op1);

  emit_byte(op2 | dst->encoding() << 3 | src->encoding());

}

void Assembler::emit_operand(Register reg,

                             Register base,

                             Register index,

                             Address::ScaleFactor scale,

                             int disp,

                             RelocationHolder const& rspec) {

  relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();

  if (base->is_valid()) {

    if (index->is_valid()) {

      assert(scale != Address::no_scale, "inconsistent address");

      // [base + index*scale + disp]

      if (disp == 0 && rtype == relocInfo::none && base != rbp) {

        // [base + index*scale]

        // [00 reg 100][ss index base]

        assert(index != rsp, "illegal addressing mode");

        emit_byte(0x04 | reg->encoding() << 3);

        emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());

      } else if (is8bit(disp) && rtype == relocInfo::none) {

        // [base + index*scale + imm8]

        // [01 reg 100][ss index base] imm8

        assert(index != rsp, "illegal addressing mode");

        emit_byte(0x44 | reg->encoding() << 3);

        emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());

        emit_byte(disp & 0xFF);

      } else {

        // [base + index*scale + imm32]

        // [10 reg 100][ss index base] imm32

        assert(index != rsp, "illegal addressing mode");

        emit_byte(0x84 | reg->encoding() << 3);

        emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());

        emit_data(disp, rspec, disp32_operand);

      }

    } else if (base == rsp) {

      // [esp + disp]

      if (disp == 0 && rtype == relocInfo::none) {

        // [esp]

        // [00 reg 100][00 100 100]

        emit_byte(0x04 | reg->encoding() << 3);

        emit_byte(0x24);

      } else if (is8bit(disp) && rtype == relocInfo::none) {

        // [esp + imm8]

        // [01 reg 100][00 100 100] imm8

        emit_byte(0x44 | reg->encoding() << 3);

        emit_byte(0x24);

        emit_byte(disp & 0xFF);

      } else {

        // [esp + imm32]

        // [10 reg 100][00 100 100] imm32

        emit_byte(0x84 | reg->encoding() << 3);

        emit_byte(0x24);

        emit_data(disp, rspec, disp32_operand);

      }

    } else {

      // [base + disp]

      assert(base != rsp, "illegal addressing mode");

      if (disp == 0 && rtype == relocInfo::none && base != rbp) {

        // [base]

        // [00 reg base]

        assert(base != rbp, "illegal addressing mode");

        emit_byte(0x00 | reg->encoding() << 3 | base->encoding());

      } else if (is8bit(disp) && rtype == relocInfo::none) {

        // [base + imm8]

        // [01 reg base] imm8

        emit_byte(0x40 | reg->encoding() << 3 | base->encoding());

        emit_byte(disp & 0xFF);

      } else {

        // [base + imm32]

        // [10 reg base] imm32

        emit_byte(0x80 | reg->encoding() << 3 | base->encoding());

        emit_data(disp, rspec, disp32_operand);

      }

    }

  } else {

    if (index->is_valid()) {

      assert(scale != Address::no_scale, "inconsistent address");

      // [index*scale + disp]

      // [00 reg 100][ss index 101] imm32

      assert(index != rsp, "illegal addressing mode");

      emit_byte(0x04 | reg->encoding() << 3);

      emit_byte(scale << 6 | index->encoding() << 3 | 0x05);

      emit_data(disp, rspec, disp32_operand);

    } else {

      // [disp]

      // [00 reg 101] imm32

      emit_byte(0x05 | reg->encoding() << 3);

      emit_data(disp, rspec, disp32_operand);

    }

  }

}

// Secret local extension to Assembler::WhichOperand:

#define end_pc_operand (_WhichOperand_limit)

address Assembler::locate_operand(address inst, WhichOperand which) {

  // Decode the given instruction, and return the address of

  // an embedded 32-bit operand word.

  // If "which" is disp32_operand, selects the displacement portion

  // of an effective address specifier.

  // If "which" is imm32_operand, selects the trailing immediate constant.

  // If "which" is call32_operand, selects the displacement of a call or jump.

  // Caller is responsible for ensuring that there is such an operand,

  // and that it is 32 bits wide.

  // If "which" is end_pc_operand, find the end of the instruction.

  address ip = inst;

  debug_only(bool has_imm32 = false);

  int tail_size = 0;    // other random bytes (#32, #16, etc.) at end of insn

 again_after_prefix:

  switch (0xFF & *ip++) {

  // These convenience macros generate groups of "case" labels for the switch.

  #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3

  #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \

             case (x)+4: case (x)+5: case (x)+6: case (x)+7

  #define REP16(x) REP8((x)+0): \

              case REP8((x)+8)

  case CS_segment:

  case SS_segment:

  case DS_segment:

  case ES_segment:

  case FS_segment:

  case GS_segment:

    assert(ip == inst+1, "only one prefix allowed");

    goto again_after_prefix;

  case 0xFF: // pushl a; decl a; incl a; call a; jmp a

  case 0x88: // movb a, r

  case 0x89: // movl a, r

  case 0x8A: // movb r, a

  case 0x8B: // movl r, a

  case 0x8F: // popl a

    break;

  case 0x68: // pushl #32(oop?)

    if (which == end_pc_operand)  return ip + 4;

    assert(which == imm32_operand, "pushl has no disp32");

    return ip;                  // not produced by emit_operand

  case 0x66: // movw ... (size prefix)

    switch (0xFF & *ip++) {

    case 0x8B: // movw r, a

    case 0x89: // movw a, r

      break;

    case 0xC7: // movw a, #16

      tail_size = 2;  // the imm16

      break;

    case 0x0F: // several SSE/SSE2 variants

      ip--;    // reparse the 0x0F

      goto again_after_prefix;

    default:

      ShouldNotReachHere();

    }

    break;

  case REP8(0xB8): // movl r, #32(oop?)

    if (which == end_pc_operand)  return ip + 4;

    assert(which == imm32_operand || which == disp32_operand, "");

    return ip;

  case 0x69: // imul r, a, #32

  case 0xC7: // movl a, #32(oop?)

    tail_size = 4;

    debug_only(has_imm32 = true); // has both kinds of operands!

    break;

  case 0x0F: // movx..., etc.

    switch (0xFF & *ip++) {

    case 0x12: // movlps

    case 0x28: // movaps

    case 0x2E: // ucomiss

    case 0x2F: // comiss

    case 0x54: // andps

    case 0x55: // andnps

    case 0x56: // orps

    case 0x57: // xorps

    case 0x6E: // movd

    case 0x7E: // movd

    case 0xAE: // ldmxcsr   a

      // amd side says it these have both operands but that doesn't

      // appear to be true.

      // debug_only(has_imm32 = true); // has both kinds of operands!

      break;

    case 0xAD: // shrd r, a, %cl

    case 0xAF: // imul r, a

    case 0xBE: // movsxb r, a

    case 0xBF: // movsxw r, a

    case 0xB6: // movzxb r, a

    case 0xB7: // movzxw r, a

    case REP16(0x40): // cmovl cc, r, a

    case 0xB0: // cmpxchgb

    case 0xB1: // cmpxchg

    case 0xC1: // xaddl

    case 0xC7: // cmpxchg8

    case REP16(0x90): // setcc a

      // fall out of the switch to decode the address

      break;

    case 0xAC: // shrd r, a, #8

      tail_size = 1;  // the imm8

      break;

    case REP16(0x80): // jcc rdisp32

      if (which == end_pc_operand)  return ip + 4;

      assert(which == call32_operand, "jcc has no disp32 or imm32");

      return ip;

    default:

      ShouldNotReachHere();

    }

    break;

  case 0x81: // addl a, #32; addl r, #32

    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl

    // in the case of cmpl, the imm32 might be an oop

    tail_size = 4;

    debug_only(has_imm32 = true); // has both kinds of operands!

    break;

  case 0x85: // test r/m, r

    break;

  case 0x83: // addl a, #8; addl r, #8

    // also: orl, adcl, sbbl, andl, subl, xorl, cmpl

    tail_size = 1;

    break;

  case 0x9B:

    switch (0xFF & *ip++) {

    case 0xD9: // fnstcw a

      break;

    default:

      ShouldNotReachHere();

    }

    break;

  case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a

  case REP4(0x10): // adc...

  case REP4(0x20): // and...

  case REP4(0x30): // xor...

  case REP4(0x08): // or...

  case REP4(0x18): // sbb...

  case REP4(0x28): // sub...

  case REP4(0x38): // cmp...

  case 0xF7: // mull a

  case 0x8D: // leal r, a

  case 0x87: // xchg r, a

    break;

  case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8

  case 0xC6: // movb a, #8

  case 0x80: // cmpb a, #8

  case 0x6B: // imul r, a, #8

    tail_size = 1; // the imm8

    break;

  case 0xE8: // call rdisp32

  case 0xE9: // jmp  rdisp32

    if (which == end_pc_operand)  return ip + 4;

    assert(which == call32_operand, "call has no disp32 or imm32");

    return ip;

  case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1

  case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl

  case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a

  case 0xDD: // fld_d a; fst_d a; fstp_d a

  case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a

  case 0xDF: // fild_d a; fistp_d a

  case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a

  case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a

  case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a

    break;

  case 0xF3:                    // For SSE

  case 0xF2:                    // For SSE2

    ip++; ip++;

    break;

  default:

    ShouldNotReachHere();

  #undef REP8

  #undef REP16

  }

  assert(which != call32_operand, "instruction is not a call, jmp, or jcc");

  assert(which != imm32_operand || has_imm32, "instruction has no imm32 field");

  // parse the output of emit_operand

  int op2 = 0xFF & *ip++;

  int base = op2 & 0x07;

  int op3 = -1;

  const int b100 = 4;

  const int b101 = 5;

  if (base == b100 && (op2 >> 6) != 3) {

    op3 = 0xFF & *ip++;

    base = op3 & 0x07;   // refetch the base

  }

  // now ip points at the disp (if any)

  switch (op2 >> 6) {

  case 0:

    // [00 reg  100][ss index base]

    // [00 reg  100][00   100  rsp]

    // [00 reg base]

    // [00 reg  100][ss index  101][disp32]

    // [00 reg  101]               [disp32]

    if (base == b101) {

      if (which == disp32_operand)

        return ip;              // caller wants the disp32

      ip += 4;                  // skip the disp32

    }

    break;

  case 1:

    // [01 reg  100][ss index base][disp8]

    // [01 reg  100][00   100  rsp][disp8]

    // [01 reg base]               [disp8]

    ip += 1;                    // skip the disp8

    break;

  case 2: