jdk-sandbox: jdk/test/sun/tools/jstat/lineCounts3.awk@b51428cf0edf (annotated)

2 90ce3da70b43 Initial load duke parents: diff changeset	1	#
90ce3da70b43 Initial load duke parents: diff changeset	2	# matching the following output specified as a pattern that verifies
90ce3da70b43 Initial load duke parents: diff changeset	3	# that the numerical values conform to a specific pattern, rather than
90ce3da70b43 Initial load duke parents: diff changeset	4	# specific values.
90ce3da70b43 Initial load duke parents: diff changeset	5	#
37328 b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	6	# S0 S1 E O M CCS YGC YGCT FGC FGCT CGC CGCT GCT
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	7	# 0.00 93.76 26.48 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	8	# 0.00 93.76 71.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	9	# 0.00 93.76 73.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	10	# 0.00 93.76 73.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	11	# 0.00 93.76 73.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	12	# 0.00 93.76 75.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	13	# 0.00 93.76 75.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	14	# 0.00 93.76 77.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	15	# 0.00 93.76 77.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	16	# 0.00 93.76 77.58 1.95 77.78 68.02 1 0.006 0 0.000 0 0.000 0.006
2 90ce3da70b43 Initial load duke parents: diff changeset	17
90ce3da70b43 Initial load duke parents: diff changeset	18	BEGIN {
90ce3da70b43 Initial load duke parents: diff changeset	19	headerlines=0; datalines=0; totallines=0
90ce3da70b43 Initial load duke parents: diff changeset	20	}
90ce3da70b43 Initial load duke parents: diff changeset	21
37328 b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	22	/^ S0 S1 E O M CCS YGC YGCT FGC FGCT CGC CGCT GCT $/ {
2 90ce3da70b43 Initial load duke parents: diff changeset	23	headerlines++;
90ce3da70b43 Initial load duke parents: diff changeset	24	}
90ce3da70b43 Initial load duke parents: diff changeset	25
37328 b51428cf0edf 8151674: STW phases at Concurrent GC should count in PerfCounter ysuenaga parents: 22562 diff changeset	26	/^[ ][0-9]+\.[0-9]+[ ][0-9]+\.[0-9]+[ ][0-9]+\.[0-9]+[ ][0-9]+\.[0-9]+[ ][0-9]+\.[0-9]+[ ]([0-9]+\.[0-9]+)\|-[ ][0-9]+[ ][0-9]+\.[0-9]+[ ][0-9]+[ ][0-9]+\.[0-9]+[ ][0-9]+[ ][0-9]+\.[0-9]+[ ]*[0-9]+\.[0-9]+$/ {
2 90ce3da70b43 Initial load duke parents: diff changeset	27	datalines++;
90ce3da70b43 Initial load duke parents: diff changeset	28	}
90ce3da70b43 Initial load duke parents: diff changeset	29
90ce3da70b43 Initial load duke parents: diff changeset	30	{ totallines++; print $0 }
90ce3da70b43 Initial load duke parents: diff changeset	31
90ce3da70b43 Initial load duke parents: diff changeset	32	END {
22562 e909d64b8dd8 6545321: [TESTBUG] jstatLineCounts4.sh has to be resilient to unexpected output sla parents: 20763 diff changeset	33	if ((headerlines == 1) && (datalines == 10)) {
2 90ce3da70b43 Initial load duke parents: diff changeset	34	exit 0
90ce3da70b43 Initial load duke parents: diff changeset	35	} else {
90ce3da70b43 Initial load duke parents: diff changeset	36	exit 1
90ce3da70b43 Initial load duke parents: diff changeset	37	}
90ce3da70b43 Initial load duke parents: diff changeset	38	}

author	ysuenaga
	Wed, 30 Mar 2016 21:05:35 +0900
changeset 37328	b51428cf0edf
parent 22562	e909d64b8dd8
child 37329	1cebe5df8ece
permissions	-rw-r--r--