/*

 * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.

 * Copyright (c) 2014, Red Hat Inc. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#include "precompiled.hpp"

#include "asm/macroAssembler.inline.hpp"

#include "asm/assembler.hpp"

#include "c1/c1_CodeStubs.hpp"

#include "c1/c1_Compilation.hpp"

#include "c1/c1_LIRAssembler.hpp"

#include "c1/c1_MacroAssembler.hpp"

#include "c1/c1_Runtime1.hpp"

#include "c1/c1_ValueStack.hpp"

#include "ci/ciArrayKlass.hpp"

#include "ci/ciInstance.hpp"

#include "gc/shared/barrierSet.hpp"

#include "gc/shared/cardTableBarrierSet.hpp"

#include "gc/shared/collectedHeap.hpp"

#include "nativeInst_aarch64.hpp"

#include "oops/objArrayKlass.hpp"

#include "runtime/frame.inline.hpp"

#include "runtime/sharedRuntime.hpp"

#include "vmreg_aarch64.inline.hpp"

#ifndef PRODUCT

#define COMMENT(x)   do { __ block_comment(x); } while (0)

#else

#define COMMENT(x)

#endif

NEEDS_CLEANUP // remove this definitions ?

const Register IC_Klass    = rscratch2;   // where the IC klass is cached

const Register SYNC_header = r0;   // synchronization header

const Register SHIFT_count = r0;   // where count for shift operations must be

#define __ _masm->

static void select_different_registers(Register preserve,

                                       Register extra,

                                       Register &tmp1,

                                       Register &tmp2) {

  if (tmp1 == preserve) {

    assert_different_registers(tmp1, tmp2, extra);

    tmp1 = extra;

  } else if (tmp2 == preserve) {

    assert_different_registers(tmp1, tmp2, extra);

    tmp2 = extra;

  }

  assert_different_registers(preserve, tmp1, tmp2);

}

static void select_different_registers(Register preserve,

                                       Register extra,

                                       Register &tmp1,

                                       Register &tmp2,

                                       Register &tmp3) {

  if (tmp1 == preserve) {

    assert_different_registers(tmp1, tmp2, tmp3, extra);

    tmp1 = extra;

  } else if (tmp2 == preserve) {

    assert_different_registers(tmp1, tmp2, tmp3, extra);

    tmp2 = extra;

  } else if (tmp3 == preserve) {

    assert_different_registers(tmp1, tmp2, tmp3, extra);

    tmp3 = extra;

  }

  assert_different_registers(preserve, tmp1, tmp2, tmp3);

}

bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }

LIR_Opr LIR_Assembler::receiverOpr() {

  return FrameMap::receiver_opr;

}

LIR_Opr LIR_Assembler::osrBufferPointer() {

  return FrameMap::as_pointer_opr(receiverOpr()->as_register());

}

//--------------fpu register translations-----------------------

address LIR_Assembler::float_constant(float f) {

  address const_addr = __ float_constant(f);

  if (const_addr == NULL) {

    bailout("const section overflow");

    return __ code()->consts()->start();

  } else {

    return const_addr;

  }

}

address LIR_Assembler::double_constant(double d) {

  address const_addr = __ double_constant(d);

  if (const_addr == NULL) {

    bailout("const section overflow");

    return __ code()->consts()->start();

  } else {

    return const_addr;

  }

}

address LIR_Assembler::int_constant(jlong n) {

  address const_addr = __ long_constant(n);

  if (const_addr == NULL) {

    bailout("const section overflow");

    return __ code()->consts()->start();

  } else {

    return const_addr;

  }

}

void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }

void LIR_Assembler::reset_FPU() { Unimplemented(); }

void LIR_Assembler::fpop() { Unimplemented(); }

void LIR_Assembler::fxch(int i) { Unimplemented(); }

void LIR_Assembler::fld(int i) { Unimplemented(); }

void LIR_Assembler::ffree(int i) { Unimplemented(); }

void LIR_Assembler::breakpoint() { Unimplemented(); }

void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }

void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }

bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }

//-------------------------------------------

static Register as_reg(LIR_Opr op) {

  return op->is_double_cpu() ? op->as_register_lo() : op->as_register();

}

static jlong as_long(LIR_Opr data) {

  jlong result;

  switch (data->type()) {

  case T_INT:

    result = (data->as_jint());

    break;

  case T_LONG:

    result = (data->as_jlong());

    break;

  default:

    ShouldNotReachHere();

    result = 0;  // unreachable

  }

  return result;

}

Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {

  Register base = addr->base()->as_pointer_register();

  LIR_Opr opr = addr->index();

  if (opr->is_cpu_register()) {

    Register index;

    if (opr->is_single_cpu())

      index = opr->as_register();

    else

      index = opr->as_register_lo();

    assert(addr->disp() == 0, "must be");

    switch(opr->type()) {

      case T_INT:

        return Address(base, index, Address::sxtw(addr->scale()));

      case T_LONG:

        return Address(base, index, Address::lsl(addr->scale()));

      default:

        ShouldNotReachHere();

      }

  } else  {

    intptr_t addr_offset = intptr_t(addr->disp());

    if (Address::offset_ok_for_immed(addr_offset, addr->scale()))

      return Address(base, addr_offset, Address::lsl(addr->scale()));

    else {

      __ mov(tmp, addr_offset);

      return Address(base, tmp, Address::lsl(addr->scale()));

    }

  }

  return Address();

}

Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {

  ShouldNotReachHere();

  return Address();

}

Address LIR_Assembler::as_Address(LIR_Address* addr) {

  return as_Address(addr, rscratch1);

}

Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {

  return as_Address(addr, rscratch1);  // Ouch

  // FIXME: This needs to be much more clever.  See x86.

}

void LIR_Assembler::osr_entry() {

  offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());

  BlockBegin* osr_entry = compilation()->hir()->osr_entry();

  ValueStack* entry_state = osr_entry->state();

  int number_of_locks = entry_state->locks_size();

  // we jump here if osr happens with the interpreter

  // state set up to continue at the beginning of the

  // loop that triggered osr - in particular, we have

  // the following registers setup:

  //

  // r2: osr buffer

  //

  // build frame

  ciMethod* m = compilation()->method();

  __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());

  // OSR buffer is

  //

  // locals[nlocals-1..0]

  // monitors[0..number_of_locks]

  //

  // locals is a direct copy of the interpreter frame so in the osr buffer

  // so first slot in the local array is the last local from the interpreter

  // and last slot is local[0] (receiver) from the interpreter

  //

  // Similarly with locks. The first lock slot in the osr buffer is the nth lock

  // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock

  // in the interpreter frame (the method lock if a sync method)

  // Initialize monitors in the compiled activation.

  //   r2: pointer to osr buffer

  //

  // All other registers are dead at this point and the locals will be

  // copied into place by code emitted in the IR.

  Register OSR_buf = osrBufferPointer()->as_pointer_register();

  { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");

    int monitor_offset = BytesPerWord * method()->max_locals() +

      (2 * BytesPerWord) * (number_of_locks - 1);

    // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in

    // the OSR buffer using 2 word entries: first the lock and then

    // the oop.

    for (int i = 0; i < number_of_locks; i++) {

      int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);

#ifdef ASSERT

      // verify the interpreter's monitor has a non-null object

      {

        Label L;

        __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));

        __ cbnz(rscratch1, L);

        __ stop("locked object is NULL");

        __ bind(L);

      }

#endif

      __ ldr(r19, Address(OSR_buf, slot_offset + 0));

      __ str(r19, frame_map()->address_for_monitor_lock(i));

      __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));

      __ str(r19, frame_map()->address_for_monitor_object(i));

    }

  }

}

// inline cache check; done before the frame is built.

int LIR_Assembler::check_icache() {

  Register receiver = FrameMap::receiver_opr->as_register();

  Register ic_klass = IC_Klass;

  int start_offset = __ offset();

  __ inline_cache_check(receiver, ic_klass);

  // if icache check fails, then jump to runtime routine

  // Note: RECEIVER must still contain the receiver!

  Label dont;

  __ br(Assembler::EQ, dont);

  __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));

  // We align the verified entry point unless the method body

  // (including its inline cache check) will fit in a single 64-byte

  // icache line.

  if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {

    // force alignment after the cache check.

    __ align(CodeEntryAlignment);

  }

  __ bind(dont);

  return start_offset;

}

void LIR_Assembler::jobject2reg(jobject o, Register reg) {

  if (o == NULL) {

    __ mov(reg, zr);

  } else {

    __ movoop(reg, o, /*immediate*/true);

  }

}

void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {

  address target = NULL;

  relocInfo::relocType reloc_type = relocInfo::none;

  switch (patching_id(info)) {

  case PatchingStub::access_field_id:

    target = Runtime1::entry_for(Runtime1::access_field_patching_id);

    reloc_type = relocInfo::section_word_type;

    break;

  case PatchingStub::load_klass_id:

    target = Runtime1::entry_for(Runtime1::load_klass_patching_id);

    reloc_type = relocInfo::metadata_type;

    break;

  case PatchingStub::load_mirror_id:

    target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);

    reloc_type = relocInfo::oop_type;

    break;

  case PatchingStub::load_appendix_id:

    target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);

    reloc_type = relocInfo::oop_type;

    break;

  default: ShouldNotReachHere();

  }

  __ far_call(RuntimeAddress(target));

  add_call_info_here(info);

}

void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {

  deoptimize_trap(info);

}

// This specifies the rsp decrement needed to build the frame

int LIR_Assembler::initial_frame_size_in_bytes() const {

  // if rounding, must let FrameMap know!

  // The frame_map records size in slots (32bit word)

  // subtract two words to account for return address and link

  return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;

}

int LIR_Assembler::emit_exception_handler() {

  // if the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci => add a nop

  // (was bug 5/14/1999 - gri)

  __ nop();

  // generate code for exception handler

  address handler_base = __ start_a_stub(exception_handler_size());

  if (handler_base == NULL) {

    // not enough space left for the handler

    bailout("exception handler overflow");

    return -1;

  }

  int offset = code_offset();

  // the exception oop and pc are in r0, and r3

  // no other registers need to be preserved, so invalidate them

  __ invalidate_registers(false, true, true, false, true, true);

  // check that there is really an exception

  __ verify_not_null_oop(r0);

  // search an exception handler (r0: exception oop, r3: throwing pc)

  __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();

  guarantee(code_offset() - offset <= exception_handler_size(), "overflow");

  __ end_a_stub();

  return offset;

}

// Emit the code to remove the frame from the stack in the exception

// unwind path.

int LIR_Assembler::emit_unwind_handler() {

#ifndef PRODUCT

  if (CommentedAssembly) {

    _masm->block_comment("Unwind handler");

  }

#endif

  int offset = code_offset();

  // Fetch the exception from TLS and clear out exception related thread state

  __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));

  __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));

  __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));

  __ bind(_unwind_handler_entry);

  __ verify_not_null_oop(r0);

  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

    __ mov(r19, r0);  // Preserve the exception

  }

  // Preform needed unlocking

  MonitorExitStub* stub = NULL;

  if (method()->is_synchronized()) {

    monitor_address(0, FrameMap::r0_opr);

    stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);

    __ unlock_object(r5, r4, r0, *stub->entry());

    __ bind(*stub->continuation());

  }

  if (compilation()->env()->dtrace_method_probes()) {

    __ call_Unimplemented();

#if 0

    __ movptr(Address(rsp, 0), rax);

    __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());

    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));

#endif

  }

  if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {

    __ mov(r0, r19);  // Restore the exception

  }

  // remove the activation and dispatch to the unwind handler

  __ block_comment("remove_frame and dispatch to the unwind handler");

  __ remove_frame(initial_frame_size_in_bytes());

  __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));

  // Emit the slow path assembly

  if (stub != NULL) {

    stub->emit_code(this);

  }

  return offset;

}

int LIR_Assembler::emit_deopt_handler() {

  // if the last instruction is a call (typically to do a throw which

  // is coming at the end after block reordering) the return address

  // must still point into the code area in order to avoid assertion

  // failures when searching for the corresponding bci => add a nop

  // (was bug 5/14/1999 - gri)

  __ nop();

  // generate code for exception handler

  address handler_base = __ start_a_stub(deopt_handler_size());

  if (handler_base == NULL) {

    // not enough space left for the handler

    bailout("deopt handler overflow");

    return -1;

  }

  int offset = code_offset();

  __ adr(lr, pc());

  __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));

  guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");

  __ end_a_stub();

  return offset;

}

void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {

  _masm->code_section()->relocate(adr, relocInfo::poll_type);

  int pc_offset = code_offset();

  flush_debug_info(pc_offset);

  info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);

  if (info->exception_handlers() != NULL) {

    compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());

  }

}

void LIR_Assembler::return_op(LIR_Opr result) {

  assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");

  // Pop the stack before the safepoint code

  __ remove_frame(initial_frame_size_in_bytes());

  if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {

    __ reserved_stack_check();

  }

  address polling_page(os::get_polling_page());

  __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);

  __ ret(lr);

}

int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {

  address polling_page(os::get_polling_page());

  guarantee(info != NULL, "Shouldn't be NULL");

  assert(os::is_poll_address(polling_page), "should be");

  __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);

  add_debug_info_for_branch(info);  // This isn't just debug info:

                                    // it's the oop map

  __ read_polling_page(rscratch1, relocInfo::poll_type);

  return __ offset();

}