author | mdoerr |
Tue, 05 Nov 2019 11:53:46 +0100 | |
changeset 58932 | 8623f75be895 |
parent 53244 | 9807daeb47c4 |
permissions | -rw-r--r-- |
1 | 1 |
/* |
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* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. |
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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* or visit www.oracle.com if you need additional information or have any |
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* questions. |
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* |
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*/ |
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#ifndef CPU_X86_NATIVEINST_X86_HPP |
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#define CPU_X86_NATIVEINST_X86_HPP |
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#include "asm/assembler.hpp" |
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#include "runtime/icache.hpp" |
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#include "runtime/os.hpp" |
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#include "runtime/safepointMechanism.hpp" |
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// We have interfaces for the following instructions: |
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// - NativeInstruction |
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// - - NativeCall |
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// - - NativeMovConstReg |
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// - - NativeMovConstRegPatching |
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// - - NativeMovRegMem |
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// - - NativeMovRegMemPatching |
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// - - NativeJump |
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// - - NativeFarJump |
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// - - NativeIllegalOpCode |
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// - - NativeGeneralJump |
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// - - NativeReturn |
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// - - NativeReturnX (return with argument) |
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// - - NativePushConst |
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// - - NativeTstRegMem |
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// The base class for different kinds of native instruction abstractions. |
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// Provides the primitive operations to manipulate code relative to this. |
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class NativeInstruction { |
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friend class Relocation; |
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public: |
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enum Intel_specific_constants { |
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nop_instruction_code = 0x90, |
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nop_instruction_size = 1 |
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}; |
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bool is_nop() { return ubyte_at(0) == nop_instruction_code; } |
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inline bool is_call(); |
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inline bool is_call_reg(); |
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inline bool is_illegal(); |
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inline bool is_return(); |
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inline bool is_jump(); |
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inline bool is_jump_reg(); |
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inline bool is_far_jump(); |
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inline bool is_cond_jump(); |
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inline bool is_safepoint_poll(); |
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inline bool is_mov_literal64(); |
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protected: |
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address addr_at(int offset) const { return address(this) + offset; } |
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s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } |
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u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } |
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jint int_at(int offset) const { return *(jint*) addr_at(offset); } |
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intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } |
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||
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oop oop_at (int offset) const { return *(oop*) addr_at(offset); } |
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void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } |
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void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } |
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void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } |
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void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } |
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// This doesn't really do anything on Intel, but it is the place where |
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// cache invalidation belongs, generically: |
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void wrote(int offset); |
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public: |
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// unit test stuff |
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static void test() {} // override for testing |
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inline friend NativeInstruction* nativeInstruction_at(address address); |
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}; |
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inline NativeInstruction* nativeInstruction_at(address address) { |
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NativeInstruction* inst = (NativeInstruction*)address; |
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#ifdef ASSERT |
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//inst->verify(); |
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#endif |
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return inst; |
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} |
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class NativePltCall: public NativeInstruction { |
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public: |
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enum Intel_specific_constants { |
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instruction_code = 0xE8, |
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instruction_size = 5, |
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instruction_offset = 0, |
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displacement_offset = 1, |
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return_address_offset = 5 |
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}; |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(return_address_offset); } |
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address displacement_address() const { return addr_at(displacement_offset); } |
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int displacement() const { return (jint) int_at(displacement_offset); } |
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address return_address() const { return addr_at(return_address_offset); } |
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address destination() const; |
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address plt_entry() const; |
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address plt_jump() const; |
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address plt_load_got() const; |
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address plt_resolve_call() const; |
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address plt_c2i_stub() const; |
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void set_stub_to_clean(); |
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void reset_to_plt_resolve_call(); |
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void set_destination_mt_safe(address dest); |
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void verify() const; |
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}; |
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inline NativePltCall* nativePltCall_at(address address) { |
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NativePltCall* call = (NativePltCall*) address; |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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inline NativePltCall* nativePltCall_before(address addr) { |
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address at = addr - NativePltCall::instruction_size; |
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return nativePltCall_at(at); |
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} |
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class NativeCall; |
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inline NativeCall* nativeCall_at(address address); |
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// The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off |
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// instructions (used to manipulate inline caches, primitive & dll calls, etc.). |
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class NativeCall: public NativeInstruction { |
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public: |
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enum Intel_specific_constants { |
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instruction_code = 0xE8, |
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instruction_size = 5, |
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instruction_offset = 0, |
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displacement_offset = 1, |
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return_address_offset = 5 |
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}; |
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enum { cache_line_size = BytesPerWord }; // conservative estimate! |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(return_address_offset); } |
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int displacement() const { return (jint) int_at(displacement_offset); } |
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address displacement_address() const { return addr_at(displacement_offset); } |
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address return_address() const { return addr_at(return_address_offset); } |
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address destination() const; |
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void set_destination(address dest) { |
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#ifdef AMD64 |
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intptr_t disp = dest - return_address(); |
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guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset"); |
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#endif // AMD64 |
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set_int_at(displacement_offset, dest - return_address()); |
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} |
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void set_destination_mt_safe(address dest); |
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void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } |
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void verify(); |
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void print(); |
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// Creation |
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inline friend NativeCall* nativeCall_at(address address); |
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inline friend NativeCall* nativeCall_before(address return_address); |
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static bool is_call_at(address instr) { |
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return ((*instr) & 0xFF) == NativeCall::instruction_code; |
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} |
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static bool is_call_before(address return_address) { |
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return is_call_at(return_address - NativeCall::return_address_offset); |
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} |
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static bool is_call_to(address instr, address target) { |
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return nativeInstruction_at(instr)->is_call() && |
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nativeCall_at(instr)->destination() == target; |
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} |
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#if INCLUDE_AOT |
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static bool is_far_call(address instr, address target) { |
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intptr_t disp = target - (instr + sizeof(int32_t)); |
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return !Assembler::is_simm32(disp); |
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} |
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#endif |
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// MT-safe patching of a call instruction. |
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static void insert(address code_pos, address entry); |
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static void replace_mt_safe(address instr_addr, address code_buffer); |
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}; |
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inline NativeCall* nativeCall_at(address address) { |
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NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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inline NativeCall* nativeCall_before(address return_address) { |
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NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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class NativeCallReg: public NativeInstruction { |
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public: |
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enum Intel_specific_constants { |
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instruction_code = 0xFF, |
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instruction_offset = 0, |
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return_address_offset_norex = 2, |
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return_address_offset_rex = 3 |
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}; |
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int next_instruction_offset() const { |
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if (ubyte_at(0) == NativeCallReg::instruction_code) { |
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return return_address_offset_norex; |
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} else { |
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return return_address_offset_rex; |
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} |
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} |
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}; |
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// An interface for accessing/manipulating native mov reg, imm32 instructions. |
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// (used to manipulate inlined 32bit data dll calls, etc.) |
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class NativeMovConstReg: public NativeInstruction { |
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#ifdef AMD64 |
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static const bool has_rex = true; |
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static const int rex_size = 1; |
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#else |
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static const bool has_rex = false; |
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static const int rex_size = 0; |
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#endif // AMD64 |
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public: |
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enum Intel_specific_constants { |
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instruction_code = 0xB8, |
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instruction_size = 1 + rex_size + wordSize, |
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instruction_offset = 0, |
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data_offset = 1 + rex_size, |
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next_instruction_offset = instruction_size, |
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register_mask = 0x07 |
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}; |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(next_instruction_offset); } |
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intptr_t data() const { return ptr_at(data_offset); } |
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void set_data(intptr_t x) { set_ptr_at(data_offset, x); } |
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276 |
||
277 |
void verify(); |
|
278 |
void print(); |
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279 |
||
280 |
// unit test stuff |
|
281 |
static void test() {} |
|
282 |
||
283 |
// Creation |
|
284 |
inline friend NativeMovConstReg* nativeMovConstReg_at(address address); |
|
285 |
inline friend NativeMovConstReg* nativeMovConstReg_before(address address); |
|
286 |
}; |
|
287 |
||
288 |
inline NativeMovConstReg* nativeMovConstReg_at(address address) { |
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289 |
NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); |
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290 |
#ifdef ASSERT |
|
291 |
test->verify(); |
|
292 |
#endif |
|
293 |
return test; |
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294 |
} |
|
295 |
||
296 |
inline NativeMovConstReg* nativeMovConstReg_before(address address) { |
|
297 |
NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); |
|
298 |
#ifdef ASSERT |
|
299 |
test->verify(); |
|
300 |
#endif |
|
301 |
return test; |
|
302 |
} |
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303 |
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304 |
class NativeMovConstRegPatching: public NativeMovConstReg { |
|
305 |
private: |
|
306 |
friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { |
|
307 |
NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); |
|
308 |
#ifdef ASSERT |
|
309 |
test->verify(); |
|
310 |
#endif |
|
311 |
return test; |
|
312 |
} |
|
313 |
}; |
|
314 |
||
315 |
// An interface for accessing/manipulating native moves of the form: |
|
1066 | 316 |
// mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem) |
317 |
// mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg |
|
318 |
// mov[s/z]x[w/b/q] [reg + offset], reg |
|
1 | 319 |
// fld_s [reg+offset] |
320 |
// fld_d [reg+offset] |
|
321 |
// fstp_s [reg + offset] |
|
322 |
// fstp_d [reg + offset] |
|
1066 | 323 |
// mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch) |
1 | 324 |
// |
325 |
// Warning: These routines must be able to handle any instruction sequences |
|
326 |
// that are generated as a result of the load/store byte,word,long |
|
327 |
// macros. For example: The load_unsigned_byte instruction generates |
|
328 |
// an xor reg,reg inst prior to generating the movb instruction. This |
|
329 |
// class must skip the xor instruction. |
|
330 |
||
331 |
class NativeMovRegMem: public NativeInstruction { |
|
332 |
public: |
|
333 |
enum Intel_specific_constants { |
|
1066 | 334 |
instruction_prefix_wide_lo = Assembler::REX, |
335 |
instruction_prefix_wide_hi = Assembler::REX_WRXB, |
|
1 | 336 |
instruction_code_xor = 0x33, |
337 |
instruction_extended_prefix = 0x0F, |
|
1066 | 338 |
instruction_code_mem2reg_movslq = 0x63, |
1 | 339 |
instruction_code_mem2reg_movzxb = 0xB6, |
340 |
instruction_code_mem2reg_movsxb = 0xBE, |
|
341 |
instruction_code_mem2reg_movzxw = 0xB7, |
|
342 |
instruction_code_mem2reg_movsxw = 0xBF, |
|
343 |
instruction_operandsize_prefix = 0x66, |
|
1066 | 344 |
instruction_code_reg2mem = 0x89, |
345 |
instruction_code_mem2reg = 0x8b, |
|
1 | 346 |
instruction_code_reg2memb = 0x88, |
347 |
instruction_code_mem2regb = 0x8a, |
|
348 |
instruction_code_float_s = 0xd9, |
|
349 |
instruction_code_float_d = 0xdd, |
|
350 |
instruction_code_long_volatile = 0xdf, |
|
351 |
instruction_code_xmm_ss_prefix = 0xf3, |
|
352 |
instruction_code_xmm_sd_prefix = 0xf2, |
|
353 |
instruction_code_xmm_code = 0x0f, |
|
354 |
instruction_code_xmm_load = 0x10, |
|
355 |
instruction_code_xmm_store = 0x11, |
|
356 |
instruction_code_xmm_lpd = 0x12, |
|
357 |
||
50102 | 358 |
instruction_code_lea = 0x8d, |
359 |
||
11427 | 360 |
instruction_VEX_prefix_2bytes = Assembler::VEX_2bytes, |
361 |
instruction_VEX_prefix_3bytes = Assembler::VEX_3bytes, |
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instruction_EVEX_prefix_4bytes = Assembler::EVEX_4bytes, |
11427 | 363 |
|
1 | 364 |
instruction_offset = 0, |
365 |
data_offset = 2, |
|
366 |
next_instruction_offset = 4 |
|
367 |
}; |
|
368 |
||
1066 | 369 |
// helper |
370 |
int instruction_start() const; |
|
371 |
||
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372 |
address instruction_address() const { |
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|
373 |
return addr_at(instruction_start()); |
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|
374 |
} |
1 | 375 |
|
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|
376 |
int num_bytes_to_end_of_patch() const { |
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|
377 |
return patch_offset() + sizeof(jint); |
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|
378 |
} |
1 | 379 |
|
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|
380 |
int offset() const { |
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|
381 |
return int_at(patch_offset()); |
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|
382 |
} |
1066 | 383 |
|
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|
384 |
void set_offset(int x) { |
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|
385 |
set_int_at(patch_offset(), x); |
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|
386 |
} |
1 | 387 |
|
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|
388 |
void add_offset_in_bytes(int add_offset) { |
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|
389 |
int patch_off = patch_offset(); |
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|
390 |
set_int_at(patch_off, int_at(patch_off) + add_offset); |
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|
391 |
} |
1 | 392 |
|
393 |
void verify(); |
|
394 |
void print (); |
|
395 |
||
396 |
// unit test stuff |
|
397 |
static void test() {} |
|
398 |
||
399 |
private: |
|
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|
400 |
int patch_offset() const; |
1 | 401 |
inline friend NativeMovRegMem* nativeMovRegMem_at (address address); |
402 |
}; |
|
403 |
||
404 |
inline NativeMovRegMem* nativeMovRegMem_at (address address) { |
|
405 |
NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); |
|
406 |
#ifdef ASSERT |
|
407 |
test->verify(); |
|
408 |
#endif |
|
409 |
return test; |
|
410 |
} |
|
411 |
||
412 |
||
413 |
// An interface for accessing/manipulating native leal instruction of form: |
|
414 |
// leal reg, [reg + offset] |
|
415 |
||
416 |
class NativeLoadAddress: public NativeMovRegMem { |
|
1066 | 417 |
#ifdef AMD64 |
418 |
static const bool has_rex = true; |
|
419 |
static const int rex_size = 1; |
|
420 |
#else |
|
421 |
static const bool has_rex = false; |
|
422 |
static const int rex_size = 0; |
|
423 |
#endif // AMD64 |
|
1 | 424 |
public: |
425 |
enum Intel_specific_constants { |
|
1066 | 426 |
instruction_prefix_wide = Assembler::REX_W, |
427 |
instruction_prefix_wide_extended = Assembler::REX_WB, |
|
428 |
lea_instruction_code = 0x8D, |
|
429 |
mov64_instruction_code = 0xB8 |
|
1 | 430 |
}; |
431 |
||
432 |
void verify(); |
|
433 |
void print (); |
|
434 |
||
435 |
// unit test stuff |
|
436 |
static void test() {} |
|
437 |
||
438 |
private: |
|
439 |
friend NativeLoadAddress* nativeLoadAddress_at (address address) { |
|
440 |
NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); |
|
441 |
#ifdef ASSERT |
|
442 |
test->verify(); |
|
443 |
#endif |
|
444 |
return test; |
|
445 |
} |
|
446 |
}; |
|
447 |
||
42650 | 448 |
// destination is rbx or rax |
449 |
// mov rbx, [rip + offset] |
|
450 |
class NativeLoadGot: public NativeInstruction { |
|
451 |
#ifdef AMD64 |
|
452 |
static const bool has_rex = true; |
|
453 |
static const int rex_size = 1; |
|
454 |
#else |
|
455 |
static const bool has_rex = false; |
|
456 |
static const int rex_size = 0; |
|
457 |
#endif |
|
458 |
public: |
|
459 |
enum Intel_specific_constants { |
|
460 |
rex_prefix = 0x48, |
|
461 |
instruction_code = 0x8b, |
|
462 |
modrm_rbx_code = 0x1d, |
|
463 |
modrm_rax_code = 0x05, |
|
464 |
instruction_length = 6 + rex_size, |
|
465 |
offset_offset = 2 + rex_size |
|
466 |
}; |
|
467 |
||
468 |
address instruction_address() const { return addr_at(0); } |
|
469 |
address rip_offset_address() const { return addr_at(offset_offset); } |
|
470 |
int rip_offset() const { return int_at(offset_offset); } |
|
471 |
address return_address() const { return addr_at(instruction_length); } |
|
472 |
address got_address() const { return return_address() + rip_offset(); } |
|
473 |
address next_instruction_address() const { return return_address(); } |
|
474 |
intptr_t data() const; |
|
475 |
void set_data(intptr_t data) { |
|
476 |
intptr_t *addr = (intptr_t *) got_address(); |
|
477 |
*addr = data; |
|
478 |
} |
|
479 |
||
480 |
void verify() const; |
|
481 |
private: |
|
482 |
void report_and_fail() const; |
|
483 |
}; |
|
484 |
||
485 |
inline NativeLoadGot* nativeLoadGot_at(address addr) { |
|
486 |
NativeLoadGot* load = (NativeLoadGot*) addr; |
|
487 |
#ifdef ASSERT |
|
488 |
load->verify(); |
|
489 |
#endif |
|
490 |
return load; |
|
491 |
} |
|
492 |
||
1 | 493 |
// jump rel32off |
494 |
||
495 |
class NativeJump: public NativeInstruction { |
|
496 |
public: |
|
497 |
enum Intel_specific_constants { |
|
498 |
instruction_code = 0xe9, |
|
499 |
instruction_size = 5, |
|
500 |
instruction_offset = 0, |
|
501 |
data_offset = 1, |
|
502 |
next_instruction_offset = 5 |
|
503 |
}; |
|
504 |
||
505 |
address instruction_address() const { return addr_at(instruction_offset); } |
|
506 |
address next_instruction_address() const { return addr_at(next_instruction_offset); } |
|
507 |
address jump_destination() const { |
|
508 |
address dest = (int_at(data_offset)+next_instruction_address()); |
|
1066 | 509 |
// 32bit used to encode unresolved jmp as jmp -1 |
510 |
// 64bit can't produce this so it used jump to self. |
|
511 |
// Now 32bit and 64bit use jump to self as the unresolved address |
|
512 |
// which the inline cache code (and relocs) know about |
|
513 |
||
1 | 514 |
// return -1 if jump to self |
515 |
dest = (dest == (address) this) ? (address) -1 : dest; |
|
516 |
return dest; |
|
517 |
} |
|
518 |
||
519 |
void set_jump_destination(address dest) { |
|
520 |
intptr_t val = dest - next_instruction_address(); |
|
1076
a4f1c0615381
6744422: incorrect handling of -1 in set_jump_destination
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parents:
1066
diff
changeset
|
521 |
if (dest == (address) -1) { |
a4f1c0615381
6744422: incorrect handling of -1 in set_jump_destination
never
parents:
1066
diff
changeset
|
522 |
val = -5; // jump to self |
a4f1c0615381
6744422: incorrect handling of -1 in set_jump_destination
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parents:
1066
diff
changeset
|
523 |
} |
1 | 524 |
#ifdef AMD64 |
1066 | 525 |
assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1"); |
1 | 526 |
#endif // AMD64 |
527 |
set_int_at(data_offset, (jint)val); |
|
528 |
} |
|
529 |
||
530 |
// Creation |
|
531 |
inline friend NativeJump* nativeJump_at(address address); |
|
532 |
||
533 |
void verify(); |
|
534 |
||
535 |
// Unit testing stuff |
|
536 |
static void test() {} |
|
537 |
||
538 |
// Insertion of native jump instruction |
|
539 |
static void insert(address code_pos, address entry); |
|
540 |
// MT-safe insertion of native jump at verified method entry |
|
541 |
static void check_verified_entry_alignment(address entry, address verified_entry); |
|
542 |
static void patch_verified_entry(address entry, address verified_entry, address dest); |
|
543 |
}; |
|
544 |
||
545 |
inline NativeJump* nativeJump_at(address address) { |
|
546 |
NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); |
|
547 |
#ifdef ASSERT |
|
548 |
jump->verify(); |
|
549 |
#endif |
|
550 |
return jump; |
|
551 |
} |
|
552 |
||
42650 | 553 |
// far jump reg |
554 |
class NativeFarJump: public NativeInstruction { |
|
555 |
public: |
|
556 |
address jump_destination() const; |
|
557 |
||
558 |
// Creation |
|
559 |
inline friend NativeFarJump* nativeFarJump_at(address address); |
|
560 |
||
561 |
void verify(); |
|
562 |
||
563 |
// Unit testing stuff |
|
564 |
static void test() {} |
|
565 |
||
566 |
}; |
|
567 |
||
568 |
inline NativeFarJump* nativeFarJump_at(address address) { |
|
569 |
NativeFarJump* jump = (NativeFarJump*)(address); |
|
570 |
#ifdef ASSERT |
|
571 |
jump->verify(); |
|
572 |
#endif |
|
573 |
return jump; |
|
574 |
} |
|
575 |
||
1 | 576 |
// Handles all kinds of jump on Intel. Long/far, conditional/unconditional |
577 |
class NativeGeneralJump: public NativeInstruction { |
|
578 |
public: |
|
579 |
enum Intel_specific_constants { |
|
580 |
// Constants does not apply, since the lengths and offsets depends on the actual jump |
|
581 |
// used |
|
582 |
// Instruction codes: |
|
583 |
// Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) |
|
584 |
// Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) |
|
585 |
unconditional_long_jump = 0xe9, |
|
586 |
unconditional_short_jump = 0xeb, |
|
587 |
instruction_size = 5 |
|
588 |
}; |
|
589 |
||
590 |
address instruction_address() const { return addr_at(0); } |
|
591 |
address jump_destination() const; |
|
592 |
||
593 |
// Creation |
|
594 |
inline friend NativeGeneralJump* nativeGeneralJump_at(address address); |
|
595 |
||
596 |
// Insertion of native general jump instruction |
|
597 |
static void insert_unconditional(address code_pos, address entry); |
|
598 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
599 |
||
600 |
void verify(); |
|
601 |
}; |
|
602 |
||
603 |
inline NativeGeneralJump* nativeGeneralJump_at(address address) { |
|
604 |
NativeGeneralJump* jump = (NativeGeneralJump*)(address); |
|
605 |
debug_only(jump->verify();) |
|
606 |
return jump; |
|
607 |
} |
|
608 |
||
42650 | 609 |
class NativeGotJump: public NativeInstruction { |
610 |
public: |
|
611 |
enum Intel_specific_constants { |
|
612 |
instruction_code = 0xff, |
|
613 |
instruction_offset = 0, |
|
614 |
instruction_size = 6, |
|
615 |
rip_offset = 2 |
|
616 |
}; |
|
617 |
||
618 |
void verify() const; |
|
619 |
address instruction_address() const { return addr_at(instruction_offset); } |
|
620 |
address destination() const; |
|
621 |
address return_address() const { return addr_at(instruction_size); } |
|
622 |
int got_offset() const { return (jint) int_at(rip_offset); } |
|
623 |
address got_address() const { return return_address() + got_offset(); } |
|
624 |
address next_instruction_address() const { return addr_at(instruction_size); } |
|
625 |
bool is_GotJump() const { return ubyte_at(0) == instruction_code; } |
|
626 |
||
627 |
void set_jump_destination(address dest) { |
|
628 |
address *got_entry = (address *) got_address(); |
|
629 |
*got_entry = dest; |
|
630 |
} |
|
631 |
}; |
|
632 |
||
633 |
inline NativeGotJump* nativeGotJump_at(address addr) { |
|
634 |
NativeGotJump* jump = (NativeGotJump*)(addr); |
|
635 |
debug_only(jump->verify()); |
|
636 |
return jump; |
|
637 |
} |
|
638 |
||
1 | 639 |
class NativePopReg : public NativeInstruction { |
640 |
public: |
|
641 |
enum Intel_specific_constants { |
|
642 |
instruction_code = 0x58, |
|
643 |
instruction_size = 1, |
|
644 |
instruction_offset = 0, |
|
645 |
data_offset = 1, |
|
646 |
next_instruction_offset = 1 |
|
647 |
}; |
|
648 |
||
649 |
// Insert a pop instruction |
|
650 |
static void insert(address code_pos, Register reg); |
|
651 |
}; |
|
652 |
||
653 |
||
654 |
class NativeIllegalInstruction: public NativeInstruction { |
|
655 |
public: |
|
656 |
enum Intel_specific_constants { |
|
657 |
instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B |
|
658 |
instruction_size = 2, |
|
659 |
instruction_offset = 0, |
|
660 |
next_instruction_offset = 2 |
|
661 |
}; |
|
662 |
||
663 |
// Insert illegal opcode as specific address |
|
664 |
static void insert(address code_pos); |
|
665 |
}; |
|
666 |
||
667 |
// return instruction that does not pop values of the stack |
|
668 |
class NativeReturn: public NativeInstruction { |
|
669 |
public: |
|
670 |
enum Intel_specific_constants { |
|
671 |
instruction_code = 0xC3, |
|
672 |
instruction_size = 1, |
|
673 |
instruction_offset = 0, |
|
674 |
next_instruction_offset = 1 |
|
675 |
}; |
|
676 |
}; |
|
677 |
||
678 |
// return instruction that does pop values of the stack |
|
679 |
class NativeReturnX: public NativeInstruction { |
|
680 |
public: |
|
681 |
enum Intel_specific_constants { |
|
682 |
instruction_code = 0xC2, |
|
683 |
instruction_size = 2, |
|
684 |
instruction_offset = 0, |
|
685 |
next_instruction_offset = 2 |
|
686 |
}; |
|
687 |
}; |
|
688 |
||
689 |
// Simple test vs memory |
|
690 |
class NativeTstRegMem: public NativeInstruction { |
|
691 |
public: |
|
692 |
enum Intel_specific_constants { |
|
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
7397
diff
changeset
|
693 |
instruction_rex_prefix_mask = 0xF0, |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
7397
diff
changeset
|
694 |
instruction_rex_prefix = Assembler::REX, |
47881
0ce0ac68ace7
8189941: Implementation JEP 312: Thread-local handshake
rehn
parents:
47216
diff
changeset
|
695 |
instruction_rex_b_prefix = Assembler::REX_B, |
8871
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
7397
diff
changeset
|
696 |
instruction_code_memXregl = 0x85, |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
7397
diff
changeset
|
697 |
modrm_mask = 0x38, // select reg from the ModRM byte |
5c3b26c4119e
6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents:
7397
diff
changeset
|
698 |
modrm_reg = 0x00 // rax |
1 | 699 |
}; |
700 |
}; |
|
701 |
||
702 |
inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } |
|
703 |
inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } |
|
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
704 |
inline bool NativeInstruction::is_call_reg() { return ubyte_at(0) == NativeCallReg::instruction_code || |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
705 |
(ubyte_at(1) == NativeCallReg::instruction_code && |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
706 |
(ubyte_at(0) == Assembler::REX || ubyte_at(0) == Assembler::REX_B)); } |
1 | 707 |
inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || |
708 |
ubyte_at(0) == NativeReturnX::instruction_code; } |
|
709 |
inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || |
|
710 |
ubyte_at(0) == 0xEB; /* short jump */ } |
|
42650 | 711 |
inline bool NativeInstruction::is_jump_reg() { |
712 |
int pos = 0; |
|
713 |
if (ubyte_at(0) == Assembler::REX_B) pos = 1; |
|
714 |
return ubyte_at(pos) == 0xFF && (ubyte_at(pos + 1) & 0xF0) == 0xE0; |
|
715 |
} |
|
716 |
inline bool NativeInstruction::is_far_jump() { return is_mov_literal64(); } |
|
1 | 717 |
inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || |
718 |
(ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } |
|
719 |
inline bool NativeInstruction::is_safepoint_poll() { |
|
49027
8dc742d9bbab
8195112: x86 (32 bit): implementation for Thread-local handshakes
mdoerr
parents:
48200
diff
changeset
|
720 |
if (SafepointMechanism::uses_thread_local_poll()) { |
1 | 721 |
#ifdef AMD64 |
47881
0ce0ac68ace7
8189941: Implementation JEP 312: Thread-local handshake
rehn
parents:
47216
diff
changeset
|
722 |
const bool has_rex_prefix = ubyte_at(0) == NativeTstRegMem::instruction_rex_b_prefix; |
48200
ed5680f2656a
8193009: compiler/c2/Test7029152.java crashes with SIGILL in java.lang.StringLatin1.indexOf with -XX:+UseJVMCICompiler
dlong
parents:
47881
diff
changeset
|
723 |
const int test_offset = has_rex_prefix ? 1 : 0; |
49027
8dc742d9bbab
8195112: x86 (32 bit): implementation for Thread-local handshakes
mdoerr
parents:
48200
diff
changeset
|
724 |
#else |
8dc742d9bbab
8195112: x86 (32 bit): implementation for Thread-local handshakes
mdoerr
parents:
48200
diff
changeset
|
725 |
const int test_offset = 0; |
8dc742d9bbab
8195112: x86 (32 bit): implementation for Thread-local handshakes
mdoerr
parents:
48200
diff
changeset
|
726 |
#endif |
48200
ed5680f2656a
8193009: compiler/c2/Test7029152.java crashes with SIGILL in java.lang.StringLatin1.indexOf with -XX:+UseJVMCICompiler
dlong
parents:
47881
diff
changeset
|
727 |
const bool is_test_opcode = ubyte_at(test_offset) == NativeTstRegMem::instruction_code_memXregl; |
ed5680f2656a
8193009: compiler/c2/Test7029152.java crashes with SIGILL in java.lang.StringLatin1.indexOf with -XX:+UseJVMCICompiler
dlong
parents:
47881
diff
changeset
|
728 |
const bool is_rax_target = (ubyte_at(test_offset + 1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg; |
ed5680f2656a
8193009: compiler/c2/Test7029152.java crashes with SIGILL in java.lang.StringLatin1.indexOf with -XX:+UseJVMCICompiler
dlong
parents:
47881
diff
changeset
|
729 |
return is_test_opcode && is_rax_target; |
47881
0ce0ac68ace7
8189941: Implementation JEP 312: Thread-local handshake
rehn
parents:
47216
diff
changeset
|
730 |
} |
49027
8dc742d9bbab
8195112: x86 (32 bit): implementation for Thread-local handshakes
mdoerr
parents:
48200
diff
changeset
|
731 |
#ifdef AMD64 |
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
732 |
// Try decoding a near safepoint first: |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
733 |
if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
734 |
ubyte_at(1) == 0x05) { // 00 rax 101 |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
735 |
address fault = addr_at(6) + int_at(2); |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
736 |
NOT_JVMCI(assert(!Assembler::is_polling_page_far(), "unexpected poll encoding");) |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
737 |
return os::is_poll_address(fault); |
1066 | 738 |
} |
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
739 |
// Now try decoding a far safepoint: |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
740 |
// two cases, depending on the choice of the base register in the address. |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
741 |
if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix && |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
742 |
ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl && |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
743 |
(ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) || |
46630
75aa3e39d02c
8182299: Enable disabled clang warnings, build on OSX 10 + Xcode 8
jwilhelm
parents:
44518
diff
changeset
|
744 |
(ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && |
75aa3e39d02c
8182299: Enable disabled clang warnings, build on OSX 10 + Xcode 8
jwilhelm
parents:
44518
diff
changeset
|
745 |
(ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg)) { |
33160
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
746 |
NOT_JVMCI(assert(Assembler::is_polling_page_far(), "unexpected poll encoding");) |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
747 |
return true; |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
748 |
} |
c59f1676d27e
8136421: JEP 243: Java-Level JVM Compiler Interface
twisti
parents:
28947
diff
changeset
|
749 |
return false; |
1 | 750 |
#else |
1066 | 751 |
return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg || |
1 | 752 |
ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && |
753 |
(ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ |
|
754 |
(os::is_poll_address((address)int_at(2))); |
|
755 |
#endif // AMD64 |
|
756 |
} |
|
757 |
||
758 |
inline bool NativeInstruction::is_mov_literal64() { |
|
759 |
#ifdef AMD64 |
|
760 |
return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && |
|
761 |
(ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); |
|
762 |
#else |
|
763 |
return false; |
|
764 |
#endif // AMD64 |
|
765 |
} |
|
7397 | 766 |
|
53244
9807daeb47c4
8216167: Update include guards to reflect correct directories
coleenp
parents:
53149
diff
changeset
|
767 |
#endif // CPU_X86_NATIVEINST_X86_HPP |