author | xdono |
Wed, 02 Jul 2008 12:55:16 -0700 | |
changeset 670 | ddf3e9583f2f |
parent 363 | 99d43e8a76ad |
child 1066 | 717c3345024f |
permissions | -rw-r--r-- |
1 | 1 |
/* |
670 | 2 |
* Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. |
1 | 3 |
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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* |
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* This code is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License version 2 only, as |
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* published by the Free Software Foundation. |
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* |
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* This code is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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* version 2 for more details (a copy is included in the LICENSE file that |
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* accompanied this code). |
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* |
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* You should have received a copy of the GNU General Public License version |
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* 2 along with this work; if not, write to the Free Software Foundation, |
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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* |
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* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
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* CA 95054 USA or visit www.sun.com if you need additional information or |
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* have any questions. |
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* |
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*/ |
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||
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// We have interfaces for the following instructions: |
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// - NativeInstruction |
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// - - NativeCall |
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// - - NativeMovConstReg |
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// - - NativeMovConstRegPatching |
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// - - NativeMovRegMem |
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// - - NativeMovRegMemPatching |
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// - - NativeJump |
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// - - NativeIllegalOpCode |
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// - - NativeGeneralJump |
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// - - NativeReturn |
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// - - NativeReturnX (return with argument) |
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// - - NativePushConst |
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// - - NativeTstRegMem |
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||
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// The base class for different kinds of native instruction abstractions. |
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// Provides the primitive operations to manipulate code relative to this. |
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||
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class NativeInstruction VALUE_OBJ_CLASS_SPEC { |
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friend class Relocation; |
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||
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public: |
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enum Intel_specific_constants { |
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nop_instruction_code = 0x90, |
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nop_instruction_size = 1 |
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}; |
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||
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bool is_nop() { return ubyte_at(0) == nop_instruction_code; } |
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363
99d43e8a76ad
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
1
diff
changeset
|
53 |
bool is_dtrace_trap(); |
1 | 54 |
inline bool is_call(); |
55 |
inline bool is_illegal(); |
|
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inline bool is_return(); |
|
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inline bool is_jump(); |
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inline bool is_cond_jump(); |
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inline bool is_safepoint_poll(); |
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inline bool is_mov_literal64(); |
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||
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protected: |
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address addr_at(int offset) const { return address(this) + offset; } |
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||
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s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } |
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u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } |
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||
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jint int_at(int offset) const { return *(jint*) addr_at(offset); } |
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||
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intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } |
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||
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oop oop_at (int offset) const { return *(oop*) addr_at(offset); } |
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||
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void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } |
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void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } |
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void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } |
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void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } |
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// This doesn't really do anything on Intel, but it is the place where |
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// cache invalidation belongs, generically: |
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void wrote(int offset); |
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public: |
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// unit test stuff |
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static void test() {} // override for testing |
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inline friend NativeInstruction* nativeInstruction_at(address address); |
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}; |
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inline NativeInstruction* nativeInstruction_at(address address) { |
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NativeInstruction* inst = (NativeInstruction*)address; |
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#ifdef ASSERT |
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//inst->verify(); |
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#endif |
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return inst; |
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} |
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inline NativeCall* nativeCall_at(address address); |
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// The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off |
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// instructions (used to manipulate inline caches, primitive & dll calls, etc.). |
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class NativeCall: public NativeInstruction { |
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public: |
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enum Intel_specific_constants { |
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instruction_code = 0xE8, |
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instruction_size = 5, |
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instruction_offset = 0, |
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displacement_offset = 1, |
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return_address_offset = 5 |
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}; |
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enum { cache_line_size = BytesPerWord }; // conservative estimate! |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(return_address_offset); } |
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int displacement() const { return (jint) int_at(displacement_offset); } |
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address displacement_address() const { return addr_at(displacement_offset); } |
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address return_address() const { return addr_at(return_address_offset); } |
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address destination() const; |
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void set_destination(address dest) { |
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#ifdef AMD64 |
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assert((labs((intptr_t) dest - (intptr_t) return_address()) & |
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0xFFFFFFFF00000000) == 0, |
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"must be 32bit offset"); |
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#endif // AMD64 |
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set_int_at(displacement_offset, dest - return_address()); |
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} |
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void set_destination_mt_safe(address dest); |
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void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } |
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void verify(); |
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void print(); |
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// Creation |
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inline friend NativeCall* nativeCall_at(address address); |
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inline friend NativeCall* nativeCall_before(address return_address); |
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static bool is_call_at(address instr) { |
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return ((*instr) & 0xFF) == NativeCall::instruction_code; |
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} |
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static bool is_call_before(address return_address) { |
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return is_call_at(return_address - NativeCall::return_address_offset); |
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} |
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static bool is_call_to(address instr, address target) { |
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return nativeInstruction_at(instr)->is_call() && |
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nativeCall_at(instr)->destination() == target; |
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} |
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// MT-safe patching of a call instruction. |
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static void insert(address code_pos, address entry); |
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static void replace_mt_safe(address instr_addr, address code_buffer); |
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}; |
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inline NativeCall* nativeCall_at(address address) { |
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NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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inline NativeCall* nativeCall_before(address return_address) { |
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NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); |
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#ifdef ASSERT |
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call->verify(); |
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#endif |
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return call; |
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} |
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// An interface for accessing/manipulating native mov reg, imm32 instructions. |
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// (used to manipulate inlined 32bit data dll calls, etc.) |
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class NativeMovConstReg: public NativeInstruction { |
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#ifdef AMD64 |
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static const bool has_rex = true; |
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static const int rex_size = 1; |
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#else |
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static const bool has_rex = false; |
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static const int rex_size = 0; |
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#endif // AMD64 |
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public: |
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enum Intel_specific_constants { |
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instruction_code = 0xB8, |
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instruction_size = 1 + rex_size + wordSize, |
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instruction_offset = 0, |
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data_offset = 1 + rex_size, |
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next_instruction_offset = instruction_size, |
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register_mask = 0x07 |
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}; |
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address instruction_address() const { return addr_at(instruction_offset); } |
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address next_instruction_address() const { return addr_at(next_instruction_offset); } |
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intptr_t data() const { return ptr_at(data_offset); } |
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void set_data(intptr_t x) { set_ptr_at(data_offset, x); } |
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void verify(); |
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void print(); |
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// unit test stuff |
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static void test() {} |
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// Creation |
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inline friend NativeMovConstReg* nativeMovConstReg_at(address address); |
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inline friend NativeMovConstReg* nativeMovConstReg_before(address address); |
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}; |
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inline NativeMovConstReg* nativeMovConstReg_at(address address) { |
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NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); |
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#ifdef ASSERT |
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test->verify(); |
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#endif |
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return test; |
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} |
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inline NativeMovConstReg* nativeMovConstReg_before(address address) { |
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NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); |
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#ifdef ASSERT |
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test->verify(); |
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#endif |
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return test; |
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} |
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class NativeMovConstRegPatching: public NativeMovConstReg { |
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private: |
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friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { |
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NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); |
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#ifdef ASSERT |
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test->verify(); |
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#endif |
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return test; |
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} |
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}; |
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#ifndef AMD64 |
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// An interface for accessing/manipulating native moves of the form: |
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// mov[b/w/l] [reg + offset], reg (instruction_code_reg2mem) |
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// mov[b/w/l] reg, [reg+offset] (instruction_code_mem2reg |
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// mov[s/z]x[w/b] [reg + offset], reg |
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// fld_s [reg+offset] |
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// fld_d [reg+offset] |
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// fstp_s [reg + offset] |
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// fstp_d [reg + offset] |
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// |
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// Warning: These routines must be able to handle any instruction sequences |
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// that are generated as a result of the load/store byte,word,long |
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// macros. For example: The load_unsigned_byte instruction generates |
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// an xor reg,reg inst prior to generating the movb instruction. This |
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// class must skip the xor instruction. |
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class NativeMovRegMem: public NativeInstruction { |
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public: |
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enum Intel_specific_constants { |
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instruction_code_xor = 0x33, |
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instruction_extended_prefix = 0x0F, |
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instruction_code_mem2reg_movzxb = 0xB6, |
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instruction_code_mem2reg_movsxb = 0xBE, |
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instruction_code_mem2reg_movzxw = 0xB7, |
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instruction_code_mem2reg_movsxw = 0xBF, |
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instruction_operandsize_prefix = 0x66, |
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instruction_code_reg2meml = 0x89, |
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instruction_code_mem2regl = 0x8b, |
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instruction_code_reg2memb = 0x88, |
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instruction_code_mem2regb = 0x8a, |
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instruction_code_float_s = 0xd9, |
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instruction_code_float_d = 0xdd, |
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instruction_code_long_volatile = 0xdf, |
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instruction_code_xmm_ss_prefix = 0xf3, |
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instruction_code_xmm_sd_prefix = 0xf2, |
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instruction_code_xmm_code = 0x0f, |
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instruction_code_xmm_load = 0x10, |
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instruction_code_xmm_store = 0x11, |
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instruction_code_xmm_lpd = 0x12, |
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instruction_size = 4, |
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instruction_offset = 0, |
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data_offset = 2, |
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next_instruction_offset = 4 |
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}; |
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address instruction_address() const { |
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if (*addr_at(instruction_offset) == instruction_operandsize_prefix && |
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*addr_at(instruction_offset+1) != instruction_code_xmm_code) { |
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return addr_at(instruction_offset+1); // Not SSE instructions |
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} |
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else if (*addr_at(instruction_offset) == instruction_extended_prefix) { |
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return addr_at(instruction_offset+1); |
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} |
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else if (*addr_at(instruction_offset) == instruction_code_xor) { |
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return addr_at(instruction_offset+2); |
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} |
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else return addr_at(instruction_offset); |
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} |
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||
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address next_instruction_address() const { |
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switch (*addr_at(instruction_offset)) { |
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case instruction_operandsize_prefix: |
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if (*addr_at(instruction_offset+1) == instruction_code_xmm_code) |
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return instruction_address() + instruction_size; // SSE instructions |
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case instruction_extended_prefix: |
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return instruction_address() + instruction_size + 1; |
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case instruction_code_reg2meml: |
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case instruction_code_mem2regl: |
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case instruction_code_reg2memb: |
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case instruction_code_mem2regb: |
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case instruction_code_xor: |
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return instruction_address() + instruction_size + 2; |
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default: |
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return instruction_address() + instruction_size; |
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} |
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} |
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int offset() const{ |
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if (*addr_at(instruction_offset) == instruction_operandsize_prefix && |
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318 |
*addr_at(instruction_offset+1) != instruction_code_xmm_code) { |
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319 |
return int_at(data_offset+1); // Not SSE instructions |
|
320 |
} |
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else if (*addr_at(instruction_offset) == instruction_extended_prefix) { |
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return int_at(data_offset+1); |
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} |
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else if (*addr_at(instruction_offset) == instruction_code_xor || |
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*addr_at(instruction_offset) == instruction_code_xmm_ss_prefix || |
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*addr_at(instruction_offset) == instruction_code_xmm_sd_prefix || |
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*addr_at(instruction_offset) == instruction_operandsize_prefix) { |
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return int_at(data_offset+2); |
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} |
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else return int_at(data_offset); |
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} |
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||
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void set_offset(int x) { |
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if (*addr_at(instruction_offset) == instruction_operandsize_prefix && |
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*addr_at(instruction_offset+1) != instruction_code_xmm_code) { |
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336 |
set_int_at(data_offset+1, x); // Not SSE instructions |
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337 |
} |
|
338 |
else if (*addr_at(instruction_offset) == instruction_extended_prefix) { |
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set_int_at(data_offset+1, x); |
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340 |
} |
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341 |
else if (*addr_at(instruction_offset) == instruction_code_xor || |
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*addr_at(instruction_offset) == instruction_code_xmm_ss_prefix || |
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343 |
*addr_at(instruction_offset) == instruction_code_xmm_sd_prefix || |
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344 |
*addr_at(instruction_offset) == instruction_operandsize_prefix) { |
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345 |
set_int_at(data_offset+2, x); |
|
346 |
} |
|
347 |
else set_int_at(data_offset, x); |
|
348 |
} |
|
349 |
||
350 |
void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } |
|
351 |
void copy_instruction_to(address new_instruction_address); |
|
352 |
||
353 |
void verify(); |
|
354 |
void print (); |
|
355 |
||
356 |
// unit test stuff |
|
357 |
static void test() {} |
|
358 |
||
359 |
private: |
|
360 |
inline friend NativeMovRegMem* nativeMovRegMem_at (address address); |
|
361 |
}; |
|
362 |
||
363 |
inline NativeMovRegMem* nativeMovRegMem_at (address address) { |
|
364 |
NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); |
|
365 |
#ifdef ASSERT |
|
366 |
test->verify(); |
|
367 |
#endif |
|
368 |
return test; |
|
369 |
} |
|
370 |
||
371 |
class NativeMovRegMemPatching: public NativeMovRegMem { |
|
372 |
private: |
|
373 |
friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { |
|
374 |
NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); |
|
375 |
#ifdef ASSERT |
|
376 |
test->verify(); |
|
377 |
#endif |
|
378 |
return test; |
|
379 |
} |
|
380 |
}; |
|
381 |
||
382 |
||
383 |
||
384 |
// An interface for accessing/manipulating native leal instruction of form: |
|
385 |
// leal reg, [reg + offset] |
|
386 |
||
387 |
class NativeLoadAddress: public NativeMovRegMem { |
|
388 |
public: |
|
389 |
enum Intel_specific_constants { |
|
390 |
instruction_code = 0x8D |
|
391 |
}; |
|
392 |
||
393 |
void verify(); |
|
394 |
void print (); |
|
395 |
||
396 |
// unit test stuff |
|
397 |
static void test() {} |
|
398 |
||
399 |
private: |
|
400 |
friend NativeLoadAddress* nativeLoadAddress_at (address address) { |
|
401 |
NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); |
|
402 |
#ifdef ASSERT |
|
403 |
test->verify(); |
|
404 |
#endif |
|
405 |
return test; |
|
406 |
} |
|
407 |
}; |
|
408 |
||
409 |
#endif // AMD64 |
|
410 |
||
411 |
// jump rel32off |
|
412 |
||
413 |
class NativeJump: public NativeInstruction { |
|
414 |
public: |
|
415 |
enum Intel_specific_constants { |
|
416 |
instruction_code = 0xe9, |
|
417 |
instruction_size = 5, |
|
418 |
instruction_offset = 0, |
|
419 |
data_offset = 1, |
|
420 |
next_instruction_offset = 5 |
|
421 |
}; |
|
422 |
||
423 |
address instruction_address() const { return addr_at(instruction_offset); } |
|
424 |
address next_instruction_address() const { return addr_at(next_instruction_offset); } |
|
425 |
address jump_destination() const { |
|
426 |
address dest = (int_at(data_offset)+next_instruction_address()); |
|
427 |
#ifdef AMD64 // What is this about? |
|
428 |
// return -1 if jump to self |
|
429 |
dest = (dest == (address) this) ? (address) -1 : dest; |
|
430 |
#endif // AMD64 |
|
431 |
return dest; |
|
432 |
} |
|
433 |
||
434 |
void set_jump_destination(address dest) { |
|
435 |
intptr_t val = dest - next_instruction_address(); |
|
436 |
#ifdef AMD64 |
|
437 |
if (dest == (address) -1) { // can't encode jump to -1 |
|
438 |
val = -5; // jump to self |
|
439 |
} else { |
|
440 |
assert((labs(val) & 0xFFFFFFFF00000000) == 0, |
|
441 |
"must be 32bit offset"); |
|
442 |
} |
|
443 |
#endif // AMD64 |
|
444 |
set_int_at(data_offset, (jint)val); |
|
445 |
} |
|
446 |
||
447 |
// Creation |
|
448 |
inline friend NativeJump* nativeJump_at(address address); |
|
449 |
||
450 |
void verify(); |
|
451 |
||
452 |
// Unit testing stuff |
|
453 |
static void test() {} |
|
454 |
||
455 |
// Insertion of native jump instruction |
|
456 |
static void insert(address code_pos, address entry); |
|
457 |
// MT-safe insertion of native jump at verified method entry |
|
458 |
static void check_verified_entry_alignment(address entry, address verified_entry); |
|
459 |
static void patch_verified_entry(address entry, address verified_entry, address dest); |
|
460 |
}; |
|
461 |
||
462 |
inline NativeJump* nativeJump_at(address address) { |
|
463 |
NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); |
|
464 |
#ifdef ASSERT |
|
465 |
jump->verify(); |
|
466 |
#endif |
|
467 |
return jump; |
|
468 |
} |
|
469 |
||
470 |
// Handles all kinds of jump on Intel. Long/far, conditional/unconditional |
|
471 |
class NativeGeneralJump: public NativeInstruction { |
|
472 |
public: |
|
473 |
enum Intel_specific_constants { |
|
474 |
// Constants does not apply, since the lengths and offsets depends on the actual jump |
|
475 |
// used |
|
476 |
// Instruction codes: |
|
477 |
// Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) |
|
478 |
// Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) |
|
479 |
unconditional_long_jump = 0xe9, |
|
480 |
unconditional_short_jump = 0xeb, |
|
481 |
instruction_size = 5 |
|
482 |
}; |
|
483 |
||
484 |
address instruction_address() const { return addr_at(0); } |
|
485 |
address jump_destination() const; |
|
486 |
||
487 |
// Creation |
|
488 |
inline friend NativeGeneralJump* nativeGeneralJump_at(address address); |
|
489 |
||
490 |
// Insertion of native general jump instruction |
|
491 |
static void insert_unconditional(address code_pos, address entry); |
|
492 |
static void replace_mt_safe(address instr_addr, address code_buffer); |
|
493 |
||
494 |
void verify(); |
|
495 |
}; |
|
496 |
||
497 |
inline NativeGeneralJump* nativeGeneralJump_at(address address) { |
|
498 |
NativeGeneralJump* jump = (NativeGeneralJump*)(address); |
|
499 |
debug_only(jump->verify();) |
|
500 |
return jump; |
|
501 |
} |
|
502 |
||
503 |
class NativePopReg : public NativeInstruction { |
|
504 |
public: |
|
505 |
enum Intel_specific_constants { |
|
506 |
instruction_code = 0x58, |
|
507 |
instruction_size = 1, |
|
508 |
instruction_offset = 0, |
|
509 |
data_offset = 1, |
|
510 |
next_instruction_offset = 1 |
|
511 |
}; |
|
512 |
||
513 |
// Insert a pop instruction |
|
514 |
static void insert(address code_pos, Register reg); |
|
515 |
}; |
|
516 |
||
517 |
||
518 |
class NativeIllegalInstruction: public NativeInstruction { |
|
519 |
public: |
|
520 |
enum Intel_specific_constants { |
|
521 |
instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B |
|
522 |
instruction_size = 2, |
|
523 |
instruction_offset = 0, |
|
524 |
next_instruction_offset = 2 |
|
525 |
}; |
|
526 |
||
527 |
// Insert illegal opcode as specific address |
|
528 |
static void insert(address code_pos); |
|
529 |
}; |
|
530 |
||
531 |
// return instruction that does not pop values of the stack |
|
532 |
class NativeReturn: public NativeInstruction { |
|
533 |
public: |
|
534 |
enum Intel_specific_constants { |
|
535 |
instruction_code = 0xC3, |
|
536 |
instruction_size = 1, |
|
537 |
instruction_offset = 0, |
|
538 |
next_instruction_offset = 1 |
|
539 |
}; |
|
540 |
}; |
|
541 |
||
542 |
// return instruction that does pop values of the stack |
|
543 |
class NativeReturnX: public NativeInstruction { |
|
544 |
public: |
|
545 |
enum Intel_specific_constants { |
|
546 |
instruction_code = 0xC2, |
|
547 |
instruction_size = 2, |
|
548 |
instruction_offset = 0, |
|
549 |
next_instruction_offset = 2 |
|
550 |
}; |
|
551 |
}; |
|
552 |
||
553 |
// Simple test vs memory |
|
554 |
class NativeTstRegMem: public NativeInstruction { |
|
555 |
public: |
|
556 |
enum Intel_specific_constants { |
|
557 |
instruction_code_memXregl = 0x85 |
|
558 |
}; |
|
559 |
}; |
|
560 |
||
561 |
inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } |
|
562 |
inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } |
|
563 |
inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || |
|
564 |
ubyte_at(0) == NativeReturnX::instruction_code; } |
|
565 |
inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || |
|
566 |
ubyte_at(0) == 0xEB; /* short jump */ } |
|
567 |
inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || |
|
568 |
(ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } |
|
569 |
inline bool NativeInstruction::is_safepoint_poll() { |
|
570 |
#ifdef AMD64 |
|
571 |
return ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && |
|
572 |
ubyte_at(1) == 0x05 && // 00 rax 101 |
|
573 |
((intptr_t) addr_at(6)) + int_at(2) == (intptr_t) os::get_polling_page(); |
|
574 |
#else |
|
575 |
return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2regl || |
|
576 |
ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && |
|
577 |
(ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ |
|
578 |
(os::is_poll_address((address)int_at(2))); |
|
579 |
#endif // AMD64 |
|
580 |
} |
|
581 |
||
582 |
inline bool NativeInstruction::is_mov_literal64() { |
|
583 |
#ifdef AMD64 |
|
584 |
return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && |
|
585 |
(ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); |
|
586 |
#else |
|
587 |
return false; |
|
588 |
#endif // AMD64 |
|
589 |
} |