/*

 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.

 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

 *

 * This code is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 only, as

 * published by the Free Software Foundation.

 *

 * This code is distributed in the hope that it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 * version 2 for more details (a copy is included in the LICENSE file that

 * accompanied this code).

 *

 * You should have received a copy of the GNU General Public License version

 * 2 along with this work; if not, write to the Free Software Foundation,

 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

 *

 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

 * or visit www.oracle.com if you need additional information or have any

 * questions.

 *

 */

#ifndef CPU_X86_VM_VERSION_X86_HPP

#define CPU_X86_VM_VERSION_X86_HPP

#include "memory/universe.hpp"

#include "runtime/globals_extension.hpp"

class VM_Version : public Abstract_VM_Version {

  friend class VMStructs;

  friend class JVMCIVMStructs;

 public:

  // cpuid result register layouts.  These are all unions of a uint32_t

  // (in case anyone wants access to the register as a whole) and a bitfield.

  union StdCpuid1Eax {

    uint32_t value;

    struct {

      uint32_t stepping   : 4,

               model      : 4,

               family     : 4,

               proc_type  : 2,

                          : 2,

               ext_model  : 4,

               ext_family : 8,

                          : 4;

    } bits;

  };

  union StdCpuid1Ebx { // example, unused

    uint32_t value;

    struct {

      uint32_t brand_id         : 8,

               clflush_size     : 8,

               threads_per_cpu  : 8,

               apic_id          : 8;

    } bits;

  };

  union StdCpuid1Ecx {

    uint32_t value;

    struct {

      uint32_t sse3     : 1,

               clmul    : 1,

                        : 1,

               monitor  : 1,

                        : 1,

               vmx      : 1,

                        : 1,

               est      : 1,

                        : 1,

               ssse3    : 1,

               cid      : 1,

                        : 1,

               fma      : 1,

               cmpxchg16: 1,

                        : 4,

               dca      : 1,

               sse4_1   : 1,

               sse4_2   : 1,

                        : 2,

               popcnt   : 1,

                        : 1,

               aes      : 1,

                        : 1,

               osxsave  : 1,

               avx      : 1,

                        : 3;

    } bits;

  };

  union StdCpuid1Edx {

    uint32_t value;

    struct {

      uint32_t          : 4,

               tsc      : 1,

                        : 3,

               cmpxchg8 : 1,

                        : 6,

               cmov     : 1,

                        : 3,

               clflush  : 1,

                        : 3,

               mmx      : 1,

               fxsr     : 1,

               sse      : 1,

               sse2     : 1,

                        : 1,

               ht       : 1,

                        : 3;

    } bits;

  };

  union DcpCpuid4Eax {

    uint32_t value;

    struct {

      uint32_t cache_type    : 5,

                             : 21,

               cores_per_cpu : 6;

    } bits;

  };

  union DcpCpuid4Ebx {

    uint32_t value;

    struct {

      uint32_t L1_line_size  : 12,

               partitions    : 10,

               associativity : 10;

    } bits;

  };

  union TplCpuidBEbx {

    uint32_t value;

    struct {

      uint32_t logical_cpus : 16,

                            : 16;

    } bits;

  };

  union ExtCpuid1Ecx {

    uint32_t value;

    struct {

      uint32_t LahfSahf     : 1,

               CmpLegacy    : 1,

                            : 3,

               lzcnt_intel  : 1,

               lzcnt        : 1,

               sse4a        : 1,

               misalignsse  : 1,

               prefetchw    : 1,

                            : 22;

    } bits;

  };

  union ExtCpuid1Edx {

    uint32_t value;

    struct {

      uint32_t           : 22,

               mmx_amd   : 1,

               mmx       : 1,

               fxsr      : 1,

                         : 4,

               long_mode : 1,

               tdnow2    : 1,

               tdnow     : 1;

    } bits;

  };

  union ExtCpuid5Ex {

    uint32_t value;

    struct {

      uint32_t L1_line_size : 8,

               L1_tag_lines : 8,

               L1_assoc     : 8,

               L1_size      : 8;

    } bits;

  };

  union ExtCpuid7Edx {

    uint32_t value;

    struct {

      uint32_t               : 8,

              tsc_invariance : 1,

                             : 23;

    } bits;

  };

  union ExtCpuid8Ecx {

    uint32_t value;

    struct {

      uint32_t cores_per_cpu : 8,

                             : 24;

    } bits;

  };

  union SefCpuid7Eax {

    uint32_t value;

  };

  union SefCpuid7Ebx {

    uint32_t value;

    struct {

      uint32_t fsgsbase : 1,

                        : 2,

                   bmi1 : 1,

                        : 1,

                   avx2 : 1,

                        : 2,

                   bmi2 : 1,

                   erms : 1,

                        : 1,

                    rtm : 1,

                        : 4,

                avx512f : 1,

               avx512dq : 1,

                        : 1,

                    adx : 1,

                        : 3,

             clflushopt : 1,

                   clwb : 1,

                        : 1,

               avx512pf : 1,

               avx512er : 1,

               avx512cd : 1,

                    sha : 1,

               avx512bw : 1,

               avx512vl : 1;

    } bits;

  };

  union SefCpuid7Ecx {

    uint32_t value;

    struct {

      uint32_t prefetchwt1 : 1,

               avx512_vbmi : 1,

                      umip : 1,

                       pku : 1,

                     ospke : 1,

                           : 1,

              avx512_vbmi2 : 1,

                           : 1,

                      gfni : 1,

                      vaes : 1,

                vpclmulqdq : 1,

               avx512_vnni : 1,

             avx512_bitalg : 1,

                           : 1,

          avx512_vpopcntdq : 1,

                           : 17;

    } bits;

  };

  union SefCpuid7Edx {

    uint32_t value;

    struct {

      uint32_t             : 2,

             avx512_4vnniw : 1,

             avx512_4fmaps : 1,

                           : 28;

    } bits;

  };

  union ExtCpuid1EEbx {

    uint32_t value;

    struct {

      uint32_t                  : 8,

               threads_per_core : 8,

                                : 16;

    } bits;

  };

  union XemXcr0Eax {

    uint32_t value;

    struct {

      uint32_t x87     : 1,

               sse     : 1,

               ymm     : 1,

               bndregs : 1,

               bndcsr  : 1,

               opmask  : 1,

               zmm512  : 1,

               zmm32   : 1,

                       : 24;

    } bits;

  };

protected:

  static int _cpu;

  static int _model;

  static int _stepping;

  static address   _cpuinfo_segv_addr; // address of instruction which causes SEGV

  static address   _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV

  enum Feature_Flag {

    CPU_CX8      = (1 << 0), // next bits are from cpuid 1 (EDX)

    CPU_CMOV     = (1 << 1),

    CPU_FXSR     = (1 << 2),

    CPU_HT       = (1 << 3),

    CPU_MMX      = (1 << 4),

    CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions

                                   // may not necessarily support other 3dnow instructions

    CPU_SSE      = (1 << 6),

    CPU_SSE2     = (1 << 7),

    CPU_SSE3     = (1 << 8),  // SSE3 comes from cpuid 1 (ECX)

    CPU_SSSE3    = (1 << 9),

    CPU_SSE4A    = (1 << 10),

    CPU_SSE4_1   = (1 << 11),

    CPU_SSE4_2   = (1 << 12),

    CPU_POPCNT   = (1 << 13),

    CPU_LZCNT    = (1 << 14),

    CPU_TSC      = (1 << 15),

    CPU_TSCINV   = (1 << 16),

    CPU_AVX      = (1 << 17),

    CPU_AVX2     = (1 << 18),

    CPU_AES      = (1 << 19),

    CPU_ERMS     = (1 << 20), // enhanced 'rep movsb/stosb' instructions

    CPU_CLMUL    = (1 << 21), // carryless multiply for CRC

    CPU_BMI1     = (1 << 22),

    CPU_BMI2     = (1 << 23),

    CPU_RTM      = (1 << 24), // Restricted Transactional Memory instructions

    CPU_ADX      = (1 << 25),

    CPU_AVX512F  = (1 << 26), // AVX 512bit foundation instructions

    CPU_AVX512DQ = (1 << 27),

    CPU_AVX512PF = (1 << 28),

    CPU_AVX512ER = (1 << 29),

    CPU_AVX512CD = (1 << 30)

    // Keeping sign bit 31 unassigned.

  };

#define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit

#define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length

#define CPU_SHA ((uint64_t)UCONST64(0x400000000))      // SHA instructions

#define CPU_FMA ((uint64_t)UCONST64(0x800000000))      // FMA instructions

#define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000))       // Vzeroupper instruction

#define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount

#define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication

#define CPU_VAES ((uint64_t)UCONST64(0x8000000000))    // Vector AES instructions

#define CPU_VNNI ((uint64_t)UCONST64(0x10000000000))   // Vector Neural Network Instructions

#define CPU_FLUSH ((uint64_t)UCONST64(0x20000000000))  // flush instruction

#define CPU_FLUSHOPT ((uint64_t)UCONST64(0x40000000000)) // flushopt instruction

#define CPU_CLWB ((uint64_t)UCONST64(0x80000000000))   // clwb instruction

enum Extended_Family {

    // AMD

    CPU_FAMILY_AMD_11H       = 0x11,

    // ZX

    CPU_FAMILY_ZX_CORE_F6    = 6,

    CPU_FAMILY_ZX_CORE_F7    = 7,

    // Intel

    CPU_FAMILY_INTEL_CORE    = 6,

    CPU_MODEL_NEHALEM        = 0x1e,

    CPU_MODEL_NEHALEM_EP     = 0x1a,

    CPU_MODEL_NEHALEM_EX     = 0x2e,

    CPU_MODEL_WESTMERE       = 0x25,

    CPU_MODEL_WESTMERE_EP    = 0x2c,

    CPU_MODEL_WESTMERE_EX    = 0x2f,

    CPU_MODEL_SANDYBRIDGE    = 0x2a,

    CPU_MODEL_SANDYBRIDGE_EP = 0x2d,

    CPU_MODEL_IVYBRIDGE_EP   = 0x3a,

    CPU_MODEL_HASWELL_E3     = 0x3c,

    CPU_MODEL_HASWELL_E7     = 0x3f,

    CPU_MODEL_BROADWELL      = 0x3d,

    CPU_MODEL_SKYLAKE        = 0x55

  };

  // cpuid information block.  All info derived from executing cpuid with

  // various function numbers is stored here.  Intel and AMD info is

  // merged in this block: accessor methods disentangle it.

  //

  // The info block is laid out in subblocks of 4 dwords corresponding to

  // eax, ebx, ecx and edx, whether or not they contain anything useful.

  struct CpuidInfo {

    // cpuid function 0

    uint32_t std_max_function;

    uint32_t std_vendor_name_0;

    uint32_t std_vendor_name_1;

    uint32_t std_vendor_name_2;

    // cpuid function 1

    StdCpuid1Eax std_cpuid1_eax;

    StdCpuid1Ebx std_cpuid1_ebx;

    StdCpuid1Ecx std_cpuid1_ecx;

    StdCpuid1Edx std_cpuid1_edx;

    // cpuid function 4 (deterministic cache parameters)

    DcpCpuid4Eax dcp_cpuid4_eax;

    DcpCpuid4Ebx dcp_cpuid4_ebx;

    uint32_t     dcp_cpuid4_ecx; // unused currently

    uint32_t     dcp_cpuid4_edx; // unused currently

    // cpuid function 7 (structured extended features)

    SefCpuid7Eax sef_cpuid7_eax;

    SefCpuid7Ebx sef_cpuid7_ebx;

    SefCpuid7Ecx sef_cpuid7_ecx;

    SefCpuid7Edx sef_cpuid7_edx;

    // cpuid function 0xB (processor topology)

    // ecx = 0

    uint32_t     tpl_cpuidB0_eax;

    TplCpuidBEbx tpl_cpuidB0_ebx;

    uint32_t     tpl_cpuidB0_ecx; // unused currently

    uint32_t     tpl_cpuidB0_edx; // unused currently

    // ecx = 1

    uint32_t     tpl_cpuidB1_eax;

    TplCpuidBEbx tpl_cpuidB1_ebx;

    uint32_t     tpl_cpuidB1_ecx; // unused currently

    uint32_t     tpl_cpuidB1_edx; // unused currently

    // ecx = 2

    uint32_t     tpl_cpuidB2_eax;

    TplCpuidBEbx tpl_cpuidB2_ebx;

    uint32_t     tpl_cpuidB2_ecx; // unused currently

    uint32_t     tpl_cpuidB2_edx; // unused currently

    // cpuid function 0x80000000 // example, unused

    uint32_t ext_max_function;

    uint32_t ext_vendor_name_0;

    uint32_t ext_vendor_name_1;

    uint32_t ext_vendor_name_2;

    // cpuid function 0x80000001

    uint32_t     ext_cpuid1_eax; // reserved

    uint32_t     ext_cpuid1_ebx; // reserved

    ExtCpuid1Ecx ext_cpuid1_ecx;

    ExtCpuid1Edx ext_cpuid1_edx;

    // cpuid functions 0x80000002 thru 0x80000004: example, unused

    uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;

    uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;

    uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;

    // cpuid function 0x80000005 // AMD L1, Intel reserved

    uint32_t     ext_cpuid5_eax; // unused currently

    uint32_t     ext_cpuid5_ebx; // reserved

    ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)

    ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)

    // cpuid function 0x80000007

    uint32_t     ext_cpuid7_eax; // reserved

    uint32_t     ext_cpuid7_ebx; // reserved

    uint32_t     ext_cpuid7_ecx; // reserved

    ExtCpuid7Edx ext_cpuid7_edx; // tscinv

    // cpuid function 0x80000008

    uint32_t     ext_cpuid8_eax; // unused currently

    uint32_t     ext_cpuid8_ebx; // reserved

    ExtCpuid8Ecx ext_cpuid8_ecx;

    uint32_t     ext_cpuid8_edx; // reserved

    // cpuid function 0x8000001E // AMD 17h

    uint32_t      ext_cpuid1E_eax;

    ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)

    uint32_t      ext_cpuid1E_ecx;

    uint32_t      ext_cpuid1E_edx; // unused currently

    // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)

    XemXcr0Eax   xem_xcr0_eax;

    uint32_t     xem_xcr0_edx; // reserved

    // Space to save ymm registers after signal handle

    int          ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15

    // Space to save zmm registers after signal handle

    int          zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31

  };

  // The actual cpuid info block

  static CpuidInfo _cpuid_info;

  // Extractors and predicates

  static uint32_t extended_cpu_family() {

    uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;

    result += _cpuid_info.std_cpuid1_eax.bits.ext_family;

    return result;

  }

  static uint32_t extended_cpu_model() {

    uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;

    result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;

    return result;

  }

  static uint32_t cpu_stepping() {

    uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;

    return result;

  }

  static uint logical_processor_count() {

    uint result = threads_per_core();

    return result;

  }

  static uint64_t feature_flags() {

    uint64_t result = 0;

    if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)

      result |= CPU_CX8;

    if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)